CN213846650U - Ramp ADC and TFT photosensitive sensor array reading chip - Google Patents
Ramp ADC and TFT photosensitive sensor array reading chip Download PDFInfo
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- CN213846650U CN213846650U CN202120012907.5U CN202120012907U CN213846650U CN 213846650 U CN213846650 U CN 213846650U CN 202120012907 U CN202120012907 U CN 202120012907U CN 213846650 U CN213846650 U CN 213846650U
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Abstract
The utility model discloses a slope ADC and TFT light sensor array read-out chip for TFT light sensor array outputs the analog and digital conversion of fingerprint signal, sets up in the rear stage of TFT light sensor array read-out chip sampling circuit, the slope ADC includes slope generator, comparator, upper and lower counter and data latch output, upper and lower counter be used for with the output of comparator is connected, and sets for the initial value; the up-down counter can start to count from the initial value upwards or downwards, the initial value can be input from the outside, so that the up-down counter can start to count from the initial value upwards or downwards, and the counting time of the up-down counter is controlled, so that the counting of the up-down counter can be ensured not to be triggered to the boundary value of the counting range and then to be continued, and therefore, the counting error can not be triggered.
Description
Technical Field
The utility model belongs to the technical field of the fingerprint identification technique and specifically relates to a slope ADC and TFT light sensor array read-out chip is related to.
Background
Fingerprint identification technology has been widely applied to electronic devices. The fingerprint identification module that is comparatively ripe on the existing market still is capacitanc fingerprint module more. Products in the optical fingerprint module class gradually mature.
In order to improve the user experience of fingerprint identification, the fingerprint identification tends to be developed by blind touch at present, namely, the fingerprint can be identified by touching any position on a screen. The development trend of the application end makes the research on the large-area fingerprint identification module more hot, and needs to commercialize and commercialize the large-area fingerprint identification module quickly.
For the cost of manufacture that reduces the fingerprint identification module product of large tracts of land, TFT optics fingerprint identification module has constituteed the product of each trade company's competitive research. The TFT optical fingerprint identification module generally includes a large-area array of TFT photosensor array chips and a readout chip matched with the TFT photosensor array chips. The readout chip needs to read and convert the signals output by the TFT photosensor array chip. However, an ADC (Analog-to-Digital Converter) is a common module for Analog and Digital signals in a chip. The ramp ADC is a type of ADC that is more common in ADC, and a general ramp ADC generally includes: a ramp generator, a comparator, a counter and a latch.
Since the difference between the corresponding fingerprint valley and ridge in the optical signal converted from the electrical signal output by the TFT photosensor array chip is weak, it may be difficult to form a clear fingerprint image by a general reading chip. In the reading chip, the precision and accuracy of ADC conversion directly affect the finally formed fingerprint image and fingerprint identification in later period.
It is noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a slope ADC for TFT light sensor array output fingerprint signal's analog and digital conversion sets up in TFT light sensor array reads out the chip, carries out analog-to-digital conversion to the analog signal of TFT light sensor array output, is used for TFT optics fingerprint identification module can finally form effectual fingerprint image.
In order to solve the technical problem, the utility model provides a slope ADC for TFT light sensor array output fingerprint signal's analog and digital conversion sets up the rear stage that reads out sampling circuit in the chip in TFT light sensor array, the slope ADC includes:
a ramp generator for outputting a ramp signal;
a comparator, a first input end of which is used for receiving the ramp signal, and a second input end of which receives the sampling signal output by the sampling circuit;
the up-down counter is used for being connected with the output end of the comparator and setting an initial value;
a data latch output for receiving the output of the up-down counter and outputting a converted digital signal;
wherein, a working period of the ramp ADC comprises a first counting window and a second counting window;
the up-down counter starts counting from an initial value to a first direction in the first counting window;
and in the second counting window, the up-down counter starts counting towards a second direction by the counting value at the end of the first counting window, and the counting directions of the first direction and the second direction are opposite.
Optionally, the first direction is counting down from the initial value, and the second direction is counting up from the up-down counter by a count value at the end of the first count window.
Optionally, the initial value of the up-down counter satisfies the following formula:
(2n-1)-T2/Tclk≥X>T1/Tclk；
wherein X is the initial value, Tclk is the clock period of the up-down counter, and T1 is the firstThe count window time, T2, is the second count window time, 2n-1 is the maximum value that the up-down counter can count within a unit duty cycle of the ramp ADC, and n is a natural number.
Optionally, the up-down counter comprises a plurality of stages of single-stage counters connected to each other and a mode selector;
each single-stage counter is connected with each other through the mode selector, wherein each single-stage counter is provided with an initial value input end and an initial control signal for correspondingly controlling whether the initial value is assigned or not.
Optionally, each stage of the single-stage counter includes an initial data selection mode selector, a flip-flop, and a flip-flop output selector;
an input end of the initial data mode selector is an initial value input end of the up-down counter, and the initial data mode selector is controlled by an initial control signal init-hold.
Optionally, the flip-flop output selector comprises a hold output selector and an up-down count selector;
the input end of the holding output selector is connected with the output of the trigger, the output end of the holding output selector is connected with one input end of the initial data selection mode selector, and the enable signal of the holding output selector is controlled by a counter holding signal hold;
the input end of the up-down counting selector is connected with the output end of the trigger, and the output end of the up-down counting selector is used as one of the output ends of the corresponding single-stage counter.
Optionally, an input signal of one input end of the mode selector is one of output signals of a pre-stage flip-flop circuit, an input signal of the other input end of the mode selector is an initial setting clock signal, and an enable signal of the operating mode selector is controlled by an initial setting signal init _ set.
Optionally, the up-down counter further comprises a logic gate circuit;
the logic gate circuit is used for receiving the output of the comparator, and the output of the logic gate circuit is connected with the input end of the mode selector.
Based on the same invention concept, the utility model also provides a TFT photosensor array reading chip, which is applied to the electronic equipment with a host, and comprises the slope ADC, the temporary storage and a communication interface communicated with the host;
wherein the up-down counter comprises a plurality of stages of interconnected single-stage counters, each of the single-stage counters having an initial value input;
the host transmits the initial value of the up-down counter to the temporary storage through the communication interface, and the temporary storage sends the initial value to the initial value input end of each single-stage counter in the up-down counter.
Optionally, the communication interface is an SPI interface.
Compared with the prior art, the utility model discloses following beneficial effect has:
the utility model provides a slope ADC for the analog and digital conversion of TFT light sensor array output fingerprint signal sets up the back level that reads out sampling circuit in the chip in TFT light sensor array, the slope ADC includes slope generator, comparator, upper and lower counter and data latch output, upper and lower counter, be used for with the output of comparator is connected, and sets for the initial value; a data latch output for receiving the output of the up-down counter and outputting a converted digital signal; wherein, a working period of the ramp ADC comprises a first counting window and a second counting window; the up-down counter starts counting from an initial value to a first direction in the first counting window; and in the second counting window, the up-down counter starts counting towards a second direction by the counting value at the end of the first counting window, and the counting directions of the first direction and the second direction are opposite. The utility model discloses a setting of initial value has been realized to the counter from top to bottom in the slope ADC among the technical scheme, to twice count window in a duty cycle of slope ADC, through carrying out the setting of initial value to wherein counter, combines the control of count window time, can avoid the slope ADC inaccurate data conversion to appear, ensures the stability of slope ADC conversion precision.
Drawings
FIG. 1 is a schematic diagram of a four-stage asynchronous counter used in a conventional ramp generator;
FIG. 2 is a schematic diagram of the internal structure of a one-stage up-down counter;
FIG. 3 is a timing diagram illustrating the operation of the up-down counter of FIG. 1;
fig. 4 is a schematic structural diagram of a slope ADC according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an internal structure of a single-stage counter in the up-down counter according to an embodiment of the present invention;
fig. 6 is a schematic view of a connection structure between single-stage counters of the up-down counter according to an embodiment of the present invention;
fig. 7 is a timing diagram illustrating initial assignment of the up-down counter according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of the up-down counter according to an embodiment of the present invention;
Detailed Description
The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In order to facilitate understanding of the technical solutions of the present application, the related art related to the present application is briefly described below.
As described above, since the fingerprint ridge difference signal of the conversion corresponding to the large-area array TFT photosensor array is weak, it is necessary that the ADC conversion in the readout chip corresponding to the TFT photosensor array chip can have higher conversion accuracy and stability of the conversion accuracy.
Currently, a ramp ADC may generally include a ramp generator, a comparator, and an up-down counter. The ramp generator is used for outputting a ramp level to the comparator. The comparator is used for receiving the analog signal and the ramp level and outputting a level signal. The up-down counter is used for outputting a digital signal to the storage unit based on the level signal. The counter in a common ramp generator consists of an asynchronous counter that adds an up/down count toggle control and a hold current value control. Fig. 1 is a schematic diagram of a four-stage asynchronous counter used in a conventional ramp generator. Of course, the asynchronous counter may include more stages of counters, which are illustrated and described herein as four stages. During the unit duty cycle of the ramp ADC, the counter will count twice. The first count is a down count and the second count is an up count. The first counting is to obtain the bottom noise information, and the second counting is to obtain the actual signal information. The real signal information can be obtained after the counting in the two opposite directions is performed through the self subtraction function of the counter. Of course, in other embodiments, the first count may be up and the second count may be down. Therefore, the counter in such a ramp ADC may be referred to as an up-down counter. Fig. 2 is a schematic diagram illustrating an internal structure of a one-stage up-down counter, and fig. 3 is a timing diagram illustrating an operation of the up-down counter shown in fig. 1.
Before comparison, resetting each stage of the counter to 0, pulling up an RST (reset) signal after the reset is finished, pulling up a HOLD signal after the first comparison is finished, and connecting the Q output of the D flip-flop to the D end to be used as input data, so that the output of the D flip-flop cannot be changed by the change of an externally accessed clock signal. When the HOLD signal is held at a high level, the up-down signal is inverted. If counting downwards first, the initial state of the up-down signal is high level, the initial state of the up-down signal is low level after turning over, and the up-down signal enters into an up-counting mode; if count up earlier, the upper and lower signal initial state is the low level, and the upset back is the high level, gets into count down mode, can be as required, and the free choice is to count down the mode, only need guarantee twice opposite direction count can. If the HOLD signal is not pulled high, the toggling of the up and down signals will change the input of the current D flip-flop to the next stage clock signal. Taking default initial count-down as an example, if Q of a certain stage is 1 and QB is 0, the clock output signal clkout will change from 0 to 1 during up-down switching, forming an edge trigger, and making the D flip-flop of the next stage read QB, so that the HOLD signal is pulled high during up-down switching, and the counter result can be kept to keep the value after the first comparison in the time window between two comparisons.
However, in practical applications, such up-down counter structures as shown in fig. 1 have the following drawbacks: the up-down counter with such a structure and operation mode may trigger a counting boundary value of the counter during counting, and thus may cause an erroneous counting, which may easily cause an unexpected deviation of the result of the analog-to-digital converter applying the up-down counter.
The ramp ADC provided by the application can avoid the wrong counting of the up-down counter in the ramp ADC so as to ensure the accuracy and precision of analog-to-digital conversion of the ramp ADC. In the ramp ADC of the present application, the up-down counter may be configured to start counting up or counting down from an initial value by inputting the initial value of the up-down counter from outside, and by controlling the counting time of the up-down counter, it may be ensured that the up-down counter does not trigger counting after the limit value of the up-down counter is reached (i.e., false counting is not triggered).
Please refer to fig. 4, 5, 6, 7, and 8 for a schematic diagram of an embodiment of the ramp ADC. Fig. 8 is a schematic diagram of an embodiment of the novel counter based on the four-stage connection illustrated in fig. 5, 6 and 7. Fig. 5 is a schematic diagram of an internal structure of a first-stage flip-flop circuit in the up-down counter, fig. 6 is a schematic diagram of a connection structure between stages of the up-down counter, and fig. 7 is a schematic diagram of an initial assignment of the novel up-down counter.
As shown in fig. 8, the novel up-down counter comprises a plurality of stages of interconnected counters, and each single-stage counter is connected with each other through an operation mode selector. The illustration in fig. 8 is only for four-level counters. Each stage of counter is provided with an initial value input end and an initial control signal init-hold which corresponds to whether the initial value is controlled to be assigned or not.
Referring to fig. 5, each stage of the counter includes an initial data selection mode selector, a flip-flop, and a flip-flop output selector. One input end of the initial data selection mode selector is an initial value input end of the counter, and the initial data selection mode selector is controlled by an initial control signal init-hold. The counter has a hold mode and a count up and down mode. Correspondingly, the output end of the flip-flop in the counter is provided with a holding output selector and an up-down counting selector. The input end of the holding output selector is connected with the output of the trigger, and the output end of the holding output selector is connected with one input end of the initial data selection mode selector. The enable signal of the hold output selector is controlled by the counter hold-hold signal. The input end of the up-down counting selector is linked with the output end of the trigger, and the output end of the up-down counting selector is used as one of the output ends of the current-stage counter. The enable terminal of the up-down count selector is controlled by an up-down count-up signal. The output end of the trigger is one of the output ends of the counter.
Referring to fig. 6, in order to realize the two modes of the initial assignment and the normal counting, the counters of the respective stages are connected through the operation mode selector. The input signal of the working mode selector is one of the output signals of the preceding stage counter, and the other input end is an initial setting clock signal. The enable signal of the operation mode selector is controlled by an initial setting signal init _ set. The connection mode of the working mode selector of the first stage counter is different from that of the working mode selector arranged between the counters of different stages.
Referring to fig. 8, the up-down counter further includes a logic gate circuit portion for electrically connecting the first counter and the output of the comparator in the ramp ADC. This logic gate section receives the output of the comparator in the ramp ADC. The output of the logic gate circuit is connected with the input end of the working mode selector of the first stage counter. In the embodiment illustrated in fig. 8, this logic gate circuit section includes a first and gate and a second and gate. A first input end of the first AND gate receives a clock signal Counter _ clk of the up-down Counter, and a second input end of the first AND gate receives a comparison enable signal Comp _ en; the output end of the first AND gate is connected with the first input end of the second AND gate, and the second input end of the second AND gate is used for receiving the output signal of the comparator in the ramp ADC after the inversion processing.
It should be noted that in the embodiments illustrated in fig. 4 to 6 and 8, the flip-flops illustrated in the counter are all implemented by D flip-flops. Due to the characteristics of the D flip-flop, the data at the data input end can be read only after the external clock is excited to be connected. Therefore, the input terminal of the working mode selector receives an initial setting clock signal for an external clock signal required when the counter of the internal D flip-flop receives an initial assignment. In other embodiments, the flip-flop may also be another type of flip-flop, for example, an RS flip-flop, a T flip-flop, or a JK flip-flop, and when the RS flip-flop, the T flip-flop, or the JK flip-flop is selected for implementation, some logic circuits need to be added to implement the same function as the D flip-flop.
Fig. 7 is a timing diagram of the up-down counter during initial assignment, and the states of the up-down counter in the initial assignment process according to the embodiments described herein are described in conjunction with fig. 4, fig. 5, and fig. 8 as follows:
at the time of t1, raising an init _ hold signal, keeping the init _ set _ clk and init _ set signals in a low level state, when the init _ set is in the low level state, not directly connecting each stage of the counter, in a mode of waiting for an external clock mode to give an initial value, raising the init _ hold signal, cutting off an internal loop of each stage of the counter, entering an external assignment mode, and connecting a D input end of an n-th stage D trigger with external data D < n >;
at the time of t2, pulling up the init _ set _ clk signal, keeping the init _ hold signal in a high level state, keeping the init _ set in a low level state, exciting an external clock of the D trigger at the moment, writing external data D < n > into the D trigger, enabling the output of Count _ out < n > to be D < n >, and finishing the assignment of an initial value;
at the time t3, pulling down the init _ hold, keeping the init _ set _ clk in a high level state, keeping the init _ set in a low level state, and reconnecting the loop of the counter;
at time t4, it keeps init _ hold low, pulls it up _ set, keeps it _ set _ clk high, and each stage of the counter is connected to form an asynchronous counter and starts counting. If init _ set _ clk is already pulled low at time t4, and the clkout of the previous stage is already at a high level, when init _ set is pulled high, the previous stage will receive a rising edge trigger, causing an erroneous count;
at time t5, init _ hold is held low, init _ set is high, and init _ set _ clk is pulled low to reset.
Referring to fig. 8, a schematic structural diagram of the up-down counter with four levels connected in the embodiment shown in fig. 8 is shown, wherein: counter _ clk is a clock signal of the up-down Counter, and a clock period is set to be Tclk; comp _ en is the comparative active time control signal, and is an active comparative time window when Comp _ en is at a high level; the Comparator _ out is the output of the previous Comparator, i.e. the level signal, and is determined to be within the effective comparison time window, and the time node of the up-down counter is stopped; init _ set _ clk, init _ set, init _ hold, up, down, reset are global control signals, D <3:0> is an initial value to be assigned, each stage of count _ out is the output of a counter of each stage, and each stage of clkout is the clock excitation of the next stage.
If the up-down counter is a 13-bit counter, the up-down counter is assigned with an initial value D<3:0>2Last (10 system X)10) It is possible to ensure that the counter does not count to 0 or 8191 limits by controlling the length of the time window for the first and second comparisons. Taking the first count down count and the second count up count as an example, taking the first comparison time window as T1 as an example, the period of the current counter is Tclk(s), that is, the counter value is decreased by one every Tclk time, and this period is multiplied by the slope K (V/s) of the ramp generator, so as to obtain the LSB (Least Significant Bit) size of the ramp ADC as Tclk K. The digital correlation double sampling noise reduction method of the ramp ADC needs to ensure that in a comparison time window, the output of the comparator needs to be capable of being inverted to obtain effective channel level information, and the condition that the output of the comparator is inverted is as follows:
Vramp_rst+T1*K>Vcom_comp
after the range of T1 is determined, the value of the first count-down is T1/Tclk, and only by ensuring that the X of the first assignment is larger than T1/Tclk, the limit value of 0 can not be triggered during the count-down.
In the limit, the time required for the first comparison is very short, the value kept by the counter after the first counting is finished is slightly smaller than the initial value X, and the time window T2 during the second counting needs to ensure that T2/Tclk + X is not more than or equal to 8191 to prevent the overflow of 8191, that is:
T2≤(8191-X)*Tclk (1)
in summary, in combination with the above and equation (1), it can be derived that the initial value of the up-down counter satisfies:
(2n-1)-T2/Tclk≥X>T1/Tclk； (2)
wherein X is the initial value, Tclk is the clock cycle of the up-down counter, T1 is the first count window time, T2 is the second count window time, 2n-1 is the unit duty cycle of the up-down counter at the ramp ADCThe maximum value of the inner count. Setting the initial value to satisfy equation (2) ensures that the final result of the up-down counter will not reach the limit boundaries of 0 and 8191.
As can be seen by comparing fig. 8 and fig. 1, the up-down counter embodiment described above with respect to fig. 8 differs from the up-down counter embodiment described with respect to fig. 1 in that the ramp ADC as used in the present application comprises an input for receiving an initial value from which the up-down counter counts up or down. When the first counting window and the second counting window in the unit working period of the ramp ADC are used, the counting directions of the up-down counter are opposite, and the counting values are continuous.
The type of up-down counter that can be initialized as described in FIG. 8 retains the hold and updown selection modes of the up-down counter described in FIG. 1. However, the up-down counter which can be endowed with the initial value is internally provided with an initial data selection mode selector which can cut off the loop of the output of the holding output selector to the data input end of the D flip-flop. The initial data selection mode selector is controlled by an init _ hold signal, and the other input end of the initial data selection mode selector is connected with initial data to be assigned. And a working mode selector is connected to the joint between each stage, and the selector can be used for switching an initial assignment mode or a normal counting mode. Due to the characteristic of the D flip-flop, the data at the data input end (D) can be read only after the external clock excitation is switched on, and the init _ set _ clk signal input at the input end of the working mode selector provides the external clock excitation required by the initial assignment.
The counters of the up-down counter and each stage of counters can realize the switching of two working modes of an initial assignment mode or a normal counting mode. The up-down counter of the ramp ADC can start to count up or down from the initial value by inputting the initial value externally, and the counting time of the up-down counter is controlled, so that the two times of counting of the up-down counter can be ensured not to trigger the counting to be continued after the limit value of the counting range in one working cycle of the ramp ADC, and therefore, the wrong counting can not be triggered.
In other embodiments, the first direction and the second direction may also be counted in other manners, for example, in an embodiment, the first direction is counted up from the initial value, and the second direction is counted down from the count value of the up-down counter at the end of the first count window, which may be selected according to actual needs. Of course, for such an embodiment, X is set to satisfy the condition of equation (3):
T2/Tclk<X<(2n-1)-T1/Tclk (3)
therefore, the set value of X may also be adaptively adjusted according to different embodiments.
Based on the same invention concept, the utility model also provides a TFT photosensor array reading chip, which is applied to the electronic equipment with a host, and comprises the slope ADC, the temporary storage and a communication interface communicated with the host; wherein the up-down counter comprises a plurality of stages of interconnected single-stage counters, each of the single-stage counters having an initial value input; the host transmits the initial value of the up-down counter to the temporary storage through the communication interface, and the temporary storage sends the initial value to the initial value input end of each single-stage counter in the up-down counter. The register may be a register in a TFT photosensor array readout chip. In other embodiments, the communication interface may be an SPI interface, and in other embodiments, the communication interface may also be an I2C interface or a UART interface, or another type of communication interface suitable for fingerprint data processing, and it should be noted that when different interfaces are used for communication, corresponding communication protocols need to be followed.
To sum up, the utility model discloses following beneficial effect has:
the utility model provides an up-down counter slope ADC for TFT light sensor array outputs the analog and digital conversion of fingerprint signal, sets up the back level of sampling circuit in TFT light sensor array reads out the chip, the slope ADC includes slope generator, comparator, up-down counter and data latch output, up-down counter, be used for with the output of comparator is connected, and sets for the initial value; a data latch output for receiving the output of the up-down counter and outputting a converted digital signal; wherein, a working period of the ramp ADC comprises a first counting window and a second counting window; the up-down counter starts counting from an initial value to a first direction in the first counting window; and in the second counting window, the up-down counter starts counting towards a second direction by the counting value at the end of the first counting window, and the counting directions of the first direction and the second direction are opposite. The technical scheme of the utility model in the up-down counter has increased the input of accepting the initial value, the up-down counter can by the initial value upwards or begins the count downwards, can pass through external input initial value, from this up-down counter can begin count upwards or count downwards from the initial value, through the time of controlling the count of the up-down counter, can guarantee that the twice count of up-down counter can not trigger and continue to count behind the boundary value of count scope, consequently, can not trigger the wrong count.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.
Claims (10)
1. The utility model provides a slope ADC for the analog and digital conversion of TFT photosensor array output fingerprint signal sets up the poststage of sampling circuit in TFT photosensor array reading chip, its characterized in that, the slope ADC includes:
a ramp generator for outputting a ramp signal;
a comparator, a first input end of which is used for receiving the ramp signal, and a second input end of which receives the sampling signal output by the sampling circuit;
the up-down counter is used for being connected with the output end of the comparator and setting an initial value;
a data latch output for receiving the output of the up-down counter and outputting a converted digital signal;
wherein, a working period of the ramp ADC comprises a first counting window and a second counting window;
the up-down counter starts counting from an initial value to a first direction in the first counting window;
and in the second counting window, the up-down counter starts counting towards a second direction by the counting value at the end of the first counting window, and the counting directions of the first direction and the second direction are opposite.
2. The ramp ADC of claim 1, wherein the first direction is counting down from the initial value and the second direction is counting up from the up-down counter by a count value at the end of the first count window.
3. The ramp ADC of claim 2, wherein the initial value of the up-down counter satisfies the following equation:
(2n-1)-T2/Tclk≥X>T1/Tclk；
wherein X is the initial value, Tclk is the clock period of the up-down counter, and T1 is the firstThe count window time, T2, is the second count window time, 2n-1 is the maximum value that the up-down counter can count within a unit duty cycle of the ramp ADC, and n is a natural number.
4. The ramp ADC of claim 1, wherein said up-down counter comprises a plurality of interconnected single-stage counters and a mode selector;
each single-stage counter is connected with each other through the mode selector, wherein each single-stage counter is provided with an initial value input end and an initial control signal for correspondingly controlling whether the initial value is assigned or not.
5. The ramp ADC of claim 4, wherein each stage of said single stage counter comprises an initial data selection mode selector, a flip-flop, and a flip-flop output selector;
an input terminal of the initial data mode selector is an initial value input terminal of the up-down counter, and the initial data mode selector is controlled by an initial control signal.
6. The ramp ADC of claim 5, wherein said flip-flop output selector comprises a hold output selector and a count up and count down selector;
the input end of the holding output selector is connected with the output of the trigger, the output end of the holding output selector is connected with one input end of the initial data selection mode selector, and the enable signal of the holding output selector is controlled by a counter holding signal;
the input end of the up-down counting selector is connected with the output end of the trigger, and the output end of the up-down counting selector is used as one of the output ends of the corresponding single-stage counter.
7. The ramp ADC of claim 4, wherein the input signal at one input terminal of the mode selector is one of the output signals of the pre-stage flip-flop circuit, the input signal at the other input terminal of the mode selector is an initial setting clock signal, and the enable signal of the operation mode selector is controlled by the initial setting signal.
8. The ramp ADC of claim 4, wherein said up-down counter further comprises a logic gate circuit;
the logic gate circuit is used for receiving the output of the comparator, and the output of the logic gate circuit is connected with the input end of the mode selector.
9. A TFT photosensor array readout chip for an electronic device with a host, comprising the ramp ADC of claim 1, a register, and a communication interface for communicating with the host;
wherein the up-down counter comprises a plurality of stages of interconnected single-stage counters, each of the single-stage counters having an initial value input;
the host transmits the initial value of the up-down counter to the temporary storage through the communication interface, and the temporary storage sends the initial value to the initial value input end of each single-stage counter in the up-down counter.
10. The TFT photosensor array readout chip of claim 9 wherein said communication interface comprises an SPI interface.
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| CN114374809A (en) * | 2022-01-07 | 2022-04-19 | 电子科技大学 | Analog-to-digital conversion circuit of infrared focal plane reading circuit |
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