WO2022213539A1 - 一种大规模mimo系统的仿真测试系统 - Google Patents

一种大规模mimo系统的仿真测试系统 Download PDF

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WO2022213539A1
WO2022213539A1 PCT/CN2021/116660 CN2021116660W WO2022213539A1 WO 2022213539 A1 WO2022213539 A1 WO 2022213539A1 CN 2021116660 W CN2021116660 W CN 2021116660W WO 2022213539 A1 WO2022213539 A1 WO 2022213539A1
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pcie
sub
chassis
pcie chassis
antenna data
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PCT/CN2021/116660
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French (fr)
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曾捷
粟欣
韩莹
李红鑫
骆杰
周世东
赵明
钟晓峰
许希斌
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清华大学
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/30—Monitoring; Testing of propagation channels
    • H04B17/391—Modelling the propagation channel
    • H04B17/3912—Simulation models, e.g. distribution of spectral power density or received signal strength indicator [RSSI] for a given geographic region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems

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  • the present invention claims the priority of the Chinese patent application with the application number 202110376432.2 and the title of the invention "A simulation test system for a massive MIMO system" submitted to the Chinese Patent Office on April 6, 2021, the entire content of which is by reference Incorporated in the present invention.
  • the present application relates to the field of wireless communication technologies, and in particular, to a simulation test system for a massive MIMO system.
  • MIMO Multiple Input Multiple Output
  • S. Sun et al. built a MIMO system in the millimeter-wave environment, analyzed the channel characteristics of the millimeter-wave environment, and made a detailed evaluation of the cell and user spectral efficiency.
  • Ove Edfors et al. developed a massive MIMO system LuMaMi based on the National Instruments (NI, national instruments) hardware platform.
  • Shepard C et al. developed Arogs, a prototyping system for massive MIMO beamforming.
  • Embodiments of the present invention provide a simulation test system for a massive MIMO system, which is used to solve the problem that the simulation test systems in the prior art are all for the simulation test of the MIMO system, but lack the simulation test for the massive MIMO system.
  • a simulation test system for a massive MIMO system including a universal software radio peripheral USRP, a high-speed serial computer expansion bus standard PCIe chassis and a high-performance general-purpose processor, wherein: the PCIe chassis includes a plurality of main PCIe chassis and Multiple sub-PCIe chassis, one main PCIe chassis is connected with multiple sub-PCIe chassis, and one sub-PCIe chassis is connected with multiple USRPs; the USRP is used for collecting antenna data, and sending the collected antenna data to a device connected to the USRP.
  • a sub PCIe chassis is used to collect the received antenna data, and send the collected antenna data to the main PCIe chassis connected to it; the main PCIe chassis is used to collect the received antenna data, and will be collected
  • the received antenna data is sent to the high-performance general-purpose processor connected to it, so that the high-performance general-purpose processor processes the received antenna data to obtain a processed baseband signal.
  • the simulation test system of the massive MIMO system includes a universal software radio peripheral USRP, a high-speed serial computer expansion bus standard PCIe chassis, and a high-performance general-purpose processor, wherein: the PCIe chassis includes a plurality of main PCIe chassis and Multiple sub-PCIe chassis, one main PCIe chassis is connected with multiple sub-PCIe chassis, and one sub-PCIe chassis is connected with multiple USRPs; the USRP is used to collect antenna data, and send the collected antenna data to the sub-PCIe connected to the USRP Chassis; the sub PCIe chassis is used to collect the received antenna data and send the collected antenna data to the main PCIe chassis connected to it; the main PCIe chassis is used to collect the received antenna data and send the collected antenna data to it A high-performance general-purpose processor is connected, so that the high-performance general-purpose processor processes the received antenna data to obtain a processed baseband signal.
  • the PCIe chassis includes a plurality of main PCIe chassis and Multiple sub-PCIe chassis,
  • one sub PCIe chassis can be connected with multiple USRPs, and one main PCIe chassis can be connected with multiple sub PCIe chassis, the connection of the USRP is expanded, and the connection problem of the large-scale USRP for the massive MIMO system is solved.
  • a high-performance general-purpose processor is used to process a large amount of aggregated antenna data, which improves the data processing efficiency of the system.
  • FIG. 1 is a schematic structural diagram of a simulation test system of a massive MIMO system according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of uplink data processing in a simulation test system for a massive MIMO system provided by an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of downlink data processing in a simulation test system of a massive MIMO system according to an embodiment of the present invention.
  • Embodiments of the present application provide a simulation test system for a massive MIMO system, because a sub PCIe chassis can be connected to multiple universal software radio peripherals (Universal Software Radio Peripheral, USRP), and a main PCIe chassis can be connected to multiple sub
  • the PCIe chassis connection extends the connection of USRP and solves the connection problem of massive USRP for massive MIMO systems.
  • a high-performance general-purpose processor is used to process a large amount of aggregated antenna data, which improves the data processing efficiency of the system.
  • FIG. 1 a schematic structural diagram of a simulation test system for a massive MIMO system provided by one or more embodiments of this specification is shown in Figure 1, including a universal software radio peripheral USRP 130, a high-speed serial computer expansion bus standard PCIe chassis 120 and a high-performance general-purpose processor 110, among others.
  • the PCIe chassis 120 includes multiple main PCIe chassis and multiple sub PCIe chassis, one main PCIe chassis is connected with multiple sub PCIe chassis, and one sub PCIe chassis is connected with multiple USRPs; the USRP 130 is used for collecting antenna data, and The collected antenna data is sent to the sub-PCIe chassis connected with the USRP; the sub-PCIe chassis is used to collect the received antenna data, and send the collected antenna data to the main PCIe chassis connected to it; the main PCIe chassis The chassis is used for collecting the received antenna data, and sending the collected antenna data to the high-performance general-purpose processor 110 connected to it, so that the high-performance general-purpose processor 110 processes the received antenna data, and after processing baseband signal.
  • the amount of calculation is greatly increased compared to the TU channel commonly used in 4G.
  • the number of FFT transformations for 3D channels in a cell is about M ⁇ Nt ⁇ Nr (the number of OFDM symbols is M, the number of receiving antennas is Nr, and the base station The number of antennas Nt), when the antenna scale is downlink 256 ⁇ 15, compared with the existing antenna scale, the calculation amount will increase linearly with the product of the number of transmit antennas and receive antennas.
  • the embodiment of the present invention adopts a high-performance general-purpose processor 110 to process the received antenna data to obtain a processed baseband signal.
  • the channel calculation can be completed by the high-performance general-purpose processor in advance, and the calculation results can be saved in the hard disk of the high-performance general-purpose processor.
  • the simulation system is initialized, the channel matrix stored in the hard disk can be directly read and stored in the memory. There is no need to calculate the channel matrix during the running of the simulation program, and the pre-calculated results are directly used, which saves the channel calculation time. If the memory is large enough, the actual time overhead only depends on the time to read the memory, and the channel calculation time is can be ignored.
  • the precoding at the transmitter mainly involves the multiplication and inversion of large matrices
  • this part of the calculation can make full use of the multi-core computing capabilities of the CPU and GPU in the high-performance general-purpose processor to perform parallel computing at the subcarrier level.
  • the joint parallel computing of CPU and GPU is adopted, and parallel computing is performed on the granularity of sub-carriers, the maximum parallel C ⁇ Nc (the cell in the system is C, and the number of subcarriers is NC) paths.
  • the USRP 130 is configured to: send the collected antenna data to a sub-PCIe chassis connected to the USRP through a Common Public Radio Interface (Common Public Radio Interface, CPRI) protocol.
  • CPRI Common Public Radio Interface
  • the sub-PCIe chassis is configured to: send the collected antenna data to the main PCIe chassis connected thereto through the CPRI protocol.
  • the main PCIe chassis is configured to: send the collected antenna data to a high-performance general-purpose processor connected thereto through a CPRI protocol.
  • the main PCIe chassis is connected to the high-performance general-purpose processor through a PCIe slot provided by the high-performance general-purpose processor.
  • an open air interface (Open Air Interface, OAI) platform is built in the high-performance general-purpose processor 110, and the OAI platform is used to process the received antenna data to obtain a processed baseband signal.
  • OAI Open Air Interface
  • the OAI platform is an open source software project initiated by the French Eurecom organization. It provides the world's first complete 3GPP protocol stack implemented in software, and is also one of the relatively complete open source software-defined radio communication methods.
  • the OAI platform can fully realize the functions of the core network, base station and user of the LTE protocol. Combined with a high-performance general-purpose processor and USRP, it can realize the simulation test of a massive MIMO system.
  • the PCIe chassis 120 includes multiple main PCIe chassis and multiple sub PCIe chassis, one main PCIe chassis is connected to 4 sub PCIe chassis, and one sub PCIe chassis is connected to 16 USRPs at most.
  • a PCIe chassis can include 2 main PCIe chassis and 8 sub PCIe chassis, one main PCIe chassis can be connected with 4 sub PCIe chassis, one sub PCIe chassis can be connected with 16 USRPs, and one USRP can include two antenna array.
  • the main PCIe1 chassis and the main PCIe2 chassis are connected to the high-performance general-purpose processor through PCIe slots provided by the high-performance general-purpose processor.
  • the main PCIe1 chassis is connected to the sub PCIe1 to sub PCIe4 chassis, and the main PCIe2 chassis is connected to the sub PCIe5 to sub PCIe8 chassis.
  • the sub-PCIe1 chassis is connected to USRP 2 ⁇ 2(1) ⁇ USRP 2 ⁇ 2(16),..., the sub-PCIe8 chassis is connected to USRP 2 ⁇ 2(113) ⁇ USRP 2 ⁇ 2(128).
  • Each USRP includes two antenna arrays.
  • the number of sub PCIe chassis connected to the multiple main PCIe chassis is consistent; or, the number of sub PCIe chassis connected to the multiple main PCIe chassis is inconsistent.
  • the high-performance general-purpose processor is connected to the multiple main PCIe chassis through a PCIe standard interface.
  • a sub-PCIe chassis is optically connected to up to 16 USRPs.
  • the user sends the pilot sequence and data information on the uplink; then, the base station uses the received pilot information and the locally stored The pilot sequence performs uplink channel estimation and demodulates uplink data, and then uses the calculated downlink precoding matrix to perform downlink pilot transmission and data transmission.
  • TDD Time Division Duplexing
  • FIG. 2 is a schematic flowchart of uplink data processing in a simulation test system of a massive MIMO system according to an embodiment of the present invention.
  • the received data will first be aggregated to the antenna combining module, and then passed to the bandwidth splitting module by the antenna combining module for data splitting.
  • the bandwidth of the received data can be allocated to
  • the channel estimation module of each subsystem performs channel estimation according to the data received from the bandwidth splitting module, and transmits the estimated channel information to the MIMO detection module for use. detection of user data.
  • the user can use the locally generated pilot sequence to generate the pilot, and insert the pilot into the time-frequency resource grid according to the determined pilot insertion method, and then use the OFDM Modulation, up-conversion, DAC and other modules are converted from baseband signals to radio frequency signals, and finally sent to the wireless channel through the antenna.
  • the information bit stream that the user needs to send is first modulated by the M-QAM modulation module, followed by resource mapping, OFDM modulation, up-conversion, and DAC, and finally sent to the channel through the radio frequency antenna.
  • the base station first collects the RF signal through the ADC, performs digital down-conversion and OFDM demodulation on the collected RF signal, then selects the corresponding channel estimation algorithm for channel estimation, and then transmits the data through the channel equalization module and QAM demodulation detected.
  • FIG. 3 is a schematic flowchart of downlink data processing in a simulation test system of a massive MIMO system according to an embodiment of the present invention.
  • the data to be sent is first transmitted by the controller to the MIMO precoding module, and the MIMO precoding module precodes the data according to the information of the channel estimation module and the radio frequency channel calibration module,
  • the encoded data is passed to the bandwidth combining module to combine the bandwidth data processed by other subsystems to form the whole bandwidth data, and finally the whole bandwidth data will be sent to the antenna splitting module to realize that the data to be sent is distributed to each actual physical device. antenna to transmit.
  • the data bit stream generated by the base station and sent to multiple users is first modulated by the QAM modulation module, and then the modulated symbols are precoded according to the estimated uplink channel and channel reciprocity, and then the precoding
  • the coded symbols are subjected to OFDM modulation and radio frequency channel calibration, and the corrected data is then sent to each radio frequency channel for up-conversion, and finally sent out through the antenna.
  • the user converts the collected RF signal into a baseband signal through ADC and down-conversion, and performs OFDM demodulation on the obtained baseband signal, and then uses the received pilot signal and the locally stored pilot sequence to analyze the downlink channel.
  • Estimate, and finally the current user performs equalization and interference cancellation on the data based on the obtained downlink channel information (because the space division multiple access method is adopted and the transmission of downlink data is for multiple users, and multiple users share the same time-frequency resources, so other users
  • the signal will cause interference to the current user's signal) to restore the data signal sent by the base station.
  • the simulation test system of the massive MIMO system includes a universal software radio peripheral USRP, a high-speed serial computer expansion bus standard PCIe chassis, and a high-performance general-purpose processor, wherein: the PCIe chassis includes a plurality of main PCIe chassis and Multiple sub-PCIe chassis, one main PCIe chassis is connected with multiple sub-PCIe chassis, and one sub-PCIe chassis is connected with multiple USRPs; the USRP is used to collect antenna data, and send the collected antenna data to the sub-PCIe connected to the USRP Chassis; the sub PCIe chassis is used to collect the received antenna data and send the collected antenna data to the main PCIe chassis connected to it; the main PCIe chassis is used to collect the received antenna data and send the collected antenna data to it A high-performance general-purpose processor is connected, so that the high-performance general-purpose processor processes the received antenna data to obtain a processed baseband signal.
  • the PCIe chassis includes a plurality of main PCIe chassis and Multiple sub-PCIe chassis,
  • a typical implementation device is a computer.
  • the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or A combination of any of these devices.
  • Computer-readable media includes both persistent and non-permanent, removable and non-removable media, and storage of information may be implemented by any method or technology.
  • Information may be computer readable instructions, data structures, modules of programs, or other data.
  • Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cartridges, magnetic tape disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
  • computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

Abstract

本申请公开了一种大规模MIMO系统的仿真测试系统，该系统包括通用软件无线电外设USRP、高速串行计算机扩展总线标准PCIe机箱和高性能通用处理器，其中：所述PCIe机箱包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与多个子PCIe机箱连接，一个子PCIe机箱与多个USRP连接；所述USRP用于采集天线数据，以及将采集到的天线数据发送给与所述USRP连接的子PCIe机箱；所述子PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的主PCIe机箱；所述主PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的高性能通用处理器，以使得所述高性能通用处理器对接收到的天线数据进行处理，得到处理后的基带信号。

Description

一种大规模MIMO系统的仿真测试系统
交叉引用
本发明要求在2021年04月06日提交中国专利局、申请号为202110376432.2、发明名称为“一种大规模MIMO系统的仿真测试系统”的中国专利申请的优先权，该申请的全部内容通过引用结合在本发明中。
技术领域
本申请涉及无线通信技术领域，尤其涉及一种大规模MIMO系统的仿真测试系统。
背景技术
一些实例中，已经有不少研究致力于构建多输入多输出(Multiple Input Multiple Output，MIMO)和大规模MIMO系统的测试评估平台。S.Sun等人搭建了毫米波环境下的MIMO系统，分析毫米波环境的信道特征，对小区和用户频谱效率进行了详尽的评估。Ove Edfors等人基于美国国家仪器公司(NI,national instruments)硬件平台开发了大规模MIMO系统LuMaMi。Shepard C等人开发了用于大规模MIMO波束成形的原型验证系统Arogs。
然而，上述平台关于大规模MIMO的研究软件层面上并不开放，且硬件设备昂贵，具有较高的门槛，可扩展性差。基于此，法国Eurecom组织发起了开源软件项目开放空中接口(OpenAirInterface，OAI)，用软件仿真的方法实现了完整的3GPP协议栈，OAI是目前最为完善的开源软件定义无线电(SDR，Software Define Radio)平台之一。Y.Yang等人在OAI的基础上开发了Open 5G通用平台，实现了MIMO并行信道和空中接口测试。
但上述这些平台都是针对MIMO系统的仿真测试，而对于大规模MIMO系统的仿真测试，仍未给出相应的仿真测试方法。
发明内容
本发明实施例提供一种大规模MIMO系统的仿真测试系统，用于解决现有技术中仿真测试系统都是针对MIMO系统的仿真测试，而缺乏对大规模MIMO系统的仿真测试的问题。
本发明实施例采用下述技术方案：
提出了一种大规模MIMO系统的仿真测试系统，包括通用软件无线电外设USRP、高速串行计算机扩展总线标准PCIe机箱和高性能通用处理器，其中：所述PCIe机箱包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与多个子PCIe机箱连接，一个子PCIe机箱与多个USRP连接；所述USRP用于采集天线数据，以及将采集到的天线数据发送给与所述USRP连接的子PCIe机箱；所述子PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的主PCIe机箱；所述主PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的高性能通用处理器，以使得所述高性能通用处理器对接收到的天线数据进行处理，得到处理后的基带信号。
本发明实施例采用的上述至少一个技术方案能够达到以下有益效果：
本发明实施例提供的大规模MIMO系统的仿真测试系统，包括通用软件无线电外设USRP、高速串行计算机扩展总线标准PCIe机箱和高性能通用处理器，其中：PCIe机箱包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与多个子PCIe机箱连接，一个子PCIe机箱与多个USRP连接；USRP用于采集天线数据，以及将采集到的天线数据发送给与所述USRP连接的子PCIe机箱；子PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的主PCIe机箱；主PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的高性能通用处理器，以使得所述高性能通用处理器对接收到的天线数据进行处理，得到处理后的基带信号。由于能够通过一个子PCIe机箱与多个USRP连接，以及通过一个主PCIe机箱 与多个子PCIe机箱连接，扩展了USRP的连接，解决了针对大规模MIMO系统的大规模USRP的连接问题。此外通过高性能通用处理器对汇聚的大量天线数据进行处理，提高了系统的数据处理效率。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本发明实施例提供的一种大规模MIMO系统的仿真测试系统的结构示意图；
图2为本发明实施例提供的大规模MIMO系统的仿真测试系统中的上行链路的数据处理流程示意图；
图3为本发明实施例提供的大规模MIMO系统的仿真测试系统中的下行链路的数据处理流程示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施例及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
以下结合附图，详细说明本发明各实施例提供的技术方案。
本申请实施例提供一种大规模MIMO系统的仿真测试系统，由于能够通过一个子PCIe机箱与多个通用软件无线电外设(Universal Software Radio Peripheral，USRP)连接，以及通过一个主PCIe机箱与多个子PCIe机箱连接，扩展了USRP的连接，解决了针对大规模MIMO系统的大规模USRP的 连接问题。此外通过高性能通用处理器对汇聚的大量天线数据进行处理，提高了系统的数据处理效率。
具体地，本说明书一个或多个实施例提供的一种大规模MIMO系统的仿真测试系统的结构示意图如图1所示，包括通用软件无线电外设USRP 130、高速串行计算机扩展总线标准PCIe机箱120和高性能通用处理器110，其中。
所述PCIe机箱120包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与多个子PCIe机箱连接，一个子PCIe机箱与多个USRP连接；所述USRP 130用于采集天线数据，以及将采集到的天线数据发送给与所述USRP连接的子PCIe机箱；所述子PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的主PCIe机箱；所述主PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的高性能通用处理器110，以使得所述高性能通用处理器110对接收到的天线数据进行处理，得到处理后的基带信号。
应理解，在大规模MIMO系统中，由于发射和接受天线数量相比4G有明显增加，并且天线、信道参数模型也较为复杂，因此计算量相比4G常用的TU信道有巨大增加。例如，仅以时域信道转为频域信道的FFT变换计算次数来分析，一个小区的3D信道FFT变换的数量约为M×Nt×Nr(OFDM符号数为M，接收天线数为Nr，基站天线数Nt)，则在天线规模为下行256×15的情况下，相比现有的天线规模，计算量将会随发射天线和接收天线数的乘积线性增加。
本发明实施例为了解决这一问题，采用高性能通用处理器110对接收到的天线数据进行处理，得到处理后的基带信号。在给定仿真参数的条件下，由于无线链路信道系数和系统调节等行为无关，因此可以预先由高性能通用处理器完成信道计算，并将计算结果保存在高性能通用处理器的硬盘中，仿真系统初始化时可以直接读取保存在硬盘中的信道矩阵，并储存在内存中。在仿真程序运行过程中就不必计算信道矩阵，直接使用预先计算好的结果， 这样就省去信道计算时间，如果内存足够大，则实际时间开销仅仅取决于读取内存的时间，信道计算时间则可以忽略不计。
由于发射端预编码主要涉及大矩阵的乘法和求逆计算，这部分计算可以充分利用高性能通用处理器中CPU和GPU的多核计算能力，在子载波层次进行并行计算。首先利用高性能通用处理器中CPU的并行计算能力，在子载波粒度做并行化处理，将不同子载波的预编码计算工作分配到高性能通用处理器中不同的CPU板卡(比如分别分配给图1中的CPU1～CPU4)上进行并行计算，由每个GPU完成矩阵求逆合乘法计算，由于采用CPU和GPU的联合并行计算，并且在子载波的粒度上进行并行计算，最大可以并行C×Nc(系统内小区为C，子载波数位NC)路。
对于大规模MIMO系统的信干噪比计算，主要是向量乘法运算，计算量相对信道计算、发射端预编码模块小得多，因此可以采用高性能通用处理器中CPU加速便能够获得较好的效果。
可选地，所述USRP 130，用于：将采集到的天线数据通过通用公共无线接口(Common Public Radio Interface，CPRI)协议发送给与所述USRP连接的子PCIe机箱。
可选地，所述子PCIe机箱，用于：将收集的天线数据通过CPRI协议发送给与其连接的主PCIe机箱。
可选地，所述主PCIe机箱，用于：将收集的天线数据通过CPRI协议发送给与其连接的高性能通用处理器。
其中，主PCIe机箱通过高性能通用处理器提供的PCIe插槽与高性能通用处理器连接。
可选地，所述高性能通用处理器110中搭建了开放空中接口(Open Air Interface，OAI)平台，所述OAI平台用于对接收到的天线数据进行处理，得到处理后的基带信号。
其中，OAI平台是由法国Eurecom组织发起的开源软件项目，它提供了 世界上首个以软件实现完整的3GPP的协议栈，也是目前较为完善的开源软件定义无线电通信方法之一。OAI平台能够完整实现LTE协议的核心网、基站和用户三部分的功能，结合高性能通用处理器和USRP，可实现大规模MIMO系统的仿真测试。
可选地，所述PCIe机箱120包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与4个子PCIe机箱连接，一个子PCIe机箱最多与16个USRP连接。
如图1所示，PCIe机箱可包括2个主PCIe机箱和8个子PCIe机箱，一个主PCIe机箱可与4个子PCIe机箱连接，一个子PCIe机箱可与16个USRP连接，一个USRP可包括两个天线阵列。其中，主PCIe1机箱和主PCIe2机箱通过高性能通用处理器提供的PCIe插槽与高性能通用处理器连接。主PCIe1机箱与子PCIe1机箱～子PCIe4机箱连接，主PCIe2机箱与子PCIe5机箱～子PCIe8机箱连接。子PCIe1机箱与USRP 2×2(1)～USRP 2×2(16)连接，……，子PCIe8机箱与USRP 2×2(113)～USRP 2×2(128)连接。每个USRP包括两个天线阵列。
可选地，在实际应用中，与所述多个主PCIe机箱连接的子PCIe机箱的数量是一致的；或者，与所述多个主PCIe机箱连接的子PCIe机箱的数量是不一致的。
可选地，所述高性能通用处理器与所述多个主PCIe机箱通过PCIe标准接口连接。
可选地，一个子PCIe机箱最多与16个USRP通过光纤连接。
在时分双工(Time Division Duplexing，TDD)大规模MIMO系统的数据传输过程中，首先，用户在上行链路发送导频序列和数据信息；然后，基站利用接收到的导频信息和本地储存的导频序列进行上行信道估计并解调上行数据，再利用计算出的下行预编码矩阵进行下行链路的导频传输和数据传输。
图2为本发明实施例提供的大规模MIMO系统的仿真测试系统中的上行链路的数据处理流程示意图。在图2中，对于上行链路，接收到的数据首先会汇聚到天线合并模块，然后由天线合并模块传递给带宽拆分模块进行数据的拆分，具体可将接收到的数据的带宽分配给与接收到的数据的带宽相对应的子系统中，各子系统的信道估计模块根据接收到来自带宽拆分模块的数据后进行信道估计，并将估计出的信道信息传递给MIMO检测模块以用于用户数据的检测。
在发送端，如果当前发送的是导频符号，用户可以利用在本地生成的导频序列产生导频，并按照确定的导频插入方式将导频插入到时频资源网格中，然后利用OFDM调制、上变频、DAC等模块从基带信号变成射频信号，最后通过天线发送到无线信道中。如果当前发送的是数据符号，那么用户需要发送的信息比特流首先经过M-QAM调制模块进行调制，然后进行资源映射、OFDM调制、上变频、DAC，最后通过射频天线送入信道。
在接收端，基站首先通过ADC采集射频信号，将采集到的射频信号进行数字下变频及OFDM解调，然后选择相应的信道估计算法进行信道估计，再经过信道均衡模块和QAM解调将发送数据检测出来。
图3为本发明实施例提供的大规模MIMO系统的仿真测试系统中的下行链路的数据处理流程示意图。在图3中，对于下行链路，要发送的数据首先由控制器传送给MIMO预编码模块，MIMO预编码模块根据信道估计模块和射频通道校准模块的信息对数据进行预编码后，将已预编码的数据传递给带宽合并模块，以合并其他子系统所处理的带宽数据从而形成整带宽数据，最后整带宽数据将被传送给天线拆分模块以实现所要发送的数据被分配给各个实际的物理天线进行发送。
在发送端，基站产生的用于发送给多个用户的数据比特流先经过QAM调制模块进行调制，接着根据估计出的上行信道以及信道互易性对调制后的符号进行预编码，然后对预编码后的符号进行OFDM调制和射频信道校准， 校正过后的数据再被送入各个射频信道进行上变频，最后通过天线发送出去。
在接收端，用户通过ADC和下变频将采集到的射频信号转换为基带信号，并对得到的基带信号进行OFDM解调，然后利用接收到的导频信号与本地存储的导频序列对下行信道进行估计，最后当前用户基于得到的下行信道信息对数据进行均衡和干扰消除(由于采用空分多址方式且下行数据的传输是面向多个用户，多个用户共享同一时频资源，所以其他用户的信号会对当前用户的信号造成干扰)还原出基站端发送的数据信号。
本发明实施例提供的大规模MIMO系统的仿真测试系统，包括通用软件无线电外设USRP、高速串行计算机扩展总线标准PCIe机箱和高性能通用处理器，其中：PCIe机箱包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与多个子PCIe机箱连接，一个子PCIe机箱与多个USRP连接；USRP用于采集天线数据，以及将采集到的天线数据发送给与所述USRP连接的子PCIe机箱；子PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的主PCIe机箱；主PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的高性能通用处理器，以使得所述高性能通用处理器对接收到的天线数据进行处理，得到处理后的基带信号。由于能够通过一个子PCIe机箱与多个USRP连接，以及通过一个主PCIe机箱与多个子PCIe机箱连接，扩展了USRP的连接，解决了针对大规模MIMO系统的大规模USRP的连接问题。此外通过高性能通用处理器对汇聚的大量天线数据进行处理，提高了系统的数据处理效率。
总之，以上所述仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算 机。具体的，计算机例如可以为个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任何设备的组合。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。

Claims (9)

  1. 一种大规模MIMO系统的仿真测试系统，其中，包括通用软件无线电外设USRP、高速串行计算机扩展总线标准PCIe机箱和高性能通用处理器，其中：
    所述PCIe机箱包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与多个子PCIe机箱连接，一个子PCIe机箱与多个USRP连接；
    所述USRP用于采集天线数据，以及将采集到的天线数据发送给与所述USRP连接的子PCIe机箱；
    所述子PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的主PCIe机箱；
    所述主PCIe机箱用于收集接收到的天线数据，以及将收集的天线数据发送给与其连接的高性能通用处理器，以使得所述高性能通用处理器对接收到的天线数据进行处理，得到处理后的基带信号。
  2. 如权利要求1所述的系统，其中，所述USRP，用于：
    将采集到的天线数据通过通用公共无线接口CPRI协议发送给与所述USRP连接的子PCIe机箱。
  3. 如权利要求1所述的系统，其中，所述子PCIe机箱，用于：
    将收集的天线数据通过CPRI协议发送给与其连接的主PCIe机箱。
  4. 如权利要求1所述的系统，其中，所述主PCIe机箱，用于：
    将收集的天线数据通过CPRI协议发送给与其连接的高性能通用处理器。
  5. 如权利要求1所述的系统，其中，所述高性能通用处理器中搭建了开放空中接口OAI平台，所述OAI平台用于对接收到的天线数据进行处理，得到处理后的基带信号。
  6. 如权利要求1所述的系统，其中，所述PCIe机箱包括多个主PCIe机箱和多个子PCIe机箱，一个主PCIe机箱与4个子PCIe机箱连接，一个子PCIe机箱最多与16个USRP连接。
  7. 如权利要求6所述的系统，其中，与所述多个主PCIe机箱连接的子PCIe机箱的数量是一致的；或者
    与所述多个主PCIe机箱连接的子PCIe机箱的数量是不一致的。
  8. 如权利要求6所述的系统，其中，所述高性能通用处理器与所述多个主PCIe机箱通过PCIe标准接口连接。
  9. 如权利要求6所述的系统，其中，一个子PCIe机箱最多与16个USRP通过光纤连接。
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