WO2022206028A1 - 一种基于平行总线的通讯系统 - Google Patents

一种基于平行总线的通讯系统 Download PDF

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Publication number
WO2022206028A1
WO2022206028A1 PCT/CN2021/138224 CN2021138224W WO2022206028A1 WO 2022206028 A1 WO2022206028 A1 WO 2022206028A1 CN 2021138224 W CN2021138224 W CN 2021138224W WO 2022206028 A1 WO2022206028 A1 WO 2022206028A1
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Prior art keywords
electronic devices
parallel bus
communication
chip
communication system
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PCT/CN2021/138224
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English (en)
French (fr)
Inventor
陈栋
刘晓锋
朱宏锋
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纵目科技（上海）股份有限公司
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Priority to JP2024500441A priority Critical patent/JP2024510351A/ja
Priority to US18/549,357 priority patent/US20240045825A1/en
Priority to EP21934664.0A priority patent/EP4290390A1/en
Publication of WO2022206028A1 publication Critical patent/WO2022206028A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention belongs to the field of communication, in particular to a communication system based on a parallel bus.
  • Ultrasonic sensors are sensors that convert ultrasonic signals into other energy signals (usually electrical signals).
  • Ultrasound is a mechanical wave whose vibration frequency is higher than 20kHz. It has the characteristics of high frequency, short wavelength, small diffraction phenomenon, especially good directionality, which can become a ray and propagate in a direction. Ultrasound has a great ability to penetrate liquids and solids, especially in solids that are opaque to sunlight. When the ultrasonic wave encounters impurities or interfaces, it will produce significant reflections to form reflected echoes, and when it encounters moving objects, it can produce Doppler effects. Ultrasonic sensors are widely used in industry, national defense, biomedicine, etc.
  • the communication method between the next-generation ultrasonic sensor and the host adopts the bus communication method.
  • the host needs to have a communication chip that supports the form of parallel bus, and the sensor communicates with the host through the communication chip. data exchange between them.
  • the serial communication method is adopted. This method requires the sensor to have 4 pins, of which 2 pins are used for communication, and the other two pins are the power supply and the ground respectively. Most of the ultrasonic sensors on the market are 3pin, if 4pin is used, it cannot be used in the sensor structure and vehicle wiring harness; secondly, serial communication is used, if one of the sensors is abnormal, other sensors on the same link will be affected.
  • the point-to-point communication method is adopted. This communication method can meet the requirements from the amount of data transmitted and the pin of the sensor, but the number of communication chips required is large, the communication structure is relatively complex, and the communication cost is relatively high. high.
  • the purpose of the present invention is to provide a communication system based on a parallel bus, which is used to solve the technical problems of the prior art that the sensors interact with each other or the communication cost is high when the sensor communicates with the host.
  • an embodiment of the present invention provides a communication system based on a parallel bus, including: a plurality of electronic devices; a host controller configured with a gating chip and a communication chip; wherein: the communication chip At least one channel parallel bus is controlled, and each of the electronic devices is independently connected to the channel parallel bus; the host controller sequentially assigns addresses to each of the electronic devices through the gating chip when powered on for the first time.
  • each of the electronic devices has a power pin, a ground pin and a communication pin.
  • the plurality of electronic devices form at least one group of electronic devices; the communication pins of each electronic device in each group of electronic devices are connected to a corresponding channel parallel bus.
  • the gating chip controls at least one power line, and each power line is correspondingly connected to a power pin of each electronic device in a group of electronic devices.
  • the gating chip controls a power line, and the power line is connected to the power pins of all electronic devices.
  • the host controller controls at least one ground wire, and each ground wire corresponds to a ground pin of each electronic device in at least one group of electronic devices.
  • the host controller controls a ground wire, and the ground wire is connected to the ground pins of all electronic devices.
  • the host controller supplies the power supply pins for the electronics. Device assigned address.
  • each of the electronic devices stores an assigned address, and when communicating with the host controller, the communication data includes the address of the electronic device.
  • the electronic device is an ultrasonic sensor.
  • the communication system based on the parallel bus of the present invention has the following beneficial effects:
  • the communication chip of the communication system adopts the communication mode of the parallel bus, and the address is allocated to each electronic device in turn through the gating chip.
  • the communication function can be realized. They are independent of each other and do not affect each other, and the existing sensor structure and vehicle wiring harness can be used, which has a cost advantage.
  • FIG. 1 is a schematic diagram showing the principle structure of a communication system based on a parallel bus of the present invention.
  • FIG. 2 is a diagram showing an exemplary structure of the communication chip of the parallel bus-based communication system of the present invention when controlling two channels of parallel buses.
  • the purpose of this embodiment is to provide a communication system based on a parallel bus, which is used to solve the technical problems in the prior art that the sensors interact with each other or the communication cost is high when the sensors communicate with the host.
  • this embodiment provides a communication system 100 based on a parallel bus.
  • the communication system 100 based on a parallel bus includes: a host controller 110 and a plurality of electronic devices 120 , and the host controller 110 is configured with The strobe chip 112 and the communication chip 111 .
  • the parallel bus-based communication system 100 is applied but not limited to a parking radar system
  • the host controller 110 is but is not limited to a parking host controller
  • the electronic device 120 is but not limited to Limited to sensors, preferably, the electronic device 120 is an ultrasonic sensor.
  • host controller 110 and the electronic device 120 are not limited to those listed in this embodiment, and any host controller 110 and electronic device in the prior art made according to the principle of the parallel bus-based communication system 100 in this embodiment
  • the modification and replacement of 120 are all included in the protection scope of the parallel bus-based communication system 100 in this embodiment.
  • the communication chip 111 controls at least one channel parallel bus, and each of the electronic devices 120 is independently connected to the channel parallel bus; when the host controller 110 is powered on for the first time, the The gating chip 112 sequentially assigns addresses to the electronic devices 120 .
  • the communication chip 111 can control one channel parallel bus, two channel parallel buses...N channel parallel buses.
  • This embodiment does not limit the number of channel parallel buses controlled by the communication chip 111 .
  • those skilled in the art can configure or select the number of channel parallel buses of the communication chip 111 according to actual needs.
  • FIG. 2 is a diagram showing an exemplary structure of the communication chip 111 of the parallel bus-based communication system of the present invention when controlling two-channel parallel buses.
  • the communication chip 111 has a first channel and a second channel, the first channel lead wire forms the first channel parallel bus 111a, and the second channel lead wire forms the first channel A two-channel parallel bus 111b. Since the communication chip 111 controls two buses, a plurality of electronic devices 120 are connected to the two buses.
  • the communication chip 111 controls the first channel parallel bus 111a and the second channel parallel bus 111b, and each of the electronic devices 120 is independently connected to the first channel parallel bus 111a or all on the second channel parallel bus 111b.
  • the communication chip 111 controls the first channel parallel bus 111a and the second channel parallel bus 111b, and each of the electronic devices 120 is independently connected to the first channel parallel bus 111a or all on the second channel parallel bus 111b.
  • the communication chip 111 of the communication system adopts the bus communication method of a parallel bus composed of a first channel parallel bus 111a and a second channel parallel bus 111b, and each electronic device 120 is independently connected to the communication chip 111. , through the data exchange between the communication chip 111 and the host controller 110 , the electronic devices 120 are independent of each other and do not affect each other.
  • the electronic devices 120 in this embodiment are respectively connected to the communication chip 111 and are independent from each other, the electronic devices 120 have three pins, so that the electronic devices 120 of this embodiment can be used in applications.
  • the existing sensor structure and vehicle wiring harness enhance the applicability of the communication structure and effectively reduce the cost of the communication structure.
  • each of the electronic devices 120 has, but is not limited to, a power pin, a ground pin and a communication pin.
  • the power pin is connected to the gating chip 112, and the power-on and power-off of the power pin is controlled by the gating chip 112; the ground pin is connected to the host controller 110; the The communication pins are connected to the first channel parallel bus 111 a or the second channel parallel bus 111 b of the communication chip 111 .
  • one communication chip 111 can realize the communication between the electronic device 120 and the host controller 110 .
  • the number of the communication chips 111 can be adjusted according to the number of electronic devices 120 and the amount of data to be transmitted.
  • one gating chip 112 can realize gating of the electrical devices, and the number of the gating chips 112 can be adjusted according to the number of electronic devices 120 .
  • the plurality of electronic devices 120 form at least one group of electronic devices; each channel parallel bus is correspondingly connected to the communication pins of each electronic device 120 in a group of electronic devices.
  • the plurality of electronic devices 120 includes a first group of electronic devices and a second group of electrical devices; that is, the plurality of electronic devices 120 are divided into two groups of electronic devices, and one group of electronic devices is connected to the On the first channel parallel bus 111a, another group of electronic devices is connected to the second channel parallel bus 111b.
  • the first channel parallel bus 111a of the communication chip 111 is connected to each communication pin of the plurality of electronic devices 120 in the first group of electronic devices, and the second channel parallel bus 111b of the communication chip 111 is connected to the The communication pins of the plurality of electronic devices 120 in the second group of electronic devices are connected to each other.
  • the communication pins of each electronic device 120 are independently connected to the parallel bus, that is, the communication pins of each electronic device 120 are independently connected to the communication chip 111, so that each electronic device 120 (sensor) is independent of each other, do not affect each other.
  • the purpose of the gating chip 112 is to control the on-off of the power line, thereby controlling whether to supply power to an electronic device 120 .
  • the gating chip 112 is used to control the gating of each electronic device 120, and the electronic device 120 that is gated by the gating chip 112 is powered on. At this time, the electronic device 120 can be controlled by the host controller 110. The gated electronic device 120 is powered off, and the electronic device 120 cannot be controlled by the host controller 110 at this time.
  • the gating chip 112 is connected to each power supply pin of each electronic device 120 respectively, and controls the power supply pin of each electronic device 120 independently. Which electronic device 120 is to be powered is determined by the gating chip 112 .
  • the gating chip 112 controls at least one power line, and each power line is correspondingly connected to the power pins of each electronic device in at least one group of electronic devices.
  • the gating chip 112 controls two power lines: a first power line and a second power line.
  • the first power line is connected to each power supply pin of a plurality of electronic devices 120 in the first group of electronic devices, and is used to control each power supply pin of a plurality of electronic devices 120 in the first group of electronic devices to supply power;
  • the second power line is connected to each power supply pin of the plurality of electronic devices 120 in the second group of electronic devices, and is used to control each power supply pin of the plurality of electronic devices 120 in the second group of electronic devices to supply power.
  • the gating chip 112 may only control one power line, and the power line is connected to the power pins of all the electronic devices 120 .
  • the gating chip 112 only selects one electronic device 120 at a time, and controls the power supply pin of one of the electronic devices 120 to supply power, so that the power supply pin of one electronic device 120 is connected to the power supply, and the other The power pins of each electronic device 120 are powered off.
  • the host controller 110 assigns addresses to the electronic devices 120 powered by the power supply pins.
  • the host controller 110 is connected to the ground pins of the electronic devices 120 respectively, and grounds the ground pins of the electronic devices 120 .
  • the host controller controls at least one ground wire, and each ground wire corresponds to a ground pin of each electronic device in at least one group of electronic devices.
  • the host controller 110 controls the first ground wire and the second ground wire.
  • the first ground wire is connected to the ground pins of the plurality of electronic devices 120 in the first group of electronic devices; the second ground wire is connected to the ground pins of the plurality of electronic devices 120 in the second group of electronic devices All ground pins are connected.
  • the host controller 110 can also control a ground wire, and the ground wire is connected to the ground pins of all the electronic devices 120 .
  • the host controller 110 assigns addresses to each of the electronic devices 120 in sequence through the gating chip 112 when the host controller 110 is powered on for the first time; , and upload the respective addresses to the host controller 110 .
  • the host controller 110 assigns addresses to the electronic devices 120 in sequence through the gating chip 112 when the host controller 110 is powered on for the first time.
  • the connection order (eg, from left to right) sequentially assigns addresses to the electronic devices 120 connected on the channel parallel bus.
  • the communication chip 111 controls a channel parallel bus, and sequentially assigns addresses to the electronic devices 120 connected to the channel parallel bus.
  • the specific allocation process is as follows:
  • the first electronic device 120 on the channel parallel bus is controlled by the gating chip 112 to be powered on, and the remaining electronic devices 120 are powered off.
  • the host controller 110 is on the channel parallel bus.
  • the address is allocated to the first electronic device 120 on the channel parallel bus, and after the address is allocated to the first electronic device 120 on the channel parallel bus, the first electronic device 120 on the channel parallel bus is controlled to be powered off by the gating chip 112,
  • the second electronic device 120 on the channel parallel bus is powered on, and the remaining electronic devices 120 are also powered off, continue to assign addresses to the second electronic device 120 on the channel parallel bus, and repeat the above process until the channel parallel bus is completed. address assignment of all electronic devices 120.
  • the communication chip 111 controls two channel parallel buses: a first channel parallel bus 111a and a second channel parallel bus 111b. First, addresses are allocated to the electronic devices 120 connected to the first channel parallel bus 111a in sequence, and then addresses are sequentially allocated to the electronic devices 120 connected to the second channel parallel bus 111b.
  • addresses are assigned to the electronic devices 120 connected to the parallel bus 111a of the first channel according to the connection order of the electronic devices 120 on the parallel bus 111a of the first channel (eg, from left to right).
  • the connection sequence on the bus 111b (eg, from left to right) sequentially assigns addresses to the electronic devices 120 connected on the second channel parallel bus 111b.
  • the specific allocation process is as follows:
  • the gating chip 112 controls the first electronic device 120 on the first channel parallel bus 111a to be powered on, and the remaining electronic devices 120 are powered off.
  • the first electronic device 120 on the one-channel parallel bus 111a is assigned an address, and after the address is assigned to the first electronic device 120 on the first-channel parallel bus 111a, the gate chip 112 controls the first-channel parallel bus
  • the first electronic device 120 on 111a is powered off, the second electronic device 120 on the first channel parallel bus 111a is powered on, and the remaining electronic devices 120 are also powered off, continuing to be the second electronic device 120 on the first channel parallel bus 111a
  • the electronic device 120 assigns addresses, and the above process is repeated until the address assignment of all the electronic devices 120 on the first channel parallel bus 111a is completed.
  • the gating chip 112 controls the power-on of the first electronic device 120 on the second channel parallel bus 111b, and powers off the remaining electronic devices 120.
  • the host controller 110 is the first electronic device 120 on the second channel parallel bus 111b.
  • An electronic device 120 assigns an address, and after assigning an address to the first electronic device 120 on the second channel parallel bus 111b, controls the first electronic device on the second channel parallel bus 111b through the gating chip 112 120 is powered off, the second electronic device 120 on the second channel parallel bus 111b is powered on, and the remaining electronic devices 120 are also powered off, continue to assign addresses to the second electronic device 120 on the second channel parallel bus 111b, repeat the above process until the address assignment of all the electronic devices 120 on the second channel parallel bus 111b is completed.
  • the electronic device 120 stores the assigned address, and when communicating with the host controller 110, the communication data includes the electronic device 120.
  • the address of device 120 is the address of device 120.
  • the instruction data packet sent by the host controller 110 includes the electronic device 120
  • the response data packet contains each electronic device. 120 address.
  • the vehicle-mounted ultrasonic sensor stores the allocated address through the built-in non-volatile memory, and the host controller 110 sends an instruction for the vehicle-mounted ultrasonic sensor according to the allocated address to realize communication with the vehicle-mounted ultrasonic sensor.
  • the vehicle-mounted ultrasonic sensor that receives the instruction feeds back data to the host controller 110, it uploads its own address, wherein the address of the vehicle-mounted ultrasonic sensor will be packaged into the communication message, so that the host controller 110 can upload the data according to the information uploaded by the vehicle-mounted ultrasonic sensor. address to decode.
  • the communication chip of the communication system adopts the communication mode of the parallel bus, and the address is assigned to each electronic device in turn through the gating chip.
  • the electronic devices (sensors) are independent of each other, and the existing sensor structure and vehicle wiring harness can be used without affecting each other, which has a cost advantage. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

Abstract

本发明提供一种基于平行总线的通讯系统，所述系统包括：多个电子器件；主机控制器，配置有选通芯片和通讯芯片；其中：所述通讯芯片至少控制一条通道平行总线，各所述电子器件分别独立地连接于所述通道平行总线上；所述主机控制器在首次上电时通过所述选通芯片依次为各所述电子器件分配地址。本发明中，通讯系统的通讯芯片采用平行总线的通讯方式，并通过选通芯片依次为各电子器件分配地址，在使用少量通讯芯片的基础上，即可实现通讯功能，各电子器件(传感器)之间相互独立，互不影响可以沿用现有的传感器结构和整车线束，具有成本优势。

Description

一种基于平行总线的通讯系统 技术领域
本发明属于通讯领域，特别是涉及一种基于平行总线的通讯系统。
背景技术
超声波传感器是将超声波信号转换成其他能量信号(通常是电信号)的传感器。超声波是振动频率高于20kHz的机械波。它具有频率高、波长短、绕射现象小，特别是方向性好、能够成为射线而定向传播等特点。超声波对液体、固体的穿透本领很大，尤其是在阳光不透明的固体中。超声波碰到杂质或分界面会产生显著反射形成反射回波，碰到活动物体能产生多普勒效应。超声波传感器广泛应用在工业、国防、生物医学等方面。
为满足功能安全要求和大量传感器原始数据传输的需求，下一代超声波传感器与主机间通讯方式采用总线的通讯方式，该方式主机上需要有对应支持平行总线形式的通讯芯片，传感器通过通讯芯片与主机之间进行数据交互。
目前市面上厂商基于总线通讯采用的主要有两种方式：
1、采用串行通讯方式，这种方式需要传感器有4个pin脚，其中2个pin脚用来进行通讯，另外两个pin脚分别是电源和地，而现有市场上的超声传感器多是3pin，如果采用4pin，在传感器结构和整车线束上无法沿用；其次采用串行通讯方式，如果其中有1颗传感器异常，其他在同一条链路上的传感器都会受到影响。
2、采用点到点(point to point)的通讯方式，这种通讯方式从传输数据量和传感器的pin脚上都可满足需求，但是需要的通讯芯片数量多，通讯结构相对复杂，通讯成本较高。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于平行总线的通讯系统，用于解决现有技术中传感器与主机通讯时各传感器相互影响或者通讯成本高的技术问题。
为实现上述目的及其他相关目的，本发明的实施例提供一种基于平行总线的通讯系统，包括：多个电子器件；主机控制器，配置有选通芯片和通讯芯片；其中：所述通讯芯片至少控制一条通道平行总线，各所述电子器件分别独立地连接于所述通道平行总线上；所述主机控制器在首次上电时通过所述选通芯片依次为各所述电子器件分配地址。
于本申请的一实施例中，每一个所述电子器件具有电源管脚，接地管脚和通讯管脚。
于本申请的一实施例中，所述多个电子器件形成至少一组电子器件；每一组电子器件中 的各电子器件的通讯管脚连接于对应的一条通道平行总线上。
于本申请的一实施例中，所述选通芯片控制至少一条电源线，每一条电源线上对应连接一组电子器件中的各电子器件的电源管脚。
于本申请的一实施例中，所述选通芯片控制一条电源线，该电源线上连接所有电子器件的电源管脚。
于本申请的一实施例中，所述主机控制器控制至少一条地线，每一条地线上对应连接至少一组电子器件中的各电子器件的接地管脚。
于本申请的一实施例中，所述主机控制器控制一条地线，该地线上连接所有电子器件的接地管脚。
于本申请的一实施例中，在所述选通芯片控制其中一个电子器件的电源管脚供电，其余各电子器件的电源管脚断电时，所述主机控制器为电源管脚供电的电子器件分配地址。
于本申请的一实施例中，各所述电子器件存储分配的地址，并在与主机控制器进行通讯时，令通讯数据中包含所述电子器件的地址。
于本申请的一实施例中，所述电子器件超声波传感器。
如上所述，本发明的基于平行总线的通讯系统，具有以下有益效果：
本发明中，通讯系统的通讯芯片采用平行总线的通讯方式，并通过选通芯片依次为各电子器件分配地址，在使用少量通讯芯片的基础上，即可实现通讯功能，各电子器件(传感器)之间相互独立，互不影响可以沿用现有的传感器结构和整车线束，具有成本优势。
附图说明
图1显示为本发明的基于平行总线的通讯系统的原理结构示意图。
图2显示为本发明的基于平行总线的通讯系统的通讯芯片在控制两条通道平行总线时的一种结构示例图。
元件标号说明
100               基于平行总线的通讯系统
110               主机控制器
111               通讯芯片
111a              第一通道平行总线
111b              第二通道平行总线
112               选通芯片
120               电子器件
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
本实施例的目的在于提供一种基于平行总线的通讯系统，用于解决现有技术中传感器与主机通讯时各传感器相互影响或者通讯成本高的问技术问题。
以下将详细阐述本实施例的基于平行总线的通讯系统的原理及实施方式，使本领域技术人员不需要创造性劳动即可理解本发明的基于平行总线的通讯系统。
如图1所示，本实施例提供一种基于平行总线的通讯系统100，所述基于平行总线的通讯系统100包括：主机控制器110和多个电子器件120，所述主机控制器110配置有选通芯片112和通讯芯片111。
其中，于本实施例中，所述基于平行总线的通讯系统100应用但不限于泊车雷达系统，所述主机控制器110为但不限于泊车主机控制器，所述电子器件120为但不限于传感器，优选地，所述电子器件120为超声波传感器。
需要说明的是，主机控制器110和电子器件120不限于本实施例所列举，凡是根据本实施例中基于平行总线的通讯系统100的原理所做的现有技术的主机控制器110和电子器件120的变形和替换，都包括在本实施例中基于平行总线的通讯系统100的保护范围内。
其中，于本实施例中，所述通讯芯片111至少控制一条通道平行总线，各所述电子器件120分别独立地连接于所述通道平行总线上；所述主机控制器110在首次上电时通过所述选通芯片112依次为各所述电子器件120分配地址。
于本实施例中，所述通讯芯片111可以控制一条通道平行总线，两条通道平行总线……N条通道平行总线。本实施例对所述通讯芯片111控制的通道平行总线的数量并不限定。在本实施例的技术原理之下，本领域技术人员可以实际需求进行配置或选取所述通讯芯片111的通道平行总线的数量。
本实施例中以通讯芯片111在控制两条通道平行总线为例进行说明。通信芯片111控制两条以上通道平行总线的技术实现原理不再赘述。图2显示为本发明的基于平行总线的通讯系统的通讯芯片111在控制两条通道平行总线时的一种结构示例图。例如，如图2所示，所 述通讯芯片111具有第一通道和第二通道，所述第一通道引出线形成所述第一通道平行总线111a，所述第二通道引出线形成所述第二通道平行总线111b。由于所述通讯芯片111控制两个总线，多个电子器件120被连接于两个总线上。
具体地，如图2所示，所述通讯芯片111控制第一通道平行总线111a和第二通道平行总线111b，各所述电子器件120分别独立地连接于所述第一通道平行总线111a或所述第二通道平行总线111b上。例如，图2中，多个电子器件120一共有2N个，电子器件N1，电子器件N2……电子器件NN一共N个电子器件120分别独立地连接于第一通道平行总线111a，电子器件M1，电子器件M2……电子器件MN一共N个电子器件120分别独立地连接于第二通道平行总线111b。
本实施例中，通讯系统的通讯芯片111采用由第一通道平行总线111a和第二通道平行总线111b构成的平行总线的总线通讯方式，各电子器件120分别独立地连接于所述通讯芯片111上，通过所述通讯芯片111与所述主机控制器110进行数据交互，各电子器件120之间相互独立，互不影响。
而且本实施例中的电子器件120由于分别与所述通讯芯片111相连，且彼此之间相互独立，所述电子器件120具有3个管脚，使得本实施例的电子器件120在应用中可以沿用现有的传感器结构和整车线束，增强通讯结构的适用性，有效降低通讯结构的成本。
于本实施例中，每一个所述电子器件120具有但不限于电源管脚，接地管脚和通讯管脚。
其中，所述电源管脚与所述选通芯片112相连，通过所述选通芯片112控制电源管脚的上电与断电；所述接地管脚与所述主机控制器110相连；所述通讯管脚与所述通讯芯片111的所述第一通道平行总线111a或所述第二通道平行总线111b相连。
其中，在电子器件120数量和传输的数据量不是很大时，一个所述通讯芯片111既可实现电子器件120与主机控制器110的通讯。所述通讯芯片111的数量可以根据电子器件120数量和传输的数据量的大小进行相应调整。
相应地，在电子器件120数量不是很多时，一个所述选通芯片112既可实现各所述电气器件的选通，所述选通芯片112的数量可以根据电子器件120数量进行相应调整。
于本实施例中，所述多个电子器件120形成至少一组电子器件；每一条通道平行总线上对应连接一组电子器件中的各电子器件120的通讯管脚。
例如，如图2所示，所述多个电子器件120包括第一组电子器件和第二组电气器件；即多个电子器件120被划分为两组电子器件，一组电子器件连接于所述第一通道平行总线111a上，另一组电子器件连接于所述第二通道平行总线111b上。
其中，所述通讯芯片111的第一通道平行总线111a与所述第一组电子器件中多个电子器件120的各通讯管脚相连，所述通讯芯片111的第二通道平行总线111b与所述第二组电子器件中多个电子器件120的各通讯管脚相连。
各电子器件120的通讯管脚分别独立地连接于平行总线上，也就是各电子器件120的通讯管脚分别独立地与通讯芯片111相连，这样使得各电子器件120(传感器)之间相互独立，互不影响。
于本实施例中，所述选通芯片112的目的是可以控制电源线的通断，进而控制是否给某个电子器件120供电。具体地，所述选通芯片112用于控制各电子器件120的选通，被所述选通芯片112选通的电子器件120得电，此时电子器件120可以被主机控制器110控制，未被选通的电子器件120断电，此时电子器件120不能被主机控制器110所控制。
其中，所述选通芯片112分别与各电子器件120的各电源管脚相连，独立控制每一个电子器件120的电源管脚。通过所述选通芯片112确定为哪一个电子器件120供电。
于本实施例中，所述选通芯片112控制至少一条电源线，每一条电源线上对应连接至少一组电子器件中的各电子器件的电源管脚。
例如，如图2所示，所述选通芯片112控制两条电源线：第一电源线和第二电源线。
所述第一电源线与所述第一组电子器件中多个电子器件120的各电源管脚相连，用于控制所述第一组电子器件中多个电子器件120的各电源管脚供电；所述第二电源线与所述第二组电子器件中多个电子器件120的各电源管脚相连，用于控制所述第二组电子器件中多个电子器件120的各电源管脚供电。
此外，所述选通芯片112也可以仅控制一条电源线，该电源线上连接所有电子器件120的电源管脚。
于本实施例中，在所述选通芯片112每次只选通一个电子器件120，控制其中一个电子器件120的电源管脚供电，使得一个电子器件120的电源管脚与电源导通，其余各电子器件120的电源管脚断电。在所述选通芯片112控制其中一个电子器件120的电源管脚供电，其余各电子器件120的电源管脚断电时，所述主机控制器110为电源管脚供电的电子器件120分配地址。
于本实施例中，所述主机控制器110分别与各所述电子器件120的各接地管脚相连，将各所述电子器件120的各接地管脚接地。
于本实施例中，所述主机控制器控制至少一条地线，每一条地线上对应连接至少一组电子器件中的各电子器件的接地管脚。
例如，如图2所示，于本实施中，所述主机控制器110控制第一地线和第二地线。
其中，所述第一地线与所述第一组电子器件中多个电子器件120的各接地管脚相连；所述第二地线与所述第二组电子器件中多个电子器件120的各接地管脚相连。
此外，所述主机控制器110也可以控制一条地线，该地线上连接所有电子器件120的接地管脚。
于本实施例中，所述主机控制器110在首次上电时通过所述选通芯片112依次为各所述电子器件120分配地址；各所述电子器件120存储分配的地址并在通讯过程中，向所述主机控制器110上传各自的地址。
具体地，于本实施例中，所述主机控制器110在首次上电时通过所述选通芯片112依次为各所述电子器件120分配地址，其中，根据各电子器件120于通道平行总线上连接顺序(例如从左到由)依次为通道平行总线上连接的电子器件120分配地址。
例如，所述通讯芯片111控制一条通道平行总线，依次为该条通道平行总线上连接的电子器件120分配地址。具体分配过程如下：
所述主机控制器110在首次上电时，通过选通芯片112控制通道平行总线上的第一个电子器件120上电，其余电子器件120断电，所述主机控制器110为通道平行总线上的第一个电子器件120分配地址，在为通道平行总线上的第一个电子器件120分配完地址之后，通过所述选通芯片112控制通道平行总线上的第一个电子器件120断电，通道平行总线上的第二个电子器件120上电，其余电子器件120同样断电，继续为通道平行总线上的第二个电子器件120分配地址，重复上述过程，直至完成该条通道平行总线上的所有电子器件120的地址分配。
又例如，所述通讯芯片111控制两条通道平行总线：第一通道平行总线111a和第二通道平行总线111b。先依次为第一通道平行总线111a上连接的电子器件120分配地址，再依次为第二通道平行总线111b上连接的电子器件120分配地址。
即根据各电子器件120于第一通道平行总线111a上连接顺序(例如从左到由)依次为第一通道平行总线111a上连接的电子器件120分配地址，根据各电子器件120于第二通道平行总线111b上连接顺序(例如从左到由)依次为第二通道平行总线111b上连接的电子器件120分配地址。具体分配过程如下：
所述主机控制器110在首次上电时，通过选通芯片112控制第一通道平行总线111a上的第一个电子器件120上电，其余电子器件120断电，所述主机控制器110为第一通道平行总线111a上的第一个电子器件120分配地址，在为第一通道平行总线111a上的第一个电子器 件120分配完地址之后，通过所述选通芯片112控制第一通道平行总线111a上的第一个电子器件120断电，第一通道平行总线111a上的第二个电子器件120上电，其余电子器件120同样断电，继续为第一通道平行总线111a上的第二个电子器件120分配地址，重复上述过程，直至完成第一通道平行总线111a上的所有电子器件120的地址分配。
然后通过所述选通芯片112控制第二通道平行总线111b上的第一个电子器件120的上电，其余电子器件120断电，所述主机控制器110为第二通道平行总线111b上的第一个电子器件120分配地址，在为第二通道平行总线111b上的第一个电子器件120分配完地址之后，通过所述选通芯片112控制第二通道平行总线111b上的第一个电子器件120断电，第二通道平行总线111b上的第二个电子器件120上电，其余电子器件120同样断电，继续为第二通道平行总线111b上的第二个电子器件120分配地址，重复上述过程，直至完成第二通道平行总线111b上的所有电子器件120的地址分配。
于本实施例中，其中，在主机控制器110为电子器件120分配完地址之后，电子器件120存储被分配的地址，并在与主机控制器110进行通讯时，令通讯数据中包含所述电子器件120的地址。
即电子器件120在与主机控制器110通讯过程中，主机控制器110下发的指令数据包中包含电子器件120，电子器件120向主机控制器110进行响应时，响应数据包中包含各个电子器件120的地址。
例如车载超声波传感器通过内置的非易失性存储器存储分配的地址，所述主机控制器110根据分配的地址为该车载超声波传感器发送指令，实现与该车载超声波传感器的通讯。接收到指令的车载超声波传感器在向主机控制器110反馈数据时，上传自己的地址，其中，车载超声波传感器的地址会被打包进通讯报文中，以使得主机控制器110根据车载超声波传感器上传的地址进行解码。
综上所述，本发明中，通讯系统的通讯芯片采用平行总线的通讯方式，并通过选通芯片依次为各电子器件分配地址，在使用少量通讯芯片的基础上，即可实现通讯功能，各电子器件(传感器)之间相互独立，互不影响可以沿用现有的传感器结构和整车线束，具有成本优势。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种基于平行总线的通讯系统，其特征在于：包括：
    多个电子器件；
    主机控制器，配置有选通芯片和通讯芯片；其中：
    所述通讯芯片至少控制一条通道平行总线，各所述电子器件分别独立地连接于所述通道平行总线上；
    所述主机控制器在首次上电时通过所述选通芯片依次为各所述电子器件分配地址。
  2. 根据权利要求1所述的基于平行总线的通讯系统，其特征在于：每一个所述电子器件具有电源管脚，接地管脚和通讯管脚。
  3. 根据权利要求2所述的基于平行总线的通讯系统，其特征在于：所述多个电子器件形成至少一组电子器件；每一条通道平行总线上对应连接一组电子器件中的各电子器件的通讯管脚。
  4. 根据权利要求3所述的基于平行总线的通讯系统，其特征在于：所述选通芯片控制至少一条电源线，每一条电源线上对应连接至少一组电子器件中的各电子器件的电源管脚。
  5. 根据权利要求2或3所述的基于平行总线的通讯系统，其特征在于：所述选通芯片控制一条电源线，该电源线上连接所有电子器件的电源管脚。
  6. 根据权利要求3所述的基于平行总线的通讯系统，其特征在于：所述主机控制器控制至少一条地线，每一条地线上对应连接至少一组电子器件中的各电子器件的接地管脚。
  7. 根据权利要求2或3所述的基于平行总线的通讯系统，其特征在于：所述主机控制器控制一条地线，该地线上连接所有电子器件的接地管脚。
  8. 根据权利要求1所述的基于平行总线的通讯系统，其特征在于：在所述选通芯片控制其中一个电子器件的电源管脚供电，其余各电子器件的电源管脚断电时，所述主机控制器为电源管脚供电的电子器件分配地址。
  9. 根据权利要求1或8所述的基于平行总线的通讯系统，其特征在于：各所述电子器件存储分配的地址，并在与主机控制器进行通讯时，令通讯数据中包含所述电子器件的地址。
  10. 根据权利要求1所述的基于平行总线的通讯系统，其特征在于：所述电子器件为超声波传感器。
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