WO2022205509A1 - 阵列基板 - Google Patents

阵列基板 Download PDF

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Publication number
WO2022205509A1
WO2022205509A1 PCT/CN2021/087433 CN2021087433W WO2022205509A1 WO 2022205509 A1 WO2022205509 A1 WO 2022205509A1 CN 2021087433 W CN2021087433 W CN 2021087433W WO 2022205509 A1 WO2022205509 A1 WO 2022205509A1
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Prior art keywords
region
light shielding
shielding portion
light
layer
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PCT/CN2021/087433
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English (en)
French (fr)
Inventor
汤富雄
管延庆
杨从星
Original Assignee
武汉华星光电技术有限公司
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Priority to US17/289,899 priority Critical patent/US20240096908A1/en
Publication of WO2022205509A1 publication Critical patent/WO2022205509A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate.
  • the active layer is usually sensitive to light signals (backlights of display devices, etc.), and different light signals can cause the current surge when the thin film transistor is off. When the current signal is large enough, the on/off ratio of the thin film transistor will decrease, which will further cause the thin film transistor array to be turned on abnormally, and finally cause the abnormal display screen.
  • the commonly used method is to add a light-shielding layer only at the bottom of the channel region to block the influence of the backlight on the thin film transistor.
  • the active layer will have a climbing phenomenon.
  • the active layer material is an inflexible material. It is precisely because of this climbing phenomenon that when the active layer is affected by subsequent etching and laser annealing processes, the active layer is prone to narrowing or cracking defects. , resulting in yield loss, which in turn affects the performance of the array substrate.
  • the embodiments of the present application provide an array substrate, so as to solve the problem that the active layer is cracked on a slope at the junction of the light shielding layer and the active layer in the prior art, thereby improving the performance of the array substrate.
  • Embodiments of the present application provide an array substrate, which includes:
  • the active layer is disposed on the light shielding layer, wherein the orthographic projection of the active layer on the substrate is located in the orthographic projection of the light shielding layer on the substrate.
  • the light-shielding layer includes a first light-shielding portion, a second light-shielding portion, and a third light-shielding portion that are connected in sequence, and the first light-shielding portion and the third light-shielding portion are located at On the same side of the second light-shielding portion, the first light-shielding portion and the third light-shielding portion are disposed opposite to each other.
  • the active layer includes a first active part, a second active part and a third active part which are connected in sequence, and the first active part is located in the first light shielding part
  • the second active part is located on the second light shielding part
  • the third active part is located on the third light shielding part.
  • the first active portion includes a first conduction region and a first channel region, and the first conduction region is located at two sides of the first channel region.
  • the third active part includes a second conduction region and a second channel region, and the second conduction region is located at both ends of the second channel region.
  • the first conduction region includes a first doping region and a second doping region, and the first doping region is located at two sides of the first channel region. end, the second doped region is located at two ends of the first doped region away from the first channel region, and the doping concentration of the first doped region is smaller than the doping concentration of the second doped region impurity concentration.
  • the second conduction region includes a third doping region and a fourth doping region
  • the third doping region is located at two sides of the second channel region.
  • the fourth doped region is located at two ends of the third doped region away from the second channel region, and the doping concentration of the third doped region is smaller than the doping concentration of the fourth doped region impurity concentration.
  • the planar shape of the first light shielding portion is provided with a first protrusion, and the protrusion direction of the first protrusion is the same as the extension direction of the first channel region.
  • the first protrusion is located in the area corresponding to the first light-shielding portion of the first doping region;
  • the plane shape of the third light-shielding portion is provided with a second protrusion, and the second protrusion is The protrusion direction is perpendicular to the extending direction of the second channel region, and the second protrusion is located in a region corresponding to the third light shielding portion of the third doping region.
  • the orthographic edge of the region other than the first doped region and the third doped region of the active layer overlaps with the orthographic edge of the light shielding layer.
  • the light-shielding layer further includes a fourth light-shielding portion, the fourth light-shielding portion is connected with the first light-shielding portion, the second light-shielding portion, and the third light-shielding portion Department connection.
  • the first light-shielding portion, the third light-shielding portion, and the fourth light-shielding portion are located on the same side of the second light-shielding portion, and the fourth light-shielding portion is located on the same side of the second light-shielding portion.
  • the portion is located between the first light shielding portion and the third light shielding portion.
  • the light-shielding layer includes a first light-shielding portion, a second light-shielding portion, and a third light-shielding portion that are connected in sequence, and the first light-shielding portion and the third light-shielding portion are located at different sides of the second shading portion.
  • the active layer includes a first active part, a second active part and a third active part which are connected in sequence, and the first active part is located in the first light shielding part
  • the second active part is located on the second light shielding part
  • the third active part is located on the third light shielding part.
  • the second active portion includes a third conduction region and a third channel region, and the third conduction region is located on two sides of the third channel region. end, the first active part and the third active part are fourth conduction regions.
  • the second light shielding portion is provided with a third protrusion, and the protrusion direction of the third protrusion is perpendicular to the extending direction of the third channel region, so The third protrusion is located in an area corresponding to the second light shielding portion where the third conduction area is disposed.
  • the orthographic edge of the region outside the third conduction region of the active layer overlaps with the orthographic edge of the light shielding layer.
  • the doping concentration of the third channel region is lower than the doping concentration of the third conduction region, and the doping concentration of the third conduction region is lower than the doping concentration of the third conduction region. the doping concentration of the fourth conduction region.
  • the distance from the edge of the orthographic projection of the third conduction region on the substrate to the edge of the orthographic projection of the light shielding layer on the substrate is 400 nm to 2000 nm. nano.
  • the orthographic edge of the first doped region on the substrate and the orthographic edge of the third doped region on the substrate reach the light shielding
  • the distances of the orthographic edges of the layers on the substrate are all 400 nm to 2000 nm.
  • the distance from the edge of the orthographic projection of the active layer on the substrate to the edge of the orthographic projection of the light shielding layer on the substrate is 0 nm to 6000 nm.
  • the thickness of the active layer is 30 nanometers to 70 nanometers.
  • the application provides an array substrate, the array substrate includes a base, a light shielding layer and an active layer, the light shielding layer is disposed on the base, and the active layer is disposed on the light shielding layer, wherein the active layer is
  • the orthographic projection of the layer on the substrate lies in the orthographic projection of the light-shielding layer on the substrate.
  • the orthographic projection of the active layer on the substrate is set to be located in the orthographic projection of the light-shielding layer on the substrate, so as to avoid the phenomenon of climbing and fracture of the active layer, thereby ensuring that performance of the array substrate.
  • FIG. 1 is a schematic top view of an array substrate in the prior art.
  • FIG. 2 is a schematic cross-sectional view of the array substrate in FIG. 1 along line AB.
  • FIG. 3 is a schematic top view of the first implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of the array substrate in FIG. 3 along CD line.
  • FIG. 5 is a schematic top view of a second implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of the array substrate in FIG. 5 along line DE.
  • FIG. 7 is a schematic top view of a third implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 8 is a schematic top view of a fourth implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional view of the array substrate in FIG. 8 along line EF.
  • FIG. 10 is a schematic top view of a fifth implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 11 is a schematic top view of a sixth implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 12 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present application.
  • FIG. 1 is a schematic top view of an array substrate in the prior art.
  • FIG. 2 is a schematic cross-sectional view of the array substrate in FIG. 1 along line AB.
  • the array substrate 10 in the prior art includes a substrate 11 , a light shielding layer 12 , a buffer layer 13 , an active layer 14 , an insulating layer 15 , a gate electrode 16 , a passivation layer 17 and a source and drain layer 18 .
  • the buffer layer 13 is disposed on the light shielding layer 12 .
  • the active layer 14 is disposed on the buffer layer 13 .
  • the insulating layer 15 completely covers the active layer 14 .
  • the gate 16 is disposed on the insulating layer 15 .
  • the passivation layer 17 covers the insulating layer 15 and the gate electrode 16 , and the source and drain layers 18 are disposed on the passivation layer 17 and are electrically connected to the active layer 14 .
  • the active layer 14 has a climbing phenomenon above the junction of the light-shielding layer 12 and the non-light-shielding layer 12, thereby causing uneven thickness of the active layer 14, and even the active layer 14 is broken. risk, which in turn affects the performance of the array substrate.
  • the present application proposes an array substrate to solve the problems existing in the array substrate in the prior art.
  • FIG. 3 is a schematic top view of the first implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of the array substrate in FIG. 3 along CD line.
  • the present application provides an array substrate 20 .
  • the array substrate 20 includes a base 100 , a light shielding layer 200 and an active layer 300 .
  • the specific description is as follows:
  • the material of the substrate 100 may be polyimide, glass, or the like.
  • the light shielding layer 200 is disposed on the substrate 100 .
  • the light shielding layer 200 includes a first light shielding portion 210 , a second light shielding portion 220 and a third light shielding portion 230 which are connected in sequence.
  • the first light-shielding portion 210 and the third light-shielding portion 230 are located on the same side of the second light-shielding portion 220 , and the first light-shielding portion 210 and the third light-shielding portion 230 are disposed opposite to each other.
  • the materials of the light shielding layer 200 include metal materials and insulating materials, wherein the metal materials can be one or a combination of Al, Cu, Ag, Au, Mn, Zn and Fe, and the insulating materials include SiN x , SiO x and SiO One or more combinations of x N y .
  • the thickness H of the light shielding layer 200 is 50 nanometers to 500 nanometers. Specifically, the thickness H of the light shielding layer 200 may be 50 nanometers, 52 nanometers, 70 nanometers, 200 nanometers, 350 nanometers, 430 nanometers, 470 nanometers, 490 nanometers, or 500 nanometers.
  • the shape of the light shielding layer 200 may be a square, a rectangle, a circle, or the like.
  • the first light shielding portion 210 and the third light shielding portion 230 are arranged on the same side of the second light shielding portion 220, which simplifies the manufacturing process and reduces the production cost.
  • the surface of the light-shielding layer 200 facing the substrate 100 is a rough surface, and the rough surface is used to reflect the light emitted from the backlight to the light-shielding layer 200 back into the backlight, so as to reduce light loss and improve the light-shielding layer 200 . Blackout effect.
  • the array substrate 20 further includes a buffer layer 400 .
  • the buffer layer 400 is disposed on the light shielding layer 200 .
  • the buffer layer 400 includes one or a combination of SiN x , SiO x and SiO x N y .
  • the active layer 300 is disposed on the light shielding layer 200 . Specifically, the active layer 300 is disposed on the buffer layer 400 . In one embodiment, the thickness h of the active layer 300 is 30 nm to 70 nm. The thickness h of the active layer 300 may be 30 nanometers, 31 nanometers, 35 nanometers, 38 nanometers, 46 nanometers, 50 nanometers, 60 nanometers, 64 nanometers, 68 nanometers, or 70 nanometers.
  • the material of the active layer 300 includes one of amorphous silicon and polysilicon.
  • the orthographic projection 301 of the active layer 300 on the substrate 100 is located in the orthographic projection 201 of the light shielding layer 200 on the substrate 100 .
  • the distance L from the edge of the orthographic projection 301 of the active layer 300 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is 0 nm to 6000 nm.
  • the distance L from the edge of the orthographic projection 301 of the active layer 300 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 may be 0 nm, 0.1 nm, 1 nm, 10 nm, 1000 nm, 2500 nm Nano, 4000 nm, 5000 nm, 5800 nm or 6000 nm etc.
  • the light shielding layer 200 when the distance L from the edge of the orthographic projection 301 of the active layer 300 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is set to 0 nm, the light shielding layer 200 just completely covers the active layer. layer 300, thereby reducing costs.
  • the active layer 300 includes a first active part 310 , a second active part 320 and a third active part 330 which are connected in sequence.
  • the first active part 310 is located on the first light shielding part 210 .
  • the second active part 320 is located on the second light shielding part 220 .
  • the third active part 330 is located on the third light shielding part 230 .
  • FIG. 5 is a schematic top view of the second implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of the array substrate in FIG. 5 along line DE. It should be noted that the difference between the second embodiment and the first embodiment is:
  • the array substrate 20 further includes an insulating layer 500 , a gate electrode 600 , a passivation layer 700 and a source and drain layer 800 .
  • the insulating layer 500 covers the active layer 300 .
  • the material of the insulating layer 500 includes one or a combination of SiO 2 and Six N y .
  • the gate 600 is disposed on the insulating layer 500 , and the gate 600 is located on the first active part 310 and the third active part 330 .
  • the material of the gate 600 includes one or a combination of Al, Cu, Ag, Au, Mn, Zn and Fe.
  • the passivation layer 700 covers the insulating layer 500 and the gate electrode 600 .
  • the passivation layer 700 is provided with through holes 701 .
  • the through hole 701 penetrates the passivation layer 700 and the insulating layer 500 to expose the active layer 300 .
  • the source and drain layers 800 are disposed on the passivation layer 700 and extend into the through holes 701 to be electrically connected to the active layer 300 .
  • the material of the source and drain layers 800 includes one or a combination of Al, Cu, Ag, Au, Mn, Zn and Fe.
  • the orthographic projection of the active layer on the substrate is set in the orthographic projection of the light shielding layer on the substrate, that is, the entire light shielding layer is arranged under the active layer, thereby preventing the active layer from climbing
  • the phenomenon of fracture or uneven thickness thereby avoiding the deterioration of the electrical properties of the array substrate, thereby ensuring the performance of the array substrate;
  • the thickness of the light-shielding layer can be thickened, thereby improving the light-shielding layer of the light-shielding layer.
  • the performance of the array substrate is guaranteed; because the active layers are all arranged on the light-shielding layer, the phenomenon of narrowing or breaking will not occur, and in some special devices, the thickness reduction limit of the active layer can be relaxed, and then reduce manufacturing cost.
  • FIG. 7 is a schematic top view of the third embodiment of the array substrate provided by the embodiment of the application. It should be noted that the difference between the third embodiment and the second embodiment is:
  • the light shielding layer 200 further includes a fourth light shielding portion 240 .
  • the fourth light shielding portion 240 is connected to the first light shielding portion 210 , the second light shielding portion 220 and the third light shielding portion 230 .
  • the first light-shielding portion 210 , the third light-shielding portion 230 and the fourth light-shielding portion 240 are located on the same side of the second light-shielding portion 220
  • the fourth light-shielding portion 240 is located between the first light-shielding portion 210 and the third light-shielding portion 230 .
  • Other structures As described in the second embodiment, details are not repeated here.
  • a fourth light-shielding portion 240 is arranged between the first light-shielding portion 210 and the third light-shielding portion 230 , so that the light-shielding range of the light-shielding layer 200 is increased, and the light-shielding effect is further improved, thereby ensuring the performance of the array substrate 20 .
  • FIG. 8 is a schematic top view of the fourth implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional view of the array substrate in FIG. 8 along line EF. It should be noted that the difference between the fourth embodiment and the second embodiment is:
  • the first active part 310 is composed of a first conduction region 311 and a first channel region 312 .
  • the first conduction region 311 is located at both ends of the first channel region 312 .
  • the third active portion 330 is composed of a second conduction region 331 and a second channel region 332 .
  • the second conduction region 331 is located at both ends of the second channel region 332 .
  • the second active portion 320 is a connection conduction region.
  • the second active part 320 connects the first conduction region 311 and the second conduction region 331 .
  • the first conduction region 311 , the connection conduction region and the second conduction region 331 are doped with one or a combination of phosphorous and arsenic, so that the first conduction region 311 , the connection conduction region 311 , the connection conduction region 331 are changed.
  • the resistance of the array substrate 20 in the pass region and the second pass region 331 is improved, thereby improving the performance of the array substrate 20 .
  • the first conduction region 311 includes a first doped region 3111 and a second doped region 3112 .
  • the first doped regions 3111 are located at both ends of the first channel region 312 .
  • the second doping region 3112 is located at two ends of the first doping region 3111 away from the first channel region 312 .
  • the doping concentration of the first doping region 3111 is lower than that of the second doping region 3112 .
  • the doping concentration of the first doping region 3111 is 3e 12 -3e 13 per square centimeter.
  • the doping concentrations of the second doping regions 3112 are all 3e 14 to 3e 15 per square centimeter.
  • the distance W from at least one edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is 400 nm to 2000 nm.
  • the distance W from at least one edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is set to 400 nanometers to 2000 nanometers, so as to shield the light
  • the layer 200 just completely covers the first doped region 3111, thereby improving the shading effect, improving the aperture ratio of the pixel and reducing the cost.
  • At least one side of the edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 and at least one side of the edge of the orthographic projection 301 of the first channel region 312 on the substrate 100 to the light shielding layer 200 on the substrate 100 can be set to 400 nanometers to 2000 nanometers, and the distance L from the edge of the orthographic projection 301 of the active layer 300 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is set to be 0 nm.
  • one side of the edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 and at least one side of the edge of the orthographic projection 301 of the first channel region 312 on the substrate 100 are connected to the light shielding layer 200 on the substrate 100
  • the distance W of the edge of the orthographic projection 201 can be set to 400 nm-2000 nm, and the light shielding layer 200 is set to cover the active layer 300 completely, so that the light shielding effect is improved, and the cost and the active layer 300 are broken. question.
  • the doping concentration of the first channel region 312 is lower than the doping concentration of the first doping region 3111 .
  • the first channel region 312 is doped with one or a combination of boron and gallium, which changes the resistance of the first channel region 312 but does not affect the first channel region 312 itself. performance, thereby improving the performance of the array substrate 20 .
  • the doping concentrations of the first doping region 3111 and the second doping region 3112 are set to be different, so that the first doping region 3111 is a resistance transition region, thereby improving the performance of the array substrate 20 .
  • the first protrusion 211 is provided on the plane shape of the first light shielding portion 210 .
  • the protruding direction of the first protrusion 211 is perpendicular to the longitudinal extension direction of the first channel region 312 .
  • the first protrusion is located in a region corresponding to the first light shielding portion 210 where the first doped region 3111 is disposed.
  • the first protrusion 211 is provided on the plane shape of the first light shielding portion 210 .
  • the protruding direction of the first protrusion 211 is perpendicular to the longitudinal extension direction of the first channel region 312 .
  • the first protrusion is located in a region corresponding to the first light shielding portion 210 where the first doping region 3111 and the first channel region 312 are provided.
  • the second conduction region 331 includes a third doped region 3311 and a fourth doped region 3312 .
  • the third doped regions 3311 are located at both ends of the second channel region 332 .
  • the fourth doping region 3312 is located at two ends of the third doping region 3311 away from the second channel region 332 .
  • the doping concentration of the third doping region 3311 is lower than that of the fourth doping region 3312 .
  • the doping concentrations of the third doping regions 3311 are all 3e 12 to 3e 13 per square centimeter.
  • the doping concentrations of the fourth doping region 3312 are all 3e 14 to 3e 15 per square centimeter.
  • the doping concentration of the second channel region 332 is lower than the doping concentration of the third doping region 3311 .
  • the second channel region 332 is doped with one or a combination of boron and gallium, which changes the resistance of the second channel region 332 but does not affect the second channel region 332 itself. performance, thereby improving the performance of the array substrate 20 .
  • the doping concentrations of the third doping region 3311 and the fourth doping region 3312 are set to be different, so that the third doping region 3311 is a resistance transition region, thereby improving the performance of the array substrate 20 .
  • the distance W from at least one edge of the orthographic projection 301 of the third doped region 3311 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is 400 nm to 2000 nm.
  • the distance W from at least one edge of the orthographic projection 301 of the third doped region 3311 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is set to 400 nanometers to 2000 nanometers, so as to shield the light
  • the layer 200 just completely covers the third doped region 3311 , so that the light-shielding effect of the light-shielding layer 200 is improved and the cost is reduced.
  • At least one side of the edge of the orthographic projection 301 of the third doping region 3311 on the substrate 100 and at least one side of the edge of the orthographic projection 301 of the second channel region 332 on the substrate 100 to the light shielding layer 200 on the substrate 100 can be set to 400 nanometers to 2000 nanometers, and the distance L from the edge of the orthographic projection 301 of the active layer 300 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is set to be 0 nm.
  • one side of the edge of the orthographic projection 301 of the third doping region 3311 on the substrate 100 and at least one side of the edge of the orthographic projection 301 of the second channel region 332 on the substrate 100 are connected to the light shielding layer 200 on the substrate 100
  • the distance W of the edge of the orthographic projection 201 can be set to be 400 nm-2000 nm, and the light shielding layer 200 is set to just cover the active layer 300 completely, so as to further improve the light shielding effect and avoid the problem of breakage of the active layer 300. and reduce costs.
  • the planar shape of the third light shielding portion 230 is provided with a second protrusion 231 .
  • the protruding direction of the second protrusions 231 is perpendicular to the longitudinal extension direction of the second channel region 332 .
  • the first protrusion is located in a region corresponding to the third light shielding portion 230 where the third doping region 3311 is disposed.
  • the planar shape of the third light shielding portion 230 is provided with a second protrusion 231 .
  • the protruding direction of the second protrusions 231 is perpendicular to the longitudinal extension direction of the second channel region 332 .
  • the second protrusion 231 is located in a region corresponding to the third light shielding portion 230 where the third doping region 3311 and the second channel region 332 are disposed.
  • the edge of the orthographic projection 301 of the region outside the first doped region 3111 and the third doped region 3311 of the active layer 300 overlaps with the edge of the orthographic projection 201 of the light shielding layer 200 .
  • Regions other than the first doped region 3111 and the third doped region 3311 of the active layer 300 include a second doped region 3112 , a second active portion 320 and a fourth doped region 3312 .
  • the edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 and the edge of the orthographic projection 301 of the third doped region 3311 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 The distances W are 400 nm-2000 nm. Specifically, the distance W from the edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 and the edge of the orthographic projection 301 of the third doped region 3311 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 It can be 400 nanometers, 500 nanometers, 800 nanometers, 1500 nanometers, 1900 nanometers or 2000 nanometers, etc.
  • the edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 and the edge of the orthographic projection 301 of the third doped region 3311 on the substrate 100 are to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100
  • the distance W is 500 nm.
  • the edge of the orthographic projection 301 of the first doped region 3111 on the substrate 100 and the edge of the orthographic projection 301 of the third doped region 3311 on the substrate 100 are set to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100
  • the distances W are set at 400 nm to 2000 nm, which can block the light entering the first doped region 3111 and the third doped region 3311 , thereby further avoiding leakage of the active layer 300 , thereby improving the performance of the array substrate 20 .
  • gate 600 is located over first channel region 312 and second channel region 332 .
  • the first doped region 3111 and the third doped region 3311 are disposed on a side of the buffer layer 400 close to the gate electrode 600 .
  • the second doped region 3112 and the fourth doped region 3312 are located on the side of the buffer layer 400 away from the gate electrode 600 .
  • the first doped region 3111 and the third doped region 3311 are lightly doped, and the second doped region 3112, the fourth doped region 3312 and the second active portion 320 are heavily doped,
  • the leakage problem of the array substrate 20 can be prevented, thereby improving the performance of the array substrate 20 .
  • FIG. 10 is a schematic top view of a fifth implementation manner of the array substrate provided by the embodiment of the present application. It should be noted that the difference between the fifth embodiment and the fourth embodiment is:
  • the light shielding layer 200 further includes a fourth light shielding portion 240 .
  • the fourth light shielding portion 240 is connected to the first light shielding portion 210 , the second light shielding portion 220 and the third light shielding portion 230 .
  • the first light-shielding portion 210 , the third light-shielding portion 230 and the fourth light-shielding portion 240 are located on the same side of the second light-shielding portion 220
  • the fourth light-shielding portion 240 is located between the first light-shielding portion 210 and the third light-shielding portion 230 .
  • Other structures As described in the fourth embodiment, details are not repeated here.
  • a fourth light-shielding portion 240 is arranged between the first light-shielding portion 210 and the third light-shielding portion 230 , so that the light-shielding range of the light-shielding layer 200 is increased, and the light-shielding effect is further improved, thereby ensuring the performance of the array substrate 20 .
  • FIG. 11 is a schematic top view of the sixth implementation manner of the array substrate provided by the embodiment of the present application. It should be noted that the difference between the sixth embodiment and the fourth embodiment is:
  • the first light shielding portion 210 and the third light shielding portion 230 are located on different sides of the second light shielding portion 220 .
  • the second active part 320 includes a third conduction region 321 and a third channel region 322 .
  • the third conduction region 321 is located at both ends of the third channel region 322 .
  • the first active part 310 and the third active part 330 are fourth conduction regions.
  • the third channel region 322 is doped with one or both of boron and gallium, which changes the resistance of the third channel region 322, but does not affect the performance of the third channel region 322 itself, thereby improving the array substrate. 20 performance.
  • the third conduction region 321 , the first active part 310 and the third active part 330 are doped with one or a combination of phosphorus and arsenic, so that the third conduction region 321 and the first active part 310 are improved. and the electrical properties of the third active part 330 .
  • the doping concentration of the third channel region 322 is lower than the doping concentration of the third conduction region 321 .
  • the doping concentration of the third conduction region 321 is smaller than that of the fourth conduction region.
  • the second light shielding portion 220 is provided with a third protrusion 221 in a planar shape.
  • the protruding direction of the third protrusions 221 is perpendicular to the lateral extension direction of the third channel region 322 .
  • the second light shielding portion 220 is provided with a third protrusion 221 in a planar shape.
  • the protruding direction of the third protrusion 221 is perpendicular to the lateral extension direction of the third channel region 322 .
  • the third protrusion 221 is located in a region corresponding to the second light shielding portion 220 where the third conduction region 321 and the third channel region 322 are disposed.
  • the edge of the orthographic projection 301 of the region outside the third conduction region 321 of the active layer 300 overlaps with the edge of the orthographic projection 201 of the light shielding layer 200 .
  • the region outside the third conduction region 321 of the active layer 300 includes the first active part 310 and the third active part 330 .
  • the distance D from at least one edge of the orthographic projection 301 of the third conducting region 321 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is 400 nm to 2000 nm.
  • the distance D from at least one side of the edge of the orthographic projection 301 of the third conduction region 321 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is set to 400 nm to 2000 nm, so that the light is shielded.
  • the layer 200 just completely covers the third conduction region 321 , so that the cost is reduced while improving the light-shielding effect of the light-shielding layer 200 .
  • At least one side of the edge of the orthographic projection 301 of the third conduction region 321 on the substrate 100 and at least one side of the edge of the orthographic projection 301 of the third channel region 322 on the substrate 100 to the light shielding layer 200 on the substrate 100 can be set to 400 nm to 2000 nm, and the distance L from the edge of the orthographic projection 301 of the active layer 300 on the substrate 100 to the edge of the orthographic projection 201 of the light shielding layer 200 on the substrate 100 is set to be 0 nm.
  • one side of the edge of the orthographic projection 301 of the third conduction region 321 on the substrate 100 and at least one side of the edge of the orthographic projection 301 of the third channel region 322 on the substrate 100 are connected to the light shielding layer 200 on the substrate 100
  • the distance D of the edge of the orthographic projection 201 can be set to 400 nm-2000 nm, and the light shielding layer 200 is set to just cover the active layer 300 completely, so as to further improve the distance between the third conduction region 321 and the third channel region 322.
  • the shading effect reduces the cost and avoids the problem of cracking at the junction of the third conduction region 321 and the third channel region 322 .
  • the gate 600 is over the third channel region 322 .
  • the array substrate 20 in the present application can be applied to mobile phones, monitors, computers and televisions.
  • FIG. 5 is a schematic top view of the second implementation manner of the array substrate provided by the embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of the array substrate in FIG. 5 along line DE.
  • FIG. 12 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present application. The present application also provides a method for preparing the array substrate 20, which is specifically described as follows:
  • Step B21 Provide a substrate.
  • the substrate 100 is pre-cleaned.
  • the material of the substrate 100 may be polyimide, glass, or the like.
  • Step B22 forming a light shielding layer on the substrate.
  • the material of the light shielding layer 200 is deposited on the substrate 100 , and the patterned light shielding layer 200 is formed by exposing and etching the material of the light shielding layer 200 .
  • the light shielding layer 200 includes a first light shielding portion 210 , a second light shielding portion 220 , a third light shielding portion 230 and a fourth light shielding portion 240 .
  • the first light shielding portion 210 , the second light shielding portion 220 and the third light shielding portion 230 are connected in sequence.
  • the first light shielding portion 210 , the third light shielding portion 230 and the fourth light shielding portion 240 are located on the same side of the second light shielding portion 220 .
  • the first light shielding portion 210 and the third light shielding portion 230 are disposed opposite to each other.
  • the fourth light shielding portion 240 is located between the first light shielding portion 210 and the third light shielding portion 230 .
  • Materials of the light shielding layer 200 include metal materials and insulating materials, wherein the metal materials may be one or a combination of Al, Cu, Ag, Au, Mn, Zn, and Fe.
  • the thickness H of the light shielding layer 200 is 50 nanometers to 500 nanometers. Specifically, the thickness H of the light shielding layer 200 may be 50 nanometers, 52 nanometers, 70 nanometers, 200 nanometers, 350 nanometers, 430 nanometers, 470 nanometers, 490 nanometers, or 500 nanometers.
  • the light-shielding layer 200 includes a first light-shielding portion 210 , a second light-shielding portion 220 , a third light-shielding portion 230 and a fourth light-shielding portion 240 , so that the light-shielding range of the light-shielding layer 200 is increased, the light-shielding effect is further improved, and the performance of the array substrate 20 .
  • step B22 it further includes:
  • the light shielding layer 200 is etched to remove the fourth light shielding portion 240 .
  • the fourth light shielding portion 240 is removed, and the first light shielding portion 210 and the third light shielding portion 230 are arranged on the same side of the second light shielding portion 220 , which simplifies the fabrication process and improves the aperture ratio of the pixel and Reduced production costs.
  • the method further includes:
  • the buffer layer 400 is formed by disposing the material of the buffer layer 400 on the light shielding layer 200 .
  • the buffer layer 400 includes one or a combination of SiN x , SiO x and SiO x N y .
  • Step B23 forming an active layer on the light shielding layer, wherein the orthographic projection of the active layer on the substrate is located in the orthographic projection of the light shielding layer on the substrate.
  • the material of the active layer 300 is provided on the buffer layer 400, and the material of the active layer 300 is exposed and etched to form the active layer 300, wherein the orthographic projection 301 of the active layer 300 on the substrate 100 is located in the light shielding layer 200 in orthographic projection 201 on substrate 100.
  • the active layer 300 includes a first active part 310 , a second active part 320 and a third active part 330 which are connected in sequence.
  • the first active part 310 is located on the first light shielding part 210 .
  • the second active part 320 is located on the second light shielding part 220 .
  • the third active part 330 is located on the third light shielding part 230 .
  • the thickness h of the active layer 300 is 30 nm to 70 nm.
  • the thickness h of the active layer 30 may be 30 nanometers, 31 nanometers, 35 nanometers, 38 nanometers, 46 nanometers, 50 nanometers, 60 nanometers, 64 nanometers, 68 nanometers, or 70
  • step B23 it further includes:
  • a shielding layer is used to shield the regions other than the prefabricated first channel region and the prefabricated second channel region, and the prefabricated first channel region and the prefabricated second channel region are doped to form the first channel region 312 and the second prefabricated channel region.
  • Channel region 332 The first channel region 312 is located above the first light shielding portion 210 .
  • the second channel region 332 is located on the third light shielding portion 230 .
  • the first active portion 310 over the first light shielding portion 210 and the third active portion 330 over the third light shielding portion 230 form the first channel region 312 and the second channel region After step B23 of 332, the method further includes:
  • the insulating layer 500 material and the gate electrode 600 material are sequentially stacked on the active layer 300 , and the insulating layer 500 and the gate electrode 600 material are etched to form the insulating layer 500 and the gate electrode 600 .
  • the gate 600 is located on the first active part 310 and the third active part 330 .
  • the material of the insulating layer 500 includes one or a combination of SiO 2 and Six N y .
  • the material of the gate 600 includes one or a combination of Al, Cu, Ag, Au, Mn, Zn and Fe.
  • the method further includes:
  • the gate 600 Taking the gate 600 as a shield, shielding the first channel region 312 and the second channel region 332, and then doping the regions other than the first channel region 312 and the second channel region 332 to form a first conduction region 311 .
  • the first conduction region 311 is located on the first light shielding portion 210 .
  • the first conduction region 311 is located at both ends of the first channel region 312 .
  • the connection conduction region is located on the second light shielding portion 220 .
  • the second conduction region 331 is located on the third light shielding portion 230 .
  • the second conduction region 331 is located at both ends of the second channel region 332 .
  • a barrier layer is used, the barrier layer covers parts of the first conduction region 311 and the second conduction region 331, and the part of the first conduction region 311 and the second conduction region 331 not covered by the barrier layer is doped
  • the dopant forms a second doped region 3112 and a fourth doped region 3312. Parts of the first conducting region 311 and the second conducting region 331 covered by the shielding layer form the first doped region 3111 and the third doped region 3311 .
  • the first doped region 3111 , the second doped region 3112 and the first channel region 312 are located on the first light shielding portion 210 .
  • the first doped regions 3111 are located at both ends of the first channel region 312 .
  • the second doping region 3112 is located at two ends of the first doping region 3111 away from the first channel region 312 .
  • the third doping region 3311 , the fourth doping region 3312 and the second conducting region 331 are located on the third light shielding portion 230 .
  • the third doped regions 3311 are located at both ends of the second channel region 332 .
  • the fourth doping region 3312 is located at two ends of the third doping region 3311 away from the second channel region 332 .
  • a first doping region 3111, a second doping region 3112, a first channel region 312, a third doping region 3311, and a fourth doping region are formed after the step of 3312 and the second channel region 332, it also includes:
  • a passivation layer 700 material and a source and drain layer 800 material are arranged on the gate 600 in sequence, and the passivation layer 700 and the source and drain layers 800 are formed by etching.
  • the passivation layer 700 is provided with through holes 701 .
  • the through hole 701 penetrates the passivation layer 700 and the insulating layer 500 to expose the active layer 300 .
  • the source and drain layers 800 extend into the through holes 701 and are electrically connected to the active layer 300 .
  • the material of the source and drain layers 800 includes one or a combination of Al, Cu, Ag, Au, Mn, Zn and Fe.
  • the present application provides an array substrate and a preparation method thereof.
  • the array substrate includes a base, a light-shielding layer and an active layer.
  • the light-shielding layer is disposed on the base and the active layer is disposed on the light-shielding layer.
  • the projection is in the orthographic projection of the shading layer on the substrate.
  • the orthographic projection of the active layer on the substrate is set to be located in the orthographic projection of the light-shielding layer on the substrate, so as to avoid the phenomenon of climbing and fracture of the active layer, thereby avoiding the deterioration of the electrical properties of the array substrate, and further Guarantee the performance of the array substrate.

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Abstract

本申请提供一种阵列基板，阵列基板包括基底、遮光层以及有源层，遮光层设置在基底上，有源层设置在遮光层上，其中，有源层在基底上的正投影位于遮光层在基底上的正投影中。在本申请中，将有源层在基底上的正投影设置为位于遮光层在基底上的正投影中，避免了有源层出现爬坡断裂的现象，进而保证阵列基板的性能。

Description

阵列基板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板。
 背景技术
目前，有源层通常对光信号（显示设备的背光源等）敏感，不同的光信号会导致薄膜晶体管关态时的电流激增。当这个电流信号足够大时，会导致薄膜晶体管的开关比下降，进一步导致薄膜晶体管阵列异常开启，最终导致显示画面异常。目前通常采用的办法是只在沟道区底部添加遮光层，以遮挡背光源对薄膜晶体管的影响，但是，在有遮光层与无遮光层的交界处将会使得有源层出现爬坡现象，且，有源层材料为非柔性材料，正是由于这种爬坡现象的存在，当有源层在受到后续的蚀刻和激光退火等制程影响时，有源层容易出现变窄或断裂的缺陷，进而造成良率损失，进而影响阵列基板的性能。
 技术问题
本申请实施例提供一种阵列基板，以解决现有技术中在遮光层与有源层的交界处有源层出现爬坡断裂的问题，进而提高阵列基板的性能。
 技术解决方案
本申请实施例提供一种阵列基板，其包括：
基底；
遮光层，所述遮光层设置在所述基底上；以及
有源层，所述有源层设置在所述遮光层上，其中，所述有源层在所述基底上的正投影位于所述遮光层在所述基底上的正投影中。
可选的，在本申请的一些实施例中，所述遮光层包括依次连接的第一遮光部、第二遮光部和第三遮光部，所述第一遮光部和所述第三遮光部位于所述第二遮光部的同侧，所述第一遮光部和所述第三遮光部相对设置。
可选的，在本申请的一些实施例中，所述有源层包括依次连接的第一有源部、第二有源部和第三有源部，第一有源部位于第一遮光部上，第二有源部位于第二遮光部上，第三有源部位于第三遮光部上。
可选的，在本申请的一些实施例中，所述第一有源部包括第一导通区和第一沟道区，所述第一导通区位于所述第一沟道区的两端，所述第三有源部包括第二导通区和第二沟道区，所述第二导通区位于所述第二沟道区的两端。
可选的，在本申请的一些实施例中，所述第一导通区包括第一掺杂区和第二掺杂区，所述第一掺杂区位于所述第一沟道区的两端，所述第二掺杂区位于所述第一掺杂区远离所述第一沟道区的两端，所述第一掺杂区的掺杂浓度小于所述第二掺杂区的掺杂浓度。
可选的，在本申请的一些实施例中，所述第二导通区包括第三掺杂区和第四掺杂区，所述第三掺杂区位于所述第二沟道区的两端，所述第四掺杂区位于所述第三掺杂区远离所述第二沟道区的两端，所述第三掺杂区的掺杂浓度小于所述第四掺杂区的掺杂浓度。
可选的，在本申请的一些实施例中，所述第一遮光部的平面形状设置有第一凸起，所述第一凸起的凸起方向与所述第一沟道区的延伸方向垂直，所述第一凸起位于对应设置有所述第一掺杂区的第一遮光部的区域；所述第三遮光部的平面形状设置有第二凸起，所述第二凸起的凸起方向与所述第二沟道区的延伸方向垂直，且所述第二凸起位于对应设置有所述第三掺杂区的第三遮光部的区域。
可选的，在本申请的一些实施例中，所述有源层的第一掺杂区和第三掺杂区之外的区域的正投影边缘与所述遮光层的正投影边缘重叠。
可选的，在本申请的一些实施例中，所述遮光层还包括第四遮光部，所述第四遮光部与所述第一遮光部、所述第二遮光部以及所述第三遮光部连接。
可选的，在本申请的一些实施例中，所述第一遮光部、所述第三遮光部和所述第四遮光部位于所述第二遮光部的同侧，且所述第四遮光部位于所述第一遮光部和所述第三遮光部之间。
可选的，在本申请的一些实施例中，所述遮光层包括依次连接的第一遮光部、第二遮光部和第三遮光部，所述第一遮光部和所述第三遮光部位于所述第二遮光部的不同侧。
可选的，在本申请的一些实施例中，所述有源层包括依次连接的第一有源部、第二有源部和第三有源部，第一有源部位于第一遮光部上，第二有源部位于第二遮光部上，第三有源部位于第三遮光部上。
可选的，在本申请的一些实施例中，所述第二有源部包括第三导通区和第三沟道区，所述第三导通区位于所述第三沟道区的两端，所述第一有源部和所述第三有源部为第四导通区。
可选的，在本申请的一些实施例中，所述第二遮光部设置有第三凸起，所述第三凸起的凸起方向与所述第三沟道区的延伸方向垂直，所述第三凸起位于对应设置有第三导通区的第二遮光部的区域。
可选的，在本申请的一些实施例中，所述有源层的第三导通区之外的区域的正投影边缘与所述遮光层的正投影边缘重叠。
可选的，在本申请的一些实施例中，所述第三沟道区的掺杂浓度小于所述第三导通区的掺杂浓度，所述第三导通区的掺杂浓度小于所述第四导通区的掺杂浓度。
可选的，在本申请的一些实施例中，所述第三导通区在所述基底上的正投影边缘到所述遮光层在所述基底上的正投影边缘的距离为400纳米-2000纳米。
可选的，在本申请的一些实施例中，所述第一掺杂区在所述基底上的正投影边缘以及所述第三掺杂区在所述基底上的正投影边缘到所述遮光层在所述基底上的正投影边缘的距离均为400纳米-2000纳米。
可选的，在本申请的一些实施例中，所述有源层在所述基底上的正投影边缘到所述遮光层在所述基底上的正投影边缘的距离为0纳米-6000纳米。
可选的，在本申请的一些实施例中，所述有源层的厚度为30纳米-70纳米。
 有益效果
本申请提供一种阵列基板，阵列基板包括基底、遮光层以及有源层，所述遮光层设置在所述基底上，所述有源层设置在所述遮光层上，其中，所述有源层在所述基底上的正投影位于所述遮光层在所述基底上的正投影中。在本申请中，将所述有源层在所述基底上的正投影设置为位于所述遮光层在所述基底上的正投影中，避免了有源层出现爬坡断裂的现象，进而保证阵列基板的性能。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术的阵列基板的俯视示意图。
图2为图1中的阵列基板沿AB线的截面示意图。
图3为本申请实施例提供的阵列基板的第一种实施方式的俯视示意图。
图4为图3中的阵列基板沿CD线的截面示意图。
图5为本申请实施例提供的阵列基板的第二种实施方式的俯视示意图。
图6为图5中的阵列基板沿DE线的截面示意图。
图7为本申请实施例提供的阵列基板的第三种实施方式的俯视示意图。
图8为本申请实施例提供的阵列基板的第四种实施方式的俯视示意图。
图9为图8中的阵列基板沿EF线的截面示意图。
图10为本申请实施例提供的阵列基板的第五种实施方式的俯视示意图。
图11为本申请实施例提供的阵列基板的第六种实施方式的俯视示意图。
图12为本申请实施例提供的阵列基板的制备方法的流程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1和图2，图1为现有技术的阵列基板的俯视示意图。图2为图1中的阵列基板沿AB线的截面示意图。现有技术中的阵列基板10包括衬底11、遮光层12、缓冲层13、有源层14、绝缘层15、栅极16、钝化层17和源漏极层18。缓冲层13设置于遮光层12上。有源层14设置于缓冲层13上。绝缘层15完全覆盖有源层14。栅极16设置于绝缘层15上。钝化层17覆盖在绝缘层15和栅极16上，源漏极层18设置于钝化层17上，并与有源层14电连接。现有技术中提供的阵列基板10，有源层14在有遮光层12和无遮光层12交界处的上方出现爬坡现象，进而造成有源层14厚度不均，甚至有源层14出现断裂的风险，进而影响阵列基板的性能。
因此，本申请提出一种阵列基板，以解决现有技术中阵列基板存在的问题。
请参阅图3和图4，图3为本申请实施例提供的阵列基板的第一种实施方式的俯视示意图。图4为图3中的阵列基板沿CD线的截面示意图。本申请提供一种阵列基板20。阵列基板20包括基底100、遮光层200以及有源层300。具体描述如下：
基底100的材料可以为聚酰亚胺或玻璃等。
遮光层200设置在基底100上。遮光层200包括依次连接的第一遮光部210、第二遮光部220和第三遮光部230。第一遮光部210和第三遮光部230位于第二遮光部220的同侧，第一遮光部210和第三遮光部230相对设置。遮光层200的材料包括金属材料和绝缘材料，其中，金属材料可以为Al、Cu、Ag、Au、Mn、Zn和Fe中的一种或几种组合，绝缘材料包括SiN x、SiO x和SiO xN y中的一种或几种组合。遮光层200的厚度H为50纳米-500纳米。具体的，遮光层200的厚度H可以为50纳米、52纳米、70纳米、200纳米、350纳米、430纳米、470纳米、490纳米或500纳米等。遮光层200的形状可以为正方形、矩形或圆形等。
在本申请中，将第一遮光部210和第三遮光部230设置为位于第二遮光部220的同侧，简化了制备工艺，并减低生产成本。
在一实施例中，遮光层200朝向基底100的表面为一粗糙面，粗糙面用于将背光源出射至遮光层200的光线反射回背光源中，降低光耗损失，并提高遮光层200的遮光效果。
在一实施例中，阵列基板20还包括缓冲层400。缓冲层400设置在遮光层200上。缓冲层400包括SiN x、SiO x和SiO xN y中的一种或几种组合。
有源层300设置在遮光层200上。具体的，有源层300设置在缓冲层400上。在一实施例中，有源层300的厚度h为30纳米-70纳米。有源层300的厚度h可以为30纳米、31纳米、35纳米、38纳米、46纳米、50纳米、60纳米、64纳米、68纳米或70纳米等。
在一实施例中，有源层300的材料包括非晶硅和多晶硅中的一种。
在一实施例中，有源层300在基底100上的正投影301位于遮光层200在基底100上的正投影201中。
在一实施例中，有源层300在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离L为0纳米-6000纳米。具体的，有源层300在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离L可以为0纳米、0.1纳米、1纳米、10纳米、1000纳米、2500纳米、4000纳米、5000纳米、5800纳米或6000纳米等。
在一实施例中，有源层300在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离L设置为0纳米时，使得遮光层200正好完全遮盖有源层300，进而降低成本。
在一实施例中，有源层300包括依次连接的第一有源部310、第二有源部320和第三有源部330。第一有源部310位于第一遮光部210之上。第二有源部320位于第二遮光部220之上。第三有源部330位于第三遮光部230之上。
请参阅图5和图6，图5为本申请实施例提供的阵列基板的第二种实施方式的俯视示意图。图6为图5中的阵列基板沿DE线的截面示意图。需要说明的是，第二种实施方式与第一种实施方式的不同之处在于：
阵列基板20还包括绝缘层500、栅极600、钝化层700和源漏极层800。绝缘层500覆盖有源层300。绝缘层500的材料包括SiO 2和Si xN y中的一种或几种组合。栅极600设置于绝缘层500上，且，栅极600位于第一有源部310和第三有源部330之上。栅极600的材料包括Al、Cu、Ag、Au、Mn、Zn和Fe中的一种或几种组合。钝化层700覆盖绝缘层500和栅极600。钝化层700设置有通孔701。通孔701贯穿钝化层700和绝缘层500以暴露有源层300。源漏极层800设置于钝化层700上，并延伸入通孔701与有源层300电连接。源漏极层800的材料包括Al、Cu、Ag、Au、Mn、Zn和Fe中的一种或几种组合。
在本申请中，将有源层在基底上的正投影设置为位于遮光层在基底上的正投影中，即，在有源层下设置整面遮光层，进而避免了有源层出现爬坡断裂或厚度不均的现象，进而避免阵列基板的电性恶化，进而保证阵列基板的性能；另外，因有源层被遮光层包裹，使得遮光层的厚度可以加厚，从而提高遮光层的遮光效果，从而保证阵列基板的性能；因有源层全部设置于遮光层上，进而不会出现变窄或断裂的现象，进而在一些特殊器件中，有源层的厚度减薄限制可以放宽，进而降低生产成本。
请参阅图7，图7为本申请实施例提供的阵列基板的第三种实施方式的俯视示意图，需要说明的是，第三种实施方式和第二种实施方式的不同之处在于：
遮光层200还包括第四遮光部240。第四遮光部240与第一遮光部210、第二遮光部220以及第三遮光部230连接。第一遮光部210、第三遮光部230和第四遮光部240位于第二遮光部220的同侧，且第四遮光部240位于第一遮光部210和第三遮光部230之间，其它结构如第二种实施方式所述，此处不再赘述。
在本申请中，在第一遮光部210和第三遮光部230之间设置第四遮光部240，使得遮光层200的遮光范围增大，进一步提高遮光效果，进而保证阵列基板20的性能。
请参阅图8和图9，图8为本申请实施例提供的阵列基板的第四种实施方式的俯视示意图。图9为图8中的阵列基板沿EF线的截面示意图。需要说明的是，第四种实施方式的和第二种实施方式的不同之处在于：
第一有源部310由第一导通区311和第一沟道区312组成。第一导通区311位于第一沟道区312的两端。
在一实施例中，第三有源部330由第二导通区331和第二沟道区332组成。第二导通区331位于第二沟道区332的两端。第二有源部320为连接导通区。第二有源部320连接第一导通区311和第二导通区331。
在一实施例中，第一导通区311、连接导通区和第二导通区331掺杂有磷和砷中的一种或两种组合，改变了第一导通区311、连接导通区和第二导通区331阵列基板20的电阻，进而提高了阵列基板20的性能。
在一实施例中，第一导通区311包括第一掺杂区3111和第二掺杂区3112。第一掺杂区3111位于第一沟道区312的两端。第二掺杂区3112位于第一掺杂区3111远离第一沟道区312的两端。第一掺杂区3111的掺杂浓度小于第二掺杂区3112的掺杂浓度。
在一实施例中，第一掺杂区3111的掺杂浓度均为3e 12～3e 13每平方厘米。第二掺杂区3112的掺杂浓度均为3e 14～3e 15每平方厘米。
在一实施例中，至少第一掺杂区3111在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W为400纳米-2000纳米。
在本申请中，将至少第一掺杂区3111在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W设置为400纳米-2000纳米，使得遮光层200正好完全遮盖第一掺杂区3111，进而使得提高遮光效果的同时，提高像素的开口率以及降低成本。
在一实施例中，至少第一掺杂区3111在基底100上的正投影301边缘的一边以及至少第一沟道区312在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W可以均设置为400纳米-2000纳米，有源层300在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离L设置为0纳米。
在本申请中，将第一掺杂区3111在基底100上的正投影301边缘的一边以及至少第一沟道区312在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W可以均设置为400纳米-2000纳米，而将遮光层200设置为正好全部遮盖有源层300，使得提高遮光效果的同时，降低成本以及有源层300出现断裂的问题。
在一实施例中，第一沟道区312的掺杂浓度小于第一掺杂区3111的掺杂浓度。
在一实施例中，第一沟道区312中掺杂有硼和镓中的一种或两种组合，改变了第一沟道区312的电阻，但并不影响第一沟道区312本身的性能，进而提高阵列基板20的性能。
在本申请中，将第一掺杂区3111和第二掺杂区3112的掺杂浓度设置为不同，从而使得第一掺杂区3111为电阻过渡区，从而提高阵列基板20的性能。
在一实施例中，第一遮光部210的平面形状设置有第一凸起211。第一凸起211的凸起方向与第一沟道区312的纵向延伸方向垂直。第一凸起位于对应设置有第一掺杂区3111的第一遮光部210的区域。
在一实施例中，第一遮光部210的平面形状设置有第一凸起211。第一凸起211的凸起方向与第一沟道区312的纵向延伸方向垂直。在第一凸起位于对应设置有第一掺杂区3111和第一沟道区312的第一遮光部210的区域。
在一实施例中，第二导通区331包括第三掺杂区3311和第四掺杂区3312。第三掺杂区3311位于第二沟道区332的两端。第四掺杂区3312位于第三掺杂区3311远离第二沟道区332的两端。第三掺杂区3311的掺杂浓度小于第四掺杂区3312的掺杂浓度。
在一实施例中，第三掺杂区3311的掺杂浓度均为3e 12～3e 13每平方厘米。第四掺杂区3312的掺杂浓度均为3e 14～3e 15每平方厘米。
在一实施例中，第二沟道区332的掺杂浓度小于第三掺杂区3311的掺杂浓度。
在一实施例中，第二沟道区332中掺杂有硼和镓中的一种或两种组合，改变了第二沟道区332的电阻，但并不影响第二沟道区332本身的性能，进而提高阵列基板20的性能。
在本申请中，将第三掺杂区3311和第四掺杂区3312的掺杂浓度设置为不同，从而使得第三掺杂区3311为电阻过渡区，从而提高阵列基板20的性能。
在一实施例中，至少第三掺杂区3311在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W为400纳米-2000纳米。
在本申请中，将至少第三掺杂区3311在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W设置为400纳米-2000纳米，使得遮光层200正好完全遮盖第三掺杂区3311，使得提高遮光层200遮光效果的同时，降低成本。
在一实施例中，至少第三掺杂区3311在基底100上的正投影301边缘的一边以及至少第二沟道区332在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W可以均设置为400纳米-2000纳米，有源层300在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离L设置为0纳米。
在本申请中，将第三掺杂区3311在基底100上的正投影301边缘的一边以及至少第二沟道区332在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离W可以均设置为400纳米-2000纳米，而将遮光层200设置为正好全部遮盖有源层300，使得进一步提高遮光效果的同时，避免有源层300出现断裂的问题以及降低成本。
在一实施例中，第三遮光部230的平面形状设置有第二凸起231。第二凸起231的凸起方向与第二沟道区332的纵向延伸方向垂直。第一凸起位于对应设置有第三掺杂区3311的第三遮光部230的区域。
在一实施例中，第三遮光部230的平面形状设置有第二凸起231。第二凸起231的凸起方向与第二沟道区332的纵向延伸方向垂直。第二凸起231位于对应设置有第三掺杂区3311和第二沟道区332的第三遮光部230的区域。
在一实施例中，有源层300的第一掺杂区3111和第三掺杂区3311之外的区域的正投影301边缘与遮光层200的正投影201边缘重叠。有源层300的第一掺杂区3111和第三掺杂区3311之外的区域包括第二掺杂区3112、第二有源部320和第四掺杂区域3312。
在一实施例中，第一掺杂区3111在基底100上的正投影301边缘以及第三掺杂区3311在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离W均为400纳米-2000纳米。具体的，第一掺杂区3111在基底100上的正投影301边缘以及第三掺杂区3311在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离W可以为400纳米、500纳米、800纳米、1500纳米、1900纳米或2000纳米等。在本实施例中，第一掺杂区3111在基底100上的正投影301边缘以及第三掺杂区3311在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离W为500纳米。
在本申请中，将第一掺杂区3111在基底100上的正投影301边缘以及第三掺杂区3311在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离W均设置为400纳米-2000纳米，可以遮挡进入第一掺杂区3111和第三掺杂区3311的光线，从而进一步避免有源层300出现漏电情况，从而提高阵列基板20的性能。
在一实施例中，栅极600位于第一沟道区312和第二沟道区332之上。第一掺杂区3111和第三掺杂区3311设置于缓冲层400靠近栅极600的一侧。第二掺杂区3112和第四掺杂区3312位于缓冲层400远离栅极600的一侧。
在本申请中，对第一掺杂区3111和第三掺杂区3311进行轻掺杂，对第二掺杂区3112、第四掺杂区3312以及第二有源部320进行重掺杂，可以防止阵列基板20出现漏电问题，进而提高了阵列基板20的性能。
请参阅图10，图10为本申请实施例提供的阵列基板的第五种实施方式的俯视示意图。需要说明的是，第五种实施方式的和第四种实施方式的不同之处在于：
遮光层200还包括第四遮光部240。第四遮光部240与第一遮光部210、第二遮光部220以及第三遮光部230连接。第一遮光部210、第三遮光部230和第四遮光部240位于第二遮光部220的同侧，且第四遮光部240位于第一遮光部210和第三遮光部230之间，其它结构如第四种实施方式所述，此处不再赘述。
在本申请中，在第一遮光部210和第三遮光部230之间设置第四遮光部240，使得遮光层200的遮光范围增大，进一步提高遮光效果，进而保证阵列基板20的性能。
请参阅图11，图11为本申请实施例提供的阵列基板的第六种实施方式的俯视示意图。需要说明的是，第六种实施方式的和第四种实施方式的不同之处在于：
第一遮光部210和第三遮光部230位于第二遮光部220的不同侧。
在一实施例中，第二有源部320包括第三导通区321和第三沟道区322。第三导通区321位于第三沟道区322的两端。第一有源部310和第三有源部330为第四导通区。第三沟道区322掺杂有硼和镓中的一种或两种组合，改变了第三沟道区322的电阻，但并不影响第三沟道区322本身的性能，进而提高阵列基板20的性能。第三导通区321、第一有源部310和第三有源部330掺杂有磷和砷中的一种或两种组合，进而提高第三导通区321、第一有源部310和第三有源部330的电性。
在一实施例中，第三沟道区322的掺杂浓度小于第三导通区321的掺杂浓度。第三导通区321的掺杂浓度小于第四导通区的掺杂浓度。
在一实施例中，第二遮光部220的平面形状设置有第三凸起221。第三凸起221的凸起方向与第三沟道区322的横向延伸方向垂直第三凸起221位于对应设置有第三导通区321的第二遮光部220的区域。
在一实施例中，第二遮光部220的平面形状设置有第三凸起221。第三凸起221的凸起方向与第三沟道区322的横向延伸方向垂直。第三凸起221位于对应设置有第三导通区321和第三沟道区322的第二遮光部220的区域。
在一实施例中，有源层300的第三导通区321之外的区域的正投影301边缘与遮光层200的正投影201边缘重叠。有源层300的第三导通区321之外的区域包括第一有源部310和第三有源部330。
在一实施例中，至少第三导通区321在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离D为400纳米-2000纳米。在本申请中，将至少第三导通区321在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离D设置为400纳米-2000纳米，使得遮光层200正好完全遮盖第三导通区321，使得提高遮光层200遮光效果的同时，降低成本。
在一实施例中，至少第三导通区321在基底100上的正投影301边缘的一边以及至少第三沟道区322在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离D可以均设置为400纳米-2000纳米，有源层300在基底100上的正投影301边缘到遮光层200在基底100上的正投影201边缘的距离L设置为0纳米。
在本申请中，将第三导通区321在基底100上的正投影301边缘的一边以及至少第三沟道区322在基底100上的正投影301边缘的一边到遮光层200在基底100上的正投影201边缘的距离D可以均设置为400纳米-2000纳米，而将遮光层200设置为正好全部遮盖有源层300，使得进一步提高第三导通区321和第三沟道区322的遮光效果同时，降低成本以及避免第三导通区321和第三沟道区322交界处出现断裂的问题。
栅极600位于第三沟道区322之上。
本申请中的阵列基板20可以应用于手机、显示器、电脑以及电视中。
请参阅图5、图6和图12，图5为本申请实施例提供的阵列基板的第二种实施方式的俯视示意图。图6为图5中的阵列基板沿DE线的截面示意图。图12为本申请实施例提供的阵列基板的制备方法的流程示意图。本申请还提供一种阵列基板20的制备方法，具体描述如下：
步骤B21：提供一基底。
对基底100进行预清洗。基底100的材料可以为聚酰亚胺或玻璃等。
步骤B22：在基底上形成遮光层。
具体的，在基底100上沉积遮光层200材料，对遮光层200材料进行曝光和蚀刻处理形成图案化的遮光层200。具体的，遮光层200包括第一遮光部210、第二遮光部220、第三遮光部230和第四遮光部240。第一遮光部210、第二遮光部220和第三遮光部230依次连接。第一遮光部210、第三遮光部230和第四遮光部240位于第二遮光部220的同侧。第一遮光部210和第三遮光部230相对设置。第四遮光部240位于第一遮光部210和第三遮光部230之间。遮光层200的材料包括金属材料和绝缘材料，其中，金属材料可以为Al、Cu、Ag、Au、Mn、Zn和Fe中的一种或几种组合。遮光层200的厚度H为50纳米-500纳米。具体的，遮光层200的厚度H可以为50纳米、52纳米、70纳米、200纳米、350纳米、430纳米、470纳米、490纳米或500纳米等。
在本申请中，遮光层200包括第一遮光部210、第二遮光部220、第三遮光部230和第四遮光部240，使得遮光层200的遮光范围增大，进一步提高遮光效果，进而保证阵列基板20的性能。
在一实施例中，在步骤B22之后，还包括：
对遮光层200进行蚀刻处理，去除第四遮光部240。
在本申请中，去除第四遮光部240，并将第一遮光部210和第三遮光部230设置为位于第二遮光部220的同侧，简化了制备工艺，并提高了像素的开口率以及降低了生产成本。
在一实施例中，在对遮光层200进行蚀刻处理，去除第四遮光部240的步骤之后，还包括：
在遮光层200上设置缓冲层400材料形成缓冲层400。缓冲层400包括SiN x、SiO x和SiO xN y中的一种或几种组合。
步骤B23：在遮光层上形成有源层，其中，有源层在基底上的正投影位于遮光层在基底上的正投影中。
具体的，在缓冲层400上设置有源层300材料，对有源层300的材料进行曝光和蚀刻处理形成有源层300，其中，有源层300在基底100上的正投影301位于遮光层200在基底100上的正投影201中。有源层300包括依次连接的第一有源部310、第二有源部320和第三有源部330。第一有源部310位于第一遮光部210之上。第二有源部320位于第二遮光部220之上。第三有源部330位于第三遮光部230之上。有源层300的厚度h为30纳米-70纳米。有源层30的厚度h可以为30纳米、31纳米、35纳米、38纳米、46纳米、50纳米、60纳米、64纳米、68纳米或70纳米等。
在一实施例中，在步骤B23之后，还包括：
采用一遮挡层，遮挡预制第一沟道区和预制第二沟道区以外的区域，对预制第一沟道区和预制第二沟道区进行掺杂形成第一沟道区312和第二沟道区332。第一沟道区312位于第一遮光部210之上。第二沟道区332位于第三遮光部230之上。
在一实施例中，在第一遮光部210之上的第一有源部310以及在第三遮光部230之上的第三有源部330形成第一沟道区312以及第二沟道区332的步骤B23之后，还包括：
在有源层300上依次层叠设置绝缘层500材料和栅极600材料，对绝缘层500和栅极600材料进行蚀刻处理，形成绝缘层500和栅极600。栅极600位于第一有源部310和第三有源部330之上。绝缘层500的材料包括SiO 2和Si xN y中的一种或几种组合。栅极600的材料包括Al、Cu、Ag、Au、Mn、Zn和Fe中的一种或几种组合。
在一实施例中，在有源层300上依次层叠设置绝缘层500和栅极600步骤之后，还包括：
以栅极600为遮挡，遮挡第一沟道区312和第二沟道区332，然后，对第一沟道区312和第二沟道区332以外的区域进行掺杂形成第一导通区311、连接导通区和第二导通区331。第一导通区311位于第一遮光部210之上。第一导通区311位于第一沟道区312的两端。连接导通区位于第二遮光部220之上。第二导通区331位于第三遮光部230之上。第二导通区331位于第二沟道区332的两端。
然后，采用一道阻挡层，阻挡层遮盖第一导通区311和第二导通区331的部分区域，对未被阻挡层遮盖的部分第一导通区311和第二导通区331进行掺杂形成第二掺杂区3112和第四掺杂区3312。被遮挡层遮盖的部分第一导通区311和第二导通区331形成第一掺杂区3111和第三掺杂区3311。
第一掺杂区3111、第二掺杂区3112和第一沟道区312位于第一遮光部210之上。第一掺杂区3111位于第一沟道区312的两端。第二掺杂区3112位于第一掺杂区3111远离第一沟道区312的两端。
第三掺杂区3311、第四掺杂区3312和第二导通区331位于第三遮光部230之上。第三掺杂区3311位于第二沟道区332的两端。第四掺杂区3312位于第三掺杂区3311远离第二沟道区332的两端。
在一实施例中，在对有源层300进行掺杂后形成第一掺杂区3111、第二掺杂区3112、第一沟道区312、第三掺杂区3311、第四掺杂区3312和第二沟道区332的步骤之后，还包括：
在栅极600上依次设置钝化层700材料和源漏极层800材料，蚀刻形成钝化层700和源漏极层800。钝化层700设置有通孔701。通孔701贯穿钝化层700和绝缘层500以暴露有源层300。源漏极层800延伸入通孔701与有源层300电连接。源漏极层800的材料包括Al、Cu、Ag、Au、Mn、Zn和Fe中的一种或几种组合。
本申请提供一种阵列基板及其制备方法，阵列基板包括基底、遮光层以及有源层，遮光层设置在基底上，有源层设置在遮光层上，其中，有源层在基底上的正投影位于遮光层在基底上的正投影中。在本申请中，将有源层在基底上的正投影设置为位于遮光层在基底上的正投影中，避免了有源层出现爬坡断裂的现象，进而避免了阵列基板电性恶化，进而保证阵列基板的性能。
以上对本申请实施方式进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其包括：
    基底；
    遮光层，所述遮光层设置在所述基底上；以及
    有源层，所述有源层设置在所述遮光层上，其中，所述有源层在所述基底上的正投影位于所述遮光层在所述基底上的正投影中。
  2. 根据权利要求1所述的阵列基板，其中，所述遮光层包括依次连接的第一遮光部、第二遮光部和第三遮光部，所述第一遮光部和所述第三遮光部位于所述第二遮光部的同侧，所述第一遮光部和所述第三遮光部相对设置。
  3. 根据权利要求2所述的阵列基板，其中，所述有源层包括依次连接的第一有源部、第二有源部和第三有源部，第一有源部位于第一遮光部上，第二有源部位于第二遮光部上，第三有源部位于第三遮光部上。
  4. 根据权利要求3所述的阵列基板，其中，所述第一有源部包括第一导通区和第一沟道区，所述第一导通区位于所述第一沟道区的两端，所述第三有源部包括第二导通区和第二沟道区，所述第二导通区位于所述第二沟道区的两端。
  5. 根据权利要求4所述的阵列基板，其中，所述第一导通区包括第一掺杂区和第二掺杂区，所述第一掺杂区位于所述第一沟道区的两端，所述第二掺杂区位于所述第一掺杂区远离所述第一沟道区的两端，所述第一掺杂区的掺杂浓度小于所述第二掺杂区的掺杂浓度。
  6. 根据权利要求5所述的阵列基板，其中，所述第二导通区包括第三掺杂区和第四掺杂区，所述第三掺杂区位于所述第二沟道区的两端，所述第四掺杂区位于所述第三掺杂区远离所述第二沟道区的两端，所述第三掺杂区的掺杂浓度小于所述第四掺杂区的掺杂浓度。
  7. 根据权利要求6所述的阵列基板，其中，所述第一遮光部的平面形状设置有第一凸起，所述第一凸起的凸起方向与所述第一沟道区的延伸方向垂直，所述第一凸起位于对应设置有所述第一掺杂区的第一遮光部的区域；所述第三遮光部的平面形状设置有第二凸起，所述第二凸起的凸起方向与所述第二沟道区的延伸方向垂直，且所述第二凸起位于对应设置有所述第三掺杂区的第三遮光部的区域。
  8. 根据权利要求7所述的阵列基板，其中，所述有源层的第一掺杂区和第三掺杂区之外的区域的正投影边缘与所述遮光层的正投影边缘重叠。
  9. 根据权利要求2所述的阵列基板，其中，所述遮光层还包括第四遮光部，所述第四遮光部与所述第一遮光部、所述第二遮光部以及所述第三遮光部连接。
  10. 根据权利要求9所述的阵列基板，其中，所述第一遮光部、所述第三遮光部和所述第四遮光部位于所述第二遮光部的同侧，且所述第四遮光部位于所述第一遮光部和所述第三遮光部之间。
  11. 根据权利要求1所述的阵列基板，其中，所述遮光层包括依次连接的第一遮光部、第二遮光部和第三遮光部，所述第一遮光部和所述第三遮光部位于所述第二遮光部的不同侧。
  12. 根据权利要求11所述的阵列基板，其中，所述有源层包括依次连接的第一有源部、第二有源部和第三有源部，第一有源部位于第一遮光部上，第二有源部位于第二遮光部上，第三有源部位于第三遮光部上。
  13. 根据权利要求12所述的阵列基板，其中，所述第二有源部包括第三导通区和第三沟道区，所述第三导通区位于所述第三沟道区的两端，所述第一有源部和所述第三有源部为第四导通区。
  14. 根据权利要求13所述的阵列基板，其中，所述第二遮光部设置有第三凸起，所述第三凸起的凸起方向与所述第三沟道区的延伸方向垂直，所述第三凸起位于对应设置有第三导通区的第二遮光部的区域。
  15. 根据权利要求14所述的阵列基板，其中，所述有源层的第三导通区之外的区域的正投影边缘与所述遮光层的正投影边缘重叠。
  16. 根据权利要求13所述的阵列基板，其中，所述第三沟道区的掺杂浓度小于所述第三导通区的掺杂浓度，所述第三导通区的掺杂浓度小于所述第四导通区的掺杂浓度。
  17. 根据权利要求13所述的阵列基板，其中，所述第三导通区在所述基底上的正投影边缘到所述遮光层在所述基底上的正投影边缘的距离为400纳米-2000纳米。
  18. 根据权利要求6所述的阵列基板，其中，所述第一掺杂区在所述基底上的正投影边缘以及所述第三掺杂区在所述基底上的正投影边缘到所述遮光层在所述基底上的正投影边缘的距离均为400纳米-2000纳米。
  19. 根据权利要求1所述的阵列基板，其中，所述有源层在所述基底上的正投影边缘到所述遮光层在所述基底上的正投影边缘的距离为0纳米-6000纳米。
  20. 根据权利要求1所述的阵列基板，其中，所述有源层的厚度为30纳米-70纳米。
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