WO2022200712A1 - Procede de fabrication d'une structure composite comprenant une couche mince en semi-conducteur monocristallin sur un substrat support - Google Patents
Procede de fabrication d'une structure composite comprenant une couche mince en semi-conducteur monocristallin sur un substrat support Download PDFInfo
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- WO2022200712A1 WO2022200712A1 PCT/FR2022/050454 FR2022050454W WO2022200712A1 WO 2022200712 A1 WO2022200712 A1 WO 2022200712A1 FR 2022050454 W FR2022050454 W FR 2022050454W WO 2022200712 A1 WO2022200712 A1 WO 2022200712A1
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- donor substrate
- thermal budget
- substrate
- composite structure
- thin layer
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Definitions
- TITLE METHOD FOR MANUFACTURING A COMPOSITE STRUCTURE COMPRISING A THIN LAYER OF MONOCRYSTALLINE SEMICONDUCTOR
- the present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a process for manufacturing a composite structure comprising a thin layer of monocrystalline semiconductor material placed on a support substrate: the thin layer can for example be made of monocrystalline silicon carbide and the support substrate of polysilicon carbide -crystalline.
- Silicon carbide (SiC) is increasingly widely used for the manufacture of innovative power devices, meeting the needs of rising areas of electronics, such as electric vehicles.
- power devices and integrated power systems based on monocrystalline silicon carbide can handle much higher power density compared to their traditional silicon counterparts, and this with smaller active area dimensions.
- vertical electrical conduction, between an electrode arranged on the front face of the Sic structure and an electrode arranged on the rear face must be permitted by said structure.
- Monocrystalline SiC substrates intended for the microelectronics industry nevertheless remain expensive and difficult to supply in large sizes. It is therefore advantageous to resort to thin layer transfer solutions, to produce composite structures typically comprising a thin monocrystalline SiC layer on a lower cost support substrate.
- a well-known thin film transfer solution is the Smart CutTM process, based on light ion implantation and direct bonding assembly.
- Such a process makes it possible, for example, to manufacture a composite structure comprising a thin layer of monocrystalline SiC (c-SiC), taken from a donor substrate of c-SiC, in direct contact with a support substrate of polycrystalline SiC (p- SiC), and allowing vertical electrical conduction. It nevertheless remains difficult to achieve direct bonding by molecular adhesion of good quality between two c-SiC and p-SiC substrates, because the management of the roughness and the surface condition of said substrates is complex.
- c-SiC monocrystalline SiC
- p- SiC polycrystalline SiC
- the document US8436363 overcomes bonding by molecular adhesion by proposing a process for manufacturing a composite structure comprising a thin layer of c-SiC placed on a metal support substrate whose coefficient of thermal expansion is matched with that of the thin layer. .
- This manufacturing process includes the following steps:
- a metal layer for example tungsten or molybdenum
- Such a manufacturing process is however not compatible when the material forming the support substrate is p-SiC requiring deposition at temperatures above 1000°C, or even above or equal to 1200°C (normal temperatures for the manufacture of p-SiC). Indeed, at these high temperatures, the growth kinetics of the cavities and microcracks present in the buried fragile plane is faster than the growth kinetics of the p-SiC layer, and the thickness required for a stiffening effect is not not reached before the appearance of the bubbling phenomenon, linked to the deformation of the thin layer directly above the microcracks.
- the kinetics of bubbling and the kinetics of fracture depend on the properties of the buried fragile plane, defined by the nature of the semiconductor material and by the ion implantation conditions applied to the donor substrate: in particular, the energy of the implantation of the light species defines the depth of the buried fragile plane, and the implanted dose defines the quantity of species capable of forming, developing microcavities and putting them under pressure by thermal activation; other implantation parameters, including temperature, will also influence the properties of the buried fragile plane and the associated bubbling and fracture kinetics.
- the bubbling appears when there is not a sufficient stiffening effect on the free face of the donor substrate, the fracture is obtained when there is a sufficient stiffening effect on this free face to allow the microcracks to join in the plane buried brittle, without deforming the layer above, thereby causing complete separation along said buried brittle plane.
- the present invention addresses the aforementioned problem. It relates to a method for manufacturing a composite structure comprising a thin layer of a semiconductor material monocrystalline arranged on a support substrate of lower quality, the composite structure being capable, in addition, of providing vertical electrical conduction between the thin layer and the support substrate.
- the invention relates to a method for manufacturing a composite structure comprising a thin layer of monocrystalline semiconductor material placed on a support substrate, the method comprising: a) a step of supplying a donor substrate composed of the semi-conductor material single-crystal conductor, b) a step of ion implantation of light species in the donor substrate, excluding an annular peripheral zone of said substrate, according to implantation conditions, to form a buried fragile plane delimiting the thin layer between the buried fragile plane and a front face of the donor substrate, the buried fragile plane comprising lenticular microcavities capable of developing by thermal activation in the form of microcracks,
- the implantation conditions defining a first thermal budget for obtaining bubbling on the front face of the donor substrate, and a second thermal budget for obtaining a fracture in the buried fragile plane
- a step of depositing a support substrate on the front face of the donor substrate provided with the stiffening film carried out by applying a thermal budget greater than the first thermal budget
- a separation step to form on the one hand the composite structure and on the other hand the rest of the donor substrate.
- the annular peripheral zone of the donor substrate, at which the ion implantation of step b) is not carried out, has a width of between 1mm and 2cm;
- step d) is carried out by applying a thermal budget greater than or equal to the second thermal budget
- the monocrystalline semiconductor material of the donor substrate is chosen from silicon carbide, silicon, germanium, a III-V or III-N compound, diamond, gallium oxide;
- the stiffening film comprises a material chosen from tungsten, silicon carbide, silicon, silicon nitride, boron nitride, silicon oxide, aluminum oxide, aluminum nitride;
- step c) comprises one or more sequence(s) of deposition, bonding, photolithography, nano-imprinting, etching and/or thinning;
- the thickness of the perforated stiffening film is between 0.5 micron and 5 microns;
- the support substrate has a monocrystalline or polycrystalline structure, and comprises at least one material chosen from silicon carbide, silicon, diamond, III-V or III-N compounds such as gallium nitride, oxide gallium;
- the support substrate has a thickness greater than or equal to 50 microns
- the manufacturing process comprises a step f) of mechanical (s) and/or chemical (s) and/or thermal (s) treatment(s) of the composite structure, to smooth the free surface of the thin layer and/or to improve the quality of the edges of the composite structure and/or to correct the thickness uniformity of the composite structure;
- step f) one (or more) mechanical (s) or chemical (s) treatment(s) of step f) are carried out before step e) of separation to improve the quality of the edges of a stack resulting from step d) and/or to correct the thickness uniformity of the support substrate;
- the manufacturing process comprises a step of reconditioning the remainder of the donor substrate with a view to reuse as donor substrate.
- the invention also relates to a composite structure resulting from the manufacturing method as above, comprising a power component all or part of which is formed on and/or in the thin layer, and comprising a metal electrode on a rear face of the substrate support.
- FIG. 1 shows a composite structure developed according to a manufacturing method according to the invention
- FIG. 2f Figures 2a, 2a', 2b, 2c, 2d, 2e and 2f show steps of a manufacturing method according to the invention
- FIG. 3 represents bubbling kinetics in the form of an Arrhenius graph, in the case of a SiC donor substrate, implanted at a dose of 6 ⁇ 10 16 H/cm 2 and an energy of 150keV, given as an example in the description below.
- the same references in the figures may be used for elements of the same type.
- the figures are schematic representations which, for the purpose of readability, are not to scale.
- the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers between them are not necessarily observed in the figures.
- the present invention relates to a method of manufacturing a composite structure 1 comprising a thin layer 10 of a single-crystal semiconductor material placed on a support substrate 200, as represented in FIG. 1.
- the method firstly comprises a step a) of supplying a donor substrate 111 composed of the single-crystal semiconductor material intended to compose the thin layer 10.
- This single-crystal semiconductor material may be chosen from among silicon carbide, silicon , germanium, a III-V or III-N compound, diamond, gallium oxide (Ga2O3) or other materials for which the removal of a thin layer is of interest.
- the donor substrate 111 is preferably in the form of a circular wafer with a diameter of 100mm, 150mm, 200mm or even 300mm or even 450mm, and with a thickness typically comprised between 300 and 800 microns. It has a front face 111a and a rear face 111b (FIG. 2a).
- the surface roughness of the front face 111a is advantageously chosen to be less than 1 nm Ra, average roughness (“average roughness” according to English terminology) measured by atomic force microscopy (AFM) on a scan of 20 microns ⁇ 20 microns.
- the thin layer 10 of the composite structure will be taken from the donor substrate 111: the latter must therefore have the mechanical, electrical and crystallographic properties required for the intended application.
- the donor substrate 111 comprises an initial substrate 11 consisting of monocrystalline semiconductor material and a donor layer 110 also formed by this material, produced by epitaxial growth on the initial substrate 11 (FIG. 2a').
- the growth step by epitaxy is carried out so that the donor layer 110 has a density of crystalline defects lower than that of the initial substrate 11.
- the thin layer 10 will, in this case, be taken from the donor layer 110: the initial substrate 11 therefore does not require a level of quality as high as the donor layer 110.
- the initial substrate 11 is made of single-crystal SiC (c-SiC), of 4H or 6H polytype, having a disorientation ("offcut") of less than or equal to 4.0 ° with respect to the crystallographic axis ⁇ 11-20> ⁇ 0.5 ° , and a density of traversing dislocations (“micropipes”) less than or equal to 5/cm 2 , or even less than 1/cm 2 .
- N-type doped (nitrogen) it has a resistivity preferably between 0.015 ohm.cm and 0.030 ohm.cm.
- an initial substrate 11 having a low density of defects of the basal plane dislocation type or BPD typically less than or equal to 3000/cm 2 .
- BPD basal plane dislocation
- c-SiC substrates exhibiting BPD densities of the order of 1500/cm 2 are reasonably available, which facilitates their supply.
- Extended defects in thin layer 10 can affect component performance and reliability.
- the c-SiC donor layer 110 is therefore produced in such a way as to have a density of BPD type defects less than or equal to 1/cm 2 .
- the growth by epitaxy of the donor layer 110 is carried out at a temperature above 1200°C, preferably between 1500°C and 1900°C.
- the precursors used are silane (SiH4), propane (C3H8) or ethylene (C2H4); the carrier gas may be hydrogen with or without argon.
- the low rate of BPD defects in the donor layer 110 is obtained by favoring the conversion of the BPD defects present in the initial substrate 11 into through-edge dislocations or TEDs (for “Threading Edge Dislocations”).
- this comprises a step b) of ion implantation of light species in the donor substrate 111, up to a determined depth representative of the thickness of thin layer 10 desired. Note that the depth will always remain less than the thickness of the donor layer 110, when the latter is present.
- This implantation generates a buried fragile plane 12 which delimits the thin layer 10 between said buried fragile plane 12 and a free surface 111a of the donor substrate 111 (FIG. 2b).
- the ion implantation is carried out so as to form a buried fragile plane 12 in a central zone 12a of the donor substrate 111, and not in an annular peripheral zone 12b.
- a mask placed on the front face 111a, facing the annular peripheral zone 12b is for example applied during the ion implantation step, so as to prevent the penetration of ions into the substrate 111, at this peripheral zone 12b.
- the annular peripheral zone 12b has a width of between 1mm and 2cm; in other words, the buried fragile plane 12 is absent in an annular peripheral zone 12b extending from the edge of the donor substrate 111 to a distance of between 1mm and 2cm towards the center of said substrate 111.
- this annular peripheral zone 12b in which the donor substrate 111 does not include the buried fragile plane 12.
- the implanted light species are preferably hydrogen, helium or a co-implantation of these two species. As is well known with reference to the Smart CutTM process, these light species will form, around the determined depth, microcavities distributed in a thin layer parallel to the front face 111a of the donor substrate 111, i.e. parallel to the plane (x, y) in the figures. This thin layer is called the buried fragile plane 12, for simplicity.
- the implantation energy of the light species is chosen so as to reach the determined depth in the donor substrate 111.
- hydrogen ions are implanted at an energy comprised between 10 keV and 250 keV, and at a dose comprised between 5 E 16/cm2 and l E 17/cm2, to delimit a thin layer 10 having a thickness of between 100 and 1500 nm, this thickness of course depending on the nature of the semiconductor material of the donor substrate 111.
- a thin protective layer may be deposited on the front face 111a of the donor substrate 111, prior to the ion implantation step.
- This protective layer can be composed of a material such as silicon oxide or silicon nitride for example, and can be removed at the end of step b).
- the buried fragile plane 12 comprises lenticular microcavities capable of developing by thermal activation in the form of microcracks.
- the implantation conditions define a first thermal budget for obtaining bubbling on the front face 111a of the donor substrate 111: this first thermal budget can be reached at different temperatures by different annealing times causing the appearance of bubbling (bubbling kinetics).
- the implantation conditions also define a second thermal budget for obtaining a fracture in the buried fragile plane 12: this second thermal budget can be reached at different temperatures by different annealing times causing the spontaneous propagation of a fracture ( fracture kinetics).
- bubbling corresponds to the deformation of the thin layer 10 directly above the microcracks, in the absence of a stiffening effect at the level of the front face 111a, and the fracture corresponds to complete cracking in the fragile plane. buried 12, in the presence of a stiffening effect at the level of the front face 111a.
- the manufacturing method then comprises a step c) of forming a stiffening film 20 on the front face 111a of the donor substrate 111 (FIG. 2c).
- This step is carried out by applying a thermal budget lower than the first thermal budget: the objective here is to remain below the thermal budget likely to generate deformation by bubbling of the thin layer 10 or its partial delamination, due to the growth microcracks in the buried fragile plane 12.
- the stiffening film 20 is perforated, taking the form of a mesh in the plane of the front face 111a, with a coverage rate less than or equal to 30%, preferably between 5% and 30%. Due to its mesh shape, the perforated stiffening film 20 defines a plurality of areas of the bare front face 111a (perforated areas of the stiffening film 20), in the form of patterns 20' whose lateral dimensions are less than or equal to 50 microns .
- the lateral dimensions are the dimensions of the patterns in the plane (x,y) of the front face 111a of the donor substrate 111. At least one dimension of the patterns 20' can be less than or equal to 20 microns, to 10 microns, even 5 microns, or even 2 microns.
- the patterns 20' can have a square, rectangular, triangular, circular or other polygonal shape.
- the width of the mesh, in the plane (x,y), that is to say the width of the walls separating the patterns 20' defined by the stiffening film 20, can be between 5 microns and 50 microns.
- the stiffening film 20 also has a thickness greater than or equal to 0.5 micron, typically between 0.5 micron and 50 microns, preferably between 0.5 micron and 5 microns.
- the role of the perforated stiffening film 20 is to maintain the mechanical integrity of the thin layer 10 during the next step d) of deposition of the support substrate 200, which requires a thermal budget greater than the first bubbling thermal budget, or even greater or equal to the second fracture thermal budget.
- the perforated stiffening film 20 allows direct contact between the thin layer 10 and the support substrate 200 over a surface greater than 70% of the surface of the thin layer 10. This is particularly advantageous for establishing conduction electric vertical in the future composite structure 1 because the deposition of the support substrate 200 at high temperatures is very favorable to good interface states with the thin layer 10.
- the perforated stiffening film 20 does not need ensure electrical conduction between the thin layer 10 and the support substrate 200. It can therefore comprise a wide variety of materials, chosen in particular from tungsten, silicon carbide, silicon, silicon nitride, boron nitride, silicon oxide, aluminum oxide, aluminum nitride, etc.
- the crystalline quality of the perforated stiffening film 20, as well as the quality of its interface with the useful layer 10 are not critical, which allows the formation of said stiffening film 20 at low thermal budgets. However, care should be taken to choose a material for the stiffening film 20 which is compatible with the temperatures applied to the following stages of the process (in particular, to the following stage d)), typically a material whose melting temperature is higher than the temperatures involved in said stages.
- step c) comprises one or more sequence(s) of deposition, bonding, photolithography, nano-imprinting, etching and/or thinning, or any other technique making it possible to form a film openwork in the form of a mesh.
- the perforated stiffening film 20 can be produced by implementing the deposition of a continuous film, then a lithography to define the shape of the mesh, and finally, an etching at the level of the patterns 20' to create the bare zones in front face 111a of the donor substrate 111.
- the temperature of step c) is chosen to be less than 800° C, or even less than or equal to 500°C. In this temperature range, the bubbling kinetics is very slow (see Figure 3), and allows the formation of a stiffening film 20 of polycrystalline silicon carbide 2 microns thick, produced by thermal CVD deposition, for example around 700° C., for about 2 hours.
- the black circle in Figure 3 represents this thermal budget, which appears well below the bubbling thermal budget.
- a conventional photolithography and etching step then makes it possible to finalize the perforated stiffening film 20 in polycrystalline SiC, which defines square patterns 20' of 25 microns in diameter. side and a 4 micron mesh. The degree of coverage of said mesh is of the order of 25%.
- the manufacturing method according to the invention then comprises step d) of depositing the support substrate 200 on the front face 111a of the donor substrate 111 provided with the perforated stiffening film 20 (FIG. 2d).
- the deposition of step d) is carried out by applying a thermal budget greater than the first thermal budget (namely, the bubbling thermal budget), or even greater than or equal to the second thermal budget (of fracture).
- the high temperatures favored in step d) promote the structural quality of the support substrate 200 and the quality of its interface with the thin layer 10.
- the deposition can be carried out by any known technique, in particular involving chemical vapor deposition. (CVD), thermal or plasma assisted, or physical vapor deposition (PVD).
- the stack 211 is formed and the support substrate 200 has a thickness greater than or equal to 50 microns, or even greater than or equal to 200 microns or even 300 microns.
- the high thermal budget applied during step d) does not irreparably damage the thin layer 10 because the perforated stiffening film 20 ensures the mechanical retention of the thin layer 10, by limiting the phenomenon of bubbling and by preventing any local exfoliation of the thin layer 10.
- the support substrate 200 can have a monocrystalline or polycrystalline structure and comprise at least one material chosen from among silicon carbide, silicon, diamond, III-V or III-N compounds such as gallium nitride, gallium oxide, etc. Since the deposition of step d) involves a thermal budget greater than the first bubbling thermal budget, or even greater than or equal to the second fracture thermal budget, and the stiffening film 20 limits the expansion of the microcracks in the form of blisters and prevents the appearance of local exfoliations of the thin layer 10, the microcracks will join together and propagate in the buried fragile plane 12, during step d).
- the buried fragile plane 12 does not extend to the edges of the donor substrate 111, due to the exclusion of an annular peripheral zone 12b, prevents the fracture, which propagates in the buried fragile plane 12 , does not cause premature separation between the composite structure 1 (thin layer 10, stiffening film 20 and support substrate 200) and the rest 111' of the donor substrate. Indeed, below a certain thickness of support substrate 200, the composite structure 1 would tend to dislocate and break, because it would be overall too thin to be self-supporting.
- the fracture along the buried fragile plane 12 quickly appearing at high thermal budgets, the annular peripheral zone 12b makes it possible to maintain the stack 211 joined, until the desired thickness of support substrate 200 is obtained, typically greater than or equal to at 50 microns.
- a support substrate 200 in p-SiC can be formed on the front face 111a of the donor substrate 111 provided with the film openwork stiffener 20.
- a thermal CVD deposition of p-SiC is carried out at a temperature between 900° C. and 1500° C., for example at 1000° C., for 4 hours, to reach a thickness of 400 microns; the black triangle in FIG. 3 represents this thermal budget which appears much higher than the first thermal budget (bubbling kinetics).
- the fracture along the buried fragile plane 12 appears less than one hour after the start of the deposition: the thermal budget of the deposition of step d) is here also greater than the fracture thermal budget.
- the stack 211 is nevertheless kept integral due to the presence of the annular peripheral zone 12b, devoid of buried fragile plane 12.
- the manufacturing method according to the invention comprises a step e) of separation of the stack 211, to form on the one hand the composite structure 1 and on the other hand the rest 111' of the donor substrate (FIG. 2e).
- This separation can be carried out mechanically or chemically.
- the application of a mechanical stress at the edges of the stack 211 for example by the insertion of a tool (for example, a blade or a bevel shape) can cause cracking of the annular peripheral zone 12b and separating the stack 211.
- a chemical etching of the edges of the donor substrate 111 (at the level of the annular peripheral zone 12b), applied alone or together with a mechanical stress also makes it possible to obtain the separation of step e ).
- the separation step can generate thickness non-uniformities and significant roughnesses of the thin layer 10, in the annular peripheral zone 12b, because said thin layer 10 does not will a priori not be entirely transferred to the peripheral zone 12b. These defects can be processed in a subsequent step f) of the method.
- the manufacturing method according to the invention may comprise a step f) of mechanical(s) and/or chemical(s) and/or thermal(s) treatment(s) of the composite structure 1, to smooth the free surface of the thin layer 10 and/or to improve the quality of edges of the composite structure 1 (edges of the thin layer 10 or edges of the support substrate 200) and/or to correct the uniformity of thickness of the composite structure 1.
- the free face 10a of the thin layer 10 of the composite structure 1 has a surface roughness of between 5 and 100 nm RMS (by measurement at atomic force microscope (AFM), on scans of 20 microns x 20 microns), at least in its central zone 12a.
- RMS atomic force microscope
- Step f) can then comprise chemical-mechanical polishing (CMP) of the free face 10a of the thin layer 10, typically with a removal of material of the order of 50 nm to 1000 nm, so as to obtain a roughness final less than 0.5 nm Rms (on an AFM field of 20x20 ym), or even less than 0.3 nm.
- Step f) can also comprise a chemical or plasma treatment (cleaning or etching), for example cleaning of the SC1/SC2 type (Standard Clean 1, Standard Clean 2) and/or HF (hydrofluoric acid), or an N2 plasma , Ar, CF4, etc., to further improve the quality of the free face 10a of the thin layer 10.
- CMP chemical-mechanical polishing
- CMP chemical-mechanical polishing
- etching or cleaning chemical treatment
- grinding mechanical treatment
- CMP chemical-mechanical polishing
- Such a treatment makes it possible to improve the uniformity of thickness of said support substrate 200 as well as its roughness on the rear face 200b.
- a roughness of less than 0.5 nm RMS (by measurement with an atomic force microscope (AFM), on fields of 20 microns x 20 microns) is desired to produce vertical components, for which at least one metal electrode will be present on the rear face 200b of the composite substrate 1.
- these treatments applied to the rear face 200b of the support substrate 200 could optionally be carried out just before step e) of separation, that is to say before the front face 10a of the composite structure 1 is exposed, so as to limit its contamination, in particular during polluting or restrictive treatments such as chemical etching or mechanical lapping (or mechanical grinding).
- step f polish or grind the edges of the composite structure 1 to make the shape of its circular contour and of the drop edge compatible with the requirements of the microelectronic manufacturing processes.
- step f) may comprise a heat treatment at high temperatures (for example, a temperature between 1000° C. and 1900° C., depending on the nature of the materials of the composite structure 1), during about an hour and up to a few hours.
- high temperatures for example, a temperature between 1000° C. and 1900° C., depending on the nature of the materials of the composite structure 1.
- the objective of this step is to stabilize the composite structure 1, by healing structural or surface defects, still present in and/or on the thin layer 10, and by changing, if necessary, the crystalline configuration of the support substrate. 200, so that the structure 1 is compatible with subsequent heat treatments at high temperatures, required for the manufacture of components on the thin layer 10, such as epitaxies, dopant activation annealings, deposits, etc.
- the method according to the invention may comprise an additional step of growth by epitaxy of an additional layer on the thin layer 10 of the composite structure 1.
- a step is applied when a relatively large thickness of useful layer is necessary for the manufacture of components, typically, of the order of 5 to 50 microns.
- the epitaxy conditions may optionally be chosen similar to those of step a), preferably at lower temperature so as to limit the stresses induced in the useful layer (corresponding to the whole layer thin 10 and additional layer) due to the potentially heterogeneous materials of the composite structure 1.
- the manufacturing process may comprise a step of reconditioning the remainder 111' of the donor substrate with a view to reuse as initial substrate 11 or as donor substrate 111.
- a reconditioning step is based on one or more treatments of face 110'a (FIG. 2e), by mechanical-chemical polishing of the surface or edges, and/or by mechanical grinding, and/or by dry or wet chemical etching.
- the thickness of the donor layer 110, when it is formed in step a) is defined so that the remainder 111' of the donor substrate 111 can be reused at least twice as donor substrate 111.
- the invention also relates to a composite structure 1 resulting from the manufacturing process as described previously.
- the composite structure 1 is particularly suitable for power applications: a composite structure comprising a thin layer 10 of c-SiC of high crystalline quality, a stiffening film 20 of p-SiC and a support substrate of p-SiC, as described example above, is very favorable for the development of vertical power components.
- the composite structure 1 can thus comprise one (or more) vertical power component(s), such as for example a transistor, a diode or any high-voltage and/or high-frequency component, whose development techniques belong to the state of the art.
- the composite structure 1 according to the invention is entirely compatible with said techniques.
- a vertical power component all or part of said component is formed on and/or in the thin layer 10, and a metal electrode is produced on the rear face 200b of the support substrate 200.
- the direct contact between the thin layer thin 10 and the support substrate 200, which exists in the perforated zones 20' of the stiffening film 20, ensures good vertical electrical conduction, as well as effective thermal conductivity. Electrical conduction is guaranteed regardless of the material of the film 20, which opens up multiple possibilities for the selection of said material, on the essential criterion of mechanical stiffness.
- the lateral dimensions of the targeted power components are of the order of a square millimeter, which is significantly larger than the size of the patterns 20' and of the grid defined by the perforated stiffening film 20: a vertical electrical contact will therefore exist always between the thin layer 10 and the support substrate 200 plumb with each component produced.
- the shape and dimensions of the mesh can be adjusted to the design and distribution of the components intended to be produced on the composite structure 1.
- composite structures 1 than the SiC-based structure given as an example can of course be produced by the manufacturing method according to the invention, from other combinations of materials.
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US18/546,057 US20240112908A1 (en) | 2021-03-23 | 2022-03-14 | Method for manufacturing a composite structure comprising a thin single-crystal semiconductor layer on a carrier substrate |
EP22712984.8A EP4315396A1 (fr) | 2021-03-23 | 2022-03-14 | Procede de fabrication d'une structure composite comprenant une couche mince en semi-conducteur monocristallin sur un substrat support |
JP2023556888A JP2024510756A (ja) | 2021-03-23 | 2022-03-14 | キャリア基板上に単結晶半導体で作られた薄層を含む複合構造体を製造するための方法 |
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FRFR2102921 | 2021-03-23 | ||
FR2102921A FR3121281B1 (fr) | 2021-03-23 | 2021-03-23 | Procede de fabrication d’une structure composite comprenant une couche mince en semi-conducteur monocristallin sur un substrat support |
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WO2022200712A1 true WO2022200712A1 (fr) | 2022-09-29 |
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PCT/FR2022/050454 WO2022200712A1 (fr) | 2021-03-23 | 2022-03-14 | Procede de fabrication d'une structure composite comprenant une couche mince en semi-conducteur monocristallin sur un substrat support |
Country Status (6)
Country | Link |
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US (1) | US20240112908A1 (fr) |
EP (1) | EP4315396A1 (fr) |
JP (1) | JP2024510756A (fr) |
FR (1) | FR3121281B1 (fr) |
TW (1) | TW202247252A (fr) |
WO (1) | WO2022200712A1 (fr) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US6191007B1 (en) * | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
US20040092087A1 (en) * | 2000-12-08 | 2004-05-13 | Bernard Aspar | Method for producing a thin film comprising introduction of gaseous species |
US20120199845A1 (en) * | 2011-02-03 | 2012-08-09 | S.O.I.Tec Silicon On Insulator Technologies | Metallic carrier for layer transfer and methods for forming the same |
WO2018149906A1 (fr) * | 2017-02-17 | 2018-08-23 | Soitec | Masquage d'une zone au bord d'un substrat donneur lors d'une étape d'implantation ionique |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
-
2021
- 2021-03-23 FR FR2102921A patent/FR3121281B1/fr active Active
-
2022
- 2022-03-14 JP JP2023556888A patent/JP2024510756A/ja active Pending
- 2022-03-14 US US18/546,057 patent/US20240112908A1/en active Pending
- 2022-03-14 TW TW111109268A patent/TW202247252A/zh unknown
- 2022-03-14 WO PCT/FR2022/050454 patent/WO2022200712A1/fr active Application Filing
- 2022-03-14 EP EP22712984.8A patent/EP4315396A1/fr active Pending
Patent Citations (5)
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US6191007B1 (en) * | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
US20040092087A1 (en) * | 2000-12-08 | 2004-05-13 | Bernard Aspar | Method for producing a thin film comprising introduction of gaseous species |
US20120199845A1 (en) * | 2011-02-03 | 2012-08-09 | S.O.I.Tec Silicon On Insulator Technologies | Metallic carrier for layer transfer and methods for forming the same |
US8436363B2 (en) | 2011-02-03 | 2013-05-07 | Soitec | Metallic carrier for layer transfer and methods for forming the same |
WO2018149906A1 (fr) * | 2017-02-17 | 2018-08-23 | Soitec | Masquage d'une zone au bord d'un substrat donneur lors d'une étape d'implantation ionique |
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ASPAR ET AL.: "The generic nature of the Smart Cut@ process for thin film transfer", JOURNAL OF ELECTRONIC MATERIALS, vol. 30, no. 7, July 2001 (2001-07-01) |
BEDELL ET AL.: "Investigation of surface blistering of hydrogen implanted crystals", JOURNAL OF APPLIED PHYSICS, vol. 90, no. 3, 2001, XP012053880, DOI: 10.1063/1.1380409 |
Also Published As
Publication number | Publication date |
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TW202247252A (zh) | 2022-12-01 |
US20240112908A1 (en) | 2024-04-04 |
FR3121281B1 (fr) | 2023-11-24 |
EP4315396A1 (fr) | 2024-02-07 |
FR3121281A1 (fr) | 2022-09-30 |
JP2024510756A (ja) | 2024-03-11 |
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