WO2022196132A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
WO2022196132A1
WO2022196132A1 PCT/JP2022/003409 JP2022003409W WO2022196132A1 WO 2022196132 A1 WO2022196132 A1 WO 2022196132A1 JP 2022003409 W JP2022003409 W JP 2022003409W WO 2022196132 A1 WO2022196132 A1 WO 2022196132A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
grinding
protective tape
semiconductor device
grinding step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/003409
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
三千矢 北野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to CN202280005770.8A priority Critical patent/CN115996816A/zh
Priority to JP2023506831A priority patent/JP7364114B2/ja
Publication of WO2022196132A1 publication Critical patent/WO2022196132A1/ja
Priority to US18/175,535 priority patent/US20230207325A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
    • B24B49/12—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/04—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor involving a rotary work-table
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device.
  • Patent Document 1 JP-A-2013-21017
  • Patent Document 2 JP-A-2007-19461
  • the method of manufacturing a semiconductor device may include an attaching step.
  • a protective tape may be attached to the first surface of the semiconductor substrate.
  • the method of manufacturing a semiconductor device may include a first grinding step.
  • the second side of the semiconductor substrate which is the side opposite to the first side, may be ground while supporting the masking tape.
  • the method of manufacturing a semiconductor device may comprise a protective tape cutting step.
  • the protective tape cutting step the second surface of the semiconductor substrate may be supported and the protective tape may be planarized.
  • the method of manufacturing a semiconductor device may comprise a second grinding step. In a second grinding step, the second side of the semiconductor substrate may be ground while supporting the masking tape.
  • the inside of the convex portion may be ground so that the convex portion remains on the outer periphery of the semiconductor substrate.
  • the semiconductor device manufacturing method may include a table processing step.
  • the table supporting the first surface of the semiconductor substrate may be processed in the second grinding step based on the shape of the second surface of the semiconductor substrate after the first grinding step.
  • the table supporting the first side of the semiconductor substrate may have a valley between the center of the portion and the end of the portion in the portion overlapping the first side of the semiconductor substrate.
  • the height of the top surface of the table in the middle part may be the highest in the part.
  • the height of the top surface of the table at the valleys may be less than the height of the top surface of the table at the ends.
  • the table for supporting the first surface of the semiconductor substrate may have a top surface whose height monotonously decreases from the center of the portion to the edge of the portion in the portion overlapping the first surface of the semiconductor substrate.
  • the maximum value of the table height difference may be 0.004% or less of the diameter of the semiconductor substrate.
  • the table for supporting the first surface of the semiconductor substrate may have a top surface whose height monotonously decreases from the center portion to the end portion of the portion overlapping the first surface of the semiconductor substrate.
  • the grinding depth in the first grinding stage may be less than the grinding depth in the second grinding stage.
  • the manufacturing method of the semiconductor device may include an estimation step.
  • appearance information of the surface of the protective tape after the protective tape cutting step may be obtained, and deterioration of the flattening tool during the protective tape cutting step may be estimated from the appearance information.
  • the appearance information may be the reflectance of the masking tape.
  • the appearance information may be image information of the protective tape.
  • FIG. 4A and 4B are diagrams illustrating an example of a method for manufacturing the semiconductor device 100; FIG. It is a figure explaining an example of sticking step S101.
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a first grinding step S102;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 after grinding in a first grinding step S102;
  • FIG. 5 is a diagram showing an example of the relationship between the grinding depth and TTV (Total Thickness Variation) in the first grinding step S102;
  • FIG. 10 is a diagram illustrating the protective tape 20 in the middle of flattening in the protective tape cutting step S103.
  • FIG. 10 is a diagram illustrating the masking tape 20 after flattening in masking tape cutting step S103.
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a second grinding step S105;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 after grinding in a second grinding step S105;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a second grinding step S105;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 after grinding in a second grinding step S105;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a first grinding step S102;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 after grinding in a first grinding step S102;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a second grinding step S105;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a second grinding step S105;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a second grinding step S105;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 before grinding in a second grinding
  • FIG. 10 is a diagram illustrating the semiconductor device 100 after grinding in a second grinding step S105; 4A to 4C are diagrams for explaining another example of the method for manufacturing the semiconductor device 100; FIG. It is a figure explaining an example of estimation step S204. 8A and 8B are diagrams for explaining a comparative example of the method for manufacturing the semiconductor device 100; FIG. It is a figure explaining an example of sticking step S301.
  • FIG. 10 is a diagram illustrating the masking tape 20 in the middle of flattening in the masking tape cutting step S302.
  • FIG. 10 is a diagram for explaining the masking tape 20 after flattening in masking tape cutting step S302.
  • FIG. 10 is a diagram for explaining the semiconductor device 100 before it is attracted to the table 140 in the substrate grinding step S303; FIG.
  • FIG. 10 is a diagram for explaining the semiconductor device 100 after being sucked to the table 140 in the substrate grinding step S303;
  • FIG. 10 is a diagram illustrating the semiconductor device 100 after grinding in a substrate grinding step S303; It is a figure explaining forward inclination angle theta1.
  • one side in the direction parallel to the depth direction of the semiconductor substrate is called “upper”, and the other side is called “lower”.
  • One of the two main surfaces of a substrate, layer or other member is called the upper surface and the other surface is called the lower surface.
  • the directions of “up” and “down” are not limited to the direction of gravity or the direction when the semiconductor module is mounted.
  • the Cartesian coordinate axes only specify the relative positions of the components and do not limit any particular orientation.
  • the Z axis does not limit the height direction with respect to the ground.
  • the +Z-axis direction and the ⁇ Z-axis direction are directions opposite to each other.
  • the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.
  • orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis.
  • the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis.
  • the Z-axis direction may be referred to as the depth direction.
  • a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as a horizontal direction.
  • FIG. 1 is a diagram explaining an example of a method for manufacturing a semiconductor device 100.
  • the manufacturing method of the semiconductor device 100 includes a table processing step S104, an attaching step S101, a first grinding step S102, a protective tape cutting step S103 and a second grinding step S105.
  • the table processing step S104 the table used in the second grinding step S105 is processed. Each step is described below with reference to FIGS. 2 to 7b. Details of the table processing step S104 will be described later with reference to FIG.
  • the semiconductor device 100 functions as a power conversion device such as an inverter.
  • the semiconductor device 100 may include an insulated gate bipolar transistor (IGBT), a diode such as a FWD (Free Wheel Diode), an RC (Reverse Conducting)-IGBT combining these, a MOS transistor, and the like.
  • the semiconductor device 100 functions as a pressure sensor, for example.
  • the semiconductor device 100 need not be limited to these examples.
  • FIG. 2 is a diagram illustrating an example of the pasting step S101.
  • a semiconductor device 100 includes a semiconductor substrate 10 .
  • the semiconductor substrate 10 in this example is a wafer having a substantially circular shape when viewed from above. In this specification, steps other than the step of grinding the semiconductor substrate 10 are omitted.
  • the method of manufacturing the semiconductor device 100 includes the steps of implanting impurities into a predetermined region of the semiconductor substrate 10, annealing the semiconductor substrate 10, and forming an insulating film, electrodes, wiring, or the like on the surface of the semiconductor substrate 10. good. Through these steps, semiconductor elements such as transistors are formed on the semiconductor substrate 10 .
  • the semiconductor substrate 10 is a substrate made of a semiconductor material.
  • the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.
  • the diameter D1 of the semiconductor substrate 10 is often 200 ⁇ 5 mm or 300 mm ⁇ 5 mm. However, it is not limited to this value.
  • the protective tape 20 is attached to the first surface 11 of the semiconductor substrate 10.
  • the first surface 11 of the semiconductor substrate 10 may be a surface on which gate structures such as IGBTs and MOS transistors are formed.
  • the gate structure is, for example, a structure including at least one of a gate electrode, a gate insulating film, a source region, an emitter region, and a channel region.
  • the gate structure may be formed on the first surface 11 or may not be formed yet.
  • the first surface 11 of the semiconductor substrate 10 may be a so-called device surface.
  • the protective tape 20 is a tape that protects the first surface 11 of the semiconductor substrate 10 . Specifically, by attaching the protective tape 20, when the second surface 12 of the semiconductor substrate 10 is ground in the first grinding step S102 and the second grinding step S105, the first surface 11 of the semiconductor substrate 10 is ground. Direct contact with the equipment table can be prevented.
  • the protective tape 20 may be an adhesive tape.
  • the protective tape 20 for example, UV tape or pressure-sensitive tape is generally used, but in addition, an organic coating film typified by a resist, an electrostatic adsorption sheet, or a supporting disk coated with an adhesive is used. is also available.
  • the second surface 12 of the semiconductor substrate 10 is the surface opposite to the first surface 11 of the semiconductor substrate 10 .
  • the protective tape 20 After attaching the protective tape 20, it is preferable to cut the protective tape 20 in order to flatten the protective tape 20.
  • the second surface 12 of the semiconductor substrate 10 is placed on a table and the protective tape 20 is cut.
  • foreign matter 30 may adhere to the second surface 12 of the semiconductor substrate 10 .
  • the foreign matter 30 is foreign matter adhered during the manufacturing process of the semiconductor device 100 .
  • the foreign matter 30 may be particles or the like, or may be an organic substance such as a resist or a residue of an oxide film. If the foreign matter 30 adheres to the second surface 12 of the semiconductor substrate 10, the masking tape 20 may not be flattened when the masking tape 20 is planarized in the masking tape cutting step S103. This problem is discussed below in Figures 13 to 16c.
  • FIG. 3a and 3b are diagrams illustrating an example of the first grinding stage S102.
  • FIG. 3a is a diagram illustrating the semiconductor device 100 before grinding in the first grinding step S102.
  • FIG. 3b is a diagram illustrating the semiconductor device 100 after grinding in the first grinding step S102.
  • the second surface 12 of the semiconductor substrate 10 is ground.
  • the protective tape 20 is supported on a table 120 in a first grinding step S102.
  • the first surface 11 of the semiconductor substrate 10 is supported by the table 120 in the first grinding step S102.
  • the first surface 11 of the semiconductor substrate 10 is supported by the table 120 via the protective tape 20 .
  • Table 120 may be a chuck table.
  • Table 120 has a top surface 121 and a bottom surface 123 .
  • the second surface 12 of the semiconductor substrate 10 is ground by the grindstone 122 in the first grinding step S102.
  • the first grinding step S102 is performed, for example, using a grinding device such as a back grinder (BG).
  • BG back grinder
  • the grindstone 122 may be tilted forward to grind the second surface 12 .
  • To incline the grindstone 122 forward means to incline the grindstone 122 with respect to the circumferential direction of the semiconductor substrate 10 .
  • the lower surface of the grindstone 122 is arranged to have an inclination (forward inclination angle) with respect to the Y-axis direction. The forward tilt angle will be described later with reference to FIG. 17 .
  • the average thickness of the semiconductor substrate 10 is T1.
  • the thickness is the difference between the height of the upper surface and the height of the lower surface in the Z-axis direction.
  • the average thickness T1 of the semiconductor substrate 10 is the difference between the height of the second surface 12 and the height of the first surface 11.
  • height is the height from a certain reference. In each drawing, the reference may be the lowermost portion of each component in the Z-axis direction. In FIG. 3a the reference is for example the underside 123 of the table 120 .
  • the grindstone 122 is drawn smaller than the semiconductor substrate 10 in FIG. 3a, the diameter of the grindstone 122 may be larger than the diameter of the semiconductor substrate 10.
  • the semiconductor substrate 10 is processed into a shape in which the central portion 14 is convex. Note that in each drawing, the unevenness of the semiconductor substrate 10 and the like is exaggerated.
  • the central portion 14 is a portion including the center of the semiconductor substrate 10 on the XY plane.
  • the semiconductor substrate 10 may also have valleys 18 between the central portion 14 and the edge portions 16 .
  • the end portions 16 are end portions of the semiconductor substrate 10 on the X-axis and the Y-axis.
  • the troughs 18 are predetermined portions that include portions that are thinner than the central portion 14 and the end portions 16 .
  • the thickness T2 of the semiconductor substrate 10 at the central portion 14 is the maximum thickness of the semiconductor substrate 10 .
  • the thickness T2 of the semiconductor substrate 10 at the central portion 14 may be the thickness of the semiconductor substrate 10 at the center.
  • the thickness T3 of the semiconductor substrate 10 at the valley portion 18 is the minimum thickness of the semiconductor substrate 10 .
  • the thickness T3 of the semiconductor substrate 10 at the valley portion 18 may be the minimum thickness of the semiconductor substrate 10 at the valley portion 18 .
  • the average thickness of the semiconductor substrate 10 is T4, which is indicated by a dotted line.
  • the grinding depth in the first grinding stage may be 50 ⁇ m or more.
  • the grinding depth in the first grinding step may be the difference between the average thickness T1 of the semiconductor substrate 10 in FIG. 3a and the average thickness T4 of the semiconductor substrate 10 in FIG. 3b.
  • FIG. 4 is a diagram showing an example of the relationship between the grinding depth and TTV (Total Thickness Variation) in the first grinding stage S102.
  • TTV is the difference between the maximum thickness and the minimum thickness of the semiconductor substrate 10 . That is, in this example, TTV is the difference between the thickness T2 of the semiconductor substrate 10 at the central portion 14 and the thickness T3 of the semiconductor substrate 10 at the valley portion 18 in FIG. 3b.
  • the in-plane uniformity represents the processing uniformity of the semiconductor substrate 10 .
  • the in-plane uniformity of the semiconductor substrate 10 in FIG. 3b is represented by (T2-T3)/T4 as an example.
  • TTV is maintained at 2 to 4 ⁇ m by setting the grinding depth in the first grinding step S102 to 50 ⁇ m or more. Therefore, if the grinding depth is 50 ⁇ m or more, the TTV after grinding can be kept substantially constant regardless of the grinding depth. The reason why the TTV after grinding can be kept constant is thought to be that the grinder operates stably by setting the grinding depth to 50 ⁇ m or more.
  • the grinding depth in the first grinding step S102 is not too large.
  • the grinding depth in the first grinding step S102 is preferably 200 ⁇ m or less.
  • the grinding depth in the first grinding step S102 may be 50 ⁇ m or more and 200 ⁇ m or less.
  • FIGS. 5a and 5b are diagrams illustrating an example of the protective tape cutting step S103.
  • FIG. 5a is a diagram illustrating the masking tape 20 in the process of flattening in the masking tape cutting step S103.
  • FIG. 5b is a diagram illustrating the masking tape 20 after flattening in the masking tape cutting step S103.
  • Masking tape 20 has a first surface 21 and a second surface 22 .
  • the second surface 22 is a surface overlapping (or in contact with) the first surface 11 of the semiconductor substrate 10 .
  • the first surface 21 is a surface opposite to the second surface 22 .
  • the protective tape 20 is flattened.
  • the first surface 21 of the protective tape 20 is flattened in the protective tape cutting step S103.
  • the second surface 12 of the semiconductor substrate 10 is supported by the table 130 in the protective tape cutting step S103.
  • the second surface 22 of the protective tape 20 is supported by the table 130 in the protective tape cutting step S103.
  • the second surface 22 of the protective tape 20 is supported by the table 130 with the semiconductor substrate 10 interposed therebetween.
  • the first surface 21 of the protective tape 20 is flattened by the flattening tool 132 in the protective tape cutting step S103.
  • the flattening tool 132 is, for example, a tool having a cutting edge. In the protective tape cutting step S ⁇ b>103 , the cutting edge of the flattening tool 132 may be brought into contact with the protective tape 20 to cut the surface of the protective tape 20 .
  • the method for manufacturing the semiconductor device 100 includes a first grinding step S102. Therefore, the foreign matter 30 adhering to the second surface 12 of the semiconductor substrate 10 can be removed, and the total thickness T5 of the semiconductor substrate 10 and the protective tape 20 can be made constant as shown in FIG. 5b. 5a, the total thickness T5 of the semiconductor substrate 10 and the protective tape 20 is the difference between the height of the first surface 21 of the protective tape 20 and the height of the second surface 12 of the semiconductor substrate 10. In FIG. As a result, the in-plane uniformity of the semiconductor substrate 10 can be improved as compared with the case where the first grinding step S102 is not provided.
  • FIG. 6 is a diagram illustrating an example of the table processing step S104.
  • the table 140 used in the second grinding step S105 is processed.
  • the table 140 supports the first surface 11 of the semiconductor substrate 10 in the second grinding step S105.
  • Table 140 has a top surface 141 and a bottom surface 143 .
  • the table 140 used in the second grinding step S105 is processed based on the expected shape of the second surface 12 of the semiconductor substrate 10 after the first grinding step S102.
  • the expected shape of the second surface 12 of the semiconductor substrate 10 after the first grinding step S102 may be a previously assumed shape. That is, it may be the shape of the second surface 12 of the semiconductor substrate 10 after performing the first grinding step S102 in the past.
  • the table 140 is processed based on the expected TTV of the semiconductor substrate 10 after the first grinding step S102.
  • the shape of the second surface 12 may be predicted from the diameter of the grindstone 122 and the forward inclination angle of the grindstone 122 .
  • first substrate portion two portions on the XY plane of the semiconductor substrate 10 are defined as a first substrate portion and a second substrate portion.
  • the portion on which the first substrate portion is placed is called the first table portion
  • the portion on which the second substrate portion is placed is called the second table portion.
  • the height of the top surface 141 of the first table portion should be greater than the height of the top surface 141 of the second table portion. You can make it higher. 6
  • the portion on which the central portion 14 of the semiconductor substrate 10 of FIG. 3b is placed is referred to as a first table portion 152.
  • the height of the top surface 141 of the first table portion 152 may be greater than the height of the top surface 141 of the second table portion 154 .
  • the height of the upper surface 141 of the table 140 is the height from the lower surface 143 (reference) of the table 140 .
  • the TTV after grinding can be kept constant by setting the grinding depth in the first grinding step S102 to 50 ⁇ m or more. Therefore, if the grinding depth in the first grinding step S102 is determined, the expected shape of the second surface 12 of the semiconductor substrate 10 after the first grinding step S102 can be determined. Therefore, it is possible to determine in advance the processing shape of the table 140 based on the expected shape of the second surface 12 of the semiconductor substrate 10 after the first grinding step S102. Therefore, the table processing step S104 can be performed in advance before the sticking step S101. Further, when the plurality of semiconductor substrates 10 are sequentially ground using the table 140, the table processing step S104 may be performed only once before the plurality of semiconductor substrates 10 are ground. That is, the affixing step S101, the first grinding step S102, the protective tape cutting step S103, and the second grinding step S105 are performed for each semiconductor substrate 10, and the table processing step S104 is performed commonly for a plurality of semiconductor substrates 10. may be
  • the table 140 is made of, for example, a ceramic or metal material, and may be a porous chuck table.
  • the processing of the table 140 may be general metal processing, or may be grinding processing performed by bringing the whetstone and table into contact. In the case of grinding, it is possible to obtain a desired table shape by adjusting the forward inclination angle of the grindstone.
  • the whetstone used at this time may be the same as that used for processing the semiconductor substrate, or may be different.
  • the forward tilt angle will be described later with reference to FIG. 17 .
  • FIG. 7a and 7b are diagrams illustrating an example of the second grinding step S105.
  • FIG. 7a is a diagram illustrating the semiconductor device 100 before grinding in the second grinding step S105.
  • FIG. 7b is a diagram illustrating the semiconductor device 100 after grinding in the second grinding step S105.
  • the second surface 12 of the semiconductor substrate 10 is ground.
  • the protective tape 20 is supported on the table 140 in the second grinding step S105.
  • the first surface 11 of the semiconductor substrate 10 is supported by the table 140 in the second grinding step S105.
  • the first surface 11 of the semiconductor substrate 10 is supported by the table 140 via the protective tape 20 .
  • Table 140 may be a chuck table.
  • the table 140 is processed based on the expected shape of the second surface 12 of the semiconductor substrate 10 after the first grinding step S102. Thickness can be made uniform.
  • the second surface 12 of the semiconductor substrate 10 is ground by the grindstone 142 in the second grinding step S105.
  • the second grinding step S105 is performed, for example, using a grinding device such as a back grinder (BG).
  • BG back grinder
  • the grindstone 142 may be tilted forward to grind the second surface 12 in the same manner as in the first grinding step S102.
  • the semiconductor substrate 10 is processed with a constant thickness T6.
  • the semiconductor substrate 10 was processed into a shape in which the central portion 14 was convex. Since the table 140 used in the second grinding step S105 is processed based on , the semiconductor substrate 10 can be flattened. Therefore, the in-plane uniformity of the semiconductor substrate 10 can be improved.
  • the table 140 has a portion 144 that overlaps the first surface 11 of the semiconductor substrate 10, and the height of the upper surface 141 monotonically decreases from the central portion 146 of the portion 144 to the edge portion 148 of the region. That is, the height H1 of the top surface 141 of the table 140 at the central portion 146 of the portion 144 may be the maximum height of the top surface 141 of the table 140 at the portion 144 .
  • the boundary between portion 144 and other portions of table 140 is indicated by a dashed line.
  • a central portion 146 of the portion 144 is a portion containing the center of the portion 144 in the XY plane.
  • the end portion 148 is the end portion of the portion 144 in the X-axis and the Y-axis. Note that in this example, the portion 144 is in contact with the first surface 11 of the semiconductor substrate 10 via the protective tape 20 .
  • the central portion 14 of the semiconductor substrate 10 can be arranged relatively higher than other portions. Therefore, the central portion 14 of the semiconductor substrate 10 can be ground more than other portions, and the in-plane uniformity of the semiconductor substrate 10 can be improved.
  • the protrusions 52 are formed on the outer periphery of the semiconductor substrate 10 . That is, in the second grinding step S ⁇ b>105 , the inside of the protrusion 52 is ground so that the protrusion 52 remains on the outer periphery of the semiconductor substrate 10 .
  • a ring-shaped reinforcing structure can be left on the semiconductor substrate 10 by leaving the convex portion 52 on the outer periphery. Therefore, warping of the semiconductor substrate 10 can be suppressed after the second grinding step S105.
  • handling of the semiconductor substrate 10 becomes easier in the post-process of the second grinding step S105.
  • the outer diameter D2 of the grindstone 142 is preferably less than or equal to the radius of the semiconductor substrate 10 (half the diameter D1 of the semiconductor substrate 10).
  • the average thickness of the semiconductor substrate 10 excluding the protrusions 52 is T6.
  • the thickness of the semiconductor substrate 10 at the convex portion 52 is T7.
  • T7 may be the maximum thickness of the semiconductor substrate 10 at the protrusion 52 .
  • the grinding depth in the second grinding step S105 may be the difference between T7 and T6.
  • a grinding depth in the second grinding step S105 may be 450 ⁇ m or more. That is, the grinding depth in the first grinding step S102 may be less than the grinding depth in the second grinding step S105. Therefore, the semiconductor substrate 10 can be thinned in the second grinding step S105.
  • FIGS. 8a and 8b are diagrams explaining a comparative example of the second grinding stage S105.
  • FIG. 8a is a diagram illustrating the semiconductor device 100 before grinding in the second grinding step S105.
  • FIG. 8b is a diagram illustrating the semiconductor device 100 after grinding in the second grinding step S105.
  • the shape of the table 140 has been changed from Figures 7a and 7b.
  • the shape of the table 140 in Figures 8a and 8b is flat, unlike in Figures 7a and 7b.
  • the thickness T6 of the semiconductor substrate 10 is not uniform. This is because the shape of the semiconductor substrate 10 formed after the first grinding step S102 remains even in the second grinding step S105.
  • the table 140 used in the second grinding step S105 it is possible to flatten the shape of the semiconductor substrate 10 formed after the first grinding step S102.
  • FIGS 9a and 9b are diagrams illustrating another example of the first grinding step S102.
  • FIG. 9a is a diagram illustrating the semiconductor device 100 before grinding in the first grinding step S102.
  • FIG. 9b is a diagram illustrating the semiconductor device 100 after grinding in the first grinding step S102.
  • the shape of the table 120 has been changed from Figures 3a and 3b.
  • the table 120 used in the first grinding step S102 is processed so as to flatten the shape of the second surface 12 of the semiconductor substrate 10 after the first grinding step S102. That is, the shape of the table 120 in this example may be the same as the shape of the table 140 in FIG. Specifically, in the table 120 , the height of the upper surface 121 monotonically decreases from the central portion 126 of the portion 124 to the end portion 128 of the portion 124 in the portion 124 overlapping the first surface 11 of the semiconductor substrate 10 . The height of the upper surface 121 of the table 120 is the height from the lower surface 123 (reference) of the table 120 .
  • the height H2 of the top surface 121 of the table 120 at the central portion 126 of the portion 124 may be the maximum height of the top surface 121 of the table 120 at the portion 124 .
  • a central portion 126 of portion 124 is a predetermined portion that includes the center of portion 124 in the X and Y axes.
  • the end portion 128 is the end portion of the portion 124 in the X-axis and the Y-axis.
  • FIGS 10a and 10b are diagrams explaining another example of the second grinding step S105.
  • FIG. 10a is a diagram illustrating the semiconductor device 100 before grinding in the second grinding step S105.
  • FIG. 10b is a diagram illustrating the semiconductor device 100 after grinding in the second grinding step S105.
  • the shape of the table 140 has been changed from Figures 7a and 7b.
  • the table 140 has a valley portion 150 between a central portion 146 of the portion 144 and an end portion 148 of the portion 144 in the portion 144 overlapping the first surface 11 of the semiconductor substrate 10 .
  • the valley portion 150 is a predetermined portion including a portion where the height of the upper surface 141 is lower than the center portion 146 and the end portions 148 .
  • the height H3 of the top surface 141 of the table 140 at the valley portion 150 may be lower than the height H1 of the top surface 141 of the table 140 at the central portion 146 .
  • the height H3 of the top surface 141 of the table 140 at the valley 150 may be lower than the height H4 of the top surface 141 of the table 140 at the end 148 .
  • the height H1 of the top surface 141 of the table 140 at the central portion 146 of the portion 144 may be the highest height of the top surface 141 of the table 140 at the portion 144 .
  • the central portion 14 of the semiconductor substrate 10 can be arranged relatively higher than other portions. Therefore, the central portion 14 of the semiconductor substrate 10 can be ground more than other portions, and the in-plane uniformity of the semiconductor substrate 10 can be improved.
  • the maximum difference in height of the upper surface 141 of the table 140 may be 0.005% or less of the diameter D1 of the semiconductor substrate 10.
  • the maximum height difference of the table 140 may be the difference between the height H1 of the top surface 141 of the table 140 at the central portion 146 and the height H3 of the top surface 141 of the table 140 at the valley portion 150 . That is, when the diameter D1 of the semiconductor substrate 10 is 300 mm, the maximum value of the height difference of the upper surface 141 of the table 140 may be 15 ⁇ m or less. Moreover, the maximum value of the height difference of the upper surface 141 of the table 140 may be 0.004% or less of the diameter D1 of the semiconductor substrate 10 .
  • the maximum height difference of the upper surface 141 of the table 140 may be 8 ⁇ m or less.
  • TTV is maintained at 2 to 4 ⁇ m by setting the grinding depth in the first grinding step S102 to 50 ⁇ m or more.
  • the forward inclination angle of the grindstone 142 may be constant.
  • FIG. 11A and 11B are diagrams for explaining another example of the method for manufacturing the semiconductor device 100.
  • the method of manufacturing the semiconductor device 100 includes a table processing step S205, an attaching step S201, a first grinding step S202, a protective tape cutting step S203, an estimation step S204 and a second grinding step S206.
  • the manufacturing method of the semiconductor device 100 of FIG. 11 differs from the manufacturing method of the semiconductor device 100 of FIG. 1 in that the estimation step S204 is provided after the protective tape cutting step S203. That is, the table processing step S205, the attaching step S201, the first grinding step S202, the protective tape cutting step S203, and the second grinding step S206 in FIG. S102 may be the same as the protective tape cutting step S103 and the second grinding step S105.
  • FIG. 12 is a diagram illustrating an example of the estimation step S204.
  • the estimation step S204 deterioration of the flattening tool 132 in the protective tape cutting step S203 is estimated.
  • the manufacturing method of the semiconductor device 100 includes the first grinding step S202 , grinding debris in the first grinding step S202 may adhere to the protective tape 20 .
  • the protective tape cutting step S ⁇ b>203 is performed in a state in which the grinding dust is attached to the protective tape 20 .
  • deterioration of the flattening tool 132 is assumed.
  • the estimation step S204 since the estimation step S204 is provided, deterioration of the flattening tool 132 can be estimated, and the replacement period and maintenance period of the flattening tool 132 can be automatically determined. Therefore, defects in the protective tape cutting step S203 can be suppressed.
  • the estimation step S204 the appearance information of the surface of the protective tape 20 after the protective tape cutting step S203 is obtained, and deterioration of the flattening tool 132 in the protective tape cutting step S203 is estimated.
  • the device 160 obtains the appearance information of the first side 21 of the protective tape 20 after the protective tape cutting step S203.
  • Appearance information is, for example, the reflectance of the protective tape 20 .
  • the change in reflectivity of the first surface 21 of the protective tape 20 after the protective tape cutting step S203 may be measured to estimate deterioration of the flattening tool 132.
  • FIG. As a result of investigation by the inventor of the present application, it was found that the visible light reflectance of the first surface 21 of the protective tape 20 after the protective tape cutting step S203 tends to monotonically decrease due to deterioration of the flattening tool 132. . Therefore, a threshold may be set for the reflectance, and the estimation step S204 may be a step of comparing the reflectance with the threshold.
  • the appearance information is image information of the protective tape 20, for example.
  • device 160 may include a camera.
  • Device 160 may perform image analysis of first side 21 of masking tape 20 .
  • the device 160 may analyze the image contrast in the image analysis of the first side 21 of the masking tape 20 .
  • the device 160 may perform image analysis to detect the density of the grind marks. That is, in the estimation step S204, the deterioration of the flattening tool 132 may be estimated by measuring the density of the grinding marks on the first surface 21 of the protective tape 20 after the protective tape cutting step S203. As a result of investigation by the inventor of the present application, it was found that the density of grinding marks tends to monotonically increase due to deterioration of the flattening tool 132 . Therefore, a threshold may be set for the density of the grinding marks, and the estimation step S204 may be a step of comparing the density of the grinding marks with the threshold.
  • the estimation step S204 is performed after the protective tape cutting step S203, but the estimation step S204 may be performed during the protective tape cutting step S203.
  • the estimation step S204 may be performed during the protective tape cutting step S203.
  • FIG. 13A and 13B are diagrams for explaining a comparative example of the method for manufacturing the semiconductor device 100.
  • the manufacturing method of the semiconductor device 100 of FIG. 13 includes a sticking step S301, a protective tape cutting step S302, and a substrate grinding step S303. Each step is described below with reference to FIGS. 14 to 16c.
  • FIG. 14 is a diagram illustrating an example of the pasting step S301.
  • the attaching step S301 of FIG. 14 may be the same as the attaching step S201 of FIG. Also in this example, the foreign matter 30 adheres to the second surface 12 of the semiconductor substrate 10 .
  • FIGS. 15a and 15b are diagrams explaining an example of the protective tape cutting step S302.
  • FIG. 15a is a diagram illustrating the masking tape 20 in the process of flattening in the masking tape cutting step S302.
  • FIG. 15b is a diagram illustrating the protective tape 20 after flattening in the protective tape cutting step S302. Similar to the protective tape cutting step S103 of FIGS. 5a and 5b, the protective tape 20 is flattened in the protective tape cutting step S302.
  • the foreign matter 30 remains attached to the second surface 12 of the semiconductor substrate 10 . Therefore, the semiconductor substrate 10 is supported by the table 130 with the portion overlapping the foreign matter 30 raised. If the protective tape 20 is flattened in this state, the thickness T8 of the protective tape 20 will not be constant as shown in FIG. 15b.
  • the thickness T8 of the protective tape 20 is the difference between the height of the first surface 21 of the protective tape 20 and the height of the second surface 22 of the protective tape 20 .
  • the protective tape 20 is processed so as to be concave in the vicinity where the foreign matter 30 adheres.
  • FIG. 16a, 16b and 16c are diagrams illustrating an example of the substrate grinding step S303.
  • FIG. 16a is a diagram for explaining the semiconductor device 100 before it is attracted to the table 140 in the substrate grinding step S303.
  • FIG. 16b is a diagram for explaining the semiconductor device 100 after being sucked to the table 140 in the substrate grinding step S303.
  • FIG. 16c is a diagram illustrating the semiconductor device 100 after grinding in the substrate grinding step S303.
  • FIG. 16a a space 170 exists between the table 140 and the protective tape 20 before the table 140 is adsorbed.
  • the protective tape 20 is sucked into the space 170 after being sucked to the table 140, so that the semiconductor substrate 10 is also held so that the portion overlapping the foreign matter 30 is concave. If the semiconductor substrate 10 is ground in this state, the thickness T6 of the semiconductor substrate 10 excluding the projections 52 will not be constant, as shown in FIG. 16c.
  • the manufacturing method of the semiconductor device 100 of FIG. 1 includes a first grinding step S102. Therefore, the foreign matter 30 adhering to the second surface 12 of the semiconductor substrate 10 can be removed. In-plane uniformity of the semiconductor substrate 10 can be improved as compared with the manufacturing method of the semiconductor device 100 of FIG.
  • FIG. 17 is a diagram explaining the forward tilt angle ⁇ 1.
  • FIG. 17 shows the first grinding step S102 on the YZ plane.
  • the lower surface of the grindstone 122 is arranged to have a forward tilt angle ⁇ 1 with respect to the Y-axis direction.
  • the lower surface of the grindstone 142 is arranged to have a forward tilt angle with respect to the Y-axis direction.
  • the forward inclination angle of the grindstone 142 in the second grinding step S105 is ⁇ 2 (not shown).
  • the forward tilting angle ⁇ 2 of the grindstone 142 in the second grinding step S105 may be smaller than the forward tilting angle ⁇ 1 of the grindstone 122 in the first grinding step S102. Further, the forward inclination angle ⁇ 2 of the grindstone 142 in the second grinding step S105 may be the same as the forward inclination angle ⁇ 1 of the grindstone 122 in the first grinding step S102. The forward tilting angle ⁇ 2 of the grindstone 142 in the second grinding step S105 may be larger than the forward tilting angle ⁇ 1 of the grindstone 122 in the first grinding step S102.
  • SYMBOLS 10 Semiconductor substrate, 11... 1st surface, 12... 2nd surface, 14... Central part, 16... Edge part, 18... Valley part, 20... Protective tape, 21... First surface , 22 second surface 30 foreign matter 52 convex portion 100 semiconductor device 120 table 121 upper surface 122 grinding wheel 123 lower surface 124 portion 126... Center part, 128... End part, 130... Table, 132... Flattening tool, 140... Table, 141... Upper surface, 142... Grindstone, 143... Lower surface, 144... Part, 146 Central portion 148 End portion 150 Valley portion 152 First table portion 154 Second table portion 160 Device 170 Space

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Milling, Broaching, Filing, Reaming, And Others (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
PCT/JP2022/003409 2021-03-17 2022-01-28 半導体装置の製造方法 Ceased WO2022196132A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202280005770.8A CN115996816A (zh) 2021-03-17 2022-01-28 半导体装置的制造方法
JP2023506831A JP7364114B2 (ja) 2021-03-17 2022-01-28 半導体装置の製造方法
US18/175,535 US20230207325A1 (en) 2021-03-17 2023-02-27 Semiconductor device manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021044168 2021-03-17
JP2021-044168 2021-03-17

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/175,535 Continuation US20230207325A1 (en) 2021-03-17 2023-02-27 Semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
WO2022196132A1 true WO2022196132A1 (ja) 2022-09-22

Family

ID=83320325

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/003409 Ceased WO2022196132A1 (ja) 2021-03-17 2022-01-28 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US20230207325A1 (https=)
JP (1) JP7364114B2 (https=)
CN (1) CN115996816A (https=)
WO (1) WO2022196132A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115714082A (zh) * 2022-10-31 2023-02-24 浙江丽水中欣晶圆半导体科技有限公司 提高硅片平坦度降低硅材料消耗的工艺

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004053967A1 (ja) * 2002-12-10 2004-06-24 Fujitsu Limited 半導体装置、配線基板の形成方法及び基板処理装置
JP2005019666A (ja) * 2003-06-26 2005-01-20 Nitto Denko Corp 半導体ウエハの研削方法および半導体ウエハ研削用粘着シート
JP2013012654A (ja) * 2011-06-30 2013-01-17 Disco Abrasive Syst Ltd 被加工物の研削方法
JP2014192204A (ja) * 2013-03-26 2014-10-06 Furukawa Electric Co Ltd:The 半導体ウエハ表面保護用粘着テープ及び半導体ウエハの加工方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021462A (ja) * 2007-07-13 2009-01-29 Disco Abrasive Syst Ltd ウェーハの加工方法
JP5877663B2 (ja) * 2011-07-07 2016-03-08 株式会社ディスコ ウエーハの研削方法
JP6129551B2 (ja) * 2012-12-27 2017-05-17 株式会社ディスコ 板状物の加工方法
CN106563980B (zh) * 2015-10-12 2020-04-10 株式会社迪思科 磨削方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004053967A1 (ja) * 2002-12-10 2004-06-24 Fujitsu Limited 半導体装置、配線基板の形成方法及び基板処理装置
JP2005019666A (ja) * 2003-06-26 2005-01-20 Nitto Denko Corp 半導体ウエハの研削方法および半導体ウエハ研削用粘着シート
JP2013012654A (ja) * 2011-06-30 2013-01-17 Disco Abrasive Syst Ltd 被加工物の研削方法
JP2014192204A (ja) * 2013-03-26 2014-10-06 Furukawa Electric Co Ltd:The 半導体ウエハ表面保護用粘着テープ及び半導体ウエハの加工方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115714082A (zh) * 2022-10-31 2023-02-24 浙江丽水中欣晶圆半导体科技有限公司 提高硅片平坦度降低硅材料消耗的工艺

Also Published As

Publication number Publication date
JP7364114B2 (ja) 2023-10-18
US20230207325A1 (en) 2023-06-29
JPWO2022196132A1 (https=) 2022-09-22
CN115996816A (zh) 2023-04-21

Similar Documents

Publication Publication Date Title
US8662485B2 (en) Suction apparatus, polishing apparatus, semiconductor device, and method of manufacturing a semiconductor device
US8772177B2 (en) Semiconductor wafer and method of producing the same
CN107437524A (zh) 基板保持装置及其制造方法
US20070249146A1 (en) Protective tape applying method
TWI767022B (zh) 基板處理方法及基板處理系統
CN1489783A (zh) 硅晶片的制造方法及硅晶片以及soi晶片
JP7721950B2 (ja) 半導体装置の製造方法
US8952496B2 (en) Semiconductor wafer and method of producing same
JP2003209080A (ja) 半導体ウェーハ保護部材及び半導体ウェーハの研削方法
CN105102189B (zh) 模板组件及模板组件的制造方法
JPH06204324A (ja) ウエハチャック
WO2022196132A1 (ja) 半導体装置の製造方法
JP4782788B2 (ja) 試料保持具とこれを用いた試料吸着装置およびこれを用いた試料処理方法
CN113205991A (zh) 一种聚焦环
JP7841906B2 (ja) 加工方法
KR20220032479A (ko) 연삭 방법
JP2024166668A (ja) ウエーハの研削方法
JP2021137934A (ja) 研削装置、及び研削方法
TWI625195B (zh) 研磨頭及研磨半導體晶圓的背側的方法
CN221940602U (zh) 静电卡盘以及薄膜沉积设备
CN108655946A (zh) 研磨头及研磨半导体晶片的背侧的方法
CN110534423B (zh) 半导体器件及其制作方法
TWM552025U (zh) 薄型化晶圓保護環
JP2024017800A (ja) 被加工物の加工方法
CN117637494A (zh) 半导体装置及半导体装置的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22770894

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023506831

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22770894

Country of ref document: EP

Kind code of ref document: A1