WO2022195692A1 - デジタルアナログ変換機 - Google Patents

デジタルアナログ変換機 Download PDF

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Publication number
WO2022195692A1
WO2022195692A1 PCT/JP2021/010469 JP2021010469W WO2022195692A1 WO 2022195692 A1 WO2022195692 A1 WO 2022195692A1 JP 2021010469 W JP2021010469 W JP 2021010469W WO 2022195692 A1 WO2022195692 A1 WO 2022195692A1
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WO
WIPO (PCT)
Prior art keywords
current
terminal
switch transistor
bit
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/010469
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English (en)
French (fr)
Japanese (ja)
Inventor
修一 坂田
研人 齋木
優治 小松崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2023506416A priority Critical patent/JP7378663B2/ja
Priority to CN202180095391.8A priority patent/CN116982261A/zh
Priority to PCT/JP2021/010469 priority patent/WO2022195692A1/ja
Priority to EP21931446.5A priority patent/EP4297280B1/en
Publication of WO2022195692A1 publication Critical patent/WO2022195692A1/ja
Priority to US18/223,861 priority patent/US12355466B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H03M1/745—Simultaneous conversion using current sources as quantisation value generators with weighted currents

Definitions

  • the present disclosure relates to a digital-to-analog converter that converts digital signals into analog signals.
  • Some digital-to-analog converters have a capacitor (capacitive load) as an output load and a current generator connected in parallel to the capacitor.
  • the digital-to-analog converter uses a digital signal to arbitrarily switch the current generator on and off to generate an analog waveform of the voltage on the capacitor.
  • Such a digital-to-analog converter generally has a driver circuit for each current generator in order to switch the timing of operating and stopping the current generator.
  • Non-Patent Document 1 discloses a digital-analog converter in which a current generator is composed of a transistor, and a driver circuit for driving the transistor is connected to the transistor (Fig. .3).
  • a driver circuit and an input terminal for inputting a digital signal to the driver circuit are required for one current generator.
  • two current generators are required for one bit
  • two driver circuits and input terminals are required for one bit, resulting in a large circuit size.
  • the circuit size becomes large and the circuit configuration becomes complicated, which makes it difficult to increase the number of bits.
  • the present disclosure has been made to solve the above problems, and aims to provide a digital-to-analog converter with a small circuit size per 1-bit element.
  • the digital-to-analog converter of the present disclosure includes, when a digital signal is input, a plurality of 1-bit elements that respectively output currents corresponding to values indicated by the digital signal, a capacitive load connected to the plurality of 1-bit elements, to generate an analog voltage waveform on a capacitive load that receives current output from a plurality of 1-bit elements, wherein the 1-bit elements generate 1-bit responsive to the value indicated by the input digital signal.
  • a switching circuit that changes the self-bias in the element and switches connection and disconnection with the power supply according to the change in the self-bias.
  • FIG. 1 is a configuration diagram showing a digital-analog converter according to Embodiment 1 of the present disclosure
  • FIG. FIG. 4 is a table showing possible patterns of current values when the digital-analog converter according to Embodiment 1 of the present disclosure is configured with four bit elements
  • FIG. FIG. 4 is a diagram for explaining the operation of the 1-bit element of the digital-analog converter according to Embodiment 1 of the present disclosure
  • FIG. 1 is a configuration diagram showing a digital-analog converter according to Embodiment 1 of the present disclosure.
  • the digital-analog converter 1 is, for example, a high-frequency digital-analog converter.
  • the digital-to-analog converter 1 includes a plurality of 1-bit elements 10 that respectively output currents corresponding to the values indicated by the digital signals, and a capacitive load 70 connected to the plurality of 1-bit elements 10. , provided.
  • the value indicated by the digital signal is a voltage value or a value indicating on/off of the switch.
  • the digital-to-analog converter 1 is configured to generate an analog voltage waveform on a capacitive load 70 that receives current output from the plurality of 1-bit devices 10 .
  • the digital-to-analog converter 1 includes a 1-bit element 10, an input terminal 20, a power supply terminal 30, a bit unit output terminal 50, an output terminal 60, and a capacitive load 70.
  • the 1-bit element 10 shown in FIG. 1 is composed of an arbitrary number of 1-bit elements 10-1, 10-2, 10-3, 10-4, . . . 10-N.
  • the number N of 1-bit elements 10 is an arbitrary number set in advance according to the analog signal to be output by the digital-to-analog converter.
  • the n-th 1-bit element is referred to as the n-th 1-bit element as required.
  • n is any number from 1 to N;
  • Each of the n-th 1-bit elements 10-n outputs a current corresponding to the value indicated by the digital signal when the digital signal is input.
  • Each n-th 1-bit element 10-n changes the self-bias in the 1-bit element according to the value indicated by the input digital signal, and the switching circuit switches connection and disconnection with the power supply according to the change in self-bias.
  • the switching circuit in the n-th 1-bit element 10-n comprises a current supply switch 41, a current discharge switch 42, and a control switch 43, for example, as shown in the first 1-bit element 10-1 of FIG. . A detailed example thereof will be described later.
  • the input terminal 20 is a terminal for inputting a digital signal to each 1-bit element.
  • the input terminals 20 shown in FIG. 1 include a first input terminal 20-1, a second input terminal 20-2, a third input terminal 20-3, a fourth input terminal 20-4, . , N-th input terminal 20-N.
  • a first input terminal 20-1 is provided to the first 1-bit element 10-1.
  • the second input terminal 20-2 is provided to the second 1-bit element 10-2
  • the third input terminal 20-3 is provided to the third 1-bit element 10-3
  • the 4 input terminals 20-4 are provided to the fourth 1-bit element 10-4, . . .
  • the Nth input terminal 20-N is provided to the Nth 1-bit element 10-N.
  • the power supply terminal 30 is a terminal connected to each of the 1-bit elements 10-1, 10-2, 10-3, 10-4, . . . 10-N and used in common.
  • the bit unit output terminal 50 is a terminal for outputting a signal from each of the 1-bit elements 10-1, 10-2, 10-3, 10-4, . . . 10-N.
  • the bit unit output terminals 50 shown in FIG. 1 include a first bit unit output terminal 50-1, a second bit unit output terminal 50-2, a third bit unit output terminal 50-3, and a fourth bit unit output. Terminals 50-4, . . . , Nth bit unit output terminals 50-N.
  • a first bit unit output terminal 50-1 is provided to the first bit element 10-1.
  • a second bit-unit output terminal 50-2 is provided for the second 1-bit element 10-2, and a third bit-unit output terminal 50-3 is provided for the third 1-bit element 10-3.
  • the fourth bit-unit output terminal 50-4 is provided to the fourth 1-bit element 10-4, . . . 10-N.
  • the output terminal 60 is the bit unit output terminals 50-1, 50-2, 50-3, 50- of the 1-bit elements 10-1, 10-2, 10-3, 10-4, . 4, . . . , 50-N are connected in parallel. Also, the output terminal 60 is connected to a capacitive load 70 . That is, the output terminal 60 connects the 1-bit elements 10-1, 10-2, 10-3, 10-4, .
  • One of the capacitive loads 70 is connected to the 1-bit elements 10-1, 10-2, 10-3, 10-4, . there is
  • the current supply switch 41 in the switching circuit of the n-th 1-bit element 10-n is, for example, an N-type normally-on transistor (current supply switch transistor). If the current supply switch 41 is a normally-on transistor, a current flows from the drain terminal D to the source terminal S when a voltage of 0 V or more is applied to the gate terminal G, and the gate terminal G receives a voltage between the gate and the source. It is a transistor that switches so that current does not flow from the drain terminal D to the source terminal S when a voltage with a negative potential is applied. The current supply switch 41 switches between connection and disconnection with the power supply terminal 30, allowing current to flow from the power supply terminal 30 in the connected state, and not allowing current to flow from the power supply terminal 30 in the non-connected state.
  • N-type normally-on transistor current supply switch transistor
  • the current discharge switch 42 in the switching circuit of the n-th 1-bit element 10-n is, for example, an N-type normally-on transistor (current discharge switch transistor). If the current discharge switch 42 is a normally-on transistor, a current flows from the drain terminal D to the source terminal S when a voltage of 0 V or more is applied to the gate terminal G, and the gate terminal G flows between the gate and the source. It is a transistor that switches so that current does not flow from the drain terminal D to the source terminal S when a voltage with a negative potential is applied. A current discharge switch 42 switches charging or discharging between the 1-bit element 10-n and the capacitive load 70. FIG.
  • control switch 43 in the switching circuit of the n-th 1-bit element 10-n is, for example, an N-type normally-on transistor (control switch transistor). If the control switch 43 is a normally-on transistor, a current flows from the drain terminal D to the source terminal S when a voltage of 0 V or more is applied to the gate terminal G, and the gate terminal G receives a potential between the gate and the source. is a transistor that switches so that current does not flow from the drain terminal D to the source terminal S when a voltage is applied in which is negative. The control switch 43 disconnects the current supply switch transistor by causing the 1-bit element 10-n and the capacitive load 70 to discharge according to the value indicated by the input digital signal.
  • the transistor size of the control switch 43 is designed to be sufficiently larger than the transistor size of the current supply switch 41 and the transistor size of the current discharge switch 42 . In other words, the control switch 43 allows current to flow more easily than the current supply switch 41 and the current discharge switch 42 .
  • n-th 1-bit element 10-n As shown in the first 1-bit element 10-1 in FIG. 42 (current discharge switch transistor) is connected to the drain terminal D.
  • the source terminal S of the current discharge switch 42 (current discharge switch transistor) and the drain terminal D of the control switch 43 (control switch transistor) are connected.
  • the gate terminal G of the current supply switch 41 (current supply switch transistor), the gate terminal G of the current discharge switch 42 (current discharge switch transistor), and the current discharge and the source terminal S of the switch 42 (current discharge switch transistor) are connected.
  • the drain terminal D and the power supply terminal of the current supply switch 41 current supply switch transistor
  • the source terminal S of the current supply switch 41 current supply switch transistor
  • the drain terminal D of the current discharge switch 42 current discharge switch transistor
  • the source terminal S of the control switch 43 is grounded.
  • the gate terminal G of the control switch 43 control switch transistor
  • the n-th input terminal 20-n are connected.
  • the n-th 1-bit element 10-n charges current at the output terminal 60 when the digital signal is input from the input terminal 20-n and the digital signal indicates low voltage or off.
  • the nth 1-bit device 10-n discharges current from the output terminal 60 when the digital signal indicates a high voltage or ON.
  • the charging and discharging current values can be determined by the sizes of the transistors that constitute the current supply switch 41 and current discharge switch 42 .
  • the charging current value is determined by the size of the current supply switch transistor that constitutes the current supply switch 41 .
  • the discharge current value is determined by the size of the current discharge switch transistor that constitutes the current discharge switch 42 .
  • the value obtained by dividing the sum of the current values by the load capacitance Cout is the time differentiation or slope of the voltage.
  • the current value In from the n -th bit element is set to the current value of the following equation (2).
  • I0 is an arbitrary current value.
  • a current value I out flowing through the output terminal is represented by the following equation (3).
  • FIG. 2 is a table showing possible patterns of current values when the digital-analog converter according to the first embodiment of the present disclosure is configured with four bit elements. As shown in the table, it is possible to create different current values by 2I0 between 15I0 and -15I0 .
  • a desired analog voltage waveform can be generated by inputting a digital signal corresponding to a value obtained by differentiating a desired analog voltage waveform with respect to time.
  • FIG. 3 is a diagram explaining the operation of the 1-bit element 10 of the digital-analog converter 1 according to Embodiment 1 of the present disclosure.
  • (a), (b), (c), (d), and (e) respectively show time changes due to ON and OFF of the control switch 43 in the n-th 1-bit element 10-n.
  • the power supply voltage Vd is 30V.
  • the case of using N-type and normally-on transistors for the current supply switch 41, the current discharge switch 42, and the control switch 43 is shown.
  • FIG. 3(a) shows the state of the n-th 1-bit element 10-n just before the control switch 43 is turned on.
  • the voltage value V out appearing at the bit unit output terminal 50 of the n-th 1-bit element 10-n is 10V.
  • the current discharge switch 42 is normally on and current passes through. All the source terminals S of the switches 42 have a voltage of 10V. As a result, the voltage between these and the drain terminal D of the control switch 43 is 15V. Also, the voltage value V out appearing at the bit unit output terminal 50 is 10V.
  • FIG. 3(b) shows the state immediately after the control switch 43 is turned on from the state of FIG. 3(a).
  • the voltage applied to the gate terminal G of the current supply switch 41, the gate terminal G of the current discharge switch 42, and the source terminal S of the current discharge switch 42 changes from 10V to 0V.
  • the voltage value V out appearing at the bit unit output terminal 50 changes from 10V to 9.8V.
  • the current flowing through the control switch 43 can be divided into three components.
  • the three current components are the following (current component 1), (current component 2), and (current component 3).
  • (Current component 1) Current from power supply terminal 30 via current supply switch 41, current discharge switch 42, and control switch 43 (hereinafter referred to as "first current”).
  • (Current component 2) A current from the bit unit output terminal 50 via the current discharge switch 42 and the control switch 43 (hereinafter referred to as "second current”).
  • Current component 3) A current from a line connecting the gate terminal G of the current supply switch 41 and the gate terminal G of the current discharge switch 42 only through the control switch 43 (hereinafter referred to as "third current”). .
  • the value of the third current (4I 0 ) is the largest and the first and the value of the second current are sufficiently small relative to the value of the third current.
  • the current source of the third current is the charges accumulated at the gate terminal of the current supply switch 41 and the gate terminal of the current discharge switch 42 . Since this is discharged by the third current, the potentials of the gate terminals of the current supply switch 41 and the current discharge switch 42 drop sharply. Due to this sudden drop in potential, the voltage between the gate and source of the current supply switch 41 becomes negative. In this way, the current supply switch 41 is switched from on to off (ON ⁇ OFF) due to the change in the self-bias of the n-th 1-bit element 10-n. Then, the state shown in FIG. 3(c) is reached (OFF).
  • FIG. 3(d) shows the state immediately after the control switch 43 is turned off from the state of FIG. 3(c).
  • a current due to the potential accumulated in the bit unit output terminal 50 flows through the current discharge switch 42 .
  • the current flowing through the current discharge switch 42 is the gate terminal G of the current supply switch 41 and the gate terminal of the current discharge switch 42. Used for charging at terminal G (0V ⁇ 8.8V).
  • the current supply switch 41 is switched from off to on (OFF ⁇ ON) due to the change in self-bias of the n-th 1-bit element 10-n.
  • FIG. 3(e) shows a state in which the current supply switch 41 is turned on.
  • the bit unit output terminal 50 is charged through the current supply switch 41, and the potential at the bit unit output terminal 50 reaches the desired level. It rises with a slope (8.8V ⁇ 10V).
  • each 1-bit element 10-1, 10-2, 10-3, 10-4, . . . , 10-n, . the self-bias is changed according to the digital signal from one input terminal, and the voltage applied to the gate terminal G of the current supply switch 41 and the gate terminal G of the current discharge switch 42 is controlled to control the current supply.
  • the switch 41 and the current discharge switch 42 can be switched, the potential of the bit unit output terminal 50 can be changed, and a circuit that operates with one input terminal can be realized without providing a driver circuit.
  • a digital-to-analog converter when a digital signal is input, is connected to a plurality of 1-bit elements that respectively output currents corresponding to values indicated by the digital signal, and a plurality of 1-bit elements. and a capacitive load output from a plurality of 1-bit elements to generate an analog voltage waveform on the capacitive load that receives current output from the plurality of 1-bit elements. and a switching circuit that changes the self-bias in the 1-bit element according to the value and switches connection and disconnection with the power supply according to the change in the self-bias.
  • the switching circuit includes a current supply switch transistor that switches between connection and disconnection with the power supply, and charging or discharging between the 1-bit element and the capacitive load. a switching current discharge switch transistor, and a control switch transistor that switches the current supply switch transistor to non-connection by discharging from the 1-bit element and the capacitive load according to the value indicated by the input digital signal. .
  • the source terminal of the current supply switch transistor and the drain terminal of the current discharge switch transistor are connected, and the source terminal of the current discharge switch transistor and the control
  • the drain terminal of the switching transistor is connected, the gate terminal of the current supply switch transistor, the gate terminal of the current discharge switch transistor, and the source terminal of the current discharge switch transistor are connected, and the current supply switch transistor is connected to the drain terminal of the switch transistor.
  • the drain terminal of the transistor is connected to the power supply terminal, the source terminal of the current supply switch transistor and the drain terminal of the current discharge switch transistor are connected to the output terminal, and the source terminal of the control switch transistor is grounded and controlled.
  • the gate terminal in the switch is configured to be connected to the input terminal. This makes it possible to provide a digital-to-analog converter that achieves the same effects as those described above without complicating the circuit configuration.
  • each of the current supply switch transistor, the current discharge switch transistor, and the control switch transistor has a voltage at which the potential between the gate and the source is negative at the gate terminal. is a transistor that switches so that no current flows between the drain and source terminals when is applied.
  • any component of the embodiment can be modified or any component of the embodiment can be omitted.
  • the digital-to-analog converter according to the present disclosure can be configured with a small circuit size per 1-bit element, so it is suitable for use in, for example, a high-frequency digital-to-analog converter or a communication device including a high-frequency digital-to-analog converter. .

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
PCT/JP2021/010469 2021-03-16 2021-03-16 デジタルアナログ変換機 Ceased WO2022195692A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2023506416A JP7378663B2 (ja) 2021-03-16 2021-03-16 デジタルアナログ変換機
CN202180095391.8A CN116982261A (zh) 2021-03-16 2021-03-16 数模转换器
PCT/JP2021/010469 WO2022195692A1 (ja) 2021-03-16 2021-03-16 デジタルアナログ変換機
EP21931446.5A EP4297280B1 (en) 2021-03-16 2021-03-16 Digital-to-analog converter
US18/223,861 US12355466B2 (en) 2021-03-16 2023-07-19 Digital-to-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/010469 WO2022195692A1 (ja) 2021-03-16 2021-03-16 デジタルアナログ変換機

Related Child Applications (1)

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US18/223,861 Continuation US12355466B2 (en) 2021-03-16 2023-07-19 Digital-to-analog converter

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WO2022195692A1 true WO2022195692A1 (ja) 2022-09-22

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PCT/JP2021/010469 Ceased WO2022195692A1 (ja) 2021-03-16 2021-03-16 デジタルアナログ変換機

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US (1) US12355466B2 (https=)
EP (1) EP4297280B1 (https=)
JP (1) JP7378663B2 (https=)
CN (1) CN116982261A (https=)
WO (1) WO2022195692A1 (https=)

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Publication number Priority date Publication date Assignee Title
US12160256B2 (en) * 2021-12-22 2024-12-03 Xilinx, Inc. DAC-based transmit driver architecture with improved bandwidth

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JPS5513545A (en) * 1978-07-14 1980-01-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor d-a converter
JPS56147519A (en) * 1980-04-18 1981-11-16 Nec Corp Digital-to-analog converter
US20180014123A1 (en) * 2016-07-05 2018-01-11 Knowles Electronics, Llc Microphone assembly with digital feedback loop

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KR101705159B1 (ko) * 2010-12-16 2017-02-10 한국전자통신연구원 전류스위치 구동회로 및 디지털 아날로그 신호변환기
FR3005815B1 (fr) 2013-05-17 2019-09-20 Thales Systeme de generation d'un signal analogique
WO2015004829A1 (ja) * 2013-07-11 2015-01-15 パナソニック株式会社 電流型ｄ／ａ変換器、デルタシグマ変調器および通信装置
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JPS5513545A (en) * 1978-07-14 1980-01-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor d-a converter
JPS56147519A (en) * 1980-04-18 1981-11-16 Nec Corp Digital-to-analog converter
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Title
See also references of EP4297280A4
WEISS, M.: "Integrated 2-b Riemann Pump RF-DAC in GaN Technology for 5G Base Stations", IEEE INTERNATIONAL MICROWAVE SYMPOSIUM (IMS, 2019

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US12355466B2 (en) 2025-07-08
US20230361783A1 (en) 2023-11-09
JPWO2022195692A1 (https=) 2022-09-22
JP7378663B2 (ja) 2023-11-13
EP4297280A1 (en) 2023-12-27
EP4297280A4 (en) 2024-04-24
CN116982261A (zh) 2023-10-31
EP4297280B1 (en) 2025-05-07

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