WO2022184129A1 - 一种时隙分配处理方法、设备及存储介质 - Google Patents

一种时隙分配处理方法、设备及存储介质 Download PDF

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Publication number
WO2022184129A1
WO2022184129A1 PCT/CN2022/079019 CN2022079019W WO2022184129A1 WO 2022184129 A1 WO2022184129 A1 WO 2022184129A1 CN 2022079019 W CN2022079019 W CN 2022079019W WO 2022184129 A1 WO2022184129 A1 WO 2022184129A1
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Prior art keywords
node device
time slot
delay
time
determining
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PCT/CN2022/079019
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English (en)
French (fr)
Inventor
韩柳燕
李晗
张德朝
Original Assignee
中国移动通信有限公司研究院
中国移动通信集团有限公司
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Application filed by 中国移动通信有限公司研究院, 中国移动通信集团有限公司 filed Critical 中国移动通信有限公司研究院
Priority to EP22762591.0A priority Critical patent/EP4304268A1/en
Priority to US18/548,886 priority patent/US20240146433A1/en
Publication of WO2022184129A1 publication Critical patent/WO2022184129A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1652—Optical Transport Network [OTN]
    • H04J3/1658—Optical Transport Network [OTN] carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H04W72/044—Wireless resource allocation based on the type of the allocated resource
    • H04W72/0446—Resources in time domain, e.g. slots or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
    • H04J2203/0082—Interaction of SDH with non-ATM protocols
    • H04J2203/0085—Support of Ethernet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0091—Time slot assignment

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a time slot allocation processing method, device, and storage medium.
  • Ethernet-based slicing isolation technology For example, the FlexE (Flex Ethernet) technology led by OIF (Optical Internet Forum) provides slicing based on Ethernet physical interfaces. It can provide an effective interface-level isolation mechanism.
  • FlexE is currently only an interface-level technology and cannot meet the networking requirements of operator networks.
  • MTN Micro transport network
  • ITU-T International Telecommunication Union Telecommunication Standardization Sector
  • 5G new business requirements
  • 5G which can realize TDM (Time Division Multiplexing) , Time division multiplexing) and effective fusion of packet switching, composed of Section (segment) layer and Path (path) layer.
  • Metro transport network segment (Section) layer supports time slot division and port binding, compatible with Ethernet bottom layer protocol stack and standard Ethernet optical modules;
  • Metro transport network path (Path) layer supports TDM switching based on 66B code blocks, with The complete end-to-end OAM (Operation Administration and Maintenance) mechanism supports the cross-multiplexing of channelized client signals of any Nx5G or smaller bandwidth granularity.
  • OAM Operaation Administration and Maintenance
  • the disadvantage of the prior art is that the current method of establishing an end-to-end slice channel may increase the processing delay inside the node due to the method of time slot allocation.
  • the present application provides a time slot allocation processing method, device and storage medium, which are used to solve the problem that the processing delay in the node increases due to the time slot allocation method.
  • a time slot allocation processing method comprising:
  • the node device determines the time delay from a certain input port time slot to another port time slot inside the node device, and the node device is the node device on the end-to-end channel;
  • the node device determines the time delay for establishing end-to-end channel time slot allocation.
  • the node device determines the time delay for establishing end-to-end channel time slot allocation, including:
  • the node device sends the delay to the centralized system; and/or,
  • the node device After the node device determines the available time slot of the node device according to the time slot with the optimal time delay, it sends it to the next node device on the channel.
  • the node device determines the delay automatically determined by the node device. and/or,
  • the time delay determined by the node device is determined after the node device receives the request for determining the time delay.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines the delay from a certain input port time slot to another port time slot inside the node device, which is the time when the node device determines a certain input port p time slot A to another output port q After the internal time delay of the node in slot B, the time delay value between other time slots is determined.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • it further includes:
  • a time slot allocation processing method comprising:
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation.
  • the node device determines the delay automatically determined by the node device. and/or,
  • the time delay determined by the node device is determined after the node device receives the request for determining the time delay.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines the delay from a certain input port time slot to another port time slot inside the node device, which is the time when the node device determines a certain input port p time slot A to another output port q After the internal time delay of the node in slot B, the time delay value between other time slots is determined.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • a time slot allocation processing method comprising:
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation.
  • the node device determines the delay automatically determined by the node device. and/or,
  • the time delay determined by the node device is determined after the node device receives the request for determining the time delay.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines the delay from a certain input port time slot to another port time slot inside the node device, which is the time when the node device determines a certain input port p time slot A to another output port q After the internal time delay of the node in slot B, the time delay value between other time slots is determined.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • a time slot allocation processing method comprising:
  • the delay is the delay from each node device to determine a certain input port time slot to another port time slot inside the node device, the node device is the node on the end-to-end channel equipment, the time delay is used for establishing end-to-end channel time slot allocation;
  • End-to-end channel time slot allocation is performed according to each time delay.
  • the node device determines the delay automatically determined by the node device. and/or,
  • the time delay determined by the node device is determined after the node device receives the request for determining the time delay.
  • it further includes:
  • the determining delay request is sent to the node device on the node device path.
  • performing end-to-end channel time slot allocation according to the delay information including:
  • the time slot with the optimal delay of each node device is determined in turn as the available time slot, and the time slot allocation is performed according to the determined available time slot.
  • a node device including:
  • the processor for reading the program in memory, performs the following processes:
  • a transceiver for receiving and transmitting data under the control of the processor.
  • determining the delay for establishing an end-to-end channel slot allocation includes:
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines a certain input port p time slot A to another output port q time slot B After the internal delay of the node, determine the delay value between other time slots.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • it further includes:
  • a node device including:
  • a first determining module configured to determine the time delay from a certain input port time slot to another port time slot inside a node device, where the node device is a node device on an end-to-end channel;
  • a first sending module configured to determine the time delay for establishing end-to-end channel time slot allocation.
  • the first sending module is further configured to send the delay to the centralized system; and/or,
  • the first determining module is further configured to automatically determine the delay; and/or, determine the delay after receiving a request for determining the delay.
  • the first sending module is further configured to receive the delay determination request sent by the centralized system to the node devices on the node device path after the centralized system determines the node device path traversed by an end-to-end channel.
  • the first determining module is further configured to determine the time delay from a certain input port time slot to another port time slot inside the node device, and to determine a certain input port p time slot A to another port time slot After the internal time delay of the output port q time slot B, the time delay value between other time slots is determined.
  • the first determining module is further configured to determine delay values between other time slots according to the time slot frame structure and a pre-acquired node delay variation model.
  • the first sending module is further configured to receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal delay; After the time slot is available, it is sent to the next node device on the channel.
  • a node device including:
  • the processor for reading the program in memory, performs the following processes:
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation;
  • a transceiver for receiving and transmitting data under the control of the processor.
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines a certain input port p time slot A to another output port q time slot B After the internal delay of the node, determine the delay value between other time slots.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • a node device including:
  • the first receiving module is used to receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal time delay;
  • the second sending module is used for determining the available time slot of the node device according to the time slot with the optimal time delay, and then sending it to the next node device on the channel;
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot in the node device, and the node device is the node device on the end-to-end channel, and the delay is calculated by For establishing end-to-end channel time slot allocation.
  • the second sending module is further configured to automatically determine the delay; and/or, determine the delay after receiving the request for determining the delay.
  • the second sending module is further configured to receive the determination delay request sent by the centralized system to the node devices on the node device path after the centralized system determines the node device path traversed by an end-to-end channel.
  • the second sending module is further configured to determine the time delay from a certain input port time slot to another port time slot inside the node device, and the node device determines a certain input port p time slot A to After the internal time delay of the other output port q time slot B, the time delay value between other time slots is determined.
  • the second sending module is further configured to determine delay values between other time slots according to the time slot frame structure and a pre-acquired node delay variation model.
  • a node device including:
  • the processor for reading the program in memory, performs the following processes:
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation;
  • a transceiver for receiving and transmitting data under the control of the processor.
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines a certain input port p time slot A to another output port q time slot B After the internal delay of the node, determine the delay value between other time slots.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • a node device including:
  • the second receiving module is used to receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal time delay;
  • the first allocation module is configured to perform end-to-end channel time slot allocation according to the available time slots of each node device after determining the available time slots of the node device according to the time slot with the optimal time delay;
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation.
  • the first allocation module is further configured to automatically determine the delay; and/or, determine the delay after receiving a request for determining the delay.
  • the first allocation module is further configured to receive the delay determination request sent by the centralized system to the node devices on the node device path after the centralized system determines the node device path traversed by an end-to-end channel.
  • the first allocation module is further configured to determine the time delay from a certain input port time slot to another port time slot inside the node device, and the node device determines a certain input port p time slot A to After the internal time delay of the other output port q time slot B, the time delay value between other time slots is determined.
  • the first allocation module is further configured to determine delay values between other time slots according to the time slot frame structure and a pre-acquired node delay variation model.
  • a centralized system that includes:
  • the processor for reading the program in memory, performs the following processes:
  • the delay is the delay from each node device to determine a certain input port time slot to another port time slot inside the node device, the node device is the node on the end-to-end channel equipment, the time delay is used for establishing end-to-end channel time slot allocation;
  • a transceiver for receiving and transmitting data under the control of the processor.
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • it further includes:
  • the delay determination request is sent to the node device on the node device path.
  • performing end-to-end channel time slot allocation according to the delay information including:
  • the time slot with the optimal delay of each node device is determined in turn as the available time slot, and the time slot allocation is performed according to the determined available time slot.
  • a centralized system that includes:
  • the third receiving module is used to receive the time delay sent by each node device, the time delay is the time delay of each node device from determining a certain input port time slot to another port time slot inside the node device, and the node device is Node devices on the end-to-end channel, the time delay is used for establishing end-to-end channel time slot allocation;
  • the second allocation module is configured to perform end-to-end channel time slot allocation according to each time delay.
  • the third receiving module is further configured to receive the delay determined by the node device spontaneously; and/or, the delay determined after the node device receives the request for determining the delay.
  • the third receiving module is further configured to receive the determining delay request sent to the node device on the node device path after the node device path traversed by an end-to-end channel is determined.
  • the second allocation module is further configured to, when performing end-to-end channel time slot allocation according to the delay information, in the direction from the source end node device to the sink end node device, sequentially determine to select each The time slot with the optimal time delay of the node equipment is the available time slot, and the time slot is allocated according to the determined available time slot.
  • a computer-readable storage medium wherein the computer-readable storage medium stores a computer program for executing the above-mentioned time slot allocation processing method.
  • the node device will determine the node internal delay from a certain input port time slot to another port time slot, because the time delay information will be used as the establishment of the end-to-end time slot in the time slot allocation.
  • the input conditions of channel time slot allocation are considered, so the time delay caused by time slot allocation can be reduced in one channel, and the end-to-end channel delay can be reduced.
  • FIG. 1 is a schematic diagram of time slot allocation of an end-to-end channel in an embodiment of the present application
  • FIG. 2 is a schematic diagram of the influence of time slot selection on node delay in an embodiment of the present application
  • FIG. 3 is a schematic flowchart of the implementation of a method for processing time slot allocation in an embodiment of the present application
  • FIG. 4 is a schematic diagram of channel path establishment in an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of the implementation of a method for processing time slot allocation on a centralized system in an embodiment of the present application
  • FIG. 6 is a schematic diagram of an implementation flowchart of a method for processing time slot allocation on the side of an intermediate node device in an embodiment of the present application
  • FIG. 8 is a schematic diagram of a process of sequentially determining optimal time slots in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a first structure of a node device in an embodiment of the present application.
  • FIG. 10 is a second schematic diagram of a node device structure in an embodiment of the present application.
  • FIG. 11 is a third schematic diagram of a node device structure in an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a centralized system in an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the time slot allocation of the end-to-end channel.
  • the mth time slot time slot m
  • the nth time slot time slot m
  • slot n use the qth time slot (time slot q) for the port that is configured for output by NE3.
  • the end-to-end time slot channel can be established only when the time slots of each node are allocated end-to-end.
  • time slot allocation is done at one time, and the time slot allocation of each node in a channel mainly considers availability, and the required number of time slots can be allocated from the time slot resources available to each node port.
  • FIG. 2 is a schematic diagram of the influence of time slot selection on node delay.
  • SPN Silicon Packet Network
  • 5G calendar slot (calendar slot)
  • time slots slots
  • the embodiment of the present application proposes a new end-to-end channel establishment time slot allocation scheme, which can optimize the time delay caused by time slot allocation in one channel and meet technical and application requirements.
  • the implementation of the source end node device, the intermediate node device, the sink end node device, and the centralized system (such as the management and control system) involved in the end-to-end channel will be described respectively, and then their coordination will be given. Examples of implementations are provided to better understand the implementation of the solutions given in the examples of this application. This description does not mean that they must be implemented together or separately. In fact, when they are implemented separately, they also solve their own problems, and when they are used in combination, better technical effects will be obtained. .
  • two schemes are provided during time slot allocation, one is allocated by the centralized system, and the other is allocated by each node device, wherein the implementation of the node device that determines the delay and the transmission delay will be based on 3, the centralized system allocation scheme will be explained in FIG. 5, and the allocation scheme by each node device will be explained in FIG. 6 (intermediate node equipment) and FIG. 7 (sink node equipment).
  • FIG. 3 is a schematic flowchart of the implementation of the time slot allocation processing method. As shown in the figure, it may include:
  • Step 301 the node device determines the time delay from a certain input port time slot to another port time slot inside the node device, and the node device is the node device on the end-to-end channel;
  • Step 302 The node device determines the time delay for establishing end-to-end channel time slot allocation.
  • the node device determines the time delay for establishing end-to-end channel time slot allocation, including:
  • the node device sends the delay to the centralized system; and/or,
  • the node device determines the available time slot of the node device according to the time slot with the optimal delay, and then sends it to the next node device on the channel.
  • the node device determines the node internal delay from a certain input port time slot to another port time slot, and uses the delay information as an input condition for establishing end-to-end channel time slot allocation.
  • the node device when it is implemented, it can record a timestamp when it detects a specific mark of a certain time slot at the entrance, and when it reaches a certain time slot mark at the exit, another timestamp is recorded, and the values of the two timestamps are subtracted to obtain The delay from this time slot of the input port to the other time slot of the output port.
  • the node device determines the delay automatically determined by the node device. and/or,
  • the time delay determined by the node device is determined after the node device receives the request for determining the time delay.
  • the node device determines whether the delay is determined by itself or after receiving a request.
  • the node device can automatically determine the internal time delay of a certain input port to another port time slot (for example, when the device is started), or the node device only starts to determine a certain input port time slot of the node when it receives a request. Node internal delay to another port slot.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the centralized system requests the node internal time delay from the input port time slot to the output port time slot of the corresponding ports of the nodes on this path.
  • Figure 4 is a schematic diagram of channel path establishment.
  • the centralized system such as a management and control system
  • the system calculates and determines a path from node m to node n based on network information (such as network topology, available time slot resources, etc.), including intermediate node information, the ingress and egress ports of each node, and then Request the node internal delay from the input port time slot to the output port time slot of the corresponding ports of these nodes on this path that has been determined.
  • network information such as network topology, available time slot resources, etc.
  • the node device determines the delay from one input port time slot to another port time slot inside the node device, which is the delay inside the node device that determines the node internal delay from one input port p time slot A to another output port q time slot B , to determine the delay value between other time slots.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • the node device determines the internal time delay of a certain input port p time slot A to another output port q time slot B, it calculates other time slots according to the time slot frame structure and the pre-acquired node time delay variation model. delay value between.
  • the internal delay of the node in slot D) does not need to be tested and determined for each one. It can be determined according to the delay value of the input port p time slot A to the output port q time slot B, according to the time slot frame structure and the pre-obtained node delay change. model is calculated.
  • Time slot allocation is performed by a centralized system.
  • FIG. 5 is a schematic flowchart of the implementation of the time slot allocation processing method on the centralized system. As shown in the figure, it may include:
  • Step 501 Receive the time delay sent by each node device, the time delay is the time delay from each node device to determine a certain input port time slot to another port time slot inside the node device, and the node device is an end-to-end channel Node equipment on the device, the time delay is used for establishing end-to-end channel time slot allocation;
  • Step 502 Perform end-to-end channel time slot allocation according to each time delay.
  • the node device determines the delay automatically determined by the node device. and/or,
  • the time delay determined by the node device is determined after the node device receives the request for determining the time delay.
  • it may further include:
  • the delay determination request is sent to the node device on the node device path.
  • performing end-to-end channel time slot allocation according to the delay information including:
  • the time slot with the optimal delay of each node device is determined in turn as the available time slot, and the time slot allocation is performed according to the determined available time slot.
  • the optimal delay is not necessarily the minimum delay, the minimum delay is one of the cases, and other strategies are also possible.
  • the optimal available time slot allocation for each node's time delay, the optimal time delay can be the time slot with the smallest time delay, or the time slot with the second smallest time delay selected considering a certain jitter tolerance. Because the time slot with the smallest delay is assumed to be jittered and the phase changes a little earlier, it may happen that the output just can’t catch up with this time slot in this round, so we have to wait one round and put it into the next round of this time slot, but the time delay will become relatively large. Case.
  • the node device reports it to the centralized system.
  • the centralized system obtains all the delay information on the path, it starts from the source node. In the direction to the sink node, the available time slot allocation with the optimal delay of each node is determined in turn.
  • the centralized system performs time slot allocation according to the determined time slot, and establishes a channel.
  • Time slot allocation is performed by each node device.
  • the time slot allocation can also be determined by each node, and then sent to the next node through a message, so as to determine the optimal time slot allocation for each node in turn.
  • FIG. 6 is a schematic diagram of the implementation flowchart of the time slot allocation processing method on the side of the intermediate node device. As shown in the figure, it may include:
  • Step 601 Receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal time delay
  • Step 602 After determining the available time slot of the node device according to the time slot with the optimal time delay, send it to the next node device on the channel;
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot in the node device, and the node device is the node device on the end-to-end channel, and the delay is calculated by For establishing end-to-end channel time slot allocation.
  • FIG. 7 is a schematic flowchart of the implementation of the time slot allocation processing method on the sink node device side. As shown in the figure, it may include:
  • Step 701 Receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal time delay
  • Step 702 After determining the available time slot of the node device according to the time slot with the optimal time delay, perform end-to-end channel time slot allocation according to the available time slot of each node device;
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot in the node device, and the node device is the node device on the end-to-end channel, and the delay is calculated by For establishing end-to-end channel time slot allocation.
  • Figure 8 is a schematic diagram of the process of determining the optimal time slot in turn.
  • the optimal time slot allocation for each node is the optimal time delay, and the optimal time delay can be the optimal time delay.
  • the time slot can also be the time slot with the second smallest delay considering the tolerance of a certain jitter. Because the time slot with the optimal delay is assumed to be jittered, and the phase changes a little earlier, it may happen that the output cannot catch up with this time slot in this round, and it must wait for one round and put it into the next round of this time slot, but the time delay will become a comparison big situation.
  • the above process can be performed independently in the two directions, respectively, and the time slot to be used is determined respectively.
  • a node device a centralized system, and a computer-readable storage medium are also provided in the embodiments of the present application. Since the principle of these devices for solving problems is similar to the time slot allocation processing method on the node device and the centralized system, Therefore, for the implementation of these devices, reference may be made to the implementation of the method, and the repetition will not be repeated.
  • Figure 9 is a schematic diagram of the structure of the node device. As shown in the figure, the node device includes:
  • the processor 900 is configured to read the program in the memory 920 and perform the following processes:
  • the transceiver 910 is used to receive and transmit data under the control of the processor 900 .
  • determining the delay for establishing an end-to-end channel slot allocation includes:
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines a certain input port p time slot A to another output port q time slot B After the internal delay of the node, determine the delay value between other time slots.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • it further includes:
  • the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 900 and various circuits of memory represented by memory 920 are linked together.
  • the bus architecture may also link together various other circuits, such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be described further herein.
  • the bus interface provides the interface.
  • Transceiver 910 may be a number of elements, including a transmitter and a receiver, that provide a means for communicating with various other devices over a transmission medium.
  • the processor 900 is responsible for managing the bus architecture and general processing, and the memory 920 may store data used by the processor 900 in performing operations.
  • the embodiment of the present application also provides a node device, including:
  • a first determining module configured to determine the time delay from a certain input port time slot to another port time slot inside a node device, where the node device is a node device on an end-to-end channel;
  • a first sending module configured to determine the time delay for establishing end-to-end channel time slot allocation.
  • the first sending module is further configured to send the time delay to the centralized system; and/or, after determining the available time slot of the node device according to the time slot with the optimal time delay, send the time delay to the channel on the channel next node device.
  • the first determining module is further configured to automatically determine the delay; and/or, determine the delay after receiving a request for determining the delay.
  • the first sending module is further configured to receive the delay determination request sent by the centralized system to the node devices on the node device path after the centralized system determines the node device path traversed by an end-to-end channel.
  • the first determining module is further configured to determine the time delay from a certain input port time slot to another port time slot inside the node device, and to determine a certain input port p time slot A to another port time slot After the internal time delay of the output port q time slot B, the time delay value between other time slots is determined.
  • the first determining module is further configured to determine delay values between other time slots according to the time slot frame structure and a pre-acquired node delay variation model.
  • the first sending module is further configured to receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal delay; After the time slot is available, it is sent to the next node device on the channel.
  • each part of the device described above is divided into various modules or units by function and described respectively.
  • the functions of each module or unit may be implemented in one or more software or hardware.
  • Figure 10 is a schematic diagram of the second structure of the node device. As shown in the figure, the node device includes:
  • the processor 1000 is configured to read the program in the memory 1020, and perform the following processes:
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation;
  • the transceiver 1010 is used for receiving and transmitting data under the control of the processor 1000 .
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines a certain input port p time slot A to another output port q time slot B After the internal delay of the node, determine the delay value between other time slots.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1000 and various circuits of memory represented by memory 1020 linked together.
  • the bus architecture may also link together various other circuits, such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be described further herein.
  • the bus interface provides the interface.
  • Transceiver 1010 may be a number of elements, including a transmitter and a receiver, that provide a means for communicating with various other devices over a transmission medium.
  • the processor 1000 is responsible for managing the bus architecture and general processing, and the memory 1020 may store data used by the processor 1000 when performing operations.
  • the embodiment of the present application also provides a node device, including:
  • the first receiving module is used to receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal time delay;
  • the second sending module is used for determining the available time slot of the node device according to the time slot with the optimal time delay, and then sending it to the next node device on the channel;
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot in the node device, and the node device is the node device on the end-to-end channel, and the delay is calculated by For establishing end-to-end channel time slot allocation.
  • the second sending module is further configured to automatically determine the delay; and/or, determine the delay after receiving the request for determining the delay.
  • the second sending module is further configured to receive the determination delay request sent by the centralized system to the node devices on the node device path after the centralized system determines the node device path traversed by an end-to-end channel.
  • the second sending module is further configured to determine the time delay from a certain input port time slot to another port time slot inside the node device, and the node device determines a certain input port p time slot A to After the internal time delay of the other output port q time slot B, the time delay value between other time slots is determined.
  • the second sending module is further configured to determine delay values between other time slots according to the time slot frame structure and a pre-acquired node delay variation model.
  • each part of the device described above is divided into various modules or units by function and described respectively.
  • the functions of each module or unit may be implemented in one or more software or hardware.
  • FIG 11 is a schematic diagram of the third structure of the node device. As shown in the figure, the node device includes:
  • the processor 1100 is configured to read the program in the memory 1120 and perform the following processes:
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation;
  • the transceiver 1110 is used to receive and transmit data under the control of the processor 1100 .
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • the request for determining the delay is sent by the centralized system to the node device on the node device path after determining the node device path traversed by an end-to-end channel.
  • the node device determines a certain input port p time slot A to another output port q time slot B After the internal delay of the node, determine the delay value between other time slots.
  • determining the delay value between other time slots is based on the time slot frame structure and a pre-acquired node delay variation model to determine the delay value between other time slots.
  • the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1100 and various circuits of memory represented by memory 1120 are linked together.
  • the bus architecture may also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein.
  • the bus interface provides the interface.
  • Transceiver 1110 may be a number of elements, including a transmitter and a receiver, that provide a means for communicating with various other devices over a transmission medium.
  • the processor 1100 is responsible for managing the bus architecture and general processing, and the memory 1120 may store data used by the processor 1100 in performing operations.
  • the embodiment of the present application also provides a node device, including:
  • the second receiving module is used to receive the available time slot determined by the previous node device on the channel according to the time slot with the optimal time delay;
  • the first allocation module is configured to perform end-to-end channel time slot allocation according to the available time slots of each node device after determining the available time slots of the node device according to the time slot with the optimal time delay;
  • the delay of determining the available time slot is the delay of each node device from determining a certain input port time slot to another port time slot within the node device.
  • the node device is the node device on the end-to-end channel, and the delay is used for establishing End-to-end channel slot allocation.
  • the first allocation module is further configured to automatically determine the delay; and/or, determine the delay after receiving a request for determining the delay.
  • the first allocation module is further configured to receive the delay determination request sent by the centralized system to the node devices on the node device path after the centralized system determines the node device path traversed by an end-to-end channel.
  • the first allocation module is further configured to determine the time delay from a certain input port time slot to another port time slot inside the node device, and the node device determines a certain input port p time slot A to After the internal time delay of the other output port q time slot B, the time delay value between other time slots is determined according to the time slot frame structure and the pre-acquired node time delay variation model.
  • the first allocation module is further configured to determine delay values between other time slots according to the time slot frame structure and a pre-acquired node delay variation model.
  • each part of the device described above is divided into various modules or units by function and described respectively.
  • the functions of each module or unit may be implemented in one or more software or hardware.
  • Figure 12 is a schematic diagram of the structure of the centralized system. As shown in the figure, the centralized system includes:
  • the processor 1200 is configured to read the program in the memory 1220 and perform the following processes:
  • the delay is the delay from each node device to determine a certain input port time slot to another port time slot inside the node device, the node device is the node on the end-to-end channel equipment, the time delay is used for establishing end-to-end channel time slot allocation;
  • the transceiver 1210 is used to receive and transmit data under the control of the processor 1200 .
  • the determination delay is determined by the node device autonomously; and/or,
  • the determination delay is determined after the node device receives the determination delay request.
  • it further includes:
  • the determining delay request is sent to the node device on the node device path.
  • performing end-to-end channel time slot allocation according to the delay information including:
  • the time slot with the optimal delay of each node device is determined in turn as the available time slot, and the time slot allocation is performed according to the determined available time slot.
  • the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1200 and various circuits of memory represented by memory 1220 are linked together.
  • the bus architecture may also link together various other circuits, such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be described further herein.
  • the bus interface provides the interface.
  • Transceiver 1210 may be a number of elements, including a transmitter and a receiver, that provide a means for communicating with various other devices over a transmission medium.
  • the processor 1200 is responsible for managing the bus architecture and general processing, and the memory 1220 may store data used by the processor 1200 in performing operations.
  • the embodiment of the present application also provides a centralized system, including:
  • the third receiving module is used to receive the time delay sent by each node device, the time delay is the time delay of each node device from determining a certain input port time slot to another port time slot inside the node device, and the node device is Node devices on the end-to-end channel, the time delay is used for establishing end-to-end channel time slot allocation;
  • the second allocation module is configured to perform end-to-end channel time slot allocation according to each time delay.
  • the third receiving module is further configured to receive the delay determined by the node device spontaneously; and/or, the delay determined after the node device receives the request for determining the delay.
  • the third receiving module is further configured to receive the determining delay request sent to the node device on the node device path after the node device path traversed by an end-to-end channel is determined.
  • the second allocation module is further configured to, when performing end-to-end channel time slot allocation according to the delay information, in the direction from the source end node device to the sink end node device, sequentially determine to select each The time slot with the optimal time delay of the node equipment is the available time slot, and the time slot is allocated according to the determined available time slot.
  • each part of the device described above is divided into various modules or units by function and described respectively.
  • the functions of each module or unit may be implemented in one or more software or hardware.
  • An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for executing the above processing method for time slot allocation.
  • the node device determines the node internal delay from a certain input port time slot to another port time slot, and uses the delay information as the time when the end-to-end channel is established. input conditions for slot assignment. Specifically, it also provides:
  • the node device determines whether the delay is determined by itself or after receiving a request.
  • the centralized system After the centralized system determines a channel path, it then requests the node internal time delay from the input port time slot to the output port time slot of the corresponding ports of these nodes on this path.
  • the centralized system After the centralized system obtains all the delay information on the path, from the source node to the sink node, the available time slot allocation with the optimal delay of each node is determined in turn. After the time slot is determined, the centralized system performs time slot allocation according to the determined time slot, and establishes a channel.
  • the time slot allocation can also be determined by each node, and then sent to the next node through a message, so as to determine the optimal time slot allocation for each node in turn.
  • the node device After the node device determines the internal time delay of a certain input port p time slot A to another output port q time slot B, it calculates the time delay between other time slots according to the time slot frame structure and the pre-acquired node time delay variation model. delay value.
  • This scheme proposes a set of effective end-to-end channel establishment including time slot allocation, which can optimize the time delay caused by time slot allocation in one channel and reduce the end-to-end channel delay.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

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Abstract

本申请公开了一种时隙分配处理方法、设备及存储介质，包括：节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；节点设备确定该时延用以供建立端到端的通道时隙分配。接收各节点设备发送的时延，根据各时延进行端到端的通道时隙分配。采用本申请，能够在一条通道中减小时隙分配带来的时延，降低端到端通道时延。

Description

一种时隙分配处理方法、设备及存储介质
相关申请的交叉引用
本申请基于申请号为202110235233.X、申请日为2021年03月03日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及通信技术领域，特别涉及一种时隙分配处理方法、设备及存储介质。
背景技术
随着5G的发展以及垂直行业用户的增多，网络对切片的需求增强。业界在基于以太网的切片隔离技术上进行了很多有益的探索，例如OIF(光联网论坛，Optical Internet Forum)主导的FlexE(灵活以太网，Flex Ethernet)技术提供了基于以太网物理接口的分片机制，能提供有效的接口级隔离机制。但FlexE当前仅为接口级技术，无法满足运营商网络的组网要求。MTN(城域传送网，Metro transport network)为ITU-T(国际电信联盟电信标准化组，ITU-Telecommunication standardization sector)针对5G等新业务需求定义的新型传送网技术体系，能够实现TDM(时分复用，Time division multiplexing)与分组交换的有效融合，由Section(段)层和Path(通路)层构成。城域传送网段(Section)层支持时隙划分支持端口绑定，兼容以太网底层协议栈及标准以太网光模块；城域传送网通路(Path)层支持基于66B码块的TDM交换，具备完善的端到端OAM(操作管理维护，Operation Administration and Maintenance)机制，支持任意Nx5G或者更小带宽颗粒的信道化客户信号的交叉复用。
现有技术的不足在于：当前在端到端的切片通道的建立方式，会因时隙分配的方式会导致在节点内部的处理时延增大。
发明内容
本申请提供了一种时隙分配处理方法、设备及存储介质，用以解决因时隙分配的方式会导致在节点内部的处理时延增大的问题。
本申请提供以下技术方案：
一种时隙分配处理方法，包括：
节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
节点设备确定该时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，节点设备确定该时延用以供建立端到端的通道时隙分配，包括：
节点设备向集中系统发送该时延；和/或，
节点设备根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
在一些可选实施方式中，节点设备确定时延是节点设备自发确定的；和/或，
节点设备确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
在一些可选实施方式中，进一步包括：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
一种时隙分配处理方法，包括：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，节点设备确定时延是节点设备自发确定的；和/或，
节点设备确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
一种时隙分配处理方法，包括：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，节点设备确定时延是节点设备自发确定的；和/或，
节点设备确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
一种时隙分配处理方法，包括：
接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
根据各时延进行端到端的通道时隙分配。
在一些可选实施方式中，节点设备确定时延是节点设备自发确定的；和/或，
节点设备确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，进一步包括：
在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，根据该时延信息进行端到端的通道时隙分配，包括：
从源端节点设备开始到宿端节点设备的方向，依次确定选取每个节点设备时延最优的时隙为可用时隙，依据确定的可用时隙进行时隙分配。
一种节点设备，包括：
处理器，用于读取存储器中的程序，执行下列过程：
确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
确定该时延用以供建立端到端的通道时隙分配；
收发机，用于在处理器的控制下接收和发送数据。
在一些可选实施方式中，确定该时延用以供建立端到端的通道时隙分配，包括：
向集中系统发送该时延；和/或，
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
在一些可选实施方式中，进一步包括：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
一种节点设备，包括：
第一确定模块，用于确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
第一发送模块，用于确定该时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，第一发送模块进一步用于向集中系统发送该时延；和/或，
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
在一些可选实施方式中，第一确定模块进一步用于自发确定时延；和/或，接收到确定时延请求后确定时延。
在一些可选实施方式中，第一发送模块进一步用于接收集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，第一确定模块进一步用于在确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延时，确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，第一确定模块进一步用于依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值。
在一些可选实施方式中，第一发送模块进一步用于接收通道上的上一 节点设备根据时延最优的时隙确定的可用时隙；根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
一种节点设备，包括：
处理器，用于读取存储器中的程序，执行下列过程：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配；
收发机，用于在处理器的控制下接收和发送数据。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
一种节点设备，包括：
第一接收模块，用于接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
第二发送模块，用于根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；
其中：确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，第二发送模块进一步用于自发确定时延；和/或，接收到确定时延请求后确定时延。
在一些可选实施方式中，第二发送模块进一步用于接收集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，第二发送模块进一步用于在确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延时，节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，第二发送模块进一步用于依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值。
一种节点设备，包括：
处理器，用于读取存储器中的程序，执行下列过程：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配；
收发机，用于在处理器的控制下接收和发送数据。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条 端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
一种节点设备，包括：
第二接收模块，用于接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
第一分配模块，用于根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，第一分配模块进一步用于自发确定时延；和/或，接收到确定时延请求后确定时延。
在一些可选实施方式中，第一分配模块进一步用于接收集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，第一分配模块进一步用于在确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延时，节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，第一分配模块进一步用于依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值。
一种集中系统，包括：
处理器，用于读取存储器中的程序，执行下列过程：
接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
根据各时延进行端到端的通道时隙分配；
收发机，用于在处理器的控制下接收和发送数据。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，进一步包括：
在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送所述确定时延请求。
在一些可选实施方式中，根据该时延信息进行端到端的通道时隙分配，包括：
从源端节点设备开始到宿端节点设备的方向，依次确定选取每个节点设备时延最优的时隙为可用时隙，依据确定的可用时隙进行时隙分配。
一种集中系统，包括：
第三接收模块，用于接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
第二分配模块，用于根据各时延进行端到端的通道时隙分配。
在一些可选实施方式中，第三接收模块进一步用于接收节点设备自发确定的时延；和/或，节点设备接收到确定时延请求后确定的时延。
在一些可选实施方式中，第三接收模块进一步用于接收在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送 的所述确定时延请求。
在一些可选实施方式中，第二分配模块进一步用于在根据该时延信息进行端到端的通道时隙分配时，从源端节点设备开始到宿端节点设备的方向，依次确定选取每个节点设备时延最优的时隙为可用时隙，依据确定的可用时隙进行时隙分配。
一种计算机可读存储介质，其中，所述计算机可读存储介质存储有执行上述时隙分配处理方法的计算机程序。
本申请有益效果如下：
在本申请实施例提供的技术方案中，节点设备会确定某一个输入端口时隙到另外一个端口时隙的节点内部时延，由于在时隙分配时会将该时延信息作为建立端到端通道时隙分配的输入条件来进行考虑，因此能够在一条通道中减小时隙分配带来的时延，降低端到端通道时延。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本申请实施例中端到端通道的时隙分配示意图；
图2为本申请实施例中时隙选择对节点时延影响示意图；
图3为本申请实施例中时隙分配处理方法实施流程示意图；
图4为本申请实施例中通道路径建立示意图；
图5为本申请实施例中集中系统上的时隙分配处理方法实施流程示意图；
图6为本申请实施例中中间节点设备侧的时隙分配处理方法实施流程示意图；
图7为本申请实施例中宿节点设备侧的时隙分配处理方法实施流程示 意图；
图8为本申请实施例中依次确定最优时隙过程示意图；
图9为本申请实施例中节点设备结构一示意图；
图10为本申请实施例中节点设备结构二示意图；
图11为本申请实施例中节点设备结构三示意图；
图12为本申请实施例中集中系统结构示意图。
具体实施方式
发明人在发明过程中注意到：
为了建立一条端到端的通道，例如从源节点NE1到宿节点NEn，需要配置每一个节点的端口时隙(slot)，如下图所示。例如端到端通道需要10Mbps带宽，每一个时隙的最小带宽颗粒是10Mbps带宽，那么需要为每个节点配置1个时隙数量。图1为端到端通道的时隙分配示意图，如图所示，给NE1配置输出的端口使用第m个时隙(时隙m)，给NE2配置输出的端口使用第n个时隙(时隙n)，给NE3配置输出的端口使用第q个时隙(时隙q)。当端到端每个节点的时隙都分配好，才能建立端到端的时隙通道。
现有技术中，时隙分配是一次完成的，一条通道中每一个节点的时隙分配主要考虑可用性，从每个节点端口可用的时隙资源中分配到需要的时隙数量就可以。
但是随着时隙带宽的减小，在节点内部的处理时延会相应增大。节点处理时延成为一个必须关注的因素。如何降低处理时延。其中时延有一大部分因素，和时隙分配是有关系的。图2为时隙选择对节点时延影响示意图，例如图2所示，假设采用SPN(切片分组网，Slicing Packet Network)10M切片颗粒度的时隙结构，在5G的calendar slot(日历时隙)内有480个时隙(slot)可以选择，选择这480个的第一个时隙还是最后一个时隙或者其他时隙，对于节点时延有明显影响。假设某个入时隙通道在节点内部 完成交叉之后要往出发送，这时候假设正好对上了480个的第一个时隙，而选择的出时隙也是第一个时隙，则时延最短；假设正好往出发送对上了480个的第一个时隙，但选择的出时隙是480个时隙的最后一个时隙，则必须等待至最后一个时隙，才能填充发出，这时时延就会比较长。
基于此，本申请实施例中提出一种新的端到端通道建立时隙分配的方案，能够在一条通道中优化时隙分配带来的时延，满足技术和应用需求。
下面结合附图对本申请的具体实施方式进行说明。
在说明过程中，将分别从端到端通道中涉及的源端节点设备、中间节点设备、宿端节点设备、以及集中系统(例如管控系统)侧的实施进行说明，然后还将给出它们配合实施的实例以更好地理解本申请实施例中给出的方案的实施。这样的说明方式并不意味着它们必须配合实施、或者必须单独实施，实际上，当它们分开实施时，其也各自解决自身一侧的问题，而它们结合使用时，会获得更好的技术效果。
本申请实施例中，在时隙分配时，提供了两种方案，一种是由集中系统分配，一种是由各节点设备分配，其中，确定时延、发送时延的节点设备的实施将在图3中进行说明，集中系统分配的方案将在图5中进行说明，由各节点设备分配的方案将在图6(中间节点设备)、图7(宿端节点设备)中进行说明。
图3为时隙分配处理方法实施流程示意图，如图所示，可以包括：
步骤301、节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
步骤302、节点设备确定该时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，节点设备确定该时延用以供建立端到端的通道时隙分配，包括：
节点设备向集中系统发送该时延；和/或，
节点设备根据时延最优的时隙确定本节点设备的可用时隙后，发送给 通道上的下一节点设备。
在一些可选实施方式中，节点设备确定某一个输入端口时隙到另外一个端口时隙的节点内部时延，并将该时延信息作为建立端到端通道时隙分配的输入条件。
具体的，节点设备实现时可以检测到入口某个时隙特定标志时，记录一个时间戳，到了出口某个时隙标志时，再记录一个时间戳，将两个时间戳数值相减，可以得到输入端口这个时隙到输出端口另一个时隙的时延。
在一些可选实施方式中，节点设备确定时延是节点设备自发确定的；和/或，
节点设备确定时延是节点设备接收到确定时延请求后确定的。
具体的，节点设备确定时延是自发确定或者接受请求再确定。
节点设备可以自发确定某一个输入端口时隙到另外一个端口时隙的节点内部时延(例如在设备启动时)，或者节点设备在收到请求时，才开始确定该节点某一个输入端口时隙到另外一个端口时隙的节点内部时延。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
具体的，集中系统确定好一条通道路径后，再请求已经确定的这条路径上的这些节点的对应端口的输入端口时隙到输出端口时隙的节点内部时延。
图4为通道路径建立示意图，如图所示，收到请求的情况可以是：集中系统(比如管控系统)确定需要建立某一个带宽从节点m到另外一个节点n的端到端通道后，集中系统基于网络信息(例如包括网络拓扑，节点可用时隙资源情况等)，计算确定好一条节点m到节点n的路径，包括中间节点信息，每个节点的入端口和出端口，这时候，再请求已经确定的这条路径上的这些节点的对应端口的输入端口时隙到输出端口时隙的节点内部 时延。
节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
具体的，节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，依据时隙帧结构以及预先获取的节点时延变化模型进行计算得到其他时隙之间的时延值。
节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，对于端口p的其他时隙(例如时隙C)到端口q的其他时隙(例如时隙D)的节点内部时延不需要每一个都进行测试确定，可以根据输入端口p时隙A到输出端口q时隙B的时延值，依据时隙帧结构以及预先获取的节点时延变化模型进行计算得到。
下面分别说明。
一、由集中系统进行时隙分配。
图5为集中系统上的时隙分配处理方法实施流程示意图，如图所示，可以包括：
步骤501、接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
步骤502、根据各时延进行端到端的通道时隙分配。
在一些可选实施方式中，节点设备确定时延是节点设备自发确定的；和/或，
节点设备确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，还可以进一步包括：
在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送所述确定时延请求。
在一些可选实施方式中，根据该时延信息进行端到端的通道时隙分配，包括：
从源端节点设备开始到宿端节点设备的方向，依次确定选取每个节点设备时延最优的时隙为可用时隙，依据确定的可用时隙进行时隙分配。
时延最优不一定是时延最小，时延最小是其中一种情况，也可以有其他策略。每个节点时延最优的可用时隙分配，这块时延最优可以是时延最小的时隙，也可以是考虑到容忍一定抖动情况下，选择的时延次小的时隙。因为时延最小的时隙假设发生抖动，相位有变化提前一点，可能正好输出赶不上这轮这个时隙，就必须等待一轮之后放入下一轮这个时隙，反而时延会变成比较大的情况。
具体的，节点设备确定某一个输入端口时隙A到另外一个端口时隙B的节点内部时延之后，上报集中系统，集中系统获取到该条路径上所有时延信息之后，从源端节点开始到宿端节点的方向，依次确定选取每个节点时延最优的可用时隙分配。在确定时隙之后，集中系统依据确定的时隙进行时隙分配，建立通道。
二、由各节点设备进行时隙分配。
在没有集中系统或者不需要集中系统的情况下，时隙分配也可以由每个节点确定之后，通过消息发送给下一个节点，从而依次确定选取每个节点时延最优的可用时隙分配。
图6为中间节点设备侧的时隙分配处理方法实施流程示意图，如图所示，可以包括：
步骤601、接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
步骤602、根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；
其中：确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
图7为宿节点设备侧的时隙分配处理方法实施流程示意图，如图所示，可以包括：
步骤701、接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
步骤702、根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；
其中：确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
图8为依次确定最优时隙过程示意图，如图所示，在上述时隙分配过程中，每个节点时延最优的可用时隙分配，这块时延最优可以是时延最优的时隙，也可以是考虑到容忍一定抖动情况下，选择的时延次小的时隙。因为时延最优的时隙假设发生抖动，相位有变化提前一点，可能正好输出赶不上这轮这个时隙，就必须等待一轮之后放入下一轮这个时隙，反而时延会变成比较大的情况。
对于双向通道，两个方向可以分别独立执行以上过程，分别确定采用的时隙。
基于同一发明构思，本申请实施例中还提供了一种节点设备、集中系统、及计算机可读存储介质，由于这些设备解决问题的原理与节点设备、集中系统上的时隙分配处理方法相似，因此这些设备的实施可以参见方法的实施，重复之处不再赘述。
在实施本申请实施例提供的技术方案时，可以按如下方式实施。
图9为节点设备结构一示意图，如图所示，节点设备中包括：
处理器900，用于读取存储器920中的程序，执行下列过程：
确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
确定该时延用以供建立端到端的通道时隙分配；
收发机910，用于在处理器900的控制下接收和发送数据。
在一些可选实施方式中，确定该时延用以供建立端到端的通道时隙分配，包括：
向集中系统发送该时延；和/或，
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
在一些可选实施方式中，进一步包括：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
其中，在图9中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器900代表的一个或多个处理器和存储器920代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机910可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元。处理器900负责管理总线架构和通常的处理，存储器920可以存储处理器900在执行操作时所使用的数据。
本申请实施例中还提供了一种节点设备，包括：
第一确定模块，用于确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
第一发送模块，用于确定该时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，第一发送模块进一步用于向集中系统发送该时延；和/或，根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
在一些可选实施方式中，第一确定模块进一步用于自发确定时延；和/或，接收到确定时延请求后确定时延。
在一些可选实施方式中，第一发送模块进一步用于接收集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，第一确定模块进一步用于在确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延时，确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，第一确定模块进一步用于依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值。
在一些可选实施方式中，第一发送模块进一步用于接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
为了描述的方便，以上所述装置的各部分以功能分为各种模块或单元分别描述。当然，在实施本申请时可以把各模块或单元的功能在同一个或多个软件或硬件中实现。
图10为节点设备结构二示意图，如图所示，节点设备中包括：
处理器1000，用于读取存储器1020中的程序，执行下列过程：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配；
收发机1010，用于在处理器1000的控制下接收和发送数据。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
其中，在图10中，总线架构可以包括任意数量的互联的总线和桥，具 体由处理器1000代表的一个或多个处理器和存储器1020代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机1010可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元。处理器1000负责管理总线架构和通常的处理，存储器1020可以存储处理器1000在执行操作时所使用的数据。
本申请实施例中还提供了一种节点设备，包括：
第一接收模块，用于接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
第二发送模块，用于根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；
其中：确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，第二发送模块进一步用于自发确定时延；和/或，接收到确定时延请求后确定时延。
在一些可选实施方式中，第二发送模块进一步用于接收集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，第二发送模块进一步用于在确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延时，节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，第二发送模块进一步用于依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值。
为了描述的方便，以上所述装置的各部分以功能分为各种模块或单元分别描述。当然，在实施本申请时可以把各模块或单元的功能在同一个或多个软件或硬件中实现。
图11为节点设备结构三示意图，如图所示，节点设备中包括：
处理器1100，用于读取存储器1120中的程序，执行下列过程：
接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配；
收发机1110，用于在处理器1100的控制下接收和发送数据。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
在一些可选实施方式中，确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
在一些可选实施方式中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
其中，在图11中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器1100代表的一个或多个处理器和存储器1120代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因 此，本文不再对其进行进一步描述。总线接口提供接口。收发机1110可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元。处理器1100负责管理总线架构和通常的处理，存储器1120可以存储处理器1100在执行操作时所使用的数据。
本申请实施例中还提供了一种节点设备，包括：
第二接收模块，用于接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
第一分配模块，用于根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
在一些可选实施方式中，第一分配模块进一步用于自发确定时延；和/或，接收到确定时延请求后确定时延。
在一些可选实施方式中，第一分配模块进一步用于接收集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，第一分配模块进一步用于在确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延时，节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值。
在一些可选实施方式中，第一分配模块进一步用于依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值。
为了描述的方便，以上所述装置的各部分以功能分为各种模块或单元分别描述。当然，在实施本申请时可以把各模块或单元的功能在同一个或 多个软件或硬件中实现。
图12为集中系统结构示意图，如图所示，集中系统中包括：
处理器1200，用于读取存储器1220中的程序，执行下列过程：
接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
根据各时延进行端到端的通道时隙分配；
收发机1210，用于在处理器1200的控制下接收和发送数据。
在一些可选实施方式中，确定时延是节点设备自发确定的；和/或，
确定时延是节点设备接收到确定时延请求后确定的。
在一些可选实施方式中，进一步包括：
在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，根据该时延信息进行端到端的通道时隙分配，包括：
从源端节点设备开始到宿端节点设备的方向，依次确定选取每个节点设备时延最优的时隙为可用时隙，依据确定的可用时隙进行时隙分配。
其中，在图12中，总线架构可以包括任意数量的互联的总线和桥，具体由处理器1200代表的一个或多个处理器和存储器1220代表的存储器的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机1210可以是多个元件，即包括发送机和接收机，提供用于在传输介质上与各种其他装置通信的单元。处理器1200负责管理总线架构和通常的处理，存储器1220可以存储处理器1200在执行操作时所使用的数据。
本申请实施例中还提供了一种集中系统，包括：
第三接收模块，用于接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
第二分配模块，用于根据各时延进行端到端的通道时隙分配。
在一些可选实施方式中，第三接收模块进一步用于接收节点设备自发确定的时延；和/或，节点设备接收到确定时延请求后确定的时延。
在一些可选实施方式中，第三接收模块进一步用于接收在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的所述确定时延请求。
在一些可选实施方式中，第二分配模块进一步用于在根据该时延信息进行端到端的通道时隙分配时，从源端节点设备开始到宿端节点设备的方向，依次确定选取每个节点设备时延最优的时隙为可用时隙，依据确定的可用时隙进行时隙分配。
为了描述的方便，以上所述装置的各部分以功能分为各种模块或单元分别描述。当然，在实施本申请时可以把各模块或单元的功能在同一个或多个软件或硬件中实现。
本申请实施例中还提供了一种计算机可读存储介质，其中，所述计算机可读存储介质存储有执行上述时隙分配处理方法的计算机程序。
具体实施可以参见节点设备、中间节点设备、宿节点设备、集中系统之一或者其组合的时隙分配处理方法的实施。
综上所述，在本申请实施例提供的技术方案中，节点设备确定某一个输入端口时隙到另外一个端口时隙的节点内部时延，并将该时延信息作为建立端到端通道时隙分配的输入条件。具体还提供了：
节点设备确定时延是自发确定或者接受请求再确定。
集中系统确定好一条通道路径后，再请求已经确定的这条路径上的这些节点的对应端口的输入端口时隙到输出端口时隙的节点内部时延。
集中系统获取到该条路径上所有时延信息之后，从源端节点开始到宿端节点的方向，依次确定选取每个节点时延最优的可用时隙分配。在确定时隙之后，集中系统依据确定的时隙进行时隙分配，建立通道。
时隙分配也可以由每个节点确定之后，通过消息发送给下一个节点，从而依次确定选取每个节点时延最优的可用时隙分配。
对于双向通道，两个方向分别独立执行以上过程，分别确定采用的时隙。
节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，依据时隙帧结构以及预先获取的节点时延变化模型进行计算得到其他时隙之间的时延值。
本方案提出了一套有效的端到端通道建立包括时隙分配的方案，能够在一条通道中优化时隙分配带来的时延，降低端到端通道时延。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产 生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (30)

  1. 一种时隙分配处理方法，包括：
    节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
    节点设备确定该时延用以供建立端到端的通道时隙分配。
  2. 如权利要求1所述的方法，其中，节点设备确定该时延用以供建立端到端的通道时隙分配，包括：
    节点设备向集中系统发送该时延；和/或，
    节点设备根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
  3. 如权利要求1所述的方法，其中，节点设备确定时延是节点设备自发确定的；和/或，
    节点设备确定时延是节点设备接收到确定时延请求后确定的。
  4. 如权利要求3所述的方法，其中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
  5. 如权利要求1所述的方法，其中，节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
  6. 如权利要求5所述的方法，其中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
  7. 如权利要求1至6任一所述的方法，其中，进一步包括：
    接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
    根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备。
  8. 一种时隙分配处理方法，包括：
    接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
    根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；
    其中：确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
  9. 如权利要求8所述的方法，其中，节点设备确定时延是节点设备自发确定的；和/或，
    节点设备确定时延是节点设备接收到确定时延请求后确定的。
  10. 如权利要求9所述的方法，其中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
  11. 如权利要求8所述的方法，其中，节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
  12. 如权利要求11所述的方法，其中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
  13. 一种时隙分配处理方法，包括：
    接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
    根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
    确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
  14. 如权利要求13所述的方法，其中，节点设备确定时延是节点设备自发确定的；和/或，
    节点设备确定时延是节点设备接收到确定时延请求后确定的。
  15. 如权利要求14所述的方法，其中，所述确定时延请求是集中系统在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径上的节点设备发送的。
  16. 如权利要求13所述的方法，其中，节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，是节点设备确定某一个输入端口p时隙A到另外一个输出端口q时隙B的节点内部时延后，确定其他时隙之间的时延值。
  17. 如权利要求16所述的方法，其中，确定其他时隙之间的时延值是依据时隙帧结构以及预先获取的节点时延变化模型确定其他时隙之间的时延值的。
  18. 一种时隙分配处理方法，其中，包括：
    接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
    根据各时延进行端到端的通道时隙分配。
  19. 如权利要求18所述的方法，其中，节点设备确定时延是节点设备自发确定的；和/或，
    节点设备确定时延是节点设备接收到确定时延请求后确定的。
  20. 如权利要求19所述的方法，其中，进一步包括：
    在确定出一条端到端的通道经过的节点设备路径后，对节点设备路径 上的节点设备发送的所述确定时延请求。
  21. 如权利要求18所述的方法，其中，根据该时延信息进行端到端的通道时隙分配，包括：
    从源端节点设备开始到宿端节点设备的方向，依次确定选取每个节点设备时延最优的时隙为可用时隙，依据确定的可用时隙进行时隙分配。
  22. 一种节点设备，包括：
    处理器，用于读取存储器中的程序，执行下列过程：
    确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
    确定该时延用以供建立端到端的通道时隙分配；
    收发机，用于在处理器的控制下接收和发送数据。
  23. 一种节点设备，包括：
    第一确定模块，用于确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备；
    第一发送模块，用于确定该时延用以供建立端到端的通道时隙分配。
  24. 一种节点设备，包括：
    处理器，用于读取存储器中的程序，执行下列过程：
    接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
    根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；其中：
    确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配；
    收发机，用于在处理器的控制下接收和发送数据。
  25. 一种节点设备，包括：
    第一接收模块，用于接收通道上的上一节点设备根据时延最优的时隙 确定的可用时隙；
    第二发送模块，用于根据时延最优的时隙确定本节点设备的可用时隙后，发送给通道上的下一节点设备；
    其中：确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
  26. 一种节点设备，包括：
    处理器，用于读取存储器中的程序，执行下列过程：
    接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
    根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
    确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配；
    收发机，用于在处理器的控制下接收和发送数据。
  27. 一种节点设备，包括：
    第二接收模块，用于接收通道上的上一节点设备根据时延最优的时隙确定的可用时隙；
    第一分配模块，用于根据时延最优的时隙确定本节点设备的可用时隙后，根据各节点设备的可用时隙进行端到端的通道时隙分配；其中：
    确定可用时隙的时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，节点设备是端到端的通道上的节点设备，时延用以供建立端到端的通道时隙分配。
  28. 一种集中系统，包括：
    处理器，用于读取存储器中的程序，执行下列过程：
    接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入 端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
    根据各时延进行端到端的通道时隙分配；
    收发机，用于在处理器的控制下接收和发送数据。
  29. 一种集中系统，包括：
    第三接收模块，用于接收各节点设备发送的时延，所述时延是各节点设备确定某一个输入端口时隙到另外一个端口时隙在节点设备内部的时延，所述节点设备是端到端的通道上的节点设备，所述时延用以供建立端到端的通道时隙分配；
    第二分配模块，用于根据各时延进行端到端的通道时隙分配。
  30. 一种计算机可读存储介质，所述计算机可读存储介质存储有执行权利要求1至21任一所述方法的计算机程序。
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