WO2022178725A1 - 显示基板和显示面板 - Google Patents

显示基板和显示面板 Download PDF

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Publication number
WO2022178725A1
WO2022178725A1 PCT/CN2021/077722 CN2021077722W WO2022178725A1 WO 2022178725 A1 WO2022178725 A1 WO 2022178725A1 CN 2021077722 W CN2021077722 W CN 2021077722W WO 2022178725 A1 WO2022178725 A1 WO 2022178725A1
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WIPO (PCT)
Prior art keywords
data
connection
line
sub
traces
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PCT/CN2021/077722
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English (en)
French (fr)
Inventor
易宏
李正坤
颜俊
王梦奇
李德
青海刚
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112021001138.3T priority Critical patent/DE112021001138T5/de
Priority to US17/628,689 priority patent/US20220344442A1/en
Priority to CN202180000307.XA priority patent/CN115244454B/zh
Priority to PCT/CN2021/077722 priority patent/WO2022178725A1/zh
Publication of WO2022178725A1 publication Critical patent/WO2022178725A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display panel.
  • the traces in the display substrate need to be as small as possible while meeting the electrical and process requirements. space.
  • the traditional method is to reduce the line width of the trace, but with the reduction of the trace width, it becomes more and more difficult to realize in the process.
  • a display substrate comprising
  • a base substrate including a display area and a peripheral area surrounding the display area
  • a plurality of data lines located in the display area, arranged in a first direction and extending in a second direction, the plurality of data lines being connected to the plurality of sub-pixels;
  • a plurality of data wirings located in the peripheral area, on one side of the display area along the second direction, the plurality of data wirings are respectively connected with the plurality of data lines,
  • the plurality of data traces include periodically arranged first data traces, second data traces and third data traces, wherein the first data traces are located in the first conductor layer, and the second data traces are located in the first conductor layer.
  • the second conductor layer, the third data wiring is located in the third conductor layer, wherein the first conductor layer is located on the side of the base substrate facing the plurality of sub-pixels, and the second conductor layer is located in the first conductor layer
  • the conductor layer is located on the side away from the base substrate, the third conductor layer is located at the side of the second conductor layer away from the base substrate, and a part of at least one first data line is located on the positive side of the base substrate.
  • the projection overlaps with the orthographic projection of a portion of the at least one third data line on the base substrate.
  • a bending area is provided in the peripheral area, and the bending area is located on a side of the plurality of data lines away from the display area along the second direction, and the display substrate further includes: a plurality of The patterned wirings are located in the bending region, and the plurality of patterned wirings are correspondingly connected to the plurality of data wirings.
  • the data line includes a first sub-line of the data line, a second sub-line of the data line, and a third sub-line of the data line, and the first sub-line of the data line and one of the plurality of data lines At least one data line is connected, the third sub-line of the data line is connected to at least one patterned line in the plurality of patterned lines, and the second sub-line of the data line is connected to the data line Between the first sub-line and the third sub-line of the data line,
  • the orthographic projection of the second data line of the at least one first data line on the base substrate at least partially overlaps the orthographic projection of the second data line of the at least one third data line on the base substrate.
  • the display substrate further includes: a plurality of connecting lines, located in the peripheral region, and located on a side of the bending region away from the display region along the second direction, the plurality of connecting lines and the A plurality of patterned traces are connected correspondingly,
  • the plurality of connection lines include periodically arranged first connection lines, second connection lines and third connection lines, wherein the first connection lines are located on the first conductor layer, and the second connection lines are located on the first conductor layer.
  • the wires are located on the second conductor layer, and the third connection wires are located on the third conductor layer.
  • each first data trace is connected to a third connection trace through a patterned trace
  • each second data trace is connected to a third connection trace through a patterned trace
  • each third connection trace is The data trace is connected to a first connection trace or a second connection trace through a patterned trace.
  • one third data trace is connected to the first connection trace through a patterned trace
  • the other third data trace is connected to the first connection trace through a patterned trace.
  • each connection trace includes a first sub-wire of the connection trace and a second sub-wire of the connection trace
  • the first sub-wire of the connection trace is connected to one patterned trace of the plurality of patterned traces
  • the second sub-wire of the connection wiring is connected to the first sub-wire of the connection wiring
  • the first sub-line of the connection line of at least one connection line of the plurality of connection lines extends to the corresponding patterned line line in a zigzag shape.
  • the display substrate further includes: an auxiliary circuit, located in the peripheral area, and located along the second direction on a side of the plurality of connection lines away from the display area,
  • connection wiring further includes a third sub-wire of the connection wiring, the third sub-wire of the connection wiring is connected to the auxiliary circuit, and the second sub-wire of the connection wiring is connected to the first sub-wire of the connection wiring. line and the connecting line between the third sub-line.
  • the auxiliary circuit includes an electrostatic discharge circuit
  • the electrostatic discharge circuit includes a plurality of electrostatic discharge units
  • the plurality of electrostatic discharge units are in a one-to-one correspondence with the third sub-wires of the connection wires of the plurality of connection wires connect.
  • the multiple data traces are divided into multiple groups of data traces, wherein the third sub-wires of the data traces belonging to two adjacent groups of data traces and adjacent to each other are separated in the first direction A distance, the third sub-lines of the data lines of the two data lines belonging to the same group and adjacent to each other are separated from each other by a second distance in the first direction, and the second distance is smaller than the first distance.
  • the plurality of connection traces are divided into multiple groups of connection traces, wherein the first sub-wires of the connection traces belonging to two adjacent groups of connection traces and adjacent to each other are separated from each other in the first direction Three distances, the first sub-wires of the two connection wires belonging to the same group and adjacent to each other are separated by a fourth distance in the first direction, and the fourth distance is smaller than the third distance.
  • connection traces is divided into a first subgroup of connection traces, a second subgroup of connection traces, and a third subgroup of connection traces, the first subgroup of connection traces and the third subgroup of connection traces
  • the group routing routing is located on both sides of the second subgroup connecting routing along the first direction
  • connection traces of each of the first connection traces and the second connection traces extend to the patterned traces in a zigzag shape, and each of the first connection traces and the length of the zigzag extending portion of the second connecting line gradually decreases along the first direction;
  • connection traces of each of the first connection traces and the second connection traces In the third subgroup of connection traces, the connection traces of each of the first connection traces and the second connection traces.
  • the length of the zigzag-shaped extending portion of the first sub-line of the connecting line and the second connecting line gradually increases along the first direction.
  • At least one of the plurality of sub-pixels includes:
  • the thin film transistor has a gate electrode, a source electrode and a drain electrode;
  • interlayer insulating layer is located between the gate electrode and the source electrode and the drain electrode;
  • the first gate insulating layer is located on the side of the interlayer insulating layer facing the base substrate;
  • the first pole of the capacitor is arranged in the same layer as the gate, and the second pole of the capacitor is arranged between the interlayer insulating layer and the second gate insulating layer,
  • the first data trace and the gate electrode are arranged in the same layer, the second data trace and the second pole of the capacitor are arranged in the same layer, and the third data trace and the source electrode or the capacitor are arranged in the same layer.
  • the drain is set on the same layer.
  • At least one electrostatic discharge unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, a gate and a first electrode of the first transistor, a gate and a first electrode of the second transistor,
  • the second pole of the third transistor T3 and the second pole of the fourth transistor are connected to a corresponding third sub-wire of a connecting wire, and the second pole of the first transistor and the second pole of the second transistor
  • the diodes are connected to the low voltage signal lines, the gate and first electrodes of the third transistor and the gate and first electrodes of the fourth transistors are connected to the high voltage signal lines.
  • the auxiliary circuit further includes a unit test circuit, and the unit test circuit includes a plurality of unit test sub-circuits, and the plurality of unit test sub-circuits are connected to the third sub-wire of the connection wire of the plurality of connection wires. connected one by one.
  • the orthographic projection of the second data line of the at least one first data line on the base substrate completely overlaps with the orthographic projection of the second data line of the at least one third data line on the base substrate,
  • the orthographic projection of the second data trace of the at least one second data trace on the base substrate and the orthographic projection of the second data trace of the at least one first data trace on the base substrate and the orthographic projection of the at least one third data trace on the base substrate do not overlap.
  • the multiple groups of data lines include a first group of data lines, a second group of data lines, a third group of data lines, a fourth group of data lines, and a fifth group of data lines arranged along the first direction and a sixth group of data lines, wherein the first group of data lines and the sixth group of data lines are arranged symmetrically with respect to the symmetry axis of the display substrate in the second direction, and the second group of data lines and all
  • the fifth group of data wirings are symmetrically arranged relative to the symmetry axis
  • the third group of data wirings and the fourth group of data wirings are symmetrically arranged relative to the symmetry axis.
  • the plurality of groups of connection lines include a first group of connection lines, a second group of connection lines, a third group of connection lines, a fourth group of connection lines, and a fifth group of connection lines arranged along the first direction and a sixth group of connection lines, wherein the first group of connection lines and the sixth group of connection lines are arranged symmetrically with respect to the symmetry axis of the display substrate in the second direction, and the second group of connection lines and all
  • the fifth group of connection wires is symmetrically arranged with respect to the symmetry axis
  • the third group of connection wires and the fourth group of connection wires are arranged symmetrically with respect to the symmetry axis.
  • a display panel including the display substrate as described above.
  • FIG. 1 shows a schematic diagram of a display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic plan view of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of data routing according to an embodiment of the present disclosure
  • Fig. 4 shows the schematic diagram of area A1 in Fig. 2;
  • Figure 5 shows a cross-sectional view along line X-X' in Figure 4.
  • Fig. 6 shows the layout diagram of area A1 in Fig. 2;
  • FIG. 7 shows a schematic diagram of connecting wires according to an embodiment of the present disclosure
  • Fig. 8 shows the schematic diagram of area A2 in Fig. 2;
  • Fig. 9 shows the layout diagram of area A2 in Fig. 2;
  • FIG. 10 shows a schematic diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure
  • FIG. 11 shows a circuit diagram of an electrostatic discharge unit in an electrostatic discharge circuit according to an embodiment of the present disclosure
  • Fig. 12A shows the layout diagram of area A3 in Fig. 2;
  • FIG. 12B shows a partial enlarged view of the electrostatic discharge circuit in FIG. 12A
  • FIG. 13 shows a schematic plan view of a display substrate according to another embodiment of the present disclosure.
  • Fig. 14 shows a schematic diagram of region B1 in Fig. 13;
  • Fig. 15 shows a schematic diagram of region B2 in Fig. 13;
  • Fig. 16 shows a schematic diagram of region B3 in Fig. 13;
  • Fig. 17 shows the layout diagram of the area B3 in Fig. 13;
  • Figures 18A to 18C show the layout diagrams of the first subgroup connection traces of groups GC1 to GC3, respectively;
  • FIG. 19 shows a schematic diagram of a sub-pixel structure of a display substrate according to an embodiment of the present disclosure.
  • connection may mean that two components are directly connected, or may mean that two components are connected via one or more other components.
  • the two components may be connected or coupled by wired or wireless means.
  • FIG. 1 shows a schematic diagram of a display area of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a base substrate 110 and a plurality of sub-pixels Px1.
  • the base substrate 110 includes a display area AA and a peripheral area PA surrounding the display area AA.
  • a plurality of sub-pixels Px1 are located in the display area AA.
  • a plurality of data lines DATA are also set in the display area AA.
  • a plurality of data lines DATA are arranged in a first direction (x direction in FIG. 1 ) and extend in a second direction (y direction in FIG. 1 ), and are connected to the plurality of sub-pixels Px1.
  • a plurality of gate lines GATE are also provided in the display area AA, and the plurality of gate lines GATE extend along the x direction and are arranged along the y direction.
  • each gate line GATE is connected to at least one row of sub-pixels Px1, and each data line DATA is connected to at least one column of sub-pixels Px1.
  • the gate drive signal at the gate line GATE turns on the row of sub-pixels connected to it, and the data signals at the data line DATA connected to the row of sub-pixels are respectively input to the row of sub-pixels Px1, thereby enabling the row of sub-pixels Pixels glow.
  • each data line is connected to one column of sub-pixels and each gate line is connected to one row of sub-pixels
  • the data lines and gate lines may connect the individual sub-pixels in any other manner as desired, such as connecting two or more rows of sub-pixels per gate line, or connecting two or more columns of sub-pixels per data line, etc. .
  • FIG. 2 shows a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 200 includes the base substrate 110 , and the above description of the base substrate 110 is also applicable to the base substrate 110 in FIG. 2 .
  • a plurality of data lines DL are disposed in the peripheral area PA of the base substrate 110 .
  • the multiple data lines DL are located on one side of the display area AA along the y direction, and are respectively connected to the multiple data lines DATA in the display area AA.
  • a bending area 120 is disposed in the peripheral area PA, and the bending area 120 is located on a side of the plurality of data lines DL away from the display area AA along the y-direction.
  • a plurality of patterned wirings may be provided in the bending region 120, and the plurality of patterned wirings are correspondingly connected to the plurality of data wirings, which will be described in further detail below.
  • a plurality of connecting lines CL may also be provided in the peripheral area PA.
  • a plurality of connection traces CL are located on the side of the bending area 120 away from the display area along the y-direction, and the connection traces are correspondingly connected to the patterned traces in the bending area 120 , which will be discussed below. This is further detailed.
  • auxiliary circuits may also be provided in the peripheral area PA, and the auxiliary circuits include, but are not limited to, the electrostatic discharge circuit 130 and the unit test circuit 140 .
  • the electrostatic discharge circuit 130 is located on the side of the plurality of connection traces CL away from the display area AA along the y direction
  • the unit test circuit 140 is located at the side of the electrostatic discharge circuit 130 away from the display area AA along the y direction.
  • One end of each connection trace CL is connected to the patterned connection line in the bending region 120 , and the other end is connected to at least one of the electrostatic discharge circuit 130 and the unit test circuit 140 .
  • the electrostatic discharge circuit 130 is used to discharge static electricity on the connection line CL.
  • the unit test circuit 140 is used to test the sub-pixels in the display area AA through the connection line CL and the data line DL.
  • the electrostatic discharge circuit 130 may include a plurality of electrostatic discharge units, and the plurality of electrostatic discharge units are connected to the plurality of connection lines CL in a one-to-one correspondence.
  • the unit test circuit 140 may include a plurality of unit test sub-circuits, and the plurality of unit test sub-circuits are also connected to the plurality of connection lines CL in a one-to-one correspondence.
  • a plurality of pins may also be provided in the peripheral area PA.
  • the plurality of pins in the area 150 are respectively connected to auxiliary circuits, for example, to at least one of the electrostatic discharge circuit 130 and the unit test circuit 140, through a plurality of pin traces FL.
  • a plurality of pins in the area 150 can be connected to pins on the driver IC, so that the data signals provided by the driver IC can be provided to the sub-ports in the display area AA through the pin traces FL, the connection traces CL and the data traces DL. pixel.
  • FIG. 3 shows a schematic diagram of data routing according to an embodiment of the present disclosure.
  • the plurality of data lines DL include a first data line DL_a, a second data line DL_b, and a third data line DL_c.
  • the first data trace DL_a is located in the first conductor layer
  • the second data trace DL_b is located in the second conductor layer
  • the third data trace DL_C is located in the third conductor layer.
  • the first data trace DL_a on the first conductor layer is represented by a thick gray line
  • the second data trace DL_b on the second conductor layer is represented by a thick black line
  • the third data trace DL_c on the third conductor layer is represented by a thick black line. Indicated by thin black lines.
  • the lines of different thicknesses representing the first data line DL_a, the second data line DL_b and the third data line DL_c in FIG. 3 are only used to distinguish different data lines, and are not intended to be used for Limit the actual line width of data traces.
  • the first data line DL_a, the second data line DL_b, and the third data line DL_c each include a first data line F1, a second data line F2, and a third data line F3.
  • the first sub-line F1 of the data wiring and the third sub-line F3 of the data wiring extend along the y-direction, and the second sub-line F2 of the data wiring extends at a certain angle with respect to the y-direction.
  • the second sub-line F2 of the data wiring is connected between the first sub-line F1 of the data wiring and the third sub-line F3 of the data wiring.
  • the angle of the second sub-line F2 of the data line with respect to the y direction may be different.
  • the second sub-line F2 of the data trace is drawn as a straight line in FIG. 3 , embodiments of the present disclosure are not limited thereto. In practice, the second sub-line F2 of the data routing can be designed in a curved shape as required.
  • the first sub-line F1 of the data wiring is connected to at least one data line DATA in the display area AA
  • the third sub-line F3 of the data wiring is connected to at least one patterned wiring in the bending area 120, This will be explained in further detail below.
  • FIG. 4 shows a schematic diagram of the area A1 in FIG. 2 .
  • Fig. 5 shows a cross-sectional view taken along line X-X' in Fig. 4 .
  • the first data line DL_a, the second data line DL_b and the third data line DL_c are arranged periodically.
  • the first data wiring DL_a is located on the first conductor layer, and the first conductor layer is located on the side of the base substrate 110 facing the sub-pixels.
  • the second data line DL_b is located on the second conductor layer, and the second conductor layer is located on the side of the first conductor layer where the first data line DL_a is located away from the base substrate 110 .
  • the third data line DL_c is located on the third conductor layer, and the third conductor layer is located on the side of the second conductor layer where the second data line DL_b is located away from the base substrate 110 .
  • the first conductor layer may be disposed on the same layer as the gate of the thin film transistor in the sub-pixel
  • the second conductor layer may be disposed in the same layer as the second pole of the capacitor in the sub-pixel
  • the third conductor layer may be disposed on the same layer as the sub-pixel
  • the source and/or drain of the thin film transistor are arranged in the same layer, which will be described in further detail below.
  • the materials of the first conductor layer and the second conductor layer include but are not limited to Mo
  • the materials of the third conductor layer include but are not limited to at least one of Ti and Al.
  • the third conductor layer can be set to Ti-Al-Ti three. layer structure.
  • the display substrate further includes a buffer layer 510, a first gate insulating layer 520, a second gate insulating layer 530 and an interlayer dielectric layer 540, wherein the buffer layer 510 is located on the side of the base substrate 110 facing the sub-pixels, and the first gate insulating layer 520 Located on the side of the buffer layer 510 away from the base substrate 110 , the first data trace DL_a is located at the side of the first gate insulating layer 520 away from the base substrate 110 and covered by the second gate insulating layer 530 .
  • the second data trace DL_b is located on the side of the second gate insulating layer 530 away from the base substrate 110 and is covered by the interlayer dielectric layer 540 .
  • the third data trace DL_c is located on the side of the interlayer dielectric layer 540 away from the base substrate 110 .
  • the orthographic projection of a portion of the at least one first data line DL_a on the base substrate 110 overlaps the orthographic projection of a portion of the at least one third data line DL_c on the base substrate 110 .
  • the orthographic projection of the second data line F2 of the first data line DL_a and the second data line F2 of the third data line DL_c on the base substrate 110 at least partially overlap, for example, the center axes of the two coincide
  • the so-called central axis of the trace here may refer to the central axis in the extending direction of the trace, and the distances from the central axis to the edges on both sides of the trace are equal.
  • the orthographic projection of the data trace second sub-line F2 of the second data trace DL_b on the base substrate 110 may be aligned with the respective data trace second sub-lines F2 of the first data trace DL_a and the third data trace DL_c None of the orthographic projections of the base substrates 110 overlap.
  • the line width of the first data line DL_a is the same as the line width of the third data line DL_c, and the so-called line width here may refer to the line width perpendicular to the extension direction of the line. size.
  • the embodiments of the present disclosure are not limited thereto.
  • the line width of the third data line DL_c may be reduced as much as possible, while the lines of the first data line DL_a and the second data line DL_b may be increased as much as possible. width.
  • the line width of the third data trace DL_c may be 1.8 ⁇ m ⁇
  • the line width of the first data trace DL_a and the second data trace DL_b may be 2.2 ⁇ m ⁇ , where ⁇ represents an allowable error.
  • the space occupied by the data lines can be reduced, for example, compared with the traditional non-overlapping structure, the space occupied by the second sub-line F2 of the data lines can be reduced by 1/3 as a whole.
  • multiple layers of dielectrics such as the first gate insulating layer 530 and the interlayer dielectric layer 540, can be arranged between the first conductor layer and the third conductor layer. The existence of these dielectrics can reduce the interference between the data traces on the first conductor layer and the interlayer dielectric layer 540. Mutual crosstalk between data traces on the third conductor layer.
  • FIG. 6 shows the layout of the area A1 in FIG. 2 .
  • a plurality of patterned wires BL are disposed in the bending region 120 .
  • the first sub-line F1 and the first sub-line F3 of the data line extend along the y direction, and the data line
  • the extension direction of the second sub-line F2 of the line is at a certain angle with respect to the first sub-line F1 of the data wiring and the first sub-line F3 of the data wiring, and the first sub-line F1 of the data wiring and at least one piece of data in the display area AA.
  • the line DATA is connected, and the third sub-line F3 of the data line is connected to at least one patterned line BL in the bending region 120 .
  • FIG. 7 shows a schematic diagram of a connection trace according to an embodiment of the present disclosure.
  • the plurality of connection lines CL include a first connection line CL_a, a second connection line CL_b, and a third connection line CL_c.
  • the first connection trace CL_a is located in the first conductor layer
  • the second connection trace CL_b is located in the second conductor layer
  • the third connection trace CL_C is located in the third conductor layer, similar to FIG. 3 , in FIG. 7 it will be located in the first conductor layer
  • the first connection trace CL_a is represented by a thick gray line
  • the second connection trace CL_b in the second conductor layer is represented by a thick black line
  • the third connection trace CL_c in the third conductor layer is represented by a thin black line .
  • the first connection line CL_a, the second connection line CL_b, and the third connection line CL_c each include a connection line first sub-line K1 and a connection line second sub-line K2.
  • each of the first connection line CL_a, the second connection line CL_b, and the third connection line CL_c may further include a connection line third sub-line K3.
  • the first sub-line K1 of the connecting line and the third sub-line K3 of the connecting line extend along the y-direction, and the second sub-line K2 of the connecting line extends at a certain angle with respect to the y-direction.
  • the second sub-wire K2 of the connecting wire is connected between the first sub-wire K1 of the connecting wire and the third sub-wire K3 of the connecting wire.
  • the angle of the second sub-line K2 of the connection line with respect to the y direction may be different.
  • the second sub-line K2 of the connecting line is drawn as a straight line in FIG. 7 , embodiments of the present disclosure are not limited thereto. In practice, the second sub-line K2 of the connecting line can be designed in a curved shape as required.
  • FIG. 8 shows a schematic diagram of the area A2 in FIG. 2 .
  • FIG. 9 shows a layout diagram of the area A2 in FIG. 2 .
  • a plurality of data lines DL may correspond to a plurality of patterned lines BL one-to-one
  • the multiple patterned traces BL can be connected to the multiple connection traces CL (including the first connection trace CL_a, the second connection trace CL_b and the third connection trace CL_c) in a one-to-one correspondence.
  • the first connection traces CL_a, the second connection traces CL_b and the third connection traces CL_c are arranged periodically, so that, for example, each of the first data traces DL_a is connected to a third connection trace through a patterned trace BL CL_c, each second data trace DL_b is connected to a third connection trace DL_c through a patterned trace BL, and each third data trace DL_c is connected to a first connection trace through a patterned trace BL CL_a or the second connection trace CL_b.
  • the third sub-line F3 of the data wiring is periodically arranged in the order of DL_a, DL_c, and DL_b, and the connection wiring is arranged in the order of CL_c, CL_a, CL_c, CL_c, CL_b, CL_c
  • the sequence and periodic arrangement of in any two adjacent third data lines DL_c (for example, the two adjacent third data lines DL_c shown in the dotted box in FIG. 8 ), one third data line DL_c and The first connection line CL_a is connected, and the other third data line DL_c is connected with the second connection line CL_b.
  • the so-called two adjacent third data lines here refer to the two third data lines with the closest distance in the y direction among the multiple third data lines, for example, the two third data lines shown in the dotted box in FIG. 8 Three data traces DL_c.
  • FIG. 10 shows a schematic diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure.
  • 11 shows a circuit diagram of an electrostatic discharge unit in an electrostatic discharge circuit according to an embodiment of the present disclosure.
  • the electrostatic discharge circuit 130 in FIG. 2 is connected to a plurality of connection lines CL.
  • the electrostatic discharge circuit 130 may include a plurality of electrostatic discharge units ESD1, ESD2, . . . , ESDh, and the plurality of electrostatic discharge units ESD1, ESD2, .
  • each of the electrostatic discharge units ESD1 , ESD2 , . . . , ESDh includes a first transistor T1 , a second transistor T2 , a third transistor T3 and a fourth transistor T4 .
  • the respective gates and first electrodes of the first transistor T1 and the second transistor T2 and the respective second electrodes of the third transistor T3 and the fourth transistor T4 are connected to a corresponding connecting line CL, and the first transistor T1 and the second transistor T1
  • the respective second electrodes of T2 are connected to the low voltage signal line VGL, and the respective gates and first electrodes of the third transistor T3 and the fourth transistor T4 are connected to the high voltage signal line VGH.
  • the transistors T1 to T4 may all be P-type transistors.
  • the high level of the signal on the connection line CL is higher than the preset high level value
  • at least one of the third transistor T3 and the fourth transistor T4 is turned on to control the connection line CL to the high voltage signal line The potential of VGH, so that the high level is released through at least one of the third transistor T3 and the fourth transistor T4.
  • the low level of the signal on the connection line CL is lower than the preset low level value
  • at least one of the first transistor T1 and the second transistor T2 is turned on to control the connection line CL to the low voltage signal line VGL , so that the excessively low level is released through at least one of the first transistor T1 and the second transistor T2.
  • electrostatic discharge unit in FIG. 11 has a specific circuit structure, embodiments of the present disclosure are not limited thereto, and the electrostatic discharge unit may have other circuit structures as required, such as including more or less transistors, or in other ways any number of transistors connected.
  • FIG. 12A shows a layout diagram of the area A3 in FIG. 2 .
  • FIG. 12B shows a partial enlarged view of the electrostatic discharge circuit 130 in FIG. 12A.
  • the electrostatic discharge circuit 130 may include a plurality of electrostatic discharge units ESD1, ESD2, . .
  • the plurality of electrostatic discharge units ESD1, ESD2, . . . , ESDh are connected to the plurality of connection lines CL in one-to-one correspondence.
  • Each of the electrostatic discharge units ESD1, ESD2, . . . , ESDh includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Different from the circuit structure of the electrostatic discharge unit shown in FIG. 11 , in FIG.
  • the first transistor T1 and the second transistor T2 are connected in series between the connection line CL and the low voltage signal line VGL
  • the third transistor T3 and the third transistor T3 are connected in series with the low voltage signal line VGL
  • the four transistors T4 are connected in series between the connection line CL and the high voltage signal line VGH.
  • FIG. 13 shows a schematic plan view of a display substrate according to another embodiment of the present disclosure.
  • the display substrate of FIG. 13 is similar to that of FIG. 2 , and the difference is at least that the data traces DL and the connection traces CL are divided into multiple groups.
  • a plurality of data lines DL are divided into groups, and from left to right along the x direction are the first group of data lines GB1, the second group of data lines GB2, the third group of data lines GB3, The fourth group of data wirings GB4, the fifth group of data wirings GB5, and the sixth group of data wirings GB6 (hereinafter collectively referred to as data wiring groups GB).
  • the first group of data lines GB1 is symmetrical with the sixth group of data lines GB6, the second group of data lines GB2 is symmetrical with the fifth group of data lines GB5, and the third group of data lines GB1 is symmetrical with the fifth group of data lines GB5.
  • the group data wiring GB3 is symmetrical with the fourth group data wiring GB4 respectively.
  • the plurality of connection wires CL are divided into a first group of connection wires GC1 to a sixth group of connection wires GC6 (hereinafter collectively referred to as a connection wire group GC).
  • the distance between adjacent two groups of GBs is greater than the distance between adjacent data traces in the group GB, and the distance between adjacent two groups of GCs is greater than the distance between adjacent connection traces in the group GC , which will be described in detail below with reference to FIG. 14 and FIG. 15 .
  • FIG. 14 shows a schematic diagram of the area B1 in FIG. 13 .
  • FIG. 15 shows a schematic diagram of the area B2 in FIG. 13 .
  • the third sub-wires F3 of the data wires DL of the two data wires DL belonging to the groups GB1 and GB2 respectively and adjacent to each other are separated by a first distance d1 in the x direction (hereinafter also referred to as the adjacent group distance between).
  • the third sub-lines F3 of the data lines DL of two data lines DL that belong to the same group are separated from each other by a second distance d2, wherein the second distance d2 is smaller than the first distance d1.
  • the adjacent group The distance between them can be set as required, for example, the distance d1 between groups GB1 and GB2 can be equal to or different from the distance d1' between GB2 and GB3. In some embodiments, as shown in FIG. 13 , The distance between groups GB3 and GB4 is greater than the distance between groups GB1 and GB2.
  • the first sub-wires K1 of the two connection wires CL belonging to the groups GC1 and GC2 and adjacent to each other are separated by a third distance d3 in the x-direction and belong to the same group (for example, The first sub-wires K1 of the two connection wires CL belonging to GC1 or GC2) and adjacent to each other are separated by a fourth distance d4 in the x direction, and the fourth distance d4 is smaller than the third distance d3.
  • the distance between two adjacent groups of connection traces may be equal to the distance between adjacent two groups of data traces connected thereto.
  • the distance d3 between groups GC1 and GC2 may be equal to the distance between groups GB1 and GC2.
  • FIG. 16 shows a schematic diagram of the area B3 in FIG. 13 .
  • FIG. 17 shows a layout diagram of the area B3 in FIG. 13 .
  • connection trace group GC3 in FIG. 13 can be divided into a first subgroup of connection traces GC3_1 , a second subgroup of connection traces GC3_2 , and a third subgroup of connection traces GC3_3 .
  • the first subgroup of connection traces GC3_3 The subgroup connection trace GC3_1 and the third subgroup trace GC3_3 are located on both sides of the second subgroup connection trace GC3_2 along the x direction.
  • the first sub-line K1 extends in a zigzag shape to the patterned line routing.
  • the first sub-wires K1 of the connection wires of each connection wire extend in a straight line.
  • the lengths of the zigzag extending portions of different connection wires may vary.
  • the length of the first group of data traces GB3_1d electrically connected to the first sub-group of connection traces GC3_1 gradually decreases from left to right.
  • each The lengths of the zigzag extending portions of the first connecting line CL_a and the second connecting line CL_b also gradually decrease from left to right (ie, along the x direction), thereby compensating for the length variation of the data lines connected thereto.
  • the length of the zigzag extending portion of the leftmost first connecting line CL_a is greater than the length of the zigzag extending portion of the second connecting line CL_b on the right, and so on.
  • the length of the zigzag-shaped extension portion of the first sub-line K1 of the connection traces of each of the first and second connection traces CL_a and CL_b may gradually increase along the x-direction Increase, for example, the length of the zigzag extending portion of the first connection trace CL_a on the far right is smaller than the length of the zigzag extending portion of the second connection trace CL_b on the left thereof, and so on.
  • the patterns formed by the extension portions of the fold lines in the first subgroup of connecting wires GC3_1 are symmetrical with the patterns formed by the extension portions of the fold lines in the connection wires GC3_3 of the third subgroup, that is, the fold lines in the two subgroups are symmetrical.
  • the linear extension decreases or increases with the same slope.
  • the embodiments of the present disclosure are not limited thereto.
  • the lengths of the extension portions of the broken lines from left to right in the first sub-group of connection traces GC3_1 decrease with a certain slope
  • the third sub-group of connection traces GC3_3 The lengths of the extension portions of the respective polylines from left to right increase with another slope smaller than the slope (depending on the change in the length of the data lines connected to the third subgroup connection line GC3_3), so that the first subgroup connection line GC3_1
  • the pattern formed with the third subgroup connecting trace GC3_3 is asymmetrical.
  • none of the third sub-group of connection traces GC3_3 has a zigzag extending portion.
  • connection wiring groups GC1, GC2, GC4, GC5 and GC6 have similar structures, which will not be repeated here.
  • traces on different conductor layers may have different resistances when the lengths are the same.
  • the resistivity of the material of the third conductor layer may be lower than the resistivity of the materials of the first and second conductor layers.
  • the length of the connection traces can be increased, thereby compensating for the data traces connected to the connection traces due to the low resistance. In this way, the resistances of the transmission paths of the respective data signals can be substantially the same.
  • the degree of gradient of the lengths of the zigzag extending portions of the connection traces in different groups may be different, which will be described in detail below with reference to FIGS. 18A to 18C .
  • Figures 18A to 18C show the layout of the first subgroup connection traces of groups GC1 to GC3, respectively.
  • the groups GC4 to GC6 are arranged symmetrically with the groups GC1 to GC3, and thus will not be repeated here.
  • the lengths of two adjacent zigzag extending portions are different, so that the lengths of the respective zigzag extending portions gradually decrease with the first slope, thereby forming a shape as indicated by the dotted line. triangle pattern shown.
  • the lengths of the respective zigzag extensions gradually decrease with the second slope, thereby forming a triangular pattern as shown in dashed lines;
  • the lengths of the respective zigzag-shaped extensions gradually decrease with a third slope, thereby forming a triangular pattern as shown by the dotted lines.
  • the first slope is greater than the second slope
  • the second slope is greater than the third slope, that is to say, the length difference between two adjacent zigzag extending parts in the group GC1 is greater than that in the group GC2
  • the length difference of the zigzag-shaped extension parts of the group GC2 is greater than the length difference of the adjacent zigzag-shaped extension parts in the group GC2.
  • FIG. 19 shows a schematic diagram of a sub-pixel structure of a display substrate according to an embodiment of the present disclosure.
  • At least one of the plurality of sub-pixels in the display substrate includes a thin film transistor and a capacitor, the thin film transistor has a gate G, a source S and a drain D, and the capacitor has a first electrode ED1 and a second electrode Pole ED2.
  • the active layer P-Si of the thin film transistor is located between the buffer layer 510 and the first gate insulating layer 520, and is connected to the source S and the drain D.
  • the interlayer insulating layer 540 is located between the gate G and the source S and drain D. As shown in FIG.
  • the first gate insulating layer 520 is located on the side of the interlayer insulating layer 540 facing the base substrate 110 .
  • the second gate insulating layer 530 is located between the interlayer insulating layer 540 and the first gate insulating layer 520 .
  • the first electrode ED1 of the capacitor is disposed in the same layer as the gate G of the thin film transistor, and the second electrode ED2 of the capacitor is disposed between the interlayer insulating layer 540 and the second gate insulating layer 530 .
  • the sub-pixel may further include a passivation layer 1901 , a first planarization layer 1902 , a via electrode 1903 and a second planarization layer 1904 .
  • the passivation layer 1901 is located on the side of the interlayer dielectric layer 540 away from the base substrate 110 .
  • the first flat layer 1902 is located on the side of the passivation layer 1901 away from the base substrate 110 .
  • the transfer electrode 1903 is located on the side of the first flat layer 1902 away from the base substrate 110 , and is connected to the source S of the thin film transistor through a via hole provided in the first flat layer 1902 and the passivation layer 1901 .
  • the second flat layer 1904 is disposed on the side of the via electrode 1903 away from the base substrate 110 and at least partially covers the via electrode 1903.
  • the sub-pixel may also include a pixel defining layer 1905 and a light emitting element including an anode 1906 , a light emitting layer 1907 and a cathode 1908 .
  • the pixel defining layer 1905 is located on the side of the second flat layer 1904 away from the base substrate 110 .
  • the anode 1906 is located on the side of the via electrode 1903 away from the base substrate 110 and is connected to the via electrode 1903 .
  • the light emitting layer 1907 is located on the side of the anode 1906 away from the base substrate 110 and partially covers the anode 1906 .
  • the cathode 1908 is located on the side of the light emitting layer 1907 away from the base substrate 110 .
  • the sub-pixel may also include an encapsulation layer 1909 on a side of the cathode 1908 away from the base substrate 110 .
  • the encapsulation layer 1909 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.
  • the first data line DL_a and the first connection line CL_a in the above-mentioned embodiment may be arranged in the same layer as the gate G of the thin film transistor, and the second data line DL_b and the second connection line CL_b may be connected to the second pole of the capacitor.
  • ED2 is arranged on the same layer, and the third data wiring DL_c and the third connection wiring CL_c may be arranged on the same layer as the source electrode S and/or the drain electrode D.
  • the patterned traces BL can be disposed on the same layer as the via electrodes 1903 .
  • Embodiments of the present disclosure also provide a display panel, which may include the display substrate of any of the foregoing embodiments.
  • the display panel may be an Active-Matrix Organic Lighting-Emitting Diode (AMOLED, Active-Matrix Organic Lighting-Emitting Diode) display panel.
  • AMOLED Active-Matrix Organic Lighting-Emitting Diode

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Abstract

一种显示基板和显示面板，所述显示基板可以包括衬底基板以及位于显示基板上的多个子像素、多条数据线和多条数据走线，所述多条数据走线包括周期排布的第一数据走线、第二数据走线和第三数据走线，其中第一数据走线位于第一导体层、第二数据走线位于第二导体层，第三数据走线位于第三导体层，至少一条第一数据走线的一部分在衬底基板的正投影与至少一条第三数据走线的一部分在衬底基板的正投影重叠。

Description

显示基板和显示面板 技术领域
本公开涉及显示技术领域，具体涉及一种显示基板和显示面板。
背景技术
随着显示技术的发展，越来越多的电子设备中对边框的尺寸要求更严希望越来越窄，因此需要显示基板中的走线在满足电学和工艺的要求的同时占用尽可能小的空间。传统方法是减小走线的线宽，但是随着走线线宽的减小，在工艺上实现难度越来越大。
发明内容
根据本公开的一方面，提供了一种显示基板，包括
衬底基板，包括显示区和围绕所述显示区域的周边区；
多个子像素，位于所述显示区中；
多条数据线，位于所述显示区中，沿第一方向排列并且沿第二方向延伸，所述多条数据线连接至所述多个子像素；
多条数据走线，位于所述周边区中，沿所述第二方向位于所述显示区的一侧，所述多条数据走线分别与所述多条数据线连接，
其中，所述多条数据走线包括周期排布的第一数据走线、第二数据走线和第三数据走线，其中第一数据走线位于第一导体层、第二数据走线位于第二导体层，第三数据走线位于第三导体层，其中所述第一导体层位于所述衬底基板面向所述多个子像素的一侧，所述第二导体层位于所述第一导体层远离所述衬底基板的一侧，所述第三导体层位于所述第二导体层远离所述衬底基板的一侧，至少一条第一数据走线的一部分在衬底基板的正投影与至少一条第三数据走线的一部分在衬底基板的正投影重叠。
例如，所述周边区中设有弯折区，所述弯折区沿所述第二方向位于所述多条数据走线远离所述显示区的一侧，所述显示基板还包括：多条图案化走线，位于所述弯折区中，所述多条图案化走线与所述多条数据走线对应地连接。
例如，所述数据走线包括数据走线第一子线、数据走线第二子线和数据走线第三子线，所述数据走线第一子线与所述多条数据线中的至少一条数据线连接，所述数据走线第三子线与所述多条图案化走线中的至少一条图案化走线连接，所述数据走线第二子线 连接在所述数据走线第一子线和所述数据走线第三子线之间，
其中至少一条第一数据走线的数据走线第二子线在衬底基板的正投影与至少一条第三数据走线的数据走线第二子线在衬底基板的正投影至少部分重叠。
例如，显示基板还包括：多条连接走线，位于所述周边区，沿所述第二方向位于所述弯折区远离所述显示区的一侧，所述多条连接走线与所述多条图案化走线对应地连接，
其中，所述多条连接走线包括周期排布的第一连接走线、第二连接走线和第三连接走线，其中第一连接走线位于所述第一导体层、第二连接走线位于所述第二导体层，第三连接走线位于所述第三导体层。
例如，每条第一数据走线通过一条图案化走线连接至一条第三连接走线，每条第二数据走线通过一条图案化走线连接至一条第三连接走线，每条第三数据走线通过一条图案化走线连接至一条第一连接走线或第二连接走线。
例如，任意相邻的两条第三数据走线中，一条第三数据走线通过一条图案化走线与第一连接走线连接，另一条第三数据走线通过一条图案化走线与第二连接走线连接。
例如，每条连接走线包括连接走线第一子线和连接走线第二子线，所述连接走线第一子线连接所述多条图案化走线中的一条图案化走线，所述连接走线第二子线与所述连接走线第一子线连接，
其中所述多条连接走线中至少一条连接走线的连接走线第一子线呈折线形延伸至相应的图案化线走线。
例如，显示基板还包括：辅助电路，位于所述周边区，沿所述第二方向位于所述多条连接走线远离所述显示区的一侧，
所述连接走线还包括连接走线第三子线，所述连接走线第三子线与所述辅助电路连接，所述连接走线第二子线连接在所述连接走线第一子线和所述连接走线第三子线之间。
例如，所述辅助电路包括静电放电电路，所述静电放电电路包括多个静电放电单元，所述多个静电放电单元与所述多条连接走线的连接走线第三子线一一对应地连接。
例如，所述多条数据走线被划分为多组数据走线，其中分别属于相邻两组且彼此相邻的两条数据走线的数据走线第三子线在第一方向上相距第一距离，属于同一组且彼此相邻的两条数据走线的数据走线第三子线在第一方向上相距第二距离，所述第二距离小于第一距离。
例如，所述多条连接走线被划分为多组连接走线，其中分别属于相邻两组且彼此相邻的两条连接走线的连接走线第一子线在第一方向上相距第三距离，属于同一组且彼此 相邻的两条连接走线的连接走线第一子线在第一方向上相距第四距离，所述第四距离小于第三距离。
例如，至少一组连接走线被划分为第一子组连接走线、第二子组连接走线和第三子组连接走线，所述第一子组连接走线和所述第三子组走线走线沿第一方向位于所述第二子组连接走线两侧，
其中，
在所述第一子组连接走线中，各个第一连接走线和第二连接走线的连接走线第一子线呈折线形延伸至图案化线走线，且各个第一连接走线和第二连接走线的折线形延伸部分的长度沿着第一方向逐渐减小；
在所述第三子组连接走线中，各个第一连接走线和第二连接走线的连接走线第一子线呈折线形延伸至图案化线走线，且各个第一连接走线和第二连接走线的连接走线第一子线的折线形延伸部分的长度沿着第一方向逐渐增大。
例如，所述多个子像素中至少一个包括：
薄膜晶体管，所述薄膜晶体管具有栅极、源极和漏极；
层间绝缘层，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；
第一栅绝缘层，所述第一栅绝缘层位于所述层间绝缘层面向所述衬底基板的一侧；
第二栅绝缘层，所述第二栅绝缘层位于所述层间绝缘层与所述第一栅绝缘层之间；以及
电容，所述电容的第一极与所述栅极同层设置，所述电容的第二极设置在所述层间绝缘层与所述第二栅绝缘层之间，
其中，所述第一数据走线与所述栅极同层设置，所述第二数据走线与所述电容的第二极同层设置，所述第三数据走线与所述源极或漏极同层设置。
例如，至少一个静电放电单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极和第一极、所述第二晶体管的栅极和第一极、所述第三晶体管T3的第二极和所述第四晶体管的第二极与相应的一条连接走线第三子线连接，所述第一晶体管的第二极和所述第二晶体管的第二极连接低电压信号线，所述第三晶体管的栅极和第一极和所述第四晶体管的栅极和第一极连接高电压信号线。
例如，所述辅助电路还包括单元测试电路，所述单元测试电路包括多个单元测试子电路，所述多个单元测试子电路与所述多条连接走线的连接走线第三子线一一对应地连接。
例如，至少一条第一数据走线的数据走线第二子线在衬底基板的正投影与至少一条第三数据走线的数据走线第二子线在衬底基板的正投影完全重叠，至少一条第二数据走线的数据走线第二子线在衬底基板的正投影与至少一条第一数据走线的数据走线第二子线在衬底基板的正投影以及至少一条第三数据走线的数据走线第二子线在衬底基板的正投影不重叠。
例如，所述多组数据走线包括沿第一方向排列的第一组数据走线、第二组数据走线、第三组数据走线、第四组数据走线、第五组数据走线和第六组数据走线，其中所述第一组数据走线与第六组数据走线相对于显示基板在第二方向上的对称轴而对称设置，所述第二组数据走线与所述第五组数据走线相对于所述对称轴而对称设置，所述第三组数据走线与第四组数据走线相对于所述对称轴而对称设置。
例如，所述多组连接走线包括沿第一方向排列的第一组连接走线、第二组连接走线、第三组连接走线、第四组连接走线、第五组连接走线和第六组连接走线，其中所述第一组连接走线与第六组连接走线相对于显示基板在第二方向上的对称轴而对称设置，所述第二组连接走线与所述第五组连接走线相对于所述对称轴而对称设置，所述第三组连接走线与第四组连接走线相对于所述对称轴而对称设置。
根据本公开另一方面，提供了一种显示面板，包括如上所述的显示基板。
附图说明
图1示出了根据本公开实施例的显示基板的显示区的示意图；
图2示出了根据本公开一实施例的显示基板的平面示意图；
图3示出了根据本公开实施例的数据走线的示意图；
图4示出了图2中区域A1的示意图；
图5示出了图4中沿X-X’线的截面图；
图6示出了图2中区域A1的布局图；
图7示出了根据本公开实施例的连接走线的示意图；
图8示出了图2中区域A2的示意图；
图9示出了图2中区域A2的布局图；
图10示出了根据本公开实施例的静电放电电路的示意图；
图11示出了根据本公开实施例的静电放电电路中的静电放电单元的电路图；
图12A示出了图2中区域A3的布局图；
图12B示出了图12A中的静电放电电路的局部放大图；
图13示出了根据本公开另一实施例的显示基板的平面示意图；
图14示出了图13中区域B1的示意图；
图15示出了图13中区域B2的示意图；
图16示出了图13中区域B3的示意图；
图17示出了图13中区域B3的布局图；
图18A至18C分别示出了组GC1至GC3的第一子组连接走线的布局图；
图19示出了根据本公开实施例的显示基板的子像素结构的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
图1示出了根据本公开实施例的显示基板的显示区的示意图。
如图1所示，显示基板100包括衬底基板110和多个子像素Pxl。衬底基板110包括显示区AA和围绕所述显示区域AA的周边区PA。多个子像素Pxl位于显示区AA中。显示区AA中还设置有多条数据线DATA。多条数据线DATA沿第一方向(图1中为x方向)排列并且沿第二方向(图1中为y方向)延伸，并且连接至所述多个子像素Pxl。显示区AA中还设置有多条栅极线GATE，多条栅极线GATE沿x方向延伸 并且沿y方向排列。在图1中，每条栅极线GATE与至少一行子像素Pxl连接，每条数据线DATA与至少一列子像素Pxl连接。在工作时，栅极线GATE处的栅极驱动信号将与其连接的一行子像素开启，与该行子像素连接的数据线DATA处的数据信号分别输入该行子像素Pxl，从而使该行子像素发光。
虽然上文中以每条数据线连接一列子像素并且每条栅极线连接一行子像素为例进行了说明，然而本公开的实施例不限于此。数据线和栅极线可以根据需要以任何其他方式连接各个子像素，例如每条栅极线连接两行或更多行子像素，或者每条数据线连接两列或更多列子像素，等等。
图2示出了根据本公开一实施例的显示基板的平面示意图。如图2所示，显示基板200包括衬底基板110，以上针对衬底基板110的描述同样适用于图2的衬底基板110。衬底基板110的周边区PA中设置有多条数据走线DL。多条数据走线DL沿y方向位于显示区AA的一侧，并且分别与显示区AA中的多条数据线DATA连接。
在一些实施例中，周边区PA中设置有弯折区120，弯折区120沿y方向位于多条数据走线DL远离显示区AA的一侧。弯折区120中可以设置有多条图案化走线，所述多条图案化走线与所述多条数据走线对应地连接，下文将对此进一步详细说明。
在一些实施例中，周边区PA中还可以设置有多条连接走线CL。多条连接走线CL沿y方向位于弯折区120远离所述显示区的一侧，所述多条连接走线与弯折区120中的多条图案化走线对应地连接，下文将对此进一步详细说明。
在一些实施例中，周边区PA中还可以设置有辅助电路，辅助电路包括但不限于静电放电电路130和单元测试电路140。如图2所示，静电放电电路130沿y方向位于多条连接走线CL远离显示区AA的一侧，单元测试电路140沿y方向位于静电放电电路130远离显示区AA的一侧。每条连接走线CL一端连接弯折区120内的图案化连接线，另一端连接静电放电电路130和单元测试电路140中的至少一者。静电放电电路130用于释放连接走线CL上的静电。单元测试电路140用于通过连接走线CL和数据走线DL对显示区AA内的子像素进行测试。在一些实施例中，静电放电电路130可以包括多个静电放电单元，多个静电放电单元与多条连接走线CL一一对应地连接。类似地，在一些实施例中，单元测试电路140可以包括多个单元测试子电路，所述多个单元测试子电路也与所述多条连接走线CL一一对应地连接。
在一些实施例中，周边区PA中还可以设置有多个引脚(在图2中位于由方框150表示的区域内)。区域150内的多个引脚分别通过多个引脚走线FL连接至辅助电路，例 如连接至静电放电电路130和单元测试电路140中的至少一者。区域150内的多个引脚可以与驱动IC上的引脚连接，使得驱动IC提供的数据信号可以通过引脚走线FL、连接走线CL和数据走线DL提供至显示区AA内的子像素。
图3示出了根据本公开实施例的数据走线的示意图。
如图3所示，多条数据走线DL包括第一数据走线DL_a、第二数据走线DL_b和第三数据走线DL_c。第一数据走线DL_a位于第一导体层，第二数据走线DL_b位于第二导体层，第三数据走线DL_C位于第三导体层，图3中为了区分三种不同的导体层，将位于第一导体层的第一数据走线DL_a用灰色粗线表示，将位于第二导体层的第二数据走线DL_b用黑色粗线表示，将位于第三导体层的第三数据走线DL_c用黑色细线表示。本领域技术人员应理解，图3中表示第一数据走线DL_a、第二数据走线DL_b和第三数据走线DL_c的不同粗细的线条仅用于区分不同的数据走线，而不旨在限制数据走线的实际线宽。
第一数据走线DL_a、第二数据走线DL_b和第三数据走线DL_c各自包括数据走线第一子线F1、数据走线第二子线F2和数据走线第三子线F3。数据走线第一子线F1和数据走线第三子线F3沿y方向延伸，数据走线第二子线F2相对于y方向成一定角度延伸。数据走线第二子线F2连接在数据走线第一子线F1和数据走线第三子线F3之间。对于不同数据走线来说，数据走线第二子线F2相对于y方向的角度可以不同。虽然图3中数据走线第二子线F2被绘制为直线，然而本公开的实施例不限于此。在实践中，数据走线第二子线F2可以根据需要被设计成曲线形状。
结合图1和2，数据走线第一子线F1与显示区AA内的至少一条数据线DATA连接，数据走线第三子线F3与弯折区120中的至少一条图案化走线连接，下文将对此进一步详细说明。
图4示出了图2中区域A1的示意图。图5示出了图4中沿X-X’线的截面图。
如图4和图5所示，第一数据走线DL_a、第二数据走线DL_b和第三数据走线DL_c呈周期排布。第一数据走线DL_a位于第一导体层，第一导体层位于衬底基板110面向子像素的一侧。第二数据走线DL_b位于第二导体层，第二导体层位于第一数据走线DL_a所在的第一导体层远离衬底基板110的一侧。第三数据走线DL_c位于第三导体层，第三导体层位于第二数据走线DL_b所在的第二导体层远离衬底基板110的一侧。在一些实施例中，第一导体层可以与子像素中薄膜晶体管的栅极同层设置，第二导体层可以与子像素中电容的第二极同层设置，第三导体层可以与子像素中薄膜晶体管的源极和/ 或漏极同层设置，下文将对此进一步详细说明。第一导体层和第二导体层的材料包括但不限于Mo，第三导体层的材料包括但不限于Ti和A1中的至少之一，例如第三导体层可以设置成Ti-Al-Ti三层结构。
显示基板还包括缓冲层510、第一栅绝缘层520、第二栅绝缘层530和层间介质层540，其中缓冲层510位于衬底基板110面向子像素的一侧，第一栅绝缘层520位于缓冲层510远离衬底基板110的一侧，第一数据走线DL_a位于第一栅绝缘层520远离衬底基板110的一侧，并且被第二栅绝缘层530覆盖。第二数据走线DL_b位于第二栅绝缘层530远离衬底基板110的一侧，并且被层间介质层540覆盖。第三数据走线DL_c位于层间介质层540远离衬底基板110的一侧。
如图4和图5所示，至少一条第一数据走线DL_a的一部分在衬底基板110的正投影与至少一条第三数据走线DL_c的一部分在衬底基板110的正投影重叠。例如第一数据走线DL_a的数据走线第二子线F2与第三数据走线DL_c的数据走线第二子线F2在衬底基板110的正投影至少部分重叠，例如二者中心轴重合，这里所谓走线的中心轴可以指的是在走线延伸方向上的中心轴，中心轴到走线两侧边缘的距离相等。第二数据走线DL_b的数据走线第二子线F2在衬底基板110上的正投影可与第一数据走线DL_a和第三数据走线DL_c各自的数据走线第二子线F2在衬底基板110的正投影均不重叠。
在图4和图5所示的实施例中，第一数据走线DL_a的线宽与第三数据走线DL_c的线宽相同，这里所谓线宽可以指的是垂直于走线延伸方向上的尺寸。然而本公开的实施例不限于此，在一些实施例中可以尽可能减小第三数据走线DL_c的线宽，同时尽可能增大第一数据走线DL_a和第二数据走线DL_b的线宽。例如第三数据走线DL_c的线宽可以为1.8μm±α，第一数据走线DL_a和第二数据走线DL_b的线宽可以为2.2μm±α，其中α表示可允许的误差。
根据本公开的实施例，通过将数据走线DL设置在三个不同的导体层，并使得位于第一导体层的数据走线与位于第三导体层的数据走线在衬底基板的正投影至少部分重叠，可以减小数据走线占用空间，例如与传统的非重叠式结构相比，可以使数据走线第二子线F2整体上占用的空间减小1/3。另外，第一导体层与第三导体层之间可以设置多层介质，例如第一栅绝缘层530和层间介质层540，这些介质的存在可以减小位于第一导体层的数据走线与位于第三导体层的数据走线之间的相互串扰。
图6示出了图2中区域A1的布局图。如图6所示，弯折区120内设置有多条图案化走线BL。在第一数据走线DL_a、第二数据走线DL_b和第三数据走线DL_c中任意 一条数据走线中，第一子线F1和数据走线第一子线F3沿y方向延伸，数据走线第二子线F2的延伸方向相对于数据走线第一子线F1和数据走线第一子线F3呈一定的角度，数据走线第一子线F1与显示区AA内的至少一条数据线DATA连接，数据走线第三子线F3与弯折区120内的至少一条图案化走线BL连接。
图7示出了根据本公开实施例的连接走线的示意图。
如图7所示，多条连接走线CL包括第一连接走线CL_a、第二连接走线CL_b和第三连接走线CL_c。第一连接走线CL_a位于第一导体层，第二连接走线CL_b位于第二导体层，第三连接走线CL_C位于第三导体层，类似于图3，图7中将位于第一导体层的第一连接走线CL_a用灰色粗线表示，将位于第二导体层的第二连接走线CL_b用黑色粗线表示，将位于第三导体层的第三连接走线CL_c用黑色细线表示。第一连接走线CL_a、第二连接走线CL_b和第三连接走线CL_c各自包括连接走线第一子线K1和连接走线第二子线K2。在一些实施例中，第一连接走线CL_a、第二连接走线CL_b和第三连接走线CL_c各自还可以包括连接走线第三子线K3。连接走线第一子线K1和连接走线第三子线K3沿y方向延伸，连接走线第二子线K2相对于y方向成一定角度延伸。连接走线第二子线K2连接在连接走线第一子线K1和连接走线第三子线K3之间。对于不同连接走线来说，连接走线第二子线K2相对于y方向的角度可以不同。虽然图7中连接走线第二子线K2被绘制为直线，然而本公开的实施例不限于此。在实践中，连接走线第二子线K2可以根据需要被设计成曲线形状。
图8示出了图2中区域A2的示意图。图9示出了图2中区域A2的布局图。
如图8和图9所示，多条数据走线DL(包括第一数据走线DL_a、第二数据走线DL_b和第三数据走线DL_c)可以与多条图案化走线BL一一对应地连接，而多条图案化走线BL可以与多条连接走线CL(包括第一连接走线CL_a、第二连接走线CL_b和第三连接走线CL_c)一一对应地连接。第一连接走线CL_a、第二连接走线CL_b和第三连接走线CL_c呈周期排布，使得例如每条第一数据走线DL_a通过一条图案化走线BL连接至一条第三连接走线CL_c，每条第二数据走线DL_b通过一条图案化走线BL连接至一条第三连接走线DL_c，每条第三数据走线DL_c通过一条图案化走线BL连接至一条第一连接走线CL_a或第二连接走线CL_b。
在一些实施例中，如图8和图9所示，数据走线第三子线F3按照DL_a、DL_c、DL_b的顺序周期排布，连接走线按照CL_c、CL_a、CL_c、CL_c、CL_b、CL_c的顺序周期排布，任意相邻的两条第三数据走线DL_c(例如图8中虚线框所示的两条相邻 的第三数据走线DL_c)中，一条第三数据走线DL_c与第一连接走线CL_a连接，另一条第三数据走线DL_c与第二连接走线CL_b连接。这里所谓相邻的两条第三数据走线指的是多条第三数据走线中在y方向上距离最近的两条第三数据走线，例如图8中虚线框所示的两条第三数据走线DL_c。
图10示出了根据本公开实施例的静电放电电路的示意图。图11示出了根据本公开实施例的静电放电电路中的静电放电单元的电路图。
如图10所示，图2中的静电放电电路130与多条连接走线CL连接。静电放电电路130可以包括多个静电放电单元ESD1，ESD2，…，ESDh，多个静电放电单元ESD1，ESD2，…，ESDh与多条连接走线CL一一对应地连接。
如图11所示，静电放电单元ESD1，ESD2，…，ESDh中的每一个包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。第一晶体管T1和第二晶体管T2各自的栅极和第一极以及第三晶体管T3和第四晶体管T4各自的第二极与相应的一条连接走线CL连接，第一晶体管T1和第二晶体管T2各自的第二极连接低电压信号线VGL，第三晶体管T3和第四晶体管T4各自的栅极和第一极连接高电压信号线VGH。
晶体管T1至T4可以均为P型晶体管。当连接走线CL上的信号高电平高于预设高电平值时，第三晶体管T3和第四晶体管T4中的至少之一导通以将连接走线CL上控制在高电压信号线VGH的电位，从而使过高电平通过第三晶体管T3和第四晶体管T4中的至少之一释放。当连接走线CL上的信号低电平低于预设低电平值时，第一晶体管T1和第二晶体管T2中的至少之一导通以将连接走线CL控制在低电压信号线VGL的电位，从而使过低电平通过第一晶体管T1和第二晶体管T2中的至少之一释放。
虽然图11中的静电放电单元具有特定的电路结构，然而本公开的实施例不限于此，静电放电单元可以根据需要而具有其他电路结构，例如包括更多或更少的晶体管，或者以其他方式连接的任意数量的晶体管。
图12A示出了图2中区域A3的布局图。图12B示出了图12A中的静电放电电路130的局部放大图。
如图12A和12B所示，静电放电电路130可以包括多个静电放电单元ESD1，ESD2，…，ESDh，图12B中为了简明起见仅标注了其中两个静电放电单元ESDi和ESD(i+1)。多个静电放电单元ESD1，ESD2，…，ESDh与多条连接走线CL一一对应地连接。静电放电单元ESD1，ESD2，…，ESDh中的每一个包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。与图11所示的静电放电单元的电路结构不同的 是，图12B中第一晶体管T1和第二晶体管T2串联连接在连接走线CL与低电压信号线VGL之间，第三晶体管T3和第四晶体管T4串联在连接走线CL与高电压信号线VGH之间。
图13示出了根据本公开另一实施例的显示基板的平面示意图。图13的显示基板与图2类似，区别至少在于数据走线DL和连接走线CL均分成多个组。
在图13中，多条数据走线DL被划分为多组，沿x方向从左至右分别为第一组数据走线GB1、第二组数据走线GB2、第三组数据走线GB3、第四组数据走线GB4、第五组数据走线GB5和第六组数据走线GB6(下文统称数据走线组GB)。以显示基板110沿y方向的中心线为对称轴，第一组数据走线GB1与第六组数据走线GB6对称，第二组数据走线GB2与第五组数据走线GB5对称，第三组数据走线GB3分别与第四组数据走线GB4对称。以类似的方式，多条连接走线CL被划分为第一组连接走线GC1至第六组连接走线GC6(下文统称连接走线组GC)。
根据本公开的实施例，相邻两组GB之间的距离大于组GB内相邻数据走线之间的距离，相邻两组GC之间的距离大于组GC内相邻连接走线之间的距离，下文将参考图14和图15进行详细说明。
图14示出了图13中区域B1的示意图。图15示出了图13中区域B2的示意图。
如图14所示，分别属于组GB1和GB2且彼此相邻的两条数据走线DL的数据走线第三子线F3在x方向上相距第一距离d1(下文也称作相邻组之间的距离)。属于同一组(例如属于GB1或者属于GB2且彼此相邻的两条数据走线DL的数据走线第三子线F3相距第二距离d2，其中第二距离d2小于第一距离d1。相邻组之间的距离可以根据需要来设置，例如组GB1和GB2之间的距离d1可以与GB2和GB3之间的距离d1’相等，也可以不等。在一些实施例中，如图13所示，组GB3和GB4之间的距离大于组GB1和GB2之间的距离。
类似地，如图15所示，分别属于组GC1和GC2且彼此相邻的两条连接走线CL的连接走线第一子线K1在x方向上相距第三距离d3，属于同一组(例如属于GC1或者属于GC2)且彼此相邻的两条连接走线CL的连接走线第一子线K1在x方向上相距第四距离d4，所述第四距离d4小于第三距离d3。在一些实施例中，相邻两组连接走线之间的距离可以等于与之连接的相邻两组数据走线之间的距离，例如组GC1和GC2之间的距离d3可以等于组GB1和GB2之间的距离d1。
图16示出了图13中区域B3的示意图。图17示出了图13中区域B3的布局图。
如图16和17所示，图13中的连接走线组GC3可以被划分为第一子组连接走线GC3_1、第二子组连接走线GC3_2和第三子组连接走线GC3_3，第一子组连接走线GC3_1和第三子组走线走线GC3_3沿x方向位于第二子组连接走线GC3_2两侧。
在第一子组连接走线GC3_1和第三子组连接走线GC3_3中，各个第一连接走线CL_a和第二连接走线CL_b的连接走线第一子线K1呈折线形延伸至图案化线走线。在第二子组连接走线GC3_2中，各个连接走线(包括CL_a、CL_b和CL_c)的连接走线第一子线K1均呈直线形延伸。
第一子组连接走线GC3_1和第三子组连接走线GC3_3中，不同连接走线的折线形延伸部分的长度可以是变化的。在一些实施例中，与第一子组连接走线GC3_1电连接的第一组数据走线GB3_1d的长度从左到右逐渐减小，相应地在第一子组连接走线GC3_1中，各个第一连接走线CL_a和第二连接走线CL_b的折线形延伸部分的长度从左到右(即沿着x方向)也逐渐减小，从而补偿与之连接的数据走线的长度变化。例如在图16中，位于最左侧的第一连接走线CL_a的折线形延伸部分的长度大于其右侧的第二连接走线CL_b的折线形延伸部分的长度，以此类推。
类似地，在第三子组连接走线GC3_3中，各个第一连接走线CL_a和第二连接走线CL_b的连接走线第一子线K1的折线形延伸部分的长度可以沿着x方向逐渐增大，例如位于最右侧的第一连接走线CL_a的折线形延伸部分的长度小于其左侧的第二连接走线CL_b的折线形延伸部分的长度，以此类推。
在图16中，第一子组连接走线GC3_1中各个折线延伸部分形成的图案与第三子组连接走线GC3_3中各个折线延伸部分形成的图案是对称的，即，两个子组中的折线形延伸部分以相同的斜率递减或递增。然而本公开的实施例不限于此，在一些实施例中，第一子组连接走线GC3_1中从左至右各个折线延伸部分的长度以一定斜率递减，而第三子组连接走线GC3_3中从左至右各个折线延伸部分的长度以小于该斜率的另一斜率递增(取决于与第三子组连接走线GC3_3连接的数据走线的长度变化)，从而第一子组连接走线GC3_1和第三子组连接走线GC3_3形成的图案是不对称的。在另一些实施例中，第三子组连接走线GC3_3均不具有折线形延伸部分。
其他连接走线组GC1、GC2、GC4、GC5和GC6具有类似的结构，这里不再赘述。
由于不同导体层的材料具有不同的电阻率，因此位于不同导体层的走线在长度相同的情况下可能电阻不同。例如第三导体层的材料的电阻率可能低于第一导体层和第二导体层的材料的电阻率。本公开的实施例通过将位于第一导体层和第二导体层的连 接走线的一部分设置成折线形状，可以增加这些连接走线的长度，从而补偿由于与这些连接走线连接的数据走线的低电阻。通过这种方式，使得各个数据信号的传输路径的电阻可以基本相同。
在一些实施例中，不同组内连接走线的折线形延伸部分的长度的渐变程度可以不同，下面将参考图18A至图18C来详细说明。
图18A至18C分别示出了组GC1至GC3的第一子组连接走线的布局。组GC4至GC6与组GC1至GC3对称设置，因此这里不再赘述。
如图18A所示，在组GC1的第一子组GC1_1中，相邻两个折线形延伸部分的长度不同，使得各个折线形延伸部分的长度以第一斜率逐渐减小，从而形成如虚线所示的三角形图案。类似地，如图18B所示，在组GC2的第一子组GC2_1中，各个折线形延伸部分的长度以第二斜率逐渐减小，从而形成如虚线所示的三角形图案；如图18C所示，在组GC3的第一子组GC3_1中，各个折线形延伸部分的长度以第三斜率逐渐减小，从而形成如虚线所示的三角形图案。
从图18A至图18C可以看出，第一斜率大于第二斜率，第二斜率大于第三斜率，也就是说，组GC1内相邻两个折线形延伸部分的长度差大于组GC2内相邻的折线形延伸部分的长度差，而组GC2内相邻的折线形延伸部分的长度差大于组GC2内相邻的折线形延伸部分的长度差。
图19示出了根据本公开实施例的显示基板的子像素结构的示意图。
如图19所示，显示基板中多个子像素中的至少一个包括薄膜晶体管和电容，所述薄膜晶体管具有栅极G、源极S和漏极D，所述电容具有第一极ED1和第二极ED2。薄膜晶体管的有源层P-Si位于缓冲层510与第一栅绝缘层520之间，并且与源极S和漏极D连接。层间绝缘层540位于栅极G与源极S和漏极D之间。第一栅绝缘层520位于层间绝缘层540面向衬底基板110的一侧。第二栅绝缘层530位于层间绝缘层540与第一栅绝缘层520之间。电容的第一极ED1与薄膜晶体管的栅极G同层设置，电容的第二极ED2设置在层间绝缘层540与第二栅绝缘层530之间。
子像素还可以包括钝化层1901、第一平坦层1902、转接电极1903和第二平坦层1904。钝化层1901位于层间介质层540远离衬底基板110的一侧。第一平坦层1902位于钝化层1901远离衬底基板110的一侧。转接电极1903位于第一平坦层1902远离衬底基板110的一侧，并且通过设置在第一平坦层1902和钝化层1901中的过孔与薄膜晶体管的源极S连接。第二平坦层1904设置在转接电极1903远离衬底基板110的一侧并 且至少部分覆盖转接电极1903。
子像素还可以包括像素界定层1905和发光元件，所述发光元件包括阳极1906、发光层1907和阴极1908。像素界定层1905位于第二平坦层1904远离衬底基板110的一侧。阳极1906位于转接电极1903远离衬底基板110的一侧并且与转接电极1903连接。发光层1907位于阳极1906远离衬底基板110的一侧并且部分地覆盖阳极1906。阴极1908位于发光层1907远离衬底基板110的一侧。
子像素还可以包括封装层1909，其位于阴极1908远离衬底基板110的一侧。在一些实施例中，封装层1909可以包括依次堆叠的第一无机封装层、有机封装层和第二无机封装层。
上述实施例中的第一数据走线DL_a和第一连接走线CL_a可以与薄膜晶体管的栅极G同层设置，第二数据走线DL_b和第二连接走线CL_b可以与电容的第二极ED2同层设置，第三数据走线DL_c和第三连接走线CL_c可以与源极S和/或漏极D同层设置。图案化走线BL可以与转接电极1903同层设置。
本公开的实施例还提供了一种显示面板，可以包括上述任意实施例的显示基板。在一些实施例中，该显示面板可以为有源矩阵有机发光二极管(AMOLED，Active-Matrix Organic Lighting-Emitting Diode)显示面板。
应当注意的是，在以上的描述中，仅以示例的方式，示出了本公开实施例的技术方案，但并不意味着本公开实施例局限于上述步骤和结构。在可能的情形下，可以根据需要对步骤和结构进行调整和取舍。因此，某些步骤和单元并非实施本公开实施例的总体发明思想所必需的元素。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开实施例的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开实施例的范围不局限于上述特定实施例，而应由所附权利要求所限定。

Claims (19)

  1. 一种显示基板，包括
    衬底基板，包括显示区和围绕所述显示区域的周边区；
    多个子像素，位于所述显示区中；
    多条数据线，位于所述显示区中，沿第一方向排列并且沿第二方向延伸，所述多条数据线连接至所述多个子像素；
    多条数据走线，位于所述周边区中，沿所述第二方向位于所述显示区的一侧，所述多条数据走线分别与所述多条数据线连接，
    其中，所述多条数据走线包括周期排布的第一数据走线、第二数据走线和第三数据走线，其中第一数据走线位于第一导体层、第二数据走线位于第二导体层，第三数据走线位于第三导体层，其中所述第一导体层位于所述衬底基板面向所述多个子像素的一侧，所述第二导体层位于所述第一导体层远离所述衬底基板的一侧，所述第三导体层位于所述第二导体层远离所述衬底基板的一侧，至少一条第一数据走线的一部分在衬底基板的正投影与至少一条第三数据走线的一部分在衬底基板的正投影重叠。
  2. 根据权利要求1所述的显示基板，其中，所述周边区中设有弯折区，所述弯折区沿所述第二方向位于所述多条数据走线远离所述显示区的一侧，所述显示基板还包括：多条图案化走线，位于所述弯折区中，所述多条图案化走线与所述多条数据走线对应地连接。
  3. 根据权利要求2所述的显示基板，其中，所述数据走线包括数据走线第一子线、数据走线第二子线和数据走线第三子线，所述数据走线第一子线与所述多条数据线中的至少一条数据线连接，所述数据走线第三子线与所述多条图案化走线中的至少一条图案化走线连接，所述数据走线第二子线连接在所述数据走线第一子线和所述数据走线第三子线之间，
    其中至少一条第一数据走线的数据走线第二子线在衬底基板的正投影与至少一条第三数据走线的数据走线第二子线在衬底基板的正投影至少部分重叠。
  4. 根据权利要求2所述的显示基板，还包括：多条连接走线，位于所述周边区，沿所述第二方向位于所述弯折区远离所述显示区的一侧，所述多条连接走线与所述多条图案化走线对应地连接，
    其中，所述多条连接走线包括周期排布的第一连接走线、第二连接走线和第三连接走线，其中第一连接走线位于所述第一导体层、第二连接走线位于所述第二导体层， 第三连接走线位于所述第三导体层。
  5. 根据权利要求4所述的显示基板，其中，每条第一数据走线通过一条图案化走线连接至一条第三连接走线，每条第二数据走线通过一条图案化走线连接至一条第三连接走线，每条第三数据走线通过一条图案化走线连接至一条第一连接走线或第二连接走线。
  6. 根据权利要求5所述的显示基板，其中，任意相邻的两条第三数据走线中，一条第三数据走线通过一条图案化走线与第一连接走线连接，另一条第三数据走线通过一条图案化走线与第二连接走线连接。
  7. 根据权利要求4所述的显示基板，其中，所述连接走线包括连接走线第一子线和连接走线第二子线，所述连接走线第一子线连接所述多条图案化走线中的一条图案化走线，所述连接走线第二子线与所述连接走线第一子线连接，
    其中，所述多条连接走线中至少一条连接走线的连接走线第一子线呈折线形延伸至相应的图案化线走线。
  8. 根据权利要求6所述的显示基板，还包括：辅助电路，位于所述周边区，沿所述第二方向位于所述多条连接走线远离所述显示区的一侧，
    所述连接走线还包括连接走线第三子线，所述连接走线第三子线与所述辅助电路连接，所述连接走线第二子线连接在所述连接走线第一子线和连接走线第三子线之间。
  9. 根据权利要求8所述的显示基板，其中，所述辅助电路包括静电放电电路，所述静电放电电路包括多个静电放电单元，所述多个静电放电单元与所述多条连接走线的连接走线第三子线一一对应地连接。
  10. 根据权利要求3所述的显示基板，其中，所述多条数据走线被划分为多组数据走线，其中分别属于相邻两组且彼此相邻的两条数据走线的数据走线第三子线在第一方向上相距第一距离，属于同一组且彼此相邻的两条数据走线的数据走线第三子线在第一方向上相距第二距离，所述第二距离小于第一距离。
  11. 根据权利要求6所述的显示基板，其中，所述多条连接走线被划分为多组连接走线，其中分别属于相邻两组且彼此相邻的两条连接走线的连接走线第一子线在第一方向上相距第三距离，属于同一组且彼此相邻的两条连接走线的连接走线第一子线在第一方向上相距第四距离，所述第四距离小于第三距离。
  12. 根据权利要求11所述的显示基板，其中，至少一组连接走线被划分为第一子组连接走线、第二子组连接走线和第三子组连接走线，所述第一子组连接走线和所述 第三子组走线走线沿第一方向位于所述第二子组连接走线两侧，
    其中，
    在所述第一子组连接走线中，各个第一连接走线和第二连接走线的连接走线第一子线呈折线形延伸至图案化线走线，且各个第一连接走线和第二连接走线的折线形延伸部分的长度沿着第一方向逐渐减小；
    在所述第三子组连接走线中，各个第一连接走线和第二连接走线的连接走线第一子线呈折线形延伸至图案化线走线，且各个第一连接走线和第二连接走线的连接走线第一子线的折线形延伸部分的长度沿着第一方向逐渐增大。
  13. 根据权利要求1至12中任一项权利要求所述的显示基板，其中，所述多个子像素中至少一个包括：
    薄膜晶体管，所述薄膜晶体管具有栅极、源极和漏极；
    层间绝缘层，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；
    第一栅绝缘层，所述第一栅绝缘层位于所述层间绝缘层面向所述衬底基板的一侧；
    第二栅绝缘层，所述第二栅绝缘层位于所述层间绝缘层与所述第一栅绝缘层之间；以及
    电容，所述电容的第一极与所述栅极同层设置，所述电容的第二极设置在所述层间绝缘层与所述第二栅绝缘层之间，
    其中，所述第一数据走线与所述栅极同层设置，所述第二数据走线与所述电容的第二极同层设置，所述第三数据走线与所述源极或所述漏极同层设置。
  14. 根据权利要求9所述的显示基板，其中，至少一个静电放电单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极和第一极、所述第二晶体管的栅极和第一极、所述第三晶体管的第二极和所述第四晶体管的第二极与相应的一条连接走线第三子线连接，所述第一晶体管的第二极和所述第二晶体管的第二极连接低电压信号线，所述第三晶体管的栅极和第一极和所述第四晶体管的栅极和第一极连接高电压信号线。
  15. 根据权利要求9所述的显示基板，其中，所述辅助电路还包括单元测试电路，所述单元测试电路包括多个单元测试子电路，所述多个单元测试子电路与所述多条连接走线的连接走线第三子线一一对应地连接。
  16. 根据权利要求3所述的显示基板，其中，至少一条第一数据走线的数据走线第二子线在衬底基板的正投影与至少一条第三数据走线的数据走线第二子线在衬底基板 的正投影完全重叠，至少一条第二数据走线的数据走线第二子线在衬底基板的正投影与至少一条第一数据走线的数据走线第二子线在衬底基板的正投影以及至少一条第三数据走线的数据走线第二子线在衬底基板的正投影不重叠。
  17. 根据权利要求10所述的显示基板，其中，所述多组数据走线包括沿第一方向排列的第一组数据走线、第二组数据走线、第三组数据走线、第四组数据走线、第五组数据走线和第六组数据走线，其中所述第一组数据走线与第六组数据走线相对于显示基板在第二方向上的对称轴而对称设置，所述第二组数据走线与所述第五组数据走线相对于所述对称轴而对称设置，所述第三组数据走线与第四组数据走线相对于所述对称轴而对称设置。
  18. 根据权利要求11所述的显示基板，其中，所述多组连接走线包括沿第一方向排列的第一组连接走线、第二组连接走线、第三组连接走线、第四组连接走线、第五组连接走线和第六组连接走线，其中所述第一组连接走线与第六组连接走线相对于显示基板在第二方向上的对称轴而对称设置，所述第二组连接走线与所述第五组连接走线相对于所述对称轴而对称设置，所述第三组连接走线与第四组连接走线相对于所述对称轴而对称设置。
  19. 一种显示面板，包括根据权利要求1至18中任一项权利要求所述的显示基板。
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