WO2022176188A1 - キャパシタ - Google Patents

キャパシタ Download PDF

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Publication number
WO2022176188A1
WO2022176188A1 PCT/JP2021/006570 JP2021006570W WO2022176188A1 WO 2022176188 A1 WO2022176188 A1 WO 2022176188A1 JP 2021006570 W JP2021006570 W JP 2021006570W WO 2022176188 A1 WO2022176188 A1 WO 2022176188A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
comb
wiring
layer
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/006570
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English (en)
French (fr)
Japanese (ja)
Inventor
照男 徐
宗彦 長谷
秀之 野坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to PCT/JP2021/006570 priority Critical patent/WO2022176188A1/ja
Priority to US18/546,526 priority patent/US20240130046A1/en
Priority to JP2023500482A priority patent/JPWO2022176188A1/ja
Publication of WO2022176188A1 publication Critical patent/WO2022176188A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor

Definitions

  • the present invention relates to capacitors used in high frequency devices.
  • capacitors are essential components for designing circuit time constants, impedance, etc.
  • Integrated circuits generally use MIM (Metal-Insulator-Metal) capacitors in which a dielectric is sandwiched between two parallel plates.
  • MIM Metal-Insulator-Metal
  • This circuit may require a capacitor with a small capacitance value of several fF to 10 fF.
  • the MIM capacitor may be limited to several tens of fF or more due to limitations imposed by process accuracy and the like.
  • a comb-shaped capacitor shown in FIG. 8 has been proposed as a capacitor capable of achieving a capacitance value of 10 fF or less with high accuracy through a normal manufacturing process (Non-Patent Document 1).
  • This comb capacitor uses a wiring layer formed in a manufacturing process. It is possible to flexibly design the spacing, width, shape, etc. of the two wirings, and it is also possible to design a capacitor with a capacitance value of 10 fF or less.
  • FIG. 9 shows simulation results of the effective capacitance value when designing a comb capacitor of 10 fF (FIG. 8).
  • the frequency at which the capacitance of the capacitor is in the range of 10% from the capacitance value on the low frequency side remains at about 150 GHz.
  • a capacitor according to the present invention is a capacitor comprising a pair of laminated electrodes facing each other and connected to an electric wiring from the outside, wherein the laminated electrodes comprise a plurality of wiring layers. and a via layer between the wiring layers, wherein the laminated electrode comprises a comb portion and a comb portion connection portion connected to a base end of the comb portion, and between one of the laminated electrodes and the other of the laminated electrodes and the comb portion of the other laminated electrode is arranged between the comb portions of the one laminated electrode.
  • FIG. 1A is a bird's-eye view showing the configuration of a capacitor according to a first embodiment of the invention.
  • FIG. 1B is a top view showing the configuration of the capacitor according to the first embodiment of the invention.
  • FIG. 1C is an IC-IC' side sectional view showing the configuration of the capacitor according to the first embodiment of the present invention.
  • FIG. 2 is a diagram for explaining the method of manufacturing the capacitor according to the first embodiment of the present invention.
  • FIG. 3 is a diagram for explaining the effect of the capacitor according to the first embodiment of the invention.
  • FIG. 4 is a top view showing an example of the configuration of the capacitor according to the first embodiment of the invention.
  • FIG. 5A is a bird's-eye view showing the configuration of a capacitor according to a second embodiment of the invention.
  • FIG. 5B is a VB-VB' front cross-sectional view showing the configuration of the capacitor according to the second embodiment of the present invention.
  • FIG. 6A is a bird's-eye view showing the configuration of a capacitor according to the third embodiment of the invention.
  • FIG. 6B is a bird's-eye view showing the configuration of a capacitor according to the third embodiment of the invention.
  • FIG. 6C is a diagram for explaining the arrangement of comb portions in the capacitor according to the third embodiment of the present invention;
  • FIG. 7 is a bird's-eye view showing the configuration of a capacitor according to the fourth embodiment of the invention.
  • FIG. 8 is a bird's-eye view showing the configuration of a conventional capacitor.
  • FIG. 9 is a diagram for explaining characteristics of a conventional capacitor.
  • FIG. 1A A capacitor according to a first embodiment of the invention will be described with reference to FIGS. 1A to 4.
  • FIG. 1A A capacitor according to a first embodiment of the invention will be described with reference to FIGS. 1A to 4.
  • FIG. 1A A capacitor according to a first embodiment of the invention will be described with reference to FIGS. 1A to 4.
  • FIG. 1A A capacitor according to a first embodiment of the invention will be described with reference to FIGS. 1A to 4.
  • a capacitor 1 according to the present embodiment is composed of a pair of laminated electrodes 10_1 and 10_2.
  • the laminated electrodes 10_1 and 10_2 have three wiring layers and two via layers, and the via layers are provided between the wiring layers.
  • the three wiring layers are lower wiring layers 11_1 and 11_2, intermediate wiring layers 12_1 and 12_2, and upper wiring layers 13_1 and 13_2.
  • the upper wiring layers 13_1 and 13_2 are thicker in this order. The number of layers and layer thickness are not limited to these.
  • the two via layers are lower via layers 14_1 and 14_2 and upper via layers 15_1 and 15_2, which are made of metal.
  • Lower via layers 14_1 and 14_2 are arranged between lower wiring layers 11_1 and 11_2 and intermediate wiring layers 12_1 and 12_2 respectively, and upper via layers 15_1 and 15_2 are arranged between intermediate wiring layers 12_1 and 12_2 and upper wiring layers 13_1 and 13_2 respectively. and electrically connect each wiring layer.
  • one laminated electrode 10_1 has an even number of comb portions 16_1, and the base ends of the comb portions 16_1 are connected to the comb portion connection portions 17_1.
  • the other laminated electrode 10_2 has an odd number of comb portions 16_2, and the base ends of the comb portions 16_2 are connected to the comb portion connection portions 17_2.
  • the X direction in the drawing is called the "comb connection portion direction”
  • the Y direction in the drawing is called the “comb section direction”
  • the Z direction in the drawing is called the “vertical direction”. Therefore, the comb portion and the comb portion connection portion are connected in the Y direction, and each wiring layer and each via layer are laminated in the Z direction.
  • the direction in which the wiring layer and the via layer are stacked is perpendicular to the direction in which the comb portion and the comb portion connection portion are connected.
  • the capacitor 1 is configured such that a pair of laminated electrodes 10_1 and 10_2 face each other, and the comb portion 16_2 of the other laminated electrode 10_2 is arranged between the comb portions 16_1 of one laminated electrode 10_1.
  • dielectrics 18_1, 18_2 and 18_3 are arranged between the laminated electrodes 10_1 and 10_2 and around the laminated electrodes 10_1 and 10_2.
  • the comb portion 16_2 of the other laminated electrode 10_2 be arranged in the center between the comb portions 16_1 of the one laminated electrode 10_1.
  • the pair of laminated electrodes 10_1 and 10_2 are configured to be line symmetrical with respect to the center line (chain line IC-IC' in FIG. 1B) in the comb direction of the central comb portion 16_2 of the other laminated electrode 10_2. be.
  • electrical wiring from the outside is connected to the central portions of the comb connection portions 17_1 and 17_2 of the upper wiring layers 13_1 and 13_2, respectively.
  • the electrical wiring may be connected to the lower wiring layers 11_1, 11_2 or the intermediate wiring layers 12_1, 12_2.
  • ⁇ Capacitor manufacturing method> An example of a method for manufacturing capacitor 1 according to the present embodiment will be described with reference to FIG. A normal semiconductor device manufacturing process is used for the manufacturing method.
  • lower wiring layers 11_1 and 11_2 are formed on the dielectric 18_1 (step S1).
  • a dielectric 18_2 is formed to cover the lower wiring layers 11_1 and 11_2 (step S2).
  • lower via layers 14_1 and 14_2 are formed in the dielectric 18_2 so as to be electrically connected to the lower wiring layers 11_1 and 11_2 (step S3).
  • intermediate wiring layers 12_1 and 12_2 are formed so as to be electrically connected to the lower via layers 14_1 and 14_2 (step S4).
  • a dielectric 18_3 is formed to cover the intermediate wiring layers 12_1 and 12_2 (step S5).
  • upper via layers 15_1 and 15_2 are formed in the dielectric 18_3 so as to be electrically connected to the intermediate wiring layers 12_1 and 12_2 (step S6).
  • upper wiring layers 13_1 and 13_2 are formed so as to be electrically connected to the upper via layers 15_1 and 15_2 (step S7).
  • a capacitor having a configuration in which comb-shaped wiring layers are formed in each of a plurality of layers of a multilayer printed circuit board and the comb-shaped wiring layers of each layer are connected by vias in the vertical direction can be manufactured.
  • the capacitor 1 according to the present embodiment can be formed on a semiconductor substrate such as a silicon substrate.
  • the capacitor 1 according to the present embodiment has a configuration in which wiring layers are increased in the vertical direction, so that the capacitance per unit area is increased compared to the conventional configuration, so an equivalent capacitance value can be realized with a smaller size capacitor.
  • the wiring length can be reduced and the parasitic inductance can be reduced. Furthermore, since the thickness of the wiring is equivalently increased compared to the configuration with only one wiring layer, the parasitic inductance can be reduced. Since the self-resonant frequency is increased by reducing the parasitic inductance in this manner, the usable frequency range of the capacitor according to the present embodiment can be expanded.
  • FIG. 3 shows the result of simulating the effective capacitance value (solid line in the figure) when a capacitor of 10 fF is designed using the configuration of the capacitor 1 according to the present embodiment.
  • the result of designing a 10 fF capacitor using the conventional configuration (dotted line in the figure, similar to FIG. 9) is also shown.
  • the resonance frequency is higher than when the conventional configuration is used, and the frequency within the range of 10% from the capacitance value on the low frequency side is 220 GHz.
  • the usable frequency range can be expanded by 40% or more compared to the case of using the conventional configuration.
  • the usable frequency range can be expanded, and a higher frequency band can be used for high-frequency circuits.
  • the resonance frequency can be increased, and the usable Can extend the frequency range.
  • two comb portions 16_1 and one comb portion 16_2 face each other. good too.
  • the comb portions of the respective laminated electrodes are even-numbered so as to be symmetrical about the center line of the central comb portion 16_2 in the comb portion direction of the laminated electrode 101_2 having an odd number of comb portions.
  • the vertical and horizontal aspect ratios of the upper surface shape of each laminated electrode are 1:1 to 1:1.5 or 1:1 to 1.5. : Desirably within the range of 1. In other words, it is desirable that the ratio of the length in the direction of the comb portion and the length in the direction of the comb portion connection portion of the capacitor according to the present embodiment is 1/1.5 or more and 1.5 or less.
  • the capacitor according to the present embodiment for example, in a manufacturing process for an element (resistor or transistor) that can be connected only to a wiring of a specific layer in a multilayer printed circuit board, the comb portion of the capacitor and the comb portion connection portion are formed in all layers. By doing so, the capacitor can be easily connected to all elements (resistors and transistors). With this configuration, the capacitance value per unit area is also increased, so the size of the comb capacitor can be reduced.
  • each wiring layer and each via layer have the same shape
  • they may be substantially the same, or may have different shapes.
  • each wiring layer and each via layer may not be completely overlapped when viewed from above.
  • the via layer may be composed of a plurality of columnar structures. Any shape or configuration may be employed as long as the wiring layer is increased in the vertical direction to increase the capacitance per unit area.
  • a capacitor according to a second embodiment of the present invention will be described with reference to FIGS. 5A and 5B.
  • the capacitor 2 according to this embodiment can be manufactured in substantially the same manner as the capacitor according to the first embodiment.
  • the capacitor 2 As shown in FIGS. 5A and 5B, the capacitor 2 according to this embodiment has a lower wiring layer 21, an intermediate wiring layer 22, an upper wiring layer 23, a lower via layer 24, and an upper via layer 25. .
  • the three wiring layers are made of metal, and the lower wiring layer 21, the intermediate wiring layer 22, and the upper wiring layer 23 are thicker in this order.
  • the number of layers and layer thickness are not limited to these.
  • the lower via layer 24 and the upper via layer 25 are made of metal.
  • a dielectric is arranged between and around the wiring layer and the via layer.
  • the lower wiring layer 21 and the upper wiring layer 23 have planar shapes. Although it is rectangular in this embodiment, the shape is not limited to this.
  • the intermediate wiring layer 22 is composed of three wiring portions, and each wiring portion is a rectangular parallelepiped (rectangular when viewed from above). Each wiring part is arranged substantially parallel.
  • Two wiring portions 22_1 are connected via the upper wiring layer 23 and the upper via layer 25 .
  • one wiring portion 22_2 is connected through the lower wiring layer 21 and the lower via layer 24 and arranged between the two wiring portions 22_1.
  • the wiring portions 22_1 and 22_2 of the intermediate wiring layer are arranged on the same horizontal plane so as to be line symmetrical with respect to the center line (dotted line AA' in the figure) in the wiring portion direction of one wiring portion 22_2. placed.
  • the electrical wiring from one outside is connected to the central portion of the upper wiring layer 23, and the electrical wiring from the other outside (port 2) is connected to the central portion of the lower wiring layer 21. .
  • the two wiring portions 22_1 and the upper via layer 25 each form a comb portion 26_1, which is connected to the upper wiring layer 23 as a comb portion connection portion 27_1 to connect one laminated electrode. 20_1.
  • a single wiring portion 22_2 and the upper via layer 24 form a comb portion 26_2, which is connected to the lower wiring layer 21 as a comb portion connecting portion 27_2 to form the other laminated electrode 20_2.
  • the comb portions 26_1 and 26_2 are arranged line-symmetrically with respect to the center line (dotted line A-A' in the drawing) of the central comb portion of the comb portion 26_2 of the other laminated electrode 20_2.
  • the Z direction in the drawing is referred to as the "vertical direction", and the comb portion and the comb portion connection portion are connected in the vertical direction, and each wiring layer and each via layer are stacked in the vertical direction.
  • the direction in which the wiring layer and the via layer are stacked is the same direction (parallel) as the direction in which the comb portion and the comb portion connection portion are connected.
  • the capacitor 2 according to the present embodiment is configured such that the pair of laminated electrodes 10_1 and 10_2, that is, the one laminated electrode 20_1 and the other laminated electrode 10_2 face each other in the vertical direction.
  • the same effects as those of the first embodiment can be obtained.
  • the number of combs in each laminated electrode is increased by an even number so that the central comb in the laminated electrode having an odd number of combs is symmetrical with respect to the center line in the direction of the comb (the total number of combs is an odd number). ), the capacitance value can be increased while maintaining a wide frequency range.
  • the inductance can be reduced.
  • the wiring layers and the via layers in the comb portion have the same shape has been shown, but they are not limited to being exactly the same, they may be substantially the same, or they may have different shapes. Also, the wiring layer and the via layer in the comb portion need not be completely overlapped when viewed from above. Also, the via layer may be composed of a plurality of columnar structures.
  • a comb portion wiring portion of an intermediate wiring layer having a rectangular upper surface shape
  • a comb portion connected to the upper wiring layer is arranged between the comb portions connected to the lower wiring layer (comb portion connection portion), and a pair of laminated electrodes are arranged so as to face each other in the vertical direction. Any shape or configuration that increases the capacity per hit may be used.
  • a capacitor according to a third embodiment of the present invention will now be described with reference to FIGS. 6A-C.
  • the capacitor 3 according to this embodiment can be manufactured in substantially the same manner as the capacitor according to the first embodiment.
  • the capacitor 3 according to the present embodiment has a lower wiring layer 31, an intermediate wiring layer 32, an upper wiring layer 33, a lower via layer 34, and an upper via layer 35, as shown in FIGS. .
  • the three wiring layers are made of metal, and the lower wiring layer 31, the intermediate wiring layer 32, and the upper wiring layer 33 are thicker in this order.
  • the number of layers and layer thickness are not limited to these.
  • the lower via layer 34 and the upper via layer 35 are made of metal.
  • a dielectric is arranged between and around the wiring layer and the via layer.
  • the lower wiring layer 31 and the upper wiring layer 33 have planar shapes. Although it is rectangular in this embodiment, the shape is not limited to this.
  • the intermediate wiring layer 32 is composed of a plurality of wiring portions 32_1 and 32_2.
  • Each of the wiring portions 32_1 and 32_2 is a rectangular parallelepiped with a square upper surface shape and is arranged periodically.
  • the wiring portion having a square upper surface shape prevents an extreme increase in the parasitic inductance component and widens the frequency range that can be used as a capacitor.
  • the five wiring portions 32_1 in the intermediate wiring layer 32 are connected via the upper wiring layer 33 and the upper via layer 35 .
  • the four wiring portions 32_2 are connected to the lower wiring layer 31 through the lower via layer 34 and arranged between the wiring portions 32_1 connected to the upper wiring layer 33 .
  • the wiring sections 32_1 and 32_2 of the intermediate wiring layer are arranged on the same horizontal plane so as to be point-symmetrical with respect to the center of one wiring section 32_1.
  • the electrical wiring from one outside is connected to the central portion of the upper wiring layer 33, and the electrical wiring from the other outside (port 2) is connected to the central portion of the lower wiring layer 31. .
  • the five wiring portions 32_1 and the upper via layer 35 each form a comb portion 36_1, which is connected to the upper wiring layer 33 as a comb portion connection portion 37_1 to connect one laminated electrode. 30_1.
  • the four wiring portions 32_2 and the lower via layer 34 form a comb portion 36_2, which is connected to the lower wiring layer 31 as a comb portion connecting portion 37_2 to constitute the other laminated electrode 30_2.
  • the comb portions 36_1 and 36_2 are arranged point-symmetrically with respect to the center point of the central comb portion of the comb portion 36_1 of one of the laminated electrodes 30_1.
  • the Z direction in the drawing is referred to as the "vertical direction", and the comb portion and the comb portion connection portion are connected in the vertical direction, and each wiring layer and each via layer are stacked in the vertical direction.
  • the direction in which the wiring layer and the via layer are stacked is the same direction (parallel) as the direction in which the comb portion and the comb portion connection portion are connected.
  • the capacitor 3 according to the present embodiment is configured such that a pair of laminated electrodes 30_1 and 30_2, that is, one laminated electrode 30_1 and the other laminated electrode 30_2 face each other in the vertical direction.
  • the same effects as those of the first and second embodiments can be obtained even when the via size is limited.
  • the number of combs in each laminated electrode is increased by an even number so that the number of combs in each laminated electrode is symmetrical with respect to the center of the central comb in the laminated electrode having an odd number of combs (so that the total number of combs is an odd number). ), the capacitance value can be increased while maintaining a wide frequency range.
  • the inductance can be reduced.
  • the wiring layers and the via layers in the comb portion have the same shape has been shown, but they are not limited to being exactly the same, they may be substantially the same, or they may have different shapes. Also, the wiring layer and the via layer in the comb portion need not be completely overlapped when viewed from above.
  • a comb portion wiring portion of an intermediate wiring layer having a square upper surface shape
  • the upper surface shape of the comb portion is not limited to this, and may be circular or other shapes.
  • a comb portion connected to the upper wiring layer (comb portion connection portion) is arranged between the comb portions connected to the lower wiring layer (comb portion connection portion), and a pair of laminated electrodes are arranged so as to face each other in the vertical direction. Any shape or configuration that increases the capacity per hit may be used.
  • a capacitor according to a fourth embodiment of the invention will be described with reference to FIG.
  • the capacitor 4 according to this embodiment can be manufactured in substantially the same manner as the capacitor according to the first embodiment.
  • the capacitor 4 according to this embodiment has substantially the same configuration as that of the first embodiment, but the configuration of the lower wiring layer is different.
  • an MIM (metal-insulator-metal) capacitor is arranged in the lower wiring layer 41. As shown in FIG.
  • the MIM capacitor is composed of an MIM upper layer metal 41_2, an MIM lower layer metal 41_1, and a dielectric between them.
  • the upper wiring layer 43_1 is connected to the intermediate wiring layer 42_1 through the upper via layer 45_1, and the intermediate wiring layer 42_1 is connected to the MIM upper layer metal 41_2 through the lower via layer 44_1. Connected.
  • the upper wiring layer 43_2 is connected to the intermediate wiring layer 42_2 through the upper via layer 45_2, and the intermediate wiring layer 42_2 is connected to the MIM lower layer metal 41_1 through the lower via layer 44_2. Connected.
  • each wiring layer is formed between layers of the multilayer circuit board, and each via layer is formed within the layers of the multilayer circuit board.
  • This configuration can be easily manufactured because it can be manufactured by a normal semiconductor device manufacturing process.
  • the capacitor according to the embodiment of the present invention has three wiring layers, it is not limited to this, and may have a plurality of wiring layers.
  • the upper wiring layer is the uppermost wiring layer
  • the lower wiring layer is the lowermost wiring layer.
  • the present invention can be applied to electronic circuits of equipment and devices used for optical communication, wireless communication, radar sensing, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/JP2021/006570 2021-02-22 2021-02-22 キャパシタ Ceased WO2022176188A1 (ja)

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Application Number Priority Date Filing Date Title
PCT/JP2021/006570 WO2022176188A1 (ja) 2021-02-22 2021-02-22 キャパシタ
US18/546,526 US20240130046A1 (en) 2021-02-22 2021-02-22 Capacitor
JP2023500482A JPWO2022176188A1 (https=) 2021-02-22 2021-02-22

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