WO2022172737A1 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
WO2022172737A1
WO2022172737A1 PCT/JP2022/002398 JP2022002398W WO2022172737A1 WO 2022172737 A1 WO2022172737 A1 WO 2022172737A1 JP 2022002398 W JP2022002398 W JP 2022002398W WO 2022172737 A1 WO2022172737 A1 WO 2022172737A1
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Prior art keywords
power supply
integrated circuit
circuit device
semiconductor integrated
standard cell
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PCT/JP2022/002398
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English (en)
French (fr)
Japanese (ja)
Inventor
秀幸 小室
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Socionext Inc
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Socionext Inc
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Priority to CN202280014374.1A priority Critical patent/CN116830257A/zh
Priority to JP2022581300A priority patent/JP7817572B2/ja
Publication of WO2022172737A1 publication Critical patent/WO2022172737A1/ja
Priority to US18/447,032 priority patent/US20230411246A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs

Definitions

  • the present disclosure relates to a semiconductor integrated circuit device with standard cells.
  • a standard cell method is known as a method of forming a semiconductor integrated circuit on a semiconductor substrate.
  • basic units with specific logic functions for example, inverters, latches, flip-flops, full adders, etc.
  • LSI chip is designed.
  • the standard cell is provided with a buried interconnect layer instead of the conventional power supply wiring provided in the metal wiring layer formed above the transistor. It has been proposed to use a buried power supply wiring (BPR: Buried Power Rail).
  • a power supply wiring is configured by an embedded power supply wiring, the source of a transistor is connected to the embedded power supply wiring, and further connected to a power supply wiring provided in an upper wiring layer.
  • a configuration is disclosed.
  • the embedded power supply wiring is embedded in the substrate, it cannot be formed in the region where the source, drain, and channel of the transistor exist. On the other hand, the embedded power wiring must have sufficient current supply capability for the transistors.
  • transistors such as fin FETs (Field Effect Transistors) and nanosheet FETs in microfabrication processes may be subject to restrictions on their size and arrangement position in order to suppress manufacturing variations.
  • An object of the present disclosure is to make it possible to arrange embedded power supply wiring having a sufficient wiring width without interfering with the regular arrangement of FinFETs in a semiconductor integrated circuit device using embedded power supply wiring.
  • a semiconductor integrated circuit device including a plurality of standard cells having FinFETs (Field Effect Transistors), wherein the plurality of fins constituting the FinFETs each extend in a first direction, Further, the plurality of standard cells are arranged on virtual grid lines at regular intervals in a second direction perpendicular to the first direction, and the plurality of standard cells are arranged in the second direction more than the first standard cells.
  • FinFETs Field Effect Transistors
  • a second standard cell having a large size in the a second embedded power supply wiring having a size in the second direction larger than that of the first embedded power supply wiring, wherein the centers of the first and second embedded power supply wirings in the second direction are on the virtual grid line; or It is in a central position between adjacent said virtual grid lines.
  • the plurality of fins forming the FinFET extend in the first direction and are arranged on imaginary grid lines equidistantly in the second direction.
  • the first and second standard cells have embedded power wiring lines, and the second standard cell having the larger size in the second direction has the embedded power wiring line having the larger size in the second direction.
  • the embedded power supply wiring provided in the first and second standard cells has a center position in the second direction on the virtual grid line or a center position between adjacent virtual grid lines. As a result, it is possible to arrange the embedded power supply wiring having a sufficient wiring width without interfering with the regular arrangement of the FinFETs.
  • FIG. 4 is a plan view showing another layout structure of the inverter cells forming the semiconductor integrated circuit device according to the embodiment;
  • a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter simply referred to as cells as appropriate), and at least some of the plurality of standard cells are FinFETs (Field FETs). Effect Transistor).
  • VDD and VVSS indicate power supply voltage or the power supply itself. Further, in the following description, in the plan views of FIG. Z direction.
  • FIG. 1 is a plan view showing an example of a layout structure of a standard cell forming a semiconductor integrated circuit device according to this embodiment. Both FIGS. 1(a) and 1(b) are inverter cells. 2A and 2B are diagrams showing the cross-sectional structure of the cell shown in FIG. 1, FIG. ) is a cross-sectional view taken along line BB' of FIG.
  • FIG. 3 is a plan view showing an example of the layout structure of another standard cell forming the semiconductor integrated circuit device according to this embodiment.
  • 3(a) and 3(b) are both 2-input NAND cells.
  • FIG. 4 shows circuit diagrams of cells
  • FIG. 4(a) is a circuit diagram of the inverter cell shown in FIG. 1
  • FIG. 4(b) is a circuit diagram of the two-input NAND cell shown in FIG.
  • the inverter cell shown in FIG. 1 and the two-input NAND cell shown in FIG. 3 have FinFETs, and a plurality of fins forming the FinFETs extend in the X direction.
  • the plurality of fins have the same width, that is, the size in the Y direction (Wf), and are arranged on virtual grid lines GL (indicated by thin dashed lines) that are equally spaced in the Y direction.
  • the pitch of the virtual grid lines GL is Pg. That is, the fins are arranged at a pitch Pg.
  • the number of fins constituting the FinFET is 2, and the cell height is Pg ⁇ 8.
  • the inverter cell shown in FIG. 1B and the 2-input NAND cell shown in FIG. FinFETs vary in drive capability depending on the number of fins that constitute them.
  • power supply wirings 11A and 12A extending in the X direction are provided at both ends in the Y direction. Both the power supply wirings 11A and 12A are embedded power supply wirings (BPR) formed in an embedded wiring layer.
  • the power supply wiring 11A supplies the power supply voltage VDD
  • the power supply wiring 12A supplies the power supply voltage VSS.
  • the center positions of the power wirings 11A and 12A in the Y direction match the center between the virtual grid lines GL.
  • the width of the power supply wirings 11A and 12A, that is, the size in the Y direction is Wb1.
  • Two fins 21A extending in the X direction are provided in the P-type transistor region on the N-well.
  • Two fins 22A extending in the X direction are provided in the N-type transistor region on the P-type substrate.
  • the gate wiring 31A extends in the Y direction from the P-type transistor area to the N-type transistor area. As shown in FIG. 2B, the gate wiring 31A is formed so as to surround the fins 21A and 22A from three directions.
  • a FinFET P1 is composed of two fins 21A and a gate wiring 31A.
  • a Fin FET N1 is composed of two fins 22A and a gate wiring 31A. For manufacturing reasons, it is necessary to set a distance Sb between the embedded power supply wiring and the fin closest to it.
  • a local wiring 41A extending in the Y direction is provided at the left end of the fin 21A in the drawing.
  • the left end of the fin 21A in the drawing is connected to the power supply wiring 11A via the local wiring 41A and the via 51A.
  • a local wiring 42A extending in the Y direction is provided at the left end of the fin 22A in the drawing.
  • the left end of the fin 22A in the drawing is connected to the power supply wiring 12A via the local wiring 42A and the via 52A.
  • a local wiring 43A extending in the Y direction is provided at the right end of the fins 21A and 22A in the drawing. One ends of the fins 21A and 22A on the right side of the drawing are connected to each other by a local wiring 43A.
  • the metal wiring 61A to which the input A is applied is connected to the gate wiring 31A via vias.
  • the metal wiring 62A for outputting the output Y is connected to the local wiring 43A via vias.
  • the FinFET is composed of three fins. Other than this, it has the same layout structure as the inverter cell of FIG. 1(a).
  • power supply wirings 11B and 12B extending in the X direction are provided at both ends in the Y direction.
  • Both the power supply wirings 11B and 12B are embedded power supply wirings (BPR) formed in an embedded wiring layer.
  • the power supply wiring 11B supplies the power supply voltage VDD
  • the power supply wiring 12B supplies the power supply voltage VSS.
  • the center position in the Y direction of the power supply wirings 11B and 12B coincides with the virtual grid line GL.
  • the width of the power supply wirings 11B and 12B, that is, the size in the Y direction is Wb2. Note that Wb2>Wb1.
  • Three fins 21B extending in the X direction are provided in the P-type transistor region on the N-well.
  • Three fins 22B extending in the X direction are provided in the N-type transistor region on the P-type substrate.
  • the gate wiring 31B extends in the Y direction from the P-type transistor area to the N-type transistor area.
  • the gate wiring 31B is formed so as to surround the fins 21B and 22B from three directions.
  • a FinFET P1 is composed of three fins 21B and a gate wiring 31B.
  • a Fin FET N1 is composed of three fins 22B and a gate wiring 31B.
  • a local wiring 41B extending in the Y direction is provided at the left end of the fin 21B in the drawing.
  • the left end of the fin 21B in the drawing is connected to the power supply wiring 11B via the local wiring 41B and the via 51B.
  • a local wiring 42B extending in the Y direction is provided at the left end of the fin 22B in the drawing.
  • the left end of the fin 22B in the drawing is connected to the power supply wiring 12B via the local wiring 42B and the via 52B.
  • a local wiring 43B extending in the Y direction is provided at the right end of the fins 21B and 22B in the drawing. The ends of the fins 21B and 22B on the right side of the drawing are connected to each other by a local wiring 43B.
  • the metal wiring 61B to which the input A is applied is connected to the gate wiring 31B through vias.
  • the metal wiring 62B for outputting the output Y is connected to the local wiring 43B via vias.
  • the layout structure of the 2-input NAND cell shown in FIG. 3 will be described. Note that the description of the configuration that can be inferred from the layout structure of the inverter cells shown in FIGS. 1 and 2 may be omitted.
  • power supply wirings 13A and 14A extending in the X direction are provided at both ends in the Y direction.
  • Both the power supply wirings 13A and 14A are embedded power supply wirings (BPR) formed in an embedded wiring layer.
  • the power supply wiring 13A supplies the power supply voltage VDD
  • the power supply wiring 14A supplies the power supply voltage VSS.
  • the center positions of the power wirings 13A and 14A in the Y direction match the center between the virtual grid lines GL.
  • the width of the power supply wirings 13A and 14A, that is, the size in the Y direction is Wb1.
  • Two fins 23A extending in the X direction are provided in the P-type transistor region on the N-well.
  • Two fins 24A extending in the X direction are provided in the N-type transistor region on the P-type substrate.
  • Gate wirings 32A and 33A extend in the Y direction from the P-type transistor region to the N-type transistor region.
  • Fin FETs P11 and P12 are configured by two fins 23A and gate wirings 32A and 33A, respectively.
  • Fin FETs N11 and N12 are formed by two fins 24A and gate wirings 32A and 33A, respectively.
  • the FinFET is composed of three fins. Other than this, it has the same layout structure as the 2-input NAND cell of FIG. 3(a).
  • power supply wirings 13B and 14B extending in the X direction are provided at both ends in the Y direction.
  • Both the power supply wirings 13B and 14B are embedded power supply wirings (BPR) formed in an embedded wiring layer.
  • the power supply wiring 13B supplies the power supply voltage VDD
  • the power supply wiring 14B supplies the power supply voltage VSS.
  • the power supply wirings 13B and 14B are aligned with the virtual grid line GL at the central position in the Y direction.
  • the width of the power supply wirings 13B and 14B, that is, the size in the Y direction is Wb2. Note that Wb2>Wb1.
  • Three fins 23B extending in the X direction are provided in the P-type transistor region on the N-well.
  • Three fins 24B extending in the X direction are provided in the N-type transistor region on the P-type substrate.
  • Gate wirings 32B and 33B extend in the Y direction from the P-type transistor region to the N-type transistor region.
  • Fin FETs P11 and P12 are configured by three fins 23B and gate wirings 32B and 33B, respectively.
  • Fin FETs N11 and N12 are configured by three fins 24B and gate wirings 32B and 33B, respectively.
  • a cell row is formed by arranging cells in the X direction, and power supply wirings 11A, 13A, etc. for supplying the power supply voltage VDD are connected, and power supply wirings 12A, 14A, etc. for supplying the power supply voltage VSS are connected. concatenated.
  • the cell rows are arranged side by side in the Y direction. Each cell column is arranged alternately in the Y direction. As a result, cell columns adjacent in the Y direction share the power wiring.
  • a cell row is formed by arranging cells in the X direction, and power supply wirings 11B, 13B, etc. for supplying the power supply voltage VDD are connected, and power supply wirings 12B, 14B, etc. for supplying the power supply voltage VSS are connected. concatenated.
  • the cell rows are arranged side by side in the Y direction. Each cell column is arranged alternately in the Y direction. As a result, cell columns adjacent in the Y direction share the power wiring.
  • FIG. 5 is a configuration example of a circuit block of the semiconductor integrated circuit device according to this embodiment.
  • block A is composed of cells with a cell height of Pg ⁇ 8
  • block B is composed of cells with a cell height of Pg ⁇ 11.
  • Blocks A and B are both composed of three columns of cells, and virtual grid lines GL are common to blocks A and B.
  • cell C1A is the inverter cell of FIG. 1(a), and cell C2A is the two-input NAND cell of FIG. 3(a).
  • Cells C2A, C2A, and C1A are arranged from the left in the drawing in the first column, cells C1A, C1A, C1A, and C1A are arranged in the second column from the left in the drawing, and cells C2A, C1A, and C1A are arranged in the third column from the left in the drawing.
  • C1A and C2A are arranged.
  • the power supply wiring 1A supplies the power supply voltage VDD, and is formed by connecting the power supply wiring 11A of the cell C1A and the power supply wiring 13A of the cell C2A.
  • the power supply wiring 2A supplies the power supply voltage VSS, and is formed by connecting the power supply wiring 12A of the cell C1A and the power supply wiring 14A of the cell C2A.
  • cell C1B is the inverter cell of FIG. 1(b), and cell C2B is the two-input NAND cell of FIG. 3(b).
  • Cells C2B, C2B, and C1B are arranged from the left side of the drawing in the first column
  • cells C1B, C1B, C1B, and C1B are arranged from the left side of the drawing in the second column
  • cells C2B, C1B, and C1B are arranged from the left side of the drawing in the third column.
  • C1B and C2B are arranged.
  • the power supply wiring 1B supplies the power supply voltage VDD, and is formed by connecting the power supply wiring 11B of the cell C1B and the power supply wiring 13B of the cell C2B.
  • the power supply wiring 2B supplies the power supply voltage VSS, and is connected to the power supply wiring 12B of the cell C1B and the power supply wiring 14B of the cell C2B.
  • the distance between the nearest fin centers is 3 ⁇ Pg.
  • the center positions of the power supply wirings 1A and 2A are located in the center between the virtual grid lines GL. Therefore, the width Wb1 of the power supply wirings 1A and 2A can be maximized.
  • the distance between the nearest fin centers is 4 ⁇ Pg.
  • the central positions of the power supply wirings 1B and 2B are on the virtual grid line GL. Therefore, the width Wb2 of the power supply wirings 1B and 2B can be maximized.
  • the cells that make up the block B have a larger number of fins that make up the FinFET than the cells that make up the block A. Therefore, the cells forming block B operate at a higher speed than the cells forming block A, but consume more power.
  • the power supply wirings 1B and 2B are wider than the power supply wirings 1A and 2A, so that a sufficient current can be supplied to the cells forming the block B.
  • the vias 51B and 52B for the power supply wirings 11B and 12B in the inverter cell of FIG. 1B are larger in size than the vias 51A and 52A for the power supply wirings 11A and 12A in the inverter cell of FIG. , the resistance is small. Therefore, the inverter cell of FIG. 1B can realize a higher current supply capability.
  • the number of vias may be increased instead of increasing the via size. For example, in the inverter cell of FIG. 1B, two vias may be provided for each of the power wirings 11B and 12B.
  • the blocks A and B share the virtual grid line GL for arranging the fins, and the cells are arranged such that the fins included in the blocks A and B are arranged on the virtual grid line GL, respectively. are placed.
  • the fins are arranged regularly throughout the layout. Therefore, the ease of manufacture of the semiconductor integrated circuit device is improved, manufacturing variations can be suppressed, and the yield can be improved.
  • the plurality of fins forming the FinFET extend in the X direction and are arranged on the virtual grid lines GL equidistantly spaced in the Y direction.
  • the standard cells have an embedded power supply wiring, and the standard cell having a larger size in the Y direction has an embedded power supply wiring having a larger size in the Y direction. This makes it possible to obtain a sufficient current supply capability for the FinFET.
  • the center position in the Y direction of the embedded power wiring provided in the standard cell is on the virtual grid line GL or at the center position between the adjacent virtual grid lines GL. As a result, it is possible to arrange the embedded power supply wiring having a sufficient wiring width without interfering with the regular arrangement of the FinFETs.
  • FIG. 6 is a partially enlarged view of the rightmost cell C1A in the upper two columns in block A in FIG.
  • FIG. 6 shows a layout structure in which the inverter cells of FIG. 1(a) are arranged adjacent to each other in the Y direction.
  • a via 53 larger than the via 52A is arranged at a location (indicated by a broken line) where the via 52A of the inverter cell in FIG. 1A is arranged adjacently.
  • FIG. 7 shows another layout structure of an inverter cell.
  • the number of fins constituting the FinFET is 4, and the cell height is Pg ⁇ 14.
  • the cell height is Pg ⁇ 14.
  • it has the same layout structure as the inverter cell of FIG.
  • power supply wirings 11C and 12C extending in the X direction are provided at both ends in the Y direction.
  • Both the power supply wirings 11C and 12C are embedded power supply wirings (BPR) formed in an embedded wiring layer.
  • the power supply wiring 11C supplies the power supply voltage VDD
  • the power supply wiring 12C supplies the power supply voltage VSS.
  • the center positions of the power supply wirings 11C and 12C in the Y direction match the center between the virtual grid lines GL.
  • the width of the power supply wirings 11C and 12C, that is, the size in the Y direction is Wb3. Note that Wb3>Wb2.
  • the gate wiring 31C extends in the Y direction from the P-type transistor area to the N-type transistor area.
  • the gate wiring 31C is formed so as to surround the fins 21C and 22C from three directions.
  • a Fin FET P1 is composed of the four fins 21C and the gate wiring 31C.
  • a fin FET N1 is composed of the four fins 22C and the gate wiring 31C.
  • a local wiring 41C extending in the Y direction is provided at the left end of the fin 21C in the drawing.
  • the left end of the fin 21C in the drawing is connected to the power supply wiring 11C via the local wiring 41C and the via 51C.
  • a local wiring 42C extending in the Y direction is provided at the left end of the fin 22C in the drawing.
  • the left end of the fin 22C in the drawing is connected to the power supply wiring 12C via the local wiring 42C and the via 52C.
  • a local wiring 43C extending in the Y direction is provided at the right end of the fins 21C and 22C in the drawing. The ends of the fins 21C and 22C on the right side of the drawing are connected to each other by a local wiring 43C.
  • the metal wiring 61C to which the input A is applied is connected to the gate wiring 31C via vias.
  • the metal wiring 62C for outputting the output Y is connected to the local wiring 43C via vias.
  • This circuit block may be arranged, for example, along with blocks A and B shown in FIG. 5, along a common virtual grid line GL.
  • width Wb3 of the power supply wirings 11C and 12C is as follows.
  • Wb3 5 ⁇ Pg ⁇ 2 ⁇ Sb ⁇ Wf That is, Wb3 is larger than Wb2 by Pg.
  • the vias 51C and 52B for the power supply wirings 11C and 12C are larger in size than the vias 51B and 52B for the power supply wirings 11B and 12B in the inverter cell of FIG. 1(b). Therefore, the inverter cell of FIG. 7 can realize a higher current supply capability.
  • the number of vias may be increased instead of increasing the via size. For example, in the inverter cell of FIG. 1B, if two vias are provided for each of the power wirings 11B and 12B, three vias are provided for each of the power wirings 11C and 12C in the inverter cell of FIG. vias may be provided.
  • the semiconductor integrated circuit device has been described as having standard cells having FinFETs, but the transistors that the standard cells have are not limited to FinFETs.
  • the present disclosure can also be applied to semiconductor integrated circuit devices having standard cells with nanosheet FETs.
  • embedded power supply wiring having a sufficient wiring width is arranged without interfering with the regular arrangement of FinFETs. Useful for improving performance.

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/JP2022/002398 2021-02-15 2022-01-24 半導体集積回路装置 Ceased WO2022172737A1 (ja)

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US18/447,032 US20230411246A1 (en) 2021-02-15 2023-08-09 Semiconductor integrated circuit device

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WO2024176933A1 (ja) * 2023-02-20 2024-08-29 株式会社ソシオネクスト 半導体集積回路装置
WO2024241869A1 (ja) * 2023-05-24 2024-11-28 株式会社ソシオネクスト 半導体集積回路装置

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
WO2021075540A1 (ja) * 2019-10-18 2021-04-22 株式会社ソシオネクスト 半導体集積回路装置

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JPH04129247A (ja) * 1990-09-20 1992-04-30 Fujitsu Ltd 半導体装置
JP2007242846A (ja) * 2006-03-08 2007-09-20 Matsushita Electric Ind Co Ltd 半導体集積回路装置および半導体集積回路装置の電源配線方法
JP2008300765A (ja) * 2007-06-04 2008-12-11 Toshiba Microelectronics Corp 半導体集積回路装置
JP2010141187A (ja) * 2008-12-12 2010-06-24 Renesas Technology Corp 半導体集積回路装置
JP2013105341A (ja) * 2011-11-14 2013-05-30 Renesas Electronics Corp 半導体集積回路、半導体集積回路の設計方法及び設計装置並びにプログラム
US20180076189A1 (en) * 2016-09-15 2018-03-15 Qualcomm Incorporated Minimum track standard cell circuits for reduced area
WO2020137746A1 (ja) * 2018-12-26 2020-07-02 株式会社ソシオネクスト 半導体集積回路装置

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JPH04129247A (ja) * 1990-09-20 1992-04-30 Fujitsu Ltd 半導体装置
JP2007242846A (ja) * 2006-03-08 2007-09-20 Matsushita Electric Ind Co Ltd 半導体集積回路装置および半導体集積回路装置の電源配線方法
JP2008300765A (ja) * 2007-06-04 2008-12-11 Toshiba Microelectronics Corp 半導体集積回路装置
JP2010141187A (ja) * 2008-12-12 2010-06-24 Renesas Technology Corp 半導体集積回路装置
JP2013105341A (ja) * 2011-11-14 2013-05-30 Renesas Electronics Corp 半導体集積回路、半導体集積回路の設計方法及び設計装置並びにプログラム
US20180076189A1 (en) * 2016-09-15 2018-03-15 Qualcomm Incorporated Minimum track standard cell circuits for reduced area
WO2020137746A1 (ja) * 2018-12-26 2020-07-02 株式会社ソシオネクスト 半導体集積回路装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024176933A1 (ja) * 2023-02-20 2024-08-29 株式会社ソシオネクスト 半導体集積回路装置
WO2024241869A1 (ja) * 2023-05-24 2024-11-28 株式会社ソシオネクスト 半導体集積回路装置

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