WO2022166147A1 - 一种形成超浅结的方法 - Google Patents

一种形成超浅结的方法 Download PDF

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Publication number
WO2022166147A1
WO2022166147A1 PCT/CN2021/111834 CN2021111834W WO2022166147A1 WO 2022166147 A1 WO2022166147 A1 WO 2022166147A1 CN 2021111834 W CN2021111834 W CN 2021111834W WO 2022166147 A1 WO2022166147 A1 WO 2022166147A1
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Prior art keywords
semiconductor substrate
epitaxial layer
dopant
ion implantation
dose
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English (en)
French (fr)
Inventor
杨健
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/454,246 priority Critical patent/US12165876B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures

Definitions

  • the present disclosure generally relates to the field of semiconductor technology, and in particular, to a method of forming an ultra-shallow junction.
  • the critical dimension of the semiconductor device is getting smaller and smaller, and the thickness of the semiconductor device is also getting smaller and smaller.
  • the ultra-shallow junction implantation process emerges as the times require.
  • the method in the related art is relatively easy to achieve high-energy and high-dose implantation, but it is more difficult to obtain low-energy and low-dose implantation effects.
  • Embodiments of the present disclosure provide a method for forming an ultra-shallow junction, which adopts high-energy and high-dose implantation, and can also achieve low-energy and low-dose implantation effects.
  • the epitaxial layer is removed to form an ultra-shallow junction in the semiconductor substrate.
  • a photoresist layer with mask openings is formed on the epitaxial layer, a part of the epitaxial layer is covered by the photoresist layer, and another part of the epitaxial layer is located under the mask opening of the photoresist layer and is located in the epitaxial layer and part of the semiconductor substrate below the mask opening form an implantation region;
  • the epitaxial layer is removed to form an ultra-shallow junction in the semiconductor substrate.
  • an epitaxial layer is formed on a semiconductor substrate, and after dopants are implanted into the epitaxial layer and part of the semiconductor substrate, the epitaxial layer is removed, and the implantation into the semiconductor substrate is controlled.
  • the dose of the dopant can be achieved by high energy and high dose implantation to obtain the implantation effect of low energy and low dose, which solves the problem that it is difficult to obtain the implantation effect of low energy and low dose in the related art.
  • FIG. 1 is a flowchart of a method for forming an ultra-shallow junction according to an embodiment of the present disclosure.
  • 2 to 5 are cross-sectional views of different process stages of a method for forming an ultra-shallow junction according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a method for forming an ultra-shallow junction according to another embodiment of the present disclosure.
  • 7 to 13 are cross-sectional views of different process stages of a method for forming an ultra-shallow junction according to another embodiment of the present disclosure.
  • FIG. 14 shows a schematic diagram of a semiconductor device transistor according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the channel size of semiconductor devices is constantly shrinking, and while the lateral size of the channel is shrinking, the thickness of the entire device is also constantly developing to shallow layers. Due to device scaling, the formation of ultra-shallow junction implants is essential.
  • the current ion implantation technology uses the accelerated ions generated by the electric field to obtain the required energy. For high-energy and high-dose ion beams, even if the beam is attenuated during the transmission process, the entire implantation can still be achieved to ensure sufficient energy. Injection uniformity.
  • ultra-shallow junction implantation requires ultra-low energy (200eV-3000eV), and it is difficult to achieve uniform implantation due to the limitation of process conditions in the related art.
  • an embodiment of the present disclosure provides a method for forming an ultra-shallow junction. By improving the process, high-energy and high-dose implantation can also be used to achieve low-energy and low-dose implantation effects.
  • FIGS. 1 to 5 show a flowchart of a method for forming an ultra-shallow junction according to an embodiment of the present disclosure.
  • 2 to 5 are cross-sectional views of different process stages of a method for forming an ultra-shallow junction according to an embodiment of the present disclosure.
  • a method for forming an ultra-shallow junction includes the following steps: providing a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; providing dopants, the epitaxial layer and part of the semiconductor substrate Dopants are implanted into the semiconductor substrate; epitaxial layers are removed to form ultra-shallow junctions in the semiconductor substrate.
  • step S101 a semiconductor substrate 100 is provided.
  • the semiconductor substrate 100 may include a semiconductor material such as base silicon or single crystal silicon. In other or additional embodiments, another semiconductor element, such as germanium of a crystalline structure, may be included in the semiconductor substrate 100 .
  • the semiconductor substrate 100 may also include semiconductor compounds such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof.
  • the semiconductor substrate 100 may also include a semiconductor-on-insulator substrate such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate.
  • the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer.
  • the semiconductor substrate 100 includes silicon or other elemental semiconductor materials, such as germanium.
  • the semiconductor substrate 100 may be doped (eg, P-type, N-type, or a combination of the foregoing) or undoped.
  • the semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer.
  • the epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination of the foregoing.
  • the semiconductor substrate 100 includes a compound semiconductor.
  • compound semiconductors include one or more III-V compound semiconductors having a composition defined by the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 , where X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. They are each greater than or equal to 0, and collectively add up to 1.
  • the compound semiconductor may comprise silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination of the foregoing.
  • Other suitable substrates comprising II-VI compound semiconductors may also be used.
  • the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate.
  • SOI semiconductor-on-insulator
  • Semiconductor-on-insulator substrates may be fabricated using separation by implantation of oxygen (SIMOX) processes, wafer bonding processes, other suitable processes, or a combination of the foregoing.
  • the semiconductor substrate 100 includes a multilayer structure.
  • the semiconductor substrate 100 includes a silicon germanium layer formed on a bulk silicon layer.
  • step S102 an epitaxial layer 110 is formed on the semiconductor substrate 100 .
  • the silicon oxide layer on the original semiconductor substrate 100 is generally first removed by hydrofluoric acid (HF) etching.
  • HF hydrofluoric acid
  • the thickness of the epitaxial layer 110 formed on the semiconductor substrate 100 can be adjusted according to the junction depth of the ultra-shallow junction 130 to be formed in the semiconductor substrate 100 subsequently. For example, when a thinner junction depth needs to be formed in the semiconductor substrate 100 , a thicker epitaxial layer 110 may be grown on the semiconductor substrate 100 . When a thicker junction depth needs to be formed in the semiconductor substrate 100 , a thinner epitaxial layer 110 may be grown on the semiconductor substrate 100 .
  • the materials of the epitaxial layer 110 and the semiconductor substrate 100 are the same, for example, the materials of the epitaxial layer 110 and the semiconductor substrate 100 are both silicon. Since the epitaxially grown silicon has a good match with the silicon of the semiconductor substrate 100 , the silicon of the epitaxial layer 110 and the silicon of the semiconductor substrate 100 have the same crystal, and there are fewer impurities. In the subsequent process of implanting dopants , will not affect the injection effect.
  • the silicon of the epitaxial layer 110 and the silicon of the semiconductor substrate 100 are not in the same crystal phase, and the dopant ions will be absorbed by the surface layer of the epitaxial layer 110 during the implantation process.
  • the confinement of vacancies in the membrane eventually causes contamination of the angle of implantation.
  • step S103 the dopant 130 is provided, and the dopant 130 is implanted into the epitaxial layer 110 and part of the semiconductor substrate 100 , and the dopant 130 is located in the epitaxial layer 110 and part of the semiconductor substrate 100 middle.
  • dopants 130 may include, but are not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • the dopant 130 may be implanted by using an ion implantation process.
  • the energy of the ion implantation process is greater than 2keV, and the dose of the ion implantation process is greater than or equal to 1E13 cm ⁇ 2 .
  • the energy of the ion implantation process can be greater than 5keV, 8keV, 10keV, 12keV, 14keV, 16keV, 18keV or 20keV, etc., and the dose of the ion implantation process can be greater than 2E13cm -2 , 5E13cm -2 , 8E13cm -2 , 1E14cm -2 , 1E15cm -2 , 5E15cm -2 or 8E15cm -2 etc.
  • the dose of the dopant 130 implanted in part of the semiconductor substrate 100 is less than 1E13cm ⁇ 2 , such as 9E10cm ⁇ 2 , 1E11cm ⁇ 2 , 1E12cm ⁇ 2 , 2E12cm ⁇ 2 or 5E12cm ⁇ 2 .
  • the method for forming an ultra-shallow junction can achieve low energy (eg, 300 eV) and low dose (eg, 2E12 cm) by using high-energy (eg, 10 keV) and high-dose (eg, 2E13 cm ⁇ 2 ) implantation conditions -2 ) injection effect.
  • low energy eg, 300 eV
  • low dose eg, 2E12 cm
  • high-energy eg, 10 keV
  • high-dose eg, 2E13 cm ⁇ 2
  • step S104 the epitaxial layer 110 is removed to form an ultra-shallow junction 120 in a portion of the semiconductor substrate 100 .
  • the removal of the epitaxial layer 110 can be performed by dry or wet etching, or by chemical mechanical polishing, grinding, dry grinding, wet cleaning, or one or more other suitable processes. or a combination of the foregoing.
  • a heat treatment step is also included, and the heat treatment includes but is not limited to low temperature thermal annealing, rapid thermal annealing, flash annealing, spike annealing or laser annealing.
  • the semiconductor device transistor shown in FIG. 14 includes a semiconductor substrate 100, a gate oxide layer 101 formed on the semiconductor substrate, a gate structure 102 formed on the gate oxide layer 101, a gate oxide layer 101 and a gate oxide layer 102 formed on the gate oxide layer 101.
  • the A region in FIG. 14 is the implantation region of the lightly doped structure, which is used to increase the threshold voltage of the device and effectively control the short channel effect of the device
  • the B region is the threshold voltage ion implantation region, which is used to adjust the threshold voltage.
  • FIGS. 6 to 13 show a flowchart of a method for forming an ultra-shallow junction according to another embodiment of the present disclosure
  • FIGS. 7 to 13 show different processes of the method for forming an ultra-shallow junction according to another embodiment of the present disclosure. Cutaway view of stages.
  • a method for forming an ultra-shallow junction includes the following steps: providing a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; forming a photoresist with mask openings on the epitaxial layer A part of the epitaxial layer is covered by the photoresist layer, and the other part of the epitaxial layer is located under the mask opening of the photoresist layer, and the epitaxial layer and part of the semiconductor substrate under the mask opening form an implantation region; implanting the first dopant into the implantation region so that the first dopant is implanted into the epitaxial layer under the mask opening and part of the semiconductor substrate; removing the photoresist layer; providing the second dopant, and implanting the second dopant into the epitaxial layer dopants to improve the etch selectivity of the epitaxial layer; removal of the epitaxial layer to form ultra-shallow junctions in the semiconductor substrate.
  • step S201 a semiconductor substrate 200 is provided.
  • the semiconductor substrate 200 may comprise a semiconductor material such as base silicon or single crystal silicon. In other or additional embodiments, another semiconductor element, such as germanium of a crystalline structure, may be included in the semiconductor substrate 200 .
  • the semiconductor substrate 200 may also include semiconductor compounds such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof.
  • the semiconductor substrate 200 may also include a semiconductor-on-insulator substrate 200 such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate.
  • the semiconductor substrate 200 is a bulk semiconductor substrate, such as a semiconductor wafer.
  • the semiconductor substrate 200 includes silicon or other elemental semiconductor materials, such as germanium.
  • the semiconductor substrate 200 may be doped (eg, P-type, N-type, or a combination of the foregoing) or undoped.
  • the semiconductor substrate 200 includes an epitaxially grown semiconductor layer on a dielectric layer.
  • the epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination of the foregoing.
  • the semiconductor substrate 200 includes a compound semiconductor.
  • compound semiconductors include one or more III-V compound semiconductors having a composition defined by the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 , where X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. They are each greater than or equal to 0, and collectively add up to 1.
  • the compound semiconductor may comprise silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination of the foregoing.
  • Other suitable substrates comprising II-VI compound semiconductors may also be used.
  • the semiconductor substrate 200 is an active layer of a semiconductor-on-insulator (SOI) substrate.
  • SOI semiconductor-on-insulator
  • the semiconductor-on-insulator substrate 200 may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other suitable processes, or a combination of the foregoing.
  • the semiconductor substrate 200 includes a multilayer structure.
  • the semiconductor substrate 200 includes a silicon germanium layer formed on a bulk silicon layer.
  • step S202 an epitaxial layer 210 is formed on the semiconductor substrate 200 .
  • the silicon oxide layer on the original semiconductor substrate 200 is generally first removed by hydrofluoric acid (HF) etching.
  • HF hydrofluoric acid
  • the thickness of the epitaxial layer 210 formed on the semiconductor substrate 200 can be adjusted according to the junction depth of the ultra-shallow junction 230 to be formed in the semiconductor substrate 200 subsequently. For example, when a thinner junction depth needs to be formed in the semiconductor substrate 200 , a thicker epitaxial layer 210 may be grown on the semiconductor substrate 200 . A thinner epitaxial layer 210 may be grown on the semiconductor substrate 200 when a thicker junction depth needs to be formed in the semiconductor substrate 200 .
  • the materials of the epitaxial layer 210 and the semiconductor substrate 200 are the same, for example, the materials of the epitaxial layer 210 and the semiconductor substrate 200 are both silicon. Since the epitaxially grown silicon has a good match with the silicon of the semiconductor substrate 200 , the silicon of the epitaxial layer 210 is consistent with the silicon of the semiconductor substrate 200 , and has less impurities. In the subsequent process of implanting dopants , will not affect the injection effect.
  • the silicon of the epitaxial layer 110 and the silicon of the semiconductor substrate 100 are not in the same crystal phase, and the dopant ions will be absorbed by the surface layer of the epitaxial layer 210 during the implantation process.
  • the confinement of vacancies in the membrane eventually causes contamination of the angle of implantation.
  • a photoresist layer 220 having mask openings 221 is formed on the epitaxial layer 210 , a part of the epitaxial layer 210 is covered by the photoresist layer 220 , and the other part of the epitaxial layer 210 is located in the photoresist layer Under the mask opening 221 of 220 , the epitaxial layer 210 and part of the semiconductor substrate 200 located under the mask opening 221 form an implantation region 222 (the region marked by the dotted line in FIG. 9 ).
  • step S204 the first dopant 240 is provided, and the first dopant 240 is implanted into the implantation region 222 , so that the first dopant 240 is implanted into the mask located in the photoresist layer 220 .
  • the first dopant 240 may include, but is not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • the first dopant 240 is implanted into the region of the epitaxial layer 210 located under the mask opening 221 of the photoresist layer 220 that is not covered by the photoresist layer 220 and into part of the semiconductor substrate 200 , and ion implantation may be used.
  • the process implants the first dopant 240 .
  • the energy of the ion implantation process is greater than 2keV, and the dose of the ion implantation process is greater than or equal to 1E13 cm ⁇ 2 .
  • the energy of the ion implantation process can be greater than 5keV, 8keV, 10keV, 12keV, 14keV, 16keV, 18keV or 20keV, etc., and the dose of the ion implantation process can be greater than 2E13cm -2 , 5E13cm -2 , 8E13cm -2 , 1E14cm -2 , 1E15cm -2 , 5E15cm -2 or 8E15cm -2 etc.
  • the dose of dopant 130 implanted in part of the semiconductor substrate 200100 is less than 1E13cm -2 , such as 9E10cm -2 , 1E11cm -2 , 1E12cm -2 , 2E12cm -2 or 5E12cm -2 , etc.
  • the method for forming an ultra-shallow junction can realize low energy (eg, 300 eV) and low dose (eg, 2E12 cm ⁇ 2 ) by using implantation conditions of high energy (eg, 10 keV) and dose (eg, 2E13 cm ⁇ 2 ) . 2 ) The injection effect.
  • low energy eg, 300 eV
  • low dose eg, 2E12 cm ⁇ 2
  • high energy eg, 10 keV
  • dose eg, 2E13 cm ⁇ 2
  • step S205 the photoresist layer 220 is removed.
  • the photoresist layer 220 may be removed by dry or wet etching, and may also be removed by, for example, chemical mechanical polishing, grinding, dry polishing, wet cleaning, or one or more other suitable processes. process or a combination of the foregoing.
  • step S206 a second dopant 250 is provided, and the second dopant 250 is implanted into the epitaxial layer 210 to improve the etching selectivity ratio of the epitaxial layer 210 .
  • the second dopant 250 may be germanium or silicon.
  • the step of implanting the second dopant 250 into the epitaxial layer 210 may use an ion implantation process.
  • the implantation depth of the second dopant 250 does not exceed the thickness of the epitaxial layer 210 .
  • the second dopant 250 destroys the crystal lattice in the epitaxial layer 210 , so that the structure of the epitaxial layer 210 implanted with the second dopant 250 is transformed into an amorphous structure, and the etching selectivity ratio thereof is obviously improved, which facilitates the subsequent removal of the epitaxial layer 210 by an etching process.
  • step S207 the epitaxial layer 210 is removed to form an ultra-shallow junction 230 in the semiconductor substrate 200 .
  • dry or wet etching is used to remove the epitaxial layer 210, and for example, a chemical mechanical polishing process, a grinding process, a dry grinding process, a wet cleaning process, one or more other suitable processes, or combination of the foregoing.
  • a heat treatment step is included, and the heat treatment includes but is not limited to low temperature thermal annealing, rapid thermal annealing, instantaneous annealing, spike annealing or laser annealing.
  • the semiconductor device transistor shown in FIG. 14 includes a semiconductor substrate 100, a gate oxide layer 101 formed on the semiconductor substrate, a gate structure 102 formed on the gate oxide layer 101, a gate oxide layer 101 and a gate oxide layer 102 formed on the gate oxide layer 101.
  • the A region in FIG. 14 is the implantation region of the lightly doped structure, which is used to increase the threshold voltage of the device and effectively control the short channel effect of the device
  • the B region is the threshold voltage ion implantation region, which is used to adjust the threshold voltage.
  • an epitaxial layer is first formed on a semiconductor substrate, and dopants are implanted into the epitaxial layer and part of the semiconductor substrate, and then the epitaxial layer is removed to control the implantation into the semiconductor substrate.
  • the high-energy and high-dose implantation process is realized to obtain the low-energy and low-dose implantation effect, which solves the problem that it is difficult to obtain the low-energy and low-dose implantation effect in the related art.
  • the terms “first” and “second” are used for descriptive purposes only, and should not be construed as indicating or implying relative importance; the term “plurality” refers to two or more, unless otherwise There are clear limits.
  • the terms “installed”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense. For example, “connected” can be a fixed connection, a detachable connection, or an integral connection; “connected” can be It is directly connected or indirectly connected through an intermediary.
  • the specific meanings of the above terms in the disclosed embodiments can be understood according to specific situations.
  • description of the terms “one embodiment,” “some embodiments,” “a specific embodiment,” etc. means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in the disclosed implementation. at least one embodiment or example of an example.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or instance.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

一种形成超浅结的方法，包括如下步骤：提供半导体衬底（100），在半导体衬底（100）上形成外延层（110），提供掺杂物（130），向外延层（110）和部分半导体衬底（100）中注入掺杂物（130），去除外延层（110），以在半导体衬底（100）中形成超浅结（120）。该形成超浅结的方法能够实现高能量和高剂量注入而获得低能量和低剂量的注入效果，解决了相关技术中存在的获得低能量和低剂量的注入效果比较困难的问题。

Description

一种形成超浅结的方法
交叉引用
本公开要求于2021年02月07日提交的申请号为202110168061.9、名称为“一种形成超浅结的方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开总体来说涉及半导体技术领域，具体而言，涉及一种形成超浅结的方法。
背景技术
随着技术的发展，半导体器件的关键尺寸越来越小，随之半导体器件的厚度也越来越小。由于半导体器件的厚度变小，超浅结注入工艺应运而生。然而，相关技术中的方法比较容易实现高能量和高剂量的注入，而要想获得低能量和低剂量的注入效果是比较困难的。
公开内容
本公开实施例提供一种形成超浅结的方法，采用高能量高剂量注入，也可实现低能量和低剂量的注入效果。
本公开实施例的形成超浅结的方法，所述方法包括以下步骤：
提供半导体衬底；
在所述半导体衬底上形成外延层；
提供掺杂物，向所述外延层和部分所述半导体衬底中注入所述掺杂物；
去除所述外延层，以在所述半导体衬底中形成超浅结。
本公开实施例的形成超浅结的方法，所述方法包括以下步骤：
提供半导体衬底；
在所述半导体衬底上形成外延层；
在所述外延层上形成具有掩膜开口的光阻层，一部分所述外延层被所述光阻层覆盖，另一部分所述外延层位于所述光阻层的所述掩膜开口下方，位于所述掩膜开口下方的所述外延层和部分所述半导体衬底形成注入区域；
提供第一掺杂物，向所述注入区域注入第一掺杂物，以使所述第一掺杂物注入位于所述掩膜开口下方的所述外延层以及所述部分所述半导体衬底中；
去除所述光阻层；
去除所述外延层，以在所述半导体衬底中形成超浅结。
上述公开中的一个实施例具有如下优点或有益效果：
本公开实施例形成超浅结的方法，通过在半导体衬底上形成一外延层，采用在外延层和部分半导体衬底中注入掺杂物后，去除外延层的方式，控制注入半导体衬底中的掺杂物的剂量，实现高能量和高剂量注入而获得低能量和低剂量的注入效果，解决了相关技术中存在的获得低能量和低剂量的注入效果比较困难的问题。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1示出的是本公开一实施例的形成超浅结的方法的流程图。
图2至图5示出的是本公开一实施例的形成超浅结的方法的不同工艺阶段的剖视图。
图6示出的是本公开另一实施例的形成超浅结的方法的流程图。
图7至图13示出的是本公开另一实施例的形成超浅结的方法的不同工艺阶段的剖视图。
图14示出的是本公开实施例的半导体器件晶体管的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
半导体器件的沟道尺寸不断的缩小，在沟道横向尺寸缩小的同时，整个器件的厚度也在不断的往浅层发展。由于器件的微缩，形成超浅结注入是必不可少的。现行的离子注入技术采用的是使产生的离子通过电场加速获得所需要的能量，对于高能量高剂量的离子束流，传输过程即使有束流的衰减，但还是可以实现整个注入，保证足够的注入均匀度。而超浅结注入需要超低能量(200eV-3000eV)，受相关技术中的工艺条件的限制，很难实现 均匀的注入。例如，对于源极/漏极的形成，由于需要的剂量较大(5E14cm -2-8E15cm -2)，相关技术中的方案中，可以实现这种低能量高剂量的注入。然而，对于沟道注入或是轻掺杂漏(light dopant drain，LDD)注入，这种低能量低剂量(9E10cm -2-5E12cm -2)的注入效果，相关技术中的工艺是较难实现的。
基于此，本公开实施例提供一种形成超浅结的方法，通过改进工艺，采用高能量和高剂量的注入，也可实现低能量和低剂量的注入效果。
下面结合图1至图5，详细说明本公开一实施例的形成超浅结的方法。其中，图1示出的是本公开一实施例的形成超浅结的方法的流程图。图2至图5示出的是本公开一实施例的形成超浅结的方法的不同工艺阶段的剖视图。
如图1所示，本公开一实施例的形成超浅结的方法，包括如下步骤：提供半导体衬底；在半导体衬底上形成外延层；提供掺杂物，向外延层和部分半导体衬底中注入掺杂物；去除外延层，以在半导体衬底中形成超浅结。
如图1和图2所示，在步骤S101，提供半导体衬底100。
在一实施方式中，半导体衬底100可以包含半导体材料如基体硅或单晶硅。在其他实施例或额外实施例中，半导体衬底100中可包含另一半导体元素如结晶结构的锗。半导体衬底100亦可包含半导体化合物如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、或上述的组合。半导体衬底100亦可包含绝缘层上半导体衬底如绝缘层上硅基底、绝缘层上硅锗基底、或绝缘层上锗基底。
在一些实施例中，半导体衬底100为块材(bulk)半导体衬底，例如半导体晶片。举例而言，半导体衬底100包含硅或其他元素半导体材料，例如锗。半导体衬底100可经掺杂(例如P型、N型或前述的组合)或不经掺杂。在一些实施例中，半导体衬底100包含介电层上外延生长的半导体层。外延生长的半导体层可由硅锗、硅、锗、一或多个其他合适的材料或前述的组合制成。
在一些其他的实施例中，半导体衬底100包含化合物半导体。举例而言，化合物半导体包含一或多个III-V族化合物半导体，具有由式Al X1Ga X2In X3As Y1P Y2N Y3Sb Y4定义的组成，其中X1、X2、X3、Y1、Y2、Y3和Y4代表相对的比例。它们各自大于或等于0，且整体相加等于1。化合物半导体可包含碳化硅、砷化镓、砷化铟、磷化铟、一或多个其他合适的化合物半导体或前述的组合。也可使用其他包含II-VI族化合物半导体的合适的基底。
在一些实施例中，半导体衬底100为绝缘体上覆半导体(semiconductor-on-insulator，SOI)基底的主动层。绝缘体上覆半导体衬底的制造可使用注入氧隔离(separation by  implantation of oxygen，SIMOX)工艺、晶片接合工艺、其他合适的工艺或前述的组合。在一些其他的实施例中，半导体衬底100包含多层结构。举例而言，半导体衬底100包含形成在块材硅层上的硅锗层。
如图1和图3所示，在步骤S102，在半导体衬底100上形成外延层110。
虽然附图中没有示出，可以理解的是，在半导体衬底100上生长外延层110之前大体上要首先通过氢氟酸(HF)蚀刻去除原有的半导体衬底100上的氧化硅层。
可以理解的是，半导体衬底100上形成的外延层110的厚度可以根据后续在半导体衬底100中所需要形成的超浅结130的结深进行调整。举例来说，当需要在半导体衬底100中形成较薄的结深时，可以在半导体衬底100上生长较厚的外延层110。当需要在半导体衬底100中形成较厚的结深时，可以在半导体衬底100上生长较薄的外延层110。
在一实施方式中，外延层110与半导体衬底100的材料相同，例如外延层110和半导体衬底100的材料均为硅。由于外延生长的硅与半导体衬底100的硅的匹配性较好，外延层110的硅与半导体衬底100的硅的晶相一致，并且杂质较少，在后续的注入掺杂物的工艺中，不会影响注入效果。反之，若外延层110与半导体衬底100的材料的匹配性较差，外延层110的硅与半导体衬底100的硅的晶相不一致，在注入过程中掺杂离子会被外延层110的表层膜中的空位束缚，最终造成注入的角度污染。
如图1和图4所示，在步骤S103，提供掺杂物130，向外延层110和部分半导体衬底100中注入掺杂物130，掺杂物130位于外延层110和部分半导体衬底100中。
在一实施方式中，掺杂物130可以包括但不限于硼、铝、镓、铟、铊、氮、磷、砷、锑和铋。
在一些实施方式中。向外延层110和部分半导体衬底100中注入掺杂物130的步骤，可以采用离子注入工艺注入掺杂物130。在一实施方式中，离子注入工艺的能量为大于2keV，离子注入工艺的剂量为大于或等于1E13cm -2。其中，离子注入工艺的能量可以为大于5keV、8keV、10keV、12keV、14keV、16keV、18keV或20keV等，离子注入工艺的剂量可以为大于2E13cm -2、5E13cm -2、8E13cm -2、1E14cm -2、1E15cm -2、5E15cm -2或8E15cm -2等。
在一实施方式中，部分半导体衬底100中注入的掺杂物130的剂量为小于1E13cm -2，例如9E10cm -2、1E11cm -2、1E12cm -2、2E12cm -2或5E12cm -2等。
本公开实施例的形成超浅结的方法，能够通过采用高能量(例如为10keV)和高剂量(例如为2E13cm -2)的注入条件实现低能量(例如为300eV)和低剂量(例如为2E12cm -2) 的注入效果。
如图1和图5所示，在步骤S104，去除外延层110，以在部分半导体衬底100中形成超浅结120。
在一实施方式中，去除外延层110可以采用干法或湿法刻蚀，也可采用例如化学机械研磨工艺、磨削工艺、干式研磨工艺、湿法清洗、一或多个其他合适的工艺或前述的组合。
虽然附图中并未示出，可以理解的是，去除外延层110之后，还包括热处理步骤，热处理包括但不限于低温热退火、快速热退火、瞬间退火、尖峰退火或激光退火。
可以理解的是，本公开实施例的形成超浅结的方法可以应用在如图14所示的器件的阈值电压离子注入区域或是在源极/漏极附近的轻掺杂结构注入。其中，图14中所示的半导体器件晶体管包括半导体衬底100、形成在半导体衬底上的栅氧化层101、形成在栅氧化层101上的栅极结构102、形成在栅氧化层101和栅极结构102侧壁的隔离侧墙104以及轻掺杂结构103和源漏极结构105。其中，图14中的A区域为轻掺杂结构的注入区域，用于提高器件的阈值电压并有效控制器件的短沟道效应，B区域为阈值电压离子注入区域，用于调整阈值电压。
下面结合图6至图13，详细说明本公开另一实施例的形成超浅结的方法。其中，图6示出的是本公开另一实施例的形成超浅结的方法的流程图，图7至图13示出的是本公开另一实施例的形成超浅结的方法的不同工艺阶段的剖视图。
如图6所示，本公开另一实施例的形成超浅结的方法，包括以下步骤：提供半导体衬底；在半导体衬底上形成外延层；在外延层上形成具有掩膜开口的光阻层，一部分外延层被光阻层覆盖，另一部分外延层位于光阻层的掩膜开口下方，位于掩膜开口下方的外延层和部分半导体衬底形成注入区域；提供第一掺杂物，向注入区域注入第一掺杂物，以使第一掺杂物注入位于掩膜开口下方的外延层以及部分半导体衬底中；去除光阻层；提供第二掺杂物，向外延层注入第二掺杂物，以提高外延层的刻蚀选择比；去除外延层，以在半导体衬底中形成超浅结。
如图6和图7所示，在步骤S201中，提供半导体衬底200。
在一实施方式中，半导体衬底200可以包含半导体材料如基体硅或单晶硅。在其他实施例或额外实施例中，半导体衬底200中可包含另一半导体元素如结晶结构的锗。半导体衬底200亦可包含半导体化合物如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、或上述的组合。半导体衬底200亦可包含绝缘层上半导体衬底200如绝缘层上硅基底、绝缘层上硅锗基底、或绝缘层上锗基底。
在一些实施例中，半导体衬底200为块材(bulk)半导体衬底，例如半导体晶片。举例而言，半导体衬底200包含硅或其他元素半导体材料，例如锗。半导体衬底200可经掺杂(例如P型、N型或前述的组合)或不经掺杂。在一些实施例中，半导体衬底200包含介电层上外延生长的半导体层。外延生长的半导体层可由硅锗、硅、锗、一或多个其他合适的材料或前述的组合制成。
在一些其他的实施例中，半导体衬底200包含化合物半导体。举例而言，化合物半导体包含一或多个III-V族化合物半导体，具有由式Al X1Ga X2In X3As Y1P Y2N Y3Sb Y4定义的组成，其中X1、X2、X3、Y1、Y2、Y3和Y4代表相对的比例。它们各自大于或等于0，且整体相加等于1。化合物半导体可包含碳化硅、砷化镓、砷化铟、磷化铟、一或多个其他合适的化合物半导体或前述的组合。也可使用其他包含II-VI族化合物半导体的合适的基底。
在一些实施例中，半导体衬底200为绝缘体上覆半导体(semiconductor-on-insulator，SOI)基底的主动层。绝缘体上覆半导体衬底200的制造可使用注入氧隔离(separation by implantation of oxygen，SIMOX)工艺、晶片接合工艺、其他合适的工艺或前述的组合。在一些其他的实施例中，半导体衬底200包含多层结构。举例而言，半导体衬底200包含形成在块材硅层上的硅锗层。
如图6和图8所示，在步骤S202，在半导体衬底200上形成外延层210。
虽然附图中没有示出，可以理解的是，在半导体衬底200上生长外延层210之前大体上要首先通过氢氟酸(HF)蚀刻去除原有的半导体衬底200上的氧化硅层。
可以理解的是，半导体衬底200上形成的外延层210的厚度可以根据后续在半导体衬底200中所需要形成的超浅结230的结深进行调整。举例来说，当需要在半导体衬底200中形成较薄的结深时，可以在半导体衬底200上生长较厚的外延层210。当需要在半导体衬底200中形成较厚的结深时，可以在半导体衬底200上生长较薄的外延层210。
在一实施方式中，外延层210与半导体衬底200的材料相同，例如外延层210和半导体衬底200的材料均为硅。由于外延生长的硅与半导体衬底200的硅的匹配性较好，外延层210的硅与半导体衬底200的硅的晶相一致，并且杂质较少，在后续的注入掺杂物的工艺中，不会影响注入效果。反之，若外延层210与半导体衬底200的材料的匹配性较差，外延层110的硅与半导体衬底100的硅的晶相不一致，在注入过程中掺杂离子会被外延层210的表层膜中的空位束缚，最终造成注入的角度污染。
如图6和图9所示，在步骤S203，在外延层210上形成具有掩膜开口221的光阻层220，一部分外延层210被光阻层220覆盖，另一部分外延层210位于光阻层220的掩膜 开口221下方，位于掩膜开口221下方的外延层210和部分半导体衬底200形成注入区域222(如图9中虚线标记的区域)。
如图6和图10所示，在步骤S204，提供第一掺杂物240，向注入区域222中注入第一掺杂物240，以使第一掺杂物240注入位于光阻层220的掩膜开口221下方的外延层210中未被光阻层220覆盖的区域以及部分半导体衬底200中。
在一实施方式中，第一掺杂物240可以包括但不限于硼、铝、镓、铟、铊、氮、磷、砷、锑和铋。
在一些实施方式中，第一掺杂物240注入位于光阻层220的掩膜开口221下方的外延层210中未被光阻层220覆盖的区域以及部分半导体衬底200中，可以采用离子注入工艺注入第一掺杂物240。在一实施方式中，离子注入工艺的能量为大于2keV，离子注入工艺的剂量为大于或等于1E13cm -2。其中，离子注入工艺的能量可以为大于5keV、8keV、10keV、12keV、14keV、16keV、18keV或20keV等，离子注入工艺的剂量可以为大于2E13cm -2、5E13cm -2、8E13cm -2、1E14cm -2、1E15cm -2、5E15cm -2或8E15cm -2等。
在一实施方式中，部分半导体衬底200100中注入的掺杂物130的剂量为小于1E13cm -2，例如9E10cm -2、1E11cm -2、1E12cm -2、2E12cm -2或5E12cm -2等。
本公开实施例的形成超浅结的方法，能够通过采用高能量(例如为10keV)和剂量(例如为2E13cm -2)的注入条件实现低能量(例如为300eV)和低剂量(例如为2E12cm -2)的注入效果。
如图6和图11所示，在步骤S205，去除光阻层220。
在一些实施方式中，去除光阻层220可以采用干法或湿法刻蚀，也可以采用例如化学机械研磨工艺、磨削工艺、干式研磨工艺、湿法清洗、一或多个其他合适的工艺或前述的组合。
如图6和图12所示，在步骤S206，提供第二掺杂物250，向外延层210注入第二掺杂物250，以提高外延层210的刻蚀选择比。
在一实施方式中，第二掺杂物250可以为锗或硅。
在一实施方式中，向外延层210注入第二掺杂物250的步骤，可以采用离子注入工艺。
可以理解的是，第二掺杂物250的注入深度不超过外延层210的厚度，外延层210内注入第二掺杂物250后，第二掺杂物250破坏了外延层210中的晶格，使注入第二掺杂物250的外延层210结构转变为非晶化结构，其刻蚀选择比明显提高，便于后续采取刻蚀工艺去除外延层210。
如图6和图13所示，在步骤S207，去除外延层210，以在半导体衬底200中形成超浅结230。
在一实施方式中，去除外延层210采用干法或湿法刻蚀，也可采用例如化学机械研磨工艺、磨削工艺、干式研磨工艺、湿法清洗、一或多个其他合适的工艺或前述的组合。
虽然附图中并未示出，可以理解的是，去除外延层210之后，还包括热处理步骤，热处理包括但不限于低温热退火、快速热退火、瞬间退火、尖峰退火或激光退火。
可以理解的是，本公开实施例的形成超浅结的方法可以应用在如图14所示的器件的阈值电压离子注入区域或是在源极/漏极附近的轻掺杂结构注入。其中，图14中所示的半导体器件晶体管包括半导体衬底100、形成在半导体衬底上的栅氧化层101、形成在栅氧化层101上的栅极结构102、形成在栅氧化层101和栅极结构102侧壁的隔离侧墙104以及轻掺杂结构103和源漏极结构105。其中，图14中的A区域为轻掺杂结构的注入区域，用于提高器件的阈值电压并有效控制器件的短沟道效应，B区域为阈值电压离子注入区域，用于调整阈值电压。
综上所述，本公开实施例的形成超浅结的方法的优点和有益效果在于：
本公开实施例形成超浅结的方法，通过先在半导体衬底上形成一外延层，采用在外延层和部分半导体衬底中注入掺杂物后，去除外延层的方式，控制注入半导体衬底中的掺杂物的剂量，实现高能量和高剂量注入工艺而获得低能量和低剂量的注入效果，解决了相关技术中存在的获得低能量和低剂量的注入效果比较困难的问题。
在公开实施例中，术语“第一”、“第二”仅用于描述的目的，而不能理解为指示或暗示相对重要性；术语“多个”则指两个或两个以上，除非另有明确的限定。术语“安装”、“相连”、“连接”、“固定”等术语均应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或一体地连接；“相连”可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在公开实施例中的具体含义。
公开实施例的描述中，需要理解的是，术语“上”、“下”、“左”、“右”、“前”、“后”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述公开实施例和简化描述，而不是指示或暗示所指的装置或单元必须具有特定的方向、以特定的方位构造和操作，因此，不能理解为对公开实施例的限制。
在本说明书的描述中，术语“一个实施例”、“一些实施例”、“具体实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或特点包含于公开实施例的至 少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或实例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上仅为公开实施例的优选实施例而已，并不用于限制公开实施例，对于本领域的技术人员来说，公开实施例可以有各种更改和变化。凡在公开实施例的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在公开实施例的保护范围之内。

Claims (20)

  1. 一种形成超浅结的方法，所述方法包括以下步骤：
    提供半导体衬底；
    在所述半导体衬底上形成外延层；
    提供掺杂物，向所述外延层和部分所述半导体衬底中注入所述掺杂物；
    去除所述外延层，以在所述半导体衬底中形成超浅结。
  2. 根据权利要求1所述的方法，其中，所述外延层与所述半导体衬底的材料相同。
  3. 根据权利要求1所述的方法，其中，向所述外延层和部分所述半导体衬底中注入所述掺杂物的步骤，包括：
    采用离子注入工艺注入所述掺杂物。
  4. 根据权利要求3所述的方法，其中，所述离子注入工艺的能量为大于2keV，所述离子注入工艺的剂量为大于或等于1E13cm -2。
  5. 根据权利要求4所述的方法，其中，所述离子注入工艺的能量为大于10keV，所述离子注入工艺的剂量为大于1E14cm -2。
  6. 根据权利要求5所述的方法，其中，所述离子注入工艺的能量为大于20keV，所述离子注入工艺的剂量为大于1E15cm -2。
  7. 根据权利要求1所述的方法，其中，所述部分所述半导体衬底中注入的所述掺杂物的剂量为小于1E13cm -2。
  8. 根据权利要求7所述的方法，其中，所述部分所述半导体衬底中注入的所述掺杂物的剂量为小于1E12cm -2。
  9. 根据权利要求1所述的方法，其中，去除所述外延层的步骤，包括：
    采用湿法或干法刻蚀，去除所述外延层。
  10. 一种形成超浅结的方法，所述方法包括以下步骤：
    提供半导体衬底；
    在所述半导体衬底上形成外延层；
    在所述外延层上形成具有掩膜开口的光阻层，一部分所述外延层被所述光阻层覆盖，另一部分所述外延层位于所述光阻层的所述掩膜开口下方，位于所述掩膜开口下方的所述外延层和部分所述半导体衬底形成注入区域；
    提供第一掺杂物，向所述注入区域注入第一掺杂物，以使所述第一掺杂物注入位于所 述掩膜开口下方的所述外延层以及所述部分所述半导体衬底中；
    去除所述光阻层；
    去除所述外延层，以在所述半导体衬底中形成超浅结。
  11. 根据权利要求10所述的方法，其中，去除所述光阻层之后，以及去除所述外延层，以在所述半导体衬底中形成超浅结之前，所述方法还包括：
    提供第二掺杂物，向所述外延层注入所述第二掺杂物，以提高所述外延层的刻蚀选择比。
  12. 根据权利要求11所述的方法，其中，所述第二掺杂物为锗或硅。
  13. 根据权利要求11所述的方法，其中，去除所述外延层的步骤，包括：
    采用湿法或干法刻蚀，去除所述外延层。
  14. 根据权利要求10所述的方法，其中，所述外延层与所述半导体衬底的材料相同。
  15. 根据权利要求10所述的方法，其中，向所述注入区域注入第一掺杂物的步骤，包括：
    采用离子注入工艺注入所述第一掺杂物。
  16. 根据权利要求15所述的方法，其中，所述离子注入工艺的能量为大于2keV，所述离子注入工艺的剂量为大于或等于1E13cm -2。
  17. 根据权利要求16所述的方法，其中，所述离子注入工艺的能量为大于10keV，所述离子注入工艺的剂量为大于1E14cm -2。
  18. 根据权利要求17所述的方法，其中，所述离子注入工艺的能量为大于20keV,所述离子注入工艺的剂量为大于1E15cm -2。
  19. 根据权利要求10所述的方法，其中，所述部分所述半导体衬底中注入的所述第一掺杂物的剂量为小于1E13cm -2。
  20. 根据权利要求19所述的方法，其中，所述部分所述半导体衬底中注入的所述掺杂物的剂量为小于1E12cm -2。
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