WO2022166131A1 - 半导体结构的熔断填充方法及半导体结构 - Google Patents

半导体结构的熔断填充方法及半导体结构 Download PDF

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Publication number
WO2022166131A1
WO2022166131A1 PCT/CN2021/109303 CN2021109303W WO2022166131A1 WO 2022166131 A1 WO2022166131 A1 WO 2022166131A1 CN 2021109303 W CN2021109303 W CN 2021109303W WO 2022166131 A1 WO2022166131 A1 WO 2022166131A1
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Prior art keywords
semiconductor structure
sealing material
material layer
shielding layer
fuse
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PCT/CN2021/109303
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English (en)
French (fr)
Inventor
宫光彩
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/649,165 priority Critical patent/US20220254718A1/en
Publication of WO2022166131A1 publication Critical patent/WO2022166131A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a fuse filling method for a semiconductor structure and a semiconductor structure.
  • a plurality of fuse array groups are formed in a semiconductor structure.
  • the connection structure can be changed by blowing the back-end interconnection lines by means of high temperature laser. After the back-end interconnection line is blown, a gap will be formed on the semiconductor structure, and the gap is not protected in the related art, so that the side of the back-end interconnection after the blown-out will be subject to external interference, thereby affecting the performance of the semiconductor structure.
  • the present disclosure provides a fuse filling method for a semiconductor structure and a semiconductor structure to improve the performance of the semiconductor structure.
  • a fuse filling method for a semiconductor structure comprising:
  • a semiconductor structure body is provided, and a plurality of fuse array groups are formed in the semiconductor structure body;
  • a layer of sealing material is formed within the gap.
  • a semiconductor structure comprising:
  • a semiconductor structure body a plurality of fuse array groups are formed in the semiconductor structure body, a gap is formed on the semiconductor structure body, and the interconnection structure of the fuse array group is fused;
  • the sealing material layer is located in the gap.
  • the fuse filling method of the semiconductor structure of the present disclosure forms a shielding layer on the semiconductor structure body with a gap, and forms a through hole exposing the gap on the shielding layer.
  • the material layer directly covers the semiconductor structure body in a large area, avoiding subsequent cleaning, and can ensure that a sealing material layer is reliably formed in the gap, thereby isolating the intrusion of external risk factors, thereby improving the performance of the semiconductor structure.
  • FIG. 1 is a schematic flowchart of a method for fuse filling of a semiconductor structure according to an exemplary embodiment
  • FIG. 2 is a schematic structural diagram of a semiconductor structure body according to an exemplary embodiment
  • Fig. 3 is the enlarged structure schematic diagram of A place in Fig. 2;
  • FIG. 4 is a schematic structural diagram of a semiconductor structure body covered with a shielding layer according to an exemplary embodiment
  • FIG. 5 is a schematic structural diagram of a semiconductor structure body covered with a shielding layer according to another exemplary embodiment
  • FIG. 6 is a schematic structural diagram of a semiconductor structure body with a second positioning portion formed on it according to an exemplary embodiment
  • FIG. 7 is a schematic structural diagram of a semiconductor structure body with a shielding layer formed on it according to an exemplary embodiment
  • FIG. 8 is a schematic structural diagram illustrating an opening formed by a fuse filling method of a semiconductor structure according to an exemplary embodiment
  • FIG. 9 is a schematic structural diagram of forming a gap by a fuse filling method of a semiconductor structure according to an exemplary embodiment
  • FIG. 10 is a schematic structural diagram of forming a shielding layer by a fuse filling method of a semiconductor structure according to an exemplary embodiment
  • FIG. 11 is a schematic structural diagram of forming an initial sealing material layer by a fuse filling method for a semiconductor structure according to an exemplary embodiment
  • FIG. 12 is a schematic structural diagram of a semiconductor structure after removing a shielding layer by a fuse filling method according to an exemplary embodiment
  • FIG. 13 is a schematic view of the structure after the initial sealing material layer is cleaned by a fuse filling method for a semiconductor structure according to an exemplary embodiment
  • FIG. 14 is a schematic structural diagram of forming a sealing material layer by a fuse filling method for a semiconductor structure according to an exemplary embodiment.
  • An embodiment of the present disclosure provides a fuse filling method for a semiconductor structure. Please refer to FIG. 1 .
  • the fuse filling method for a semiconductor structure includes:
  • S101 providing a semiconductor structure body 10, and a plurality of fuse array groups 20 are formed in the semiconductor structure body 10;
  • a method for filling a semiconductor structure with a fuse forms a shielding layer 30 on the semiconductor structure body 10 having the notch 11 , and a through hole 31 exposing the notch 11 is formed on the shielding layer 30 , that is, when the notch 11 is subsequently filled , because the existence of the shielding layer 30 will not make the sealing material layer 40 directly cover the semiconductor structure body 10 in a large area, avoiding subsequent cleaning, and can ensure that the sealing material layer 40 is reliably formed in the gap 11, thereby isolating external risk factors intrusion, thereby improving the performance of the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • connection structure is changed by burning the back-end interconnection lines (ie, the interconnection structure 21 of the fuse array group 20 ) by means of a high temperature laser.
  • the interconnect structure 21 of the fuse array group 20 is blown, a gap 11 will be formed. If the gap 11 is not protected, the side surfaces of the rear-end interconnect after the fuse will become external moisture, impurity metal ions, and even external static electricity and static electricity.
  • the intrusion of stress which in turn leads to the weakening of the material strength and dielectric effect of the back-end interconnect dielectric layer, eventually leads to structural delamination, cracking, leakage, deterioration of device performance, reduced reliability, and impact on bonding and product use. Wait.
  • the above problems can be avoided by forming the sealing material layer 40 in the gap 11 .
  • the shielding layer 30 formed on the semiconductor structure body 10 is used to prevent the sealing material layer 40 from being formed in some areas of the semiconductor structure body 10 , for example, the bonding welding in which the sealing material layer 40 covers the semiconductor structure body 10 may occur.
  • the covering sealing material layer 40 needs to be removed in the subsequent process. Since the material and structural limitations of the sealing material layer 40 themselves are difficult to be removed, the bonding pad may be damaged in severe cases, thereby affecting the bonding (bonding). ).
  • the setting of the shielding layer 30 can avoid the above problems, and ensure that the sealing material layer 40 does not cover the position that should not be covered.
  • the fuse array group 20 includes an interconnect structure 21 , a bonding pad 22 and a contact hole 23 , the interconnect structure 21 is connected with the bonding pad 22 and the contact hole 23 , and the bonding pad 22 can be are bonding aluminum pads, the contact holes 23 can be connected to the substrate 14 of the semiconductor structure body 10 .
  • the specific structure of the fuse array group 20 is not limited here, and may be various fuse array groups of semiconductor structures formed in the related art.
  • the shielding layer 30 is made of a hard material, that is, the shielding layer 30 has a certain hardness, so as to ensure that there will be no damage, so as to avoid the problem of weakening protection performance, and also facilitate subsequent removal of the shielding Layer 30.
  • the shielding layer 30 is made of polymer material, ceramic, or metal material to ensure that the shielding layer 30 has a certain strength.
  • the shielding layer 30 is a protection structure and will be removed later, and the shielding layer 30 made of hard material is also easily removed, thereby improving the formation efficiency.
  • the sealing material layer 40 may be an epoxy resin material or a polyimide resin material.
  • a plurality of fuse array groups 20 are blown to form a plurality of independent notches 11 on the semiconductor structural body 10. In some cases, there may be problems with multiple fuse array groups 20. In this state, multiple fuse array groups 20 need to be blown, so that multiple independent gaps are formed on the semiconductor structure body 10. 11.
  • FIG. 2 a plurality of fuse array groups 20 are formed on the semiconductor structure body 10 , and the plurality of fuse array groups 20 are arranged at intervals.
  • FIG. 3 is an enlarged schematic view of the structure at A in FIG. 2 .
  • a sealing ring 50 is provided on the outer circumferential side of each fuse array group 20 for protection, and each fuse array group 20 includes multiple device.
  • a plurality of through holes 31 are formed on the shielding layer 30 , and the plurality of through holes 31 respectively expose a plurality of gaps 11 , that is, a corresponding sealing material layer 40 is formed in each gap 11 . There will be no connection between them.
  • the fuse array group 20 after being blown is determined, that is, it is determined that a plurality of notches 11 are formed on the semiconductor structure body 10 .
  • the shielding layer 30 covering the semiconductor structure body 10 is formed with corresponding The number of through holes 31, after covering the shielding layer 30 on the semiconductor structure body 10, forms the structure shown in FIG. Corresponding to the corresponding notch 11 .
  • two fuse array groups 20 that are blown are disposed adjacent to each other.
  • an unblown fuse array may be disposed between the two blown fuse array groups 20 Group 20.
  • a through hole 31 exposes a plurality of notches 11 , that is, an integral sealing material layer 40 is formed in each of the notches 11 .
  • the fuse array group 20 after being blown is determined, that is, it is determined that a plurality of notches 11 are formed on the semiconductor structure body 10 .
  • a shielding layer 30 covering the semiconductor structure body 10 is formed with a The large through hole 31 , the large through hole 31 can correspond to a plurality of notches 11 at the same time, that is, the part of the semiconductor structure body 10 between the notches 11 is also exposed.
  • the structure shown in FIG. 5 is formed.
  • One through hole 31 corresponds to multiple fuse array groups 20 , that is, one through hole 31 corresponds to multiple notches 11 .
  • the sealing material layer 40 is formed, the sealing material layer 40 is formed in the through hole 31 , that is, a large piece of the sealing material layer 40 fills the plurality of gaps 11 .
  • the fuse array groups 20 to be blown are arranged adjacent to each other, so that the subsequent removal of the sealing material layer 40 is not required. process, thereby improving the molding efficiency, avoiding subsequent use of etching and other processes, and preventing damage to the semiconductor structure body 10 .
  • FIG. 4 shows one through hole 31 corresponding to one gap 11
  • FIG. 5 shows one through hole 31 corresponding to multiple gaps 11 .
  • a plurality of through holes 31 are formed on the shielding layer 30, and the plurality of through holes 31 are arranged at intervals. Some of the through holes 31 correspond to the plurality of notches 11 .
  • the specific formation of the corresponding gap 11 is not limited, and can be determined by the actual fusing process, as long as the interconnect structure 21 can be guaranteed to be blown, that is, the corresponding fuse array group 20 is disconnected.
  • the specific shape of the through hole 31 is also not limited, and can be adjusted adaptively according to the shape of the notch 11 , that is, to ensure that the notch 11 can be exposed.
  • the area of the through hole 31 is larger than the area of the gap 11 , so that the sealing material layer 40 covers part of the upper surface of the semiconductor structure body 10 , that is, the sealing material layer 40 needs to partially cover the gap after filling the gap 11 .
  • the part of the plane where the opening 11 is located, that is, the top area of the formed sealing material layer 40 is larger than the opening area of the notch 11 , so as to achieve reliable protection for the notch 11 .
  • the size of the top area of the sealing material layer 40 should not be too large, so as to avoid covering some areas that should not be covered. It is only necessary to ensure that the opening of the notch 11 can be reliably covered, which is not limited here. , which can be determined according to the time situation of the semiconductor structure.
  • forming the sealing material layer 40 includes: forming an initial sealing material layer 41 on the shielding layer 30, the initial sealing material layer 41 covering the shielding layer 30, and filling the gap 11 and the through hole 31; removing the shielding layer 30 and covering The initial sealing material layer 41 of the shielding layer 30 is used, and the remaining initial sealing material layer 41 is used as the sealing material layer 40 .
  • an initial sealing material layer 41 needs to be formed on the shielding layer 30.
  • the initial sealing material layer 41 may cover the entire shielding layer 30, that is, the entire shielding layer 30 is buried in the initial sealing material layer. Therefore, the initial sealing material layer 41 covering the shielding layer 30 needs to be removed later, and correspondingly, the shielding layer 30 is also removed, so that the sealing material layer 40 protecting the gap 11 remains.
  • the initial sealing material layer 41 can be formed by adopting a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, or an atomic layer deposition (Atomic Layer Deposition, ALD) process, etc. .
  • PVD Physical Vapor Deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the shielding layer 30 and the initial sealing material layer 41 covering the shielding layer 30 are removed simultaneously, that is, the shielding layer 30 and the initial sealing material layer 41 covering the shielding layer 30 can be removed simultaneously in one operation step.
  • the initial sealing material layer 41 covering the shielding layer 30 is removed by removing the shielding layer 30 . Since the initial sealing material layer 41 is not yet cured, and the material of the shielding layer 30 is relatively hard, the shielding layer 30 can be pulled to remove the shielding layer 30 and the initial sealing material layer 41 covering the shielding layer 30 .
  • the initial sealing material layer 41 covering the shielding layer 30 will be separated from the initial sealing located in the notch 11 and the through hole 31 under the action of force material layer 41, so that only the initial sealing material layer 41 covering the shielding layer 30 can be removed, ensuring that the initial sealing material layer 41 in the gap 11 and the through hole 31 will not be removed, of course, it is not excluded.
  • a part of the initial sealing material layer 41 is removed, but it will not affect the overall protective effect of the initial sealing material layer 41 on the notch 11 .
  • the removal process is relatively simple, and the operation process is also relatively simple, and the efficiency is high.
  • the initial sealing material layer 41 covering the shielding layer 30 is removed first, and then the shielding layer 30 is removed, that is, the initial sealing material layer 41 and the shielding layer 30 covering the shielding layer 30 are removed successively, so as to ensure accurate removal. Spend.
  • the initial sealing material layer 41 is cured, so as to ensure that the initial sealing material layer 41 filled in the through hole 31 will not be removed by mistake.
  • the initial sealing material layer 41 when the initial sealing material layer 41 is cured first, and then part of the initial sealing material layer 41 is removed, the initial sealing material layer 41 can reliably seal the gap 11, and the initial sealing material layer is subsequently removed by etching and other processes. 41 , since the lower part of the initial sealing material layer 41 will be covered with the shielding layer 30 , the semiconductor structure body 10 will not be damaged.
  • the shielding layer 30 and the initial sealing material layer 41 covering the shielding layer 30 are simultaneously removed, compared with the initial sealing covering the shielding layer 30 after curing the initial sealing material layer 41
  • the material layer 41 and the blocking layer 30 are sequentially removed.
  • the simultaneous removal of the shielding layer 30 and the formation of the initial sealing material layer 41 covering the shielding layer 30 may be more efficient.
  • forming the shielding layer 30 includes: arranging the first positioning portion on the shielding layer 30 to be opposite to the second positioning portion on the semiconductor structure body 10 , so that the through hole 31 exposes the gap 11 , that is, the shielding layer 30 is ensured.
  • the through holes on the upper part can accurately expose the corresponding notches 11 .
  • first positioning portion and the second positioning portion are disposed opposite to each other, that is, the first positioning portion and the second positioning portion are aligned with each other.
  • first positioning portion and the second positioning portion may be holes with the same structure, that is, to ensure that the two holes are coincident, or the first positioning portion and the second positioning portion may be protrusions with the same structure, that is, the two protrusions are aligned with each other.
  • first positioning portion and the second positioning portion may be protrusions and grooves, respectively, and the protrusions and grooves are matched.
  • the semiconductor structure body 10 is provided with a plurality of die 1, and the semiconductor structure body 10 has a second positioning portion, and the second positioning portion may be a wafer notch 12.
  • the semiconductor structure body 10 may represent a wafer, the wafer may be covered with die 1, each die 1 may include one or more fuse array groups 20, and the wafer may be circular or rectangular, which is not limited here.
  • a first positioning portion is formed on the shielding layer 30.
  • the first positioning portion and the second positioning portion are arranged opposite to each other, thereby realizing the exposure of the through hole 31 to the notch 11.
  • the first positioning portion may be a coating positioning hole 32 , and in this case, the coating positioning hole may correspond to the wafer notch 12 .
  • the first positioning portion may be a film positioning mark 33
  • the second positioning portion provided on the semiconductor structure body 10 may be a corresponding wafer positioning mark 15
  • the film positioning mark 33 corresponds to the wafer positioning mark 15 .
  • the shielding layer 30 may be formed with a coating positioning hole 32 and a coating positioning mark 33
  • the semiconductor structure body 10 may be formed with a corresponding wafer notch 12 and a wafer positioning mark 15 .
  • 32 corresponds to the chip notch 12
  • the film positioning mark 33 corresponds to the wafer positioning mark 15 , so as to realize the exposure of the through hole 31 to the notch 11 .
  • the shielding layer 30 may be circular or rectangular, which is not specifically limited here.
  • the shielding layer 30 may touch the surface of the wafer by a simple pressing method, or may be fixed on the wafer by an electrostatic method or an adhesive method.
  • the first positioning part and the second positioning part are arranged opposite to each other, and the positioning adopts laser direct or indirect alignment. In this way, the structure shown in FIG. 7 is formed, that is, the through hole 31 can expose the die 1 .
  • the fuse filling method for the semiconductor structure further includes: removing the shielding layer 30; cleaning the outer surface of the sealing material layer 40, that is, after removing the shielding layer 30 to form the sealing material layer 40, the sealing material layer 40 needs to be cleaned , to remove residue on the surface, reduce the line width, and reduce the coverage of other areas.
  • cleaning the outer surface of the sealing material layer 40 includes: thinning the sealing material layer 40 and reducing the dimension of the sealing material layer 40 in the width direction. That is, the thickness and width of the sealing material layer 40 can be reduced after the shielding layer 30 is removed, so as to avoid the problem that the sealing material layer 40 is too thick and the coverage is too large.
  • the outer surface of the sealing material layer 40 is subjected to residue removal, trimming and cleaning.
  • the residue can be further removed by argon sputtering (Ar sputter) or wet cleaning (WET cleaning) (SPM+SC1+SC2 or special cleaning agent suitable for Al).
  • FIG. 8 to FIG. 14 A specific embodiment of a fuse filling method for a semiconductor structure is shown in FIG. 8 to FIG. 14 :
  • an opening 13 is formed on the semiconductor structure body 10 , and the lower part of the opening 13 corresponds to the interconnection structure 21 of the fuse array group 20 .
  • the opening 13 may be formed by forming a mask on the semiconductor structure body 10, the mask covering the area outside the opening 13, and then the opening 13 may be formed by etching or laser fusing.
  • the interconnect structure 21 is fused by laser, and a gap 11 is formed on the basis of the opening 13 , as shown in FIG. 9 , at this time, the gap 11 is exposed to the external environment.
  • the shielding layer 30 is covered on the semiconductor structure body 10 , and the through hole 31 of the shielding layer 30 exposes the notch 11 , as shown in FIG. 10 .
  • the first positioning portion on the shielding layer 30 and the second positioning portion on the semiconductor structure body 10 may be positioned directly or indirectly by means of a laser. That is, the position of the through hole 31 is aligned with the position of the fuse array group 20, and the size of the through hole 31 can be determined according to the requirements and influence of the required sealing area. If the area between the multiple fuse array groups 20 will not be affected by the sealing process, it may be considered to expand the through hole 31 to the entire fuse area to form a large opening instead of multiple independent island structures.
  • an initial sealing material layer 41 is formed on the shielding layer 30 . As shown in FIG. 11 , the initial sealing material layer 41 covers the shielding layer 30 and fills the through holes 31 and the gaps 11 .
  • the initial sealing material layer 41 can be based on epoxy resin material or polyimide resin material or other resin materials that meet the requirements (expansion coefficient, adhesive strength and wettability with the target interface, chemical stability and compatibility properties, moisture resistance and barrier effect, degree of antistatic, fluidity, ease of application, etc.).
  • the brushing method of the initial sealing material layer 41 may be a rigid scraping method, a flexible material (PP, PVA%) brushing method, or a rotary spraying method, and the specific process is not limited.
  • the shielding layer 30 and the initial sealing material layer 41 covering the shielding layer 30 are removed to form the structure shown in FIG. 12 .
  • the residues on the surface are removed by ashing or Etch trim, the line width is reduced (that is, the top width of the finally formed sealing material layer 40 is reduced), and the initial sealing material layer 41 is reduced to other areas. coverage, as shown in Figure 13.
  • the line width of the initial sealing material layer 41 is B, and after surface treatment, as shown in FIG. 13 , the line width of the initial sealing material layer 41 is C, and C is smaller than B, and the sealing material layer The final line width of 40 is C.
  • the initial sealing material layer 41 is thermally cured to form the sealing material layer 40 , as shown in FIG. 14 .
  • curing can be performed at a temperature of 120° C. to 400° C. for 30 minutes to 500 minutes, and an appropriate atmosphere, such as nitrogen, argon, water vapor, or mixed gas, can be selected according to material properties.
  • an appropriate atmosphere such as nitrogen, argon, water vapor, or mixed gas, can be selected according to material properties.
  • the semiconductor structure formed by the fuse filling method of the semiconductor structure of the present disclosure can isolate the intrusion of external risk factors.
  • the semiconductor structure includes: a semiconductor structure body 10 , a plurality of fuse array groups 20 are formed in the semiconductor structure body 10 , and a plurality of fuse array groups 20 are formed on the semiconductor structure body 10 In the gap 11 , the interconnect structure 21 of the fuse array group 20 is fused; the sealing material layer 40 , the sealing material layer 40 is located in the gap 11 .
  • the sealing material layer 40 is filled in the gap 11 of the semiconductor structure body 10 , so as to isolate the intrusion of external risk factors, thereby improving the performance of the semiconductor structure.
  • the sealing material layer 40 is disposed protruding from the semiconductor structure body 10 to cover part of the upper surface of the semiconductor structure body 10 , that is, the top area of the sealing material layer 40 is larger than the opening area of the notch 11 , so as to improve the protection performance.
  • the semiconductor structure further includes: a plurality of sealing rings 50 , each fuse array group 20 is located in each sealing ring 50 , and the sealing ring 50 realizes the protection of each fuse array group 20 .
  • the semiconductor structure is formed by the above-described fuse fill method of the semiconductor structure.

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Abstract

本公开涉及半导体技术领域，提出了一种半导体结构的熔断填充方法及半导体结构。半导体结构的熔断填充方法包括：提供一半导体结构本体，半导体结构本体内形成有多个熔断器阵列组；熔断熔断器阵列组的互连结构，以在半导体结构本体上形成缺口；在半导体结构本体上形成遮挡层，遮挡层上形成有暴露缺口的通孔；在缺口内形成密封材料层。通过在具有缺口的半导体结构本体上形成遮挡层，且遮挡层上形成有暴露缺口的通孔，即在后续填充缺口时，由于遮挡层的存在不会使得密封材料层大面积地直接覆盖半导体结构本体，避免了后续的清理，且可以保证缺口内可靠地形成密封材料层，以此隔绝外部危险因素的侵入，以此改善半导体结构的使用性能。

Description

半导体结构的熔断填充方法及半导体结构
交叉引用
本公开要求于2021年02月07日提交的申请号为202110177190.4、名称为“半导体结构的熔断填充方法及半导体结构”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构的熔断填充方法及半导体结构。
背景技术
相关技术中，半导体结构内形成有多个熔断器阵列组。在测试过程中如果有部分熔断器阵列组出现问题，则可以通过激光高温的方式来烧断后端互连线路来改变连接结构。在烧断后端互连线路后，半导体结构上会形成一个缺口，相关技术中并未对缺口进行保护，致使烧断后的后端互连侧面会受到外部干扰，从而影响半导体结构的使用性能。
发明内容
本公开提供一种半导体结构的熔断填充方法及半导体结构，以改善半导体结构的性能。
根据本公开的第一个方面，提供了一种半导体结构的熔断填充方法，包括：
提供一半导体结构本体，半导体结构本体内形成有多个熔断器阵列组；
熔断熔断器阵列组的互连结构，以在半导体结构本体上形成缺口；
在半导体结构本体上形成遮挡层，遮挡层上形成有暴露缺口的通孔；
在缺口内形成密封材料层。
根据本公开的第二个方面，提供了一种半导体结构，包括：
半导体结构本体，半导体结构本体内形成有多个熔断器阵列组，半导体结构本体上形成有缺口，熔断器阵列组的互连结构被熔断；
密封材料层，密封材料层位于缺口内。
本公开的半导体结构的熔断填充方法通过在具有缺口的半导体结构本体上形成遮挡 层，且遮挡层上形成有暴露缺口的通孔，即在后续填充缺口时，由于遮挡层的存在不会使得密封材料层大面积地直接覆盖半导体结构本体，避免了后续的清理，且可以保证缺口内可靠地形成密封材料层，以此隔绝外部危险因素的侵入，以此改善半导体结构的使用性能。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的熔断填充方法的流程示意图；
图2是根据一示例性实施方式示出的一种半导体结构本体的结构示意图；
图3是图2中A处的放大结构示意图；
图4是根据一示例性实施方式示出的一种半导体结构本体上覆盖有遮挡层的结构示意图；
图5是根据另一示例性实施方式示出的一种半导体结构本体上覆盖有遮挡层的结构示意图；
图6是根据一示例性实施方式示出的一种半导体结构本体上形成有第二定位部的结构示意图；
图7是根据一示例性实施方式示出的一种半导体结构本体上形成有遮挡层的结构示意图；
图8是根据一示例性实施方式示出的一种半导体结构的熔断填充方法形成开口的结构示意图；
图9是根据一示例性实施方式示出的一种半导体结构的熔断填充方法形成缺口的结构示意图；
图10是根据一示例性实施方式示出的一种半导体结构的熔断填充方法形成遮挡层的结构示意图；
图11是根据一示例性实施方式示出的一种半导体结构的熔断填充方法形成初始密封材料层的结构示意图；
图12是根据一示例性实施方式示出的一种半导体结构的熔断填充方法去除遮挡层后的结构示意图；
图13是根据一示例性实施方式示出的一种半导体结构的熔断填充方法清理初始密封 材料层后的结构示意图；
图14是根据一示例性实施方式示出的一种半导体结构的熔断填充方法形成密封材料层的结构示意图。
附图标记说明如下：
1、晶粒；10、半导体结构本体；11、缺口；12、晶片缺口；13、开口；14、衬底；15、晶片定位标识；20、熔断器阵列组；21、互连结构；22、键合焊盘；23、接触孔；30、遮挡层；31、通孔；32、覆膜定位孔；33、覆膜定位标识；40、密封材料层；41、初始密封材料层；50、密封圈。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构，系统和步骤。应理解的是，可以使用部件，结构，示例性装置，系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”，“之间”，“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体结构的熔断填充方法，请参考图1，半导体结构的熔断填充方法包括：
S101，提供一半导体结构本体10，半导体结构本体10内形成有多个熔断器阵列组20；
S103，熔断熔断器阵列组20的互连结构21，以在半导体结构本体10上形成缺口11；
S105，在半导体结构本体10上形成遮挡层30，遮挡层30上形成有暴露缺口11的通孔31；
S107，在缺口11内形成密封材料层40。
本公开一个实施例的半导体结构的熔断填充方法通过在具有缺口11的半导体结构本体10上形成遮挡层30，且遮挡层30上形成有暴露缺口11的通孔31，即在后续填充缺口11时，由于遮挡层30的存在不会使得密封材料层40大面积地直接覆盖半导体结构本体 10，避免了后续的清理，且可以保证缺口11内可靠地形成密封材料层40，以此隔绝外部危险因素的侵入，以此改善半导体结构的使用性能。
需要说明的是，DRAM(Dynamic Random Access Memory)在测试完后发现有失效的电容、字线、位线等时，相关技术中，这些失效的位元会通过熔断器(fuse)的熔断来修复，其过程是改变连接线路结构，并使其连接到备用的位元来替换失效的位元，从而达到修复的效果。
在一些实施例中，通过激光高温的方式来烧断后端互连线路(即熔断器阵列组20的互连结构21)来改变连接结构。在烧断熔断器阵列组20的互连结构21时会形成有缺口11，如果不对缺口11进行保护，则致使烧断后的后端互连侧面会成为外部湿气和杂质金属离子甚至外部静电和应力的侵入口，进而导致后端互连介电层的材料强度、介电效果减弱，最终导致结构分层、破裂、漏电、器件性能恶化、可靠性降低、影响键合(bonding)和产品使用等。而本实施例中，通过在缺口11内形成密封材料层40可以避免上述问题。
需要注意的是，在半导体结构本体10上形成的遮挡层30用于避免密封材料层40形成在半导体结构本体10的某些区域，例如会出现密封材料层40覆盖半导体结构本体10的键合焊盘的情况，后续过程中需要对覆盖的密封材料层40进行清除，由于密封材料层40本身材料和结构限定很难被清除，严重情况下可能会破坏键合焊盘，从而影响键合(bonding)。而本实施例中遮挡层30的设置可以避免上述问题，保证密封材料层40不会覆盖不该覆盖的位置。
在一些实施例中，熔断器阵列组20包括互连结构21、键合焊盘22以及接触孔23，互连结构21和键合焊盘22以及接触孔23均连接，键合焊盘22可以是键合铝焊盘，接触孔23可以连接至半导体结构本体10的衬底14。对于熔断器阵列组20的具体结构此处不作限定，可以是相关技术中形成的半导体结构的各类熔断器阵列组。
在一个实施例中，遮挡层30由硬质材料制备而成，即遮挡层30具有一定的硬度，从而保证不会出现破损等情况，以此避免防护性能减弱的问题，且也方便后续去除遮挡层30。
在一个实施例中，遮挡层30由高分子材料、陶瓷、或金属材料制备而成，保证遮挡层30具备一定的强度。
需要说明的是，遮挡层30属于保护结构，在后续会进行去除，而硬质材料制备而成的遮挡层30也方便去除，从而提高形成效率。
在一个实施例中，密封材料层40可以是环氧树脂材料或聚酰亚胺树脂材料。
在一个实施例中，熔断多个熔断器阵列组20，以在半导体结构本体10上形成多个独 立的缺口11。在某些情况下，会存在多个熔断器阵列组20都出现问题的情况，此状态下需要对多个熔断器阵列组20进行熔断，从而会在半导体结构本体10上形成多个独立的缺口11。
在一个实施例中，如图2所示，半导体结构本体10上形成有多个熔断器阵列组20，多个熔断器阵列组20间隔设置。图3是图2中A处的放大结构示意图，结合图3所示，每个熔断器阵列组20的周向外侧均设置有密封圈50进行防护，且每个熔断器阵列组20均包括多个器件。
在一个实施例中，遮挡层30上形成有多个通孔31，多个通孔31分别暴露多个缺口11，即会在各个缺口11内形成相应的密封材料层40，密封材料层40之间不会出现连接的情况。
具体的，在图2的基础上，确定熔断后的熔断器阵列组20，即确定了半导体结构本体10上形成有多个缺口11，此时覆盖半导体结构本体10的遮挡层30上形成有相应数量的通孔31，将遮挡层30覆盖在半导体结构本体10上后，形成如图4所示的结构，多个通孔31分别对应多个熔断器阵列组20，即每个通孔31均对应相应的缺口11。图4中所示的是被熔断的两个熔断器阵列组20相邻设置，在某些实施例中，两个被熔断的熔断器阵列组20之间可以设置有未被熔断的熔断器阵列组20。
在一个实施例中，一个通孔31暴露多个缺口11，即在各个缺口11内形成一个整体的密封材料层40。
具体的，在图2的基础上，确定熔断后的熔断器阵列组20，即确定了半导体结构本体10上形成有多个缺口11，此时覆盖半导体结构本体10的遮挡层30上形成有一个大通孔31，此大通孔31可以同时对应多个缺口11，即将缺口11之间半导体结构本体10的部分也进行暴露。将遮挡层30覆盖在半导体结构本体10上后，形成如图5所示的结构，一个通孔31对应多个熔断器阵列组20，即一个通孔31对应多个缺口11。后续在形成密封材料层40后，密封材料层40会形成于通孔31内，即一大块密封材料层40填充多个缺口11。
需要说明的是，在使用一个通孔31暴露多个缺口11时，最佳的实施例是，被熔断的多个熔断器阵列组20均相邻设置，从而不用后续进行密封材料层40的去除工艺，以此提高成型效率，避免后续使用蚀刻等工艺，防止出现对半导体结构本体10造成损伤。
需要说明的是，对于图4和图5所示出的实施例，区别点在于图4为一个通孔31对应一个缺口11，而图5为一个通孔31对应多个缺口11。
在一些实施例中，遮挡层30上形成有多个通孔31，多个通孔31间隔设置，多个通孔 31的大小可以不相同，即某些通孔31分别对应一个缺口11，而某些通孔31对应多个缺口11。
在一些实施例中，对应缺口11的具体形成不作限定，可以由实际熔断工艺确定，只要可以保证互连结构21处于熔断即可，即对应的熔断器阵列组20断开。相应的，通孔31的具体形状也不作限定，可以根据缺口11的形状进行适应性的调整，即保证能够暴露缺口11。
在一个实施例中，通孔31的面积大于缺口11的面积，以使密封材料层40覆盖半导体结构本体10的部分上表面，即密封材料层40在填充缺口11的基础上，需要部分覆盖缺口11开口所在平面的部分，即形成的密封材料层40的顶部面积大于缺口11的开口面积，以此实现对缺口11的可靠防护。
需要说明的是，对于密封材料层40的顶部面积的尺寸不宜太大，以此避免覆盖某些不该覆盖的区域，只需要保证能够对缺口11的开口进行可靠覆盖即可，此处不作限定，可以根据半导体结构的时间情况确定。
在一个实施例中，形成密封材料层40包括：在遮挡层30上形成初始密封材料层41，初始密封材料层41覆盖遮挡层30，且填充缺口11和通孔31；去除遮挡层30和覆盖遮挡层30的初始密封材料层41，并使得剩余的初始密封材料层41作为密封材料层40。
具体的，在覆盖遮挡层30后，需要在遮挡层30上形成初始密封材料层41，此时初始密封材料层41可能会覆盖整个遮挡层30，即将遮挡层30整体埋入到初始密封材料层41中，因此后续需要将覆盖遮挡层30的初始密封材料层41进行去除，相应的，遮挡层30也进行去除，以此剩余下保护缺口11的密封材料层40。
需要注意的是，初始密封材料层41可以通过采用物理气相沉积(Physical Vapor Deposition，PVD)工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺或原子层沉积(Atomic Layer Deposition，ALD)工艺等形成。
在一个实施例中，同步去除遮挡层30和覆盖遮挡层30的初始密封材料层41，即可以采用一个操作步骤将遮挡层30和覆盖遮挡层30的初始密封材料层41同时去除。
在一个实施例中，在固化形成密封材料层40之前，通过去除遮挡层30，以将覆盖遮挡层30的初始密封材料层41去除。由于初始密封材料层41还未固化，而遮挡层30的材质相对较硬，以此可以拉动遮挡层30将遮挡层30和覆盖遮挡层30的初始密封材料层41去除。
需要说明的是，在拉动遮挡层30时，由于初始密封材料层41没有固化，因此覆盖遮 挡层30的初始密封材料层41会在力的作用下脱离位于缺口11和通孔31内的初始密封材料层41，从而可以实现仅去除覆盖遮挡层30的初始密封材料层41的情况，保证缺口11和通孔31内的初始密封材料层41不会被去除，当然也不排除位于通孔31内的部分初始密封材料层41被去除，但不会影响初始密封材料层41对于缺口11的整体防护效果。此去除过程较为简单，且操作工艺也较为简单，效率较高。
在一个实施例中，先去除覆盖遮挡层30的初始密封材料层41，然后去除遮挡层30，即将覆盖遮挡层30的初始密封材料层41和遮挡层30进行先后去除，以此保证去除的精确度。
在一个实施例中，去除覆盖遮挡层30的初始密封材料层41之前，固化初始密封材料层41，从而可以保证填充在通孔31内的初始密封材料层41不会被误去除。
需要说明的是，在将初始密封材料层41先固化，然后进行部分初始密封材料层41的去除，此时初始密封材料层41能够可靠密封缺口11，而后续通过蚀刻等工艺去除初始密封材料层41时，由于初始密封材料层41下部会覆盖有遮挡层30，因此也不会出现损伤半导体结构本体10的情况。
需要注意的是，初始密封材料层41固化前，同步去除遮挡层30和覆盖遮挡层30的初始密封材料层41，相比于，固化初始密封材料层41之后，进行覆盖遮挡层30的初始密封材料层41和遮挡层30的先后去除。同步去除遮挡层30和覆盖遮挡层30的初始密封材料层41的形成效率会更高。
在一个实施例中，形成遮挡层30包括：使得遮挡层30上的第一定位部与半导体结构本体10上的第二定位部相对设置，以使通孔31暴露缺口11，即保证遮挡层30上的通孔能够准确暴露相应的缺口11。
需要注意的是，第一定位部与第二定位部相对设置，即第一定位部与第二定位部相互对准。例如，第一定位部与第二定位部可以是结构相同的孔，即保证两个孔相重合，或者第一定位部与第二定位部可以是结构相同的凸起，即两个凸起相重合，或者第一定位部与第二定位部可以分别是凸起和凹槽，凸起和凹槽相适配。
具体的，结合图6所示的，半导体结构本体10上设置有多个晶粒1，且半导体结构本体10上具有第二定位部，第二定位部可以是晶片缺口12(wafer notch)。半导体结构本体10可以表示晶圆，晶圆上可以布满晶粒1，每个晶粒1可以包括一个或多个熔断器阵列组20，晶圆可以是圆形或者矩形，此处不作限定。
遮挡层30上形成有第一定位部，在图6的基础上，将第一定位部与第二定位部相对 设置，从而实现了通孔31对缺口11的暴露。如图7所示，第一定位部可以是覆膜定位孔32，此时覆膜定位孔可以对应晶片缺口12。或者，第一定位部可以是覆膜定位标识33，而半导体结构本体10上设置的第二定位部可以是相应的晶片定位标识15，覆膜定位标识33和晶片定位标识15相对应。
在一些实施例中，遮挡层30上可以形成有覆膜定位孔32和覆膜定位标识33，而半导体结构本体10上可以形成有相应的晶片缺口12和晶片定位标识15，将覆膜定位孔32与晶片缺口12相对应，覆膜定位标识33与晶片定位标识15相对应，从而实现通孔31对缺口11的暴露。
遮挡层30可以是圆形或矩形，此处不作具体限定。遮挡层30可以采用简单的按压方式碰触晶圆表面，也可以考虑采用静电的方式或胶黏合的方式固定于晶圆上。第一定位部和第二定位部相对设置，定位采用激光直接或间接对位。以此形成图7所示的结构，即通孔31可以暴露晶粒1。
在一个实施例中，半导体结构的熔断填充方法还包括：去除遮挡层30；清理密封材料层40的外表面，即在去除遮挡层30形成密封材料层40后，需要对密封材料层40进行清理，以此去除表面的残渣，减小线宽，并减少对其他区域的覆盖。
在一些实施例中，清理密封材料层40的外表面包括：减薄密封材料层40，并减小密封材料层40宽度方向的尺寸。即去除遮挡层30后可以对密封材料层40的厚度和宽度进行减小，以此避免密封材料层40太厚且覆盖范围太大的问题。
具体的，对密封材料层40的外表面进行去残渣、修整以及清洗。
通过灰化(N2/H2/O2或混合气体)或蚀刻修整(Etch trim)的方式去除表面的残渣，减小线宽，及减少对其他区域的覆盖。后续可以通过氩溅射(Ar sputter)或湿法清洗(WET clean)(SPM+SC1+SC2或适用于Al的特殊清洗剂)的方式进一步去除残渣。
针对半导体结构的熔断填充方法的一个具体实施例，如图8至图14所示：
如图8所示，在半导体结构本体10上形成开口13，开口13下方对应熔断器阵列组20的互连结构21。开口13的形成可以在半导体结构本体10上形成掩膜，掩膜覆盖开口13之外的区域，后续可以通过蚀刻或者激光熔断等方式形成开口13。
在图8的基础上，采用激光熔断互连结构21，并在开口13的基础上形成缺口11，如图9所示，此时缺口11暴露在外界环境中。
在图9的基础上，在半导体结构本体10上覆盖遮挡层30，遮挡层30的通孔31暴露缺口11，如图10所示。
具体的，可以采用激光直接或者间接的方式使得遮挡层30上的第一定位部与半导体结构本体10上的第二定位部实现定位。即通孔31的位置与熔断器阵列组20的位置对齐，通孔31的大小可以依据所需密封区域的需求和影响进行确定。如果多个熔断器阵列组20之间的区域不会因密封工艺而受影响，可以考虑将通孔31扩大整个熔断器区域，形成一个大开口，而不是多个独立的岛状结构。
在图10的基础上，在遮挡层30上形成初始密封材料层41，如图11所示，初始密封材料层41覆盖遮挡层30，且填充通孔31和缺口11。
具体的，初始密封材料层41可以是基于环氧树脂材料或聚酰亚胺树脂材料或其他满足要求的树脂材料(膨胀系数，与目标界面的黏合强度和可润湿性，化学稳定性和兼容性，抗湿性和隔绝效果，防静电程度，流动性，涂敷难易性等等)。初始密封材料层41的刷涂方式可以是硬性的刮刀刮涂方式或柔性材料(PP，PVA…)刷子刷涂方式，或者旋转喷涂方式，具体工艺不作限定。
在图11的基础上，去除遮挡层30和覆盖在遮挡层30上的初始密封材料层41，形成如图12所示的结构。
在图12的基础上，通过灰化或Etch trim的方式去除表面的残渣，减小线宽(即最终形成的密封材料层40的顶部宽度变小)，及减少初始密封材料层41对其他区域的覆盖，如图13所示。在图12的基础上，初始密封材料层41的线宽为B，而在进行表面处理后，如图13所示，初始密封材料层41的线宽为C，且C小于B，密封材料层40的最终线宽为C。
在图13的基础上，热固化初始密封材料层41，以形成密封材料层40，如图14所示。
具体的，可以在120℃～400℃温度下进行30min～500min的固化，根据材料属性选择合适的气氛，例如氮气，氩气，水汽，或混合气体等。
本公开的半导体结构的熔断填充方法形成的半导体结构可以隔绝外部危险因素的侵入。
本公开的一个实施例还提供了一种半导体结构，请参考图14，半导体结构包括：半导体结构本体10，半导体结构本体10内形成有多个熔断器阵列组20，半导体结构本体10上形成有缺口11，熔断器阵列组20的互连结构21被熔断；密封材料层40，密封材料层40位于缺口11内。
本公开一个实施例的半导体结构通过在半导体结构本体10的缺口11内填充密封材料层40，从而可以隔绝外部危险因素的侵入，以此改善半导体结构的使用性能。
在一个实施例中，密封材料层40突出半导体结构本体10设置，以覆盖半导体结构本体10的部分上表面，即密封材料层40的顶部面积大于缺口11的开口面积，以此提高防护性能。
在一个实施例中，半导体结构还包括：密封圈50，密封圈50为多个，各个熔断器阵列组20分别位于各个密封圈50内，密封圈50实现了对各个熔断器阵列组20的保护。
在一个实施例中，半导体结构通过上述的半导体结构的熔断填充方法形成。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由前面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种半导体结构的熔断填充方法，包括：
    提供一半导体结构本体，所述半导体结构本体内形成有多个熔断器阵列组；
    熔断所述熔断器阵列组的互连结构，以在所述半导体结构本体上形成缺口；
    在所述半导体结构本体上形成遮挡层，所述遮挡层上形成有暴露所述缺口的通孔；
    在所述缺口内形成密封材料层。
  2. 根据权利要求1所述的半导体结构的熔断填充方法，其中，所述遮挡层由硬质材料制备而成。
  3. 根据权利要求1所述的半导体结构的熔断填充方法，其中，所述遮挡层由高分子材料、陶瓷、或金属材料制备而成。
  4. 根据权利要求1所述的半导体结构的熔断填充方法，其中，熔断多个所述熔断器阵列组，以在所述半导体结构本体上形成多个独立的缺口。
  5. 根据权利要求4所述的半导体结构的熔断填充方法，其中，所述遮挡层上形成有多个所述通孔，多个所述通孔分别暴露多个所述缺口。
  6. 根据权利要求4所述的半导体结构的熔断填充方法，其中，一个所述通孔暴露多个所述缺口。
  7. 根据权利要求1所述的半导体结构的熔断填充方法，其中，所述通孔的面积大于所述缺口的面积，以使所述密封材料层覆盖所述半导体结构本体的部分上表面。
  8. 根据权利要求1至7中任一项所述的半导体结构的熔断填充方法，其中，形成所述密封材料层包括：
    在所述遮挡层上形成初始密封材料层，所述初始密封材料层覆盖所述遮挡层，且填充所述缺口和所述通孔；
    去除所述遮挡层和覆盖所述遮挡层的初始密封材料层，并使得剩余的所述初始密封材料层作为所述密封材料层。
  9. 根据权利要求8所述的半导体结构的熔断填充方法，其中，同步去除所述遮挡层和覆盖所述遮挡层的初始密封材料层。
  10. 根据权利要求9所述的半导体结构的熔断填充方法，其中，在固化形成所述密封材料层之前，通过去除所述遮挡层，以将覆盖所述遮挡层的所述初始密封材料层去除。
  11. 根据权利要求8所述的半导体结构的熔断填充方法，其中，先去除覆盖所述遮挡层 的所述初始密封材料层，然后去除所述遮挡层。
  12. 根据权利要求11所述的半导体结构的熔断填充方法，其中，去除覆盖所述遮挡层的所述初始密封材料层之前，固化所述初始密封材料层。
  13. 根据权利要求1所述的半导体结构的熔断填充方法，其中，形成所述遮挡层包括：
    使得所述遮挡层上的第一定位部与所述半导体结构本体上的第二定位部相对设置，以使所述通孔暴露所述缺口。
  14. 根据权利要求1所述的半导体结构的熔断填充方法，其中，所述半导体结构的熔断填充方法还包括：
    去除所述遮挡层；
    清理所述密封材料层的外表面。
  15. 根据权利要求14所述的半导体结构的熔断填充方法，其中，清理所述密封材料层的外表面包括：
    减薄所述密封材料层。
  16. 根据权利要求15所述的半导体结构的熔断填充方法，其中，清理所述密封材料层的外表面还包括：
    减小所述密封材料层宽度方向的尺寸。
  17. 一种半导体结构，包括：
    半导体结构本体，所述半导体结构本体内形成有多个熔断器阵列组，所述半导体结构本体上形成有缺口，所述熔断器阵列组的互连结构被熔断；
    密封材料层，所述密封材料层位于所述缺口内。
  18. 根据权利要求17所述的半导体结构，其中，所述密封材料层突出所述半导体结构本体设置，以覆盖所述半导体结构本体的部分上表面。
  19. 根据权利要求17所述的半导体结构，其中，所述半导体结构还包括：
    密封圈，所述密封圈为多个，各个所述熔断器阵列组分别位于各个所述密封圈内。
  20. 根据权利要求17所述的半导体结构，其中，所述熔断器阵列组还包括键合焊盘和接触孔，所述互连结构和所述键合焊盘连接，所述互连结构和所述接触孔连接。
PCT/CN2021/109303 2021-02-07 2021-07-29 半导体结构的熔断填充方法及半导体结构 Ceased WO2022166131A1 (zh)

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