CN107256855B - 一种熔断器及其制造方法 - Google Patents
一种熔断器及其制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 148
- 229920005591 polysilicon Polymers 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 18
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- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract description 7
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- 238000010586 diagram Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 3
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
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- 150000003839 salts Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- 239000010937 tungsten Substances 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
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Abstract
本发明公开了一种多晶硅熔断器及其制造方法,该多晶硅熔断器包括多晶硅熔断体和两个引出端口,该多晶硅熔断体包括一衬底、第一绝缘层和一多晶硅熔体,衬底上形成有一凹槽,第一绝缘层覆盖在具有凹槽一侧的衬底表面上,多晶硅熔体形成于第一绝缘层上且位于所述凹槽内呈埋入式形态。本发明将多晶硅熔体以埋入的方式放在衬底的凹槽内,使熔体可以和附近其它器件保持足够的安全距离,有效消除传统熔丝熔断后形成颗粒影响旁边器件的可能性,且能够根据实际需要调节多晶硅熔体的关键尺寸,生成工艺对光刻和干刻的要求不高,使用一般的蚀刻机即可实现。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种埋入式多晶硅熔丝熔断器(fuse)的结构和制造方法。
背景技术
熔断器(fuse)是指当电流超过规定值时,以本身产生的热量使熔体熔断,断开电路的一种电器。熔断器是根据电流超过规定值一段时间后,以其自身产生的热量使熔体(熔丝)熔化,从而使电路断开以制成电流保护器。熔丝技术广泛用于各种可编程逻辑器件(programmable logic device,简称PLD)中,通常,熔丝可以分为铝熔丝和多晶硅熔丝(poly fuse)。多晶硅熔丝以其易熔化性在小电流的情况下非常适用。
目前,现有技术中的多晶硅熔丝(poly fuse)通常是平面设计的。请参阅图1,图1示出了现有技术中多晶硅熔丝熔断器的结构示意图;如图所示,标号1表示为熔断位置,标号2和3表示为引出端口;标号1处的两条横线示意为熔断体,可以称为多晶硅熔丝或熔片。
标号2和3处阵列设置的小矩形框示意为通孔(contact),为了防止熔丝熔断时不会烧坏通孔,通孔数量通常设置为多个,熔断器通过标号2和标号3处的通孔接入电路;为了与标号1处熔丝电气连通以及保持电流均一性,标号2和标号3处的大矩形板与1处熔丝为同性材料,均为多晶硅;其中,熔断体1与引出端口2和3位于同一个平面中。
上述熔断器的工作原理为:当标号3处流入标号1处的电流超过规定值时,熔丝熔断,切断标号2和标号3接的电路,从而保护标号2引出端连接的器件不受过电流损坏。然而,上述熔断器存在一个问题:熔丝烧断的瞬间会产生颗粒影响Y向上附近其它器件的工作。
此外,熔断器的原理是利用熔体(如熔丝或熔片等)高阻值和低熔点的特性,当通过熔体的电流达到一定时,电阻越大,其自身产生的热量越多,温度更快地到达熔点使熔丝熔断,即熔断时间越短。因此,通过调整熔体的电阻值,能达到不同的熔断目的。根据电阻公式R=ρL/S,其中ρ为电阻率,一般由导体材料决定,L为导体长度,S为导体横截面积,当熔体的材料、长度L一定时,横截面积S越小,阻值越大。
请参阅图2,图2示出了一种多晶硅熔丝结构示意图。如图所示,假设该多晶硅熔丝的电流方向为b,即多晶硅熔丝的导体长度L方向,那么,横截面积S取决于熔丝的宽度a和高度c;由于多晶硅熔丝必须有一定高度,因此,在工艺上,通常将多晶硅熔丝宽度a作为关键尺寸(critical dimension)去调节,从而改变多晶硅熔丝阻值,控制多晶硅熔丝的熔断时间。
然而,要使多晶硅熔丝宽度a达到例如60nm及以下时,就必须使用高端光刻机,而此类光刻机的价格非常昂贵,会大大增加生产成本。
发明内容
本发明的目的在于克服现有技术存在的上述缺陷,提供一种多晶硅熔断器及其制造工艺,将多晶硅熔体埋入衬底的凹槽内,使熔体在熔断时喷射的颗粒被凹槽阻挡,从而有效避免或减少熔断颗粒对附近位于衬底上的其他器件的影响,且能够根据需要低成本地对多晶硅熔体的关键尺寸进行调节。
为实现上述目的,本发明的技术方案如下:
一种多晶硅熔断器,包括多晶硅熔断体和两个引出端口;其特征在于,所述多晶硅熔断体包括一衬底、第一绝缘层和一多晶硅熔体,所述衬底上形成有一凹槽,所述第一绝缘层覆盖在具有凹槽一侧的衬底表面上,所述多晶硅熔体形成于第一绝缘层上且位于所述凹槽内呈埋入式形态。
进一步地,所述凹槽包括凹槽开口、槽壁和与凹槽开口相对的凹槽槽底,所述凹槽开口的宽度大于所述凹槽槽底的宽度。
进一步地,所述凹槽包括槽壁和与凹槽开口相对的槽底,位于所述凹槽槽底的第一绝缘层上的所述多晶硅熔体具有绝缘侧壁。
进一步地,所述多晶硅熔体位于槽底的第一绝缘层上且与两侧槽壁间隔一定距离。
进一步地,所述熔体宽度小于熔体长度;其中,所述多晶硅熔体电流流向方向上的间距为熔体长度,所述多晶硅熔体顶部与槽底上第一绝缘层的间距为熔体高度,与熔体长度和熔体高度均垂直的间距为熔体宽度。
进一步地,所述多晶硅熔体的宽度为55nm-300nm。
进一步地,所述多晶硅熔体的顶部形成有金属硅化物层。
为实现上述目的,本发明还包括技术方案如下:
一种多晶硅熔断器的制造方法,包括以下步骤:
步骤N1:在衬底上进行沟槽刻蚀,形成一凹槽;在具有凹槽一侧的衬底表面形成第一绝缘层;
步骤N2:在覆盖有第一绝缘层的衬底上形成多晶硅熔体膜层;
步骤N3:在多晶硅熔体膜层上形成第二绝缘层;
步骤N4:对第二绝缘层和多晶硅熔体膜层进行显影和刻蚀,在凹槽内形成多晶硅熔体。优选地,对所述第二绝缘层和多晶硅熔体膜层进行各向同性刻蚀。
进一步地,所述步骤N5包括:通过湿法刻蚀法去除多晶硅熔体上的第二绝缘层。
进一步地,还包括步骤N6:在多晶硅熔体两侧形成绝缘侧墙。
进一步地,所述的熔断器结构的制造方法还包括步骤N7:对多晶硅熔体进行自对准硅化物刻蚀,在熔体顶端形成金属硅化物层。
从上述技术方案可以看出,本发明提供了一种埋入式的多晶硅熔断器及其制造方法,将多晶硅熔体以埋入的方式放在衬底的凹槽内,使熔体可以和附近其它器件保持足够的安全距离,有效消除传统熔丝熔断后形成颗粒影响旁边器件的可能性,且能够根据需要对多晶硅熔体的关键尺寸进行有效调节,使用一般的光刻机即能达到55nm-300nm的刻蚀精度,有效节省生产成本。
附图说明
图1为现有技术中多晶硅熔丝熔断器的结构示意图
图2为一种导体的示意图
图3为本发明熔断器中熔断体一较佳实施例的结构示意图
图4为本发明熔断器中两个熔断体的立体结构示意图
图5为本发明熔断器中熔断体的制程示意图
图6为本发明中多晶硅熔体宽度与干刻刻蚀时间的关系图
图7为本发明熔断器中熔断体Y向上与旁边其他器件的关系示意图
具体实施方式
下面结合附图,对本发明的具体实施方式作进一步的详细说明。
需要说明的是,在下述的具体实施方式中,为了清楚地表示本发明的结构以便于说明,附图中的结构不依照一般比例绘图,并进行了局部放大、变形及简化处理,因此,应避免以此作为对本发明的限定来加以理解。
请参阅图3,图3为本发明多晶硅熔断器中熔断体一较佳实施例的剖面结构示意图。在本发明的实施例中,与现有技术相同的是,该多晶硅熔断器包括多晶硅熔断体和两个引出端口,多晶硅熔断体和两个引出端口位于具有绝缘层的衬底上。
多晶硅熔断体通常为多晶硅熔丝或熔片,多晶硅熔断体相连在两个引出端口相连之间;两个引出端口通常为两个大矩形板,在每个大矩形板阵列设置的小矩形通孔(contact)。为了防止多晶硅熔丝熔断时不会烧坏通孔,小矩形通孔数量通常设置为多个,多晶硅熔断器通过两个引出端口的通孔接入电路;为了多晶硅熔丝电气连通以及保持电流均一性,两个引出端口的大矩形板与熔丝为同性材料,均为多晶硅。
在本发明的实施例中,与现有技术不同的是,熔断体与两个引出端口不位于同一个平面中。具体地,该熔断体包括一衬底1、第一绝缘层2和一多晶硅熔体3,衬底1上形成有一凹槽4,第一绝缘层2覆盖在具有凹槽4一侧的衬底1表面上,多晶硅熔体3形成于第一绝缘层2上且位于凹槽4内呈埋入式形态。
在本实施例中,衬底1可以为硅衬底,第一绝缘层2可以为二氧化硅或者氮化硅等绝缘层,多晶硅熔体3由多晶硅经刻蚀而形成;凹槽4包括凹槽开口、槽壁和与凹槽开口相对的槽底,较佳地,在工艺的形成过程中,通常将凹槽4的槽口制作成宽于与凹槽4的槽底的形状,即凹槽开口的宽度大于凹槽槽底的宽度。
如图3所示,多晶硅熔体3位于将凹槽4的槽底的第一绝缘层2上,且与两侧槽壁间隔一定距离。
请参阅图4,图4是本发明熔断器中两个熔断体的立体结构示意图。在本发明的实施例中,多晶硅熔体3可刻蚀成长方体结构,图4中,多晶硅熔体3的电流方向为b的方向,若将多晶硅熔体3看作一导体,则b为图2中的导体长度L,那么,横截面积S取决于熔体的宽度a和高度c;由于多晶硅必须有一定高度,因此,在工艺上,通常将多晶硅熔体宽度a作为关键尺寸(critical dimension)去调节,从而改变多晶硅熔体阻值,控制多晶硅熔体的熔断时间。
因此,在本发明的实施例中,可扩展地,多晶硅熔体3在多晶硅熔丝宽度a方向可以通过延展到靠近槽壁或与两侧槽壁均接触,也可以位于槽底但只与一侧槽壁或靠近或相接触,以达到预期的减少熔断时熔丝颗粒喷射的目的。多晶硅熔体3的高度c可以根据需要高出第一绝缘层2、与第一绝缘层2平齐或低于第一绝缘层2。
在本发明的一个较佳的实施例中,多晶硅熔体3的宽度a小于多晶硅熔体3的长度b。多晶硅熔体3的宽度(即多晶硅熔体的关键尺寸)a可根据实际需要在55nm-1μm的范围内进行调节。较佳地,该多晶硅熔体3的宽度取值范围可以为55nm-300nm。
进一步地,多晶硅熔体3顶部可以具有金属硅化物层5,用以降低多晶硅熔体的电阻,使通过多晶硅熔体的电流更均匀,增强熔断可控性。金属硅化物可以为镍硅化合物或钨硅化合物等金属与多晶硅反应物。
下面通过图5对本发明的埋入式多晶硅熔丝熔断器(fuse)的制造方法进行详细说明。请参阅图5,图5是本发明埋入式多晶硅熔丝熔断器中熔断体制造方法的工艺步骤所形成的剖面示意图。
一种熔断器的制造方法,包括以下步骤:
步骤N1:在衬底1上进行沟槽刻蚀,形成凹槽4;在具有凹槽4一侧的衬底1表面形成第一绝缘层2;
步骤N2:在覆盖有第一绝缘层2的衬底1上形成多晶硅熔体膜层(poly);
步骤N3:在多晶硅熔体膜层上形成第二绝缘层;
步骤N4:对第二绝缘层和多晶硅熔体膜层进行显影和刻蚀,刻蚀后在凹槽4内保留一定高度的多晶硅熔体膜形成多晶硅熔体3。
在本实施例中,步骤N1中的沟槽刻蚀包括先进行光刻工艺形成图案化的光阻胶层为掩膜,再进行干刻刻蚀,形成沟槽;
步骤N1和N3中,绝缘层的形成可通过炉管或其他常规手段实现;
优选地,步骤N2包括:通过化学气相沉淀法在衬底的第一绝缘层上形成一定高度的多晶硅熔体膜层。
步骤N3中第二绝缘层包括:先在多晶硅熔体上形成一层氮化硅(SiN)膜6,在氮化硅膜6上形成二氧化硅膜7,或者第二绝缘层仅为氮化硅膜或二氧化硅膜或其他绝缘膜均可,作为刻蚀阻挡层;由图5可以看到,由于多晶硅沉积于具有凹槽的衬底的第一绝缘层表面,多晶硅熔体膜层的上表面形成有一凹形开口,工艺上也可以做到没有凹形开口,氮化硅膜6覆盖于多晶硅熔体膜层的上表面,随其形状一起形成该凹形开口,二氧化硅7覆盖于氮化硅膜6上,填平或不完全填平该凹形开口对后续工艺没有实质影响。
步骤N4包括:对第二绝缘层进行显影形成腌膜8,对腌膜8下的第二绝缘层和多晶硅熔体膜层借助进行各向同性刻蚀干刻工艺;当然也可以采用各向异性刻蚀工艺,进行特定方向的蚀刻,形成垂直的轮廓,但因为各向异性刻蚀的刻蚀宽度取决于光罩尺寸,刻蚀宽度越小,须选用的相应小尺寸的光罩,光罩价格就越贵,而各向同性刻蚀则可以选用尺寸较大、价格相对较低的光罩,实现小宽度刻蚀,更有利于降低成本;
请参阅图6。图6为本发明中多晶硅熔体宽度与干刻刻蚀时间的关系图。通过实验数据采集和拟合,发现本发明中多晶硅熔体宽度a与刻蚀时间接近线性关系,即刻蚀时间越长,多晶硅熔体的关键尺寸越小,刻蚀60nm大概需要30秒左右。
可选地,还包括步骤N5:通过湿法刻蚀法去除多晶硅熔体上的第二绝缘层;第二绝缘层也可以不去除,但如需执行步骤N6则必须要去除;
可选地,还包括步骤N6:在多晶硅熔体3两侧形成绝缘侧墙9(spacer);若执行步骤N6,不加绝缘侧墙9,会导致金属覆盖物(金属硅化物层5)短路。侧墙9可以是二氧化硅或氮化硅等绝缘材料通过化学/物理气相沉积而成。
可选地,还包括步骤N7:对多晶硅熔体进行自对准硅化物刻蚀,在熔体顶端形成金属硅化物,金属硅化物是金属诸如镍、钨与多晶硅反应形成合金体,目的是降低多晶硅阻值,使通过熔丝的电流更均匀,增加熔断可控性。
以上工艺步骤对光刻和干刻的要求不高,使用一般的蚀刻机即能达到55nm-300nm的刻蚀精度,有效节省生产成本。本发明的刻蚀工艺使用一般的光刻机和干刻机可实现,使宽度a达到55nm-60nm,60nm-300nm的精度。
请参阅图7。图7为本发明熔断器中熔断体Y向上与旁边其他器件的关系示意图。可以看到,由于多晶硅熔体埋入衬底的凹槽内,而非完全露出于衬底上,因而在熔断时喷射的颗粒不会影响左侧其他器件如MOS管的工作。
以上所述的仅为本发明的优选实施例,所述实施例并非用以限制本发明的专利保护范围,因此凡是运用本发明的说明书及附图内容所作的等同结构变化,同理均应包含在本发明的保护范围内。
Claims (9)
1.一种多晶硅熔断器,包括多晶硅熔断体和两个引出端口;其特征在于,所述多晶硅熔断体包括一衬底、第一绝缘层和一多晶硅熔体,所述衬底上形成有一凹槽,所述第一绝缘层覆盖在具有凹槽一侧的衬底表面上,所述多晶硅熔体仅形成于凹槽底部的第一绝缘层上且位于所述凹槽内呈埋入式形态;所述多晶硅熔体宽度小于多晶硅熔体长度;其中,所述多晶硅熔体电流流向方向上的间距为多晶硅熔体长度,所述多晶硅熔体顶部与槽底上第一绝缘层的间距为多晶硅熔体高度,与多晶硅熔体长度和多晶硅熔体高度均垂直的间距为多晶硅熔体宽度,通过调节多晶硅熔体宽度来改变多晶硅熔体阻值,控制多晶硅熔体的熔断时间。
2.根据权利要求1所述的多晶硅熔断器,其特征在于,所述凹槽包括凹槽开口、槽壁和与凹槽开口相对的凹槽槽底,所述凹槽开口的宽度大于所述凹槽槽底的宽度。
3.根据权利要求1所述的多晶硅熔断器,其特征在于,所述凹槽包括槽壁和与凹槽开口相对的槽底,位于所述凹槽槽底的第一绝缘层上的所述多晶硅熔体具有绝缘侧壁。
4.根据权利要求1所述的多晶硅熔断器,其特征在于,所述多晶硅熔体位于槽底的第一绝缘层上且与两侧槽壁间隔一定距离。
5.根据权利要求1所述的多晶硅熔断器,其特征在于,所述多晶硅熔体的顶部形成有金属硅化物层。
6.一种根据权利要求1所述的多晶硅熔断器的制造方法,其特征在于,包括以下步骤:
步骤N1:在衬底上进行沟槽刻蚀,形成一凹槽;在具有凹槽一侧的衬底表面形成第一绝缘层;
步骤N2:在覆盖有第一绝缘层的衬底上形成多晶硅熔体膜层;
步骤N3:在多晶硅熔体膜层上形成第二绝缘层;
步骤N4:对第二绝缘层和多晶硅熔体膜层进行显影和刻蚀,仅在凹槽底部的第一绝缘层上形成多晶硅熔体;所述多晶硅熔体宽度小于多晶硅熔体长度;其中,所述多晶硅熔体电流流向方向上的间距为多晶硅熔体长度,所述多晶硅熔体顶部与槽底上第一绝缘层的间距为多晶硅熔体高度,与多晶硅熔体长度和多晶硅熔体高度均垂直的间距为多晶硅熔体宽度,通过调节多晶硅熔体宽度来改变多晶硅熔体阻值,控制多晶硅熔体的熔断时间。
7.根据权利要求6所述的制造方法,其特征在于,还包括步骤N5包括:通过湿法刻蚀法去除多晶硅熔体上的第二绝缘层。
8.根据权利要求7所述的制造方法,其特征在于,还包括步骤N6:在多晶硅熔体两侧形成绝缘侧墙。
9.根据权利要求8所述的制造方法,其特征在于,还包括步骤N7:对多晶硅熔体进行自对准硅化物刻蚀,在熔体顶端形成金属硅化物层。
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