WO2022165895A1

WO2022165895A1 - Semiconductor epitaxial structure and manufacturing method therefor, and led chip

Info

Publication number: WO2022165895A1
Application number: PCT/CN2021/079038
Authority: WO
Inventors: 林志伟; 陈凯轩; 蔡建九; 卓祥景; 尧刚
Original assignee: 厦门乾照光电股份有限公司
Priority date: 2021-02-07
Filing date: 2021-03-04
Publication date: 2022-08-11
Also published as: CN112768578A

Abstract

The present invention provides a semiconductor epitaxial structure and a manufacturing method therefor, and an LED chip. A cooling layer and a deep well layer are sequentially disposed on the side surface of at least one barrier layer close to a first-type semiconductor layer, and a shallow well layer and a heating layer are sequentially disposed on the side surface of the at least one barrier layer close to a second-type semiconductor layer. The cooling layer and the heating layer are used for growth temperature transition between the barrier layer and a potential well layer, and the deep well layer and the shallow well layer are used for electron confinement to the barrier layer. By controlling the growth temperature, the stress between the barrier layer and the potential well layer can be effectively released; in addition, further forming well structures on front and rear ends of the potential well layer facilitates enhancing the electron confinement to the barrier layer, thereby improving the quantum efficiency in the barrier layer.

Description

A kind of semiconductor epitaxial structure and its manufacturing method, LED chip

This application claims the priority of the Chinese patent application filed on February 7, 2021 with the State Intellectual Property Office of China, the application number is CN202110176774.X, and the invention name is "a semiconductor epitaxial structure and its production method, LED chip", which The entire contents of this application are incorporated by reference.

technical field

The invention relates to the field of light emitting diodes, in particular to a semiconductor epitaxial structure, a manufacturing method thereof, and an LED chip.

Background technique

Light Emitting Diode (English: Light Emitting Diode, referred to as: LED) is a semiconductor electronic component that can emit light. LED has the advantages of high efficiency, long life, small size, low power consumption, etc., and can be used in indoor and outdoor white light lighting, screen display, backlight and other fields. In the development of the LED industry, gallium nitride (GaN)-based materials are typical representatives of V-III compound semiconductors, and improving the optoelectronic properties of GaN-based LEDs has become the key to the semiconductor lighting industry.

Epitaxial wafers are the primary finished products in the LED fabrication process. The existing GaN-based LED epitaxial wafer includes a substrate, an N-type semiconductor layer, an active region and a P-type semiconductor layer. The substrate is used to provide a growth surface for the epitaxial material, the N-type semiconductor layer is used to provide electrons for recombination emission, the P-type semiconductor layer is used to provide holes for recombination emission, and the active region is used to radiate electrons and holes Compound luminescence.

In the GaN-based semiconductor light-emitting epitaxial structure in the prior art, in the growth process of the quantum well light-emitting layer, the InGaN well layer is usually stacked on the GaN barrier layer. However, due to the lattice mismatch between InGaN and GaN, GaN When the InGaN well layer is grown on the barrier layer, dislocation defects will be generated in the InGaN well layer, which reduces the luminous efficiency of the entire quantum well light-emitting layer.

In view of this, the inventor specially designed a semiconductor epitaxial structure, a method for manufacturing the same, and an LED chip, and this case came into being.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a semiconductor epitaxial structure, a manufacturing method thereof, and an LED chip to solve the problem of large lattice mismatch between the well layer and the barrier layer, and the There is a large lattice mismatch, which leads to the problem that the stress generated by the accumulation of lattice mismatch will seriously affect the recombination efficiency of electrons and holes in space.

In order to achieve the above object, the technical scheme adopted in the present invention is as follows:

A semiconductor epitaxial structure, comprising:

substrate;

A first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence on the surface of the substrate;

The active region includes alternately stacked barrier layers and potential well layers, and at least one side surface of the barrier layer close to the first type semiconductor layer is sequentially provided with a cooling layer and a deep well layer, and at least one side surface of the barrier layer is provided with a cooling layer and a deep well layer. A shallow well layer and a temperature rise layer are arranged on the surface of the barrier layer close to the second type semiconductor layer in sequence; wherein, the temperature drop layer and the temperature rise layer are used for the growth temperature transition between the barrier layer and the potential well layer ; The deep well layer and the shallow well layer are used for electron confinement of the barrier layer.

Preferably, during the growth process of the deep well layer, the growth temperature of the deep well layer is lowered from the growth temperature of the cooling layer to lower than the growth temperature of the potential well layer; during the growth process of the shallow well layer, the growth temperature The growth temperature of the potential well layer is increased to the growth temperature of the elevated temperature layer.

Preferably, the growth temperature of the temperature-raising layer is lower than the growth temperature of the barrier layer.

Preferably, the deep well layer and the shallow well layer respectively comprise _AlxGayInzN material layers with graded In composition, wherein 0≤x≤1, _0≤y≤1 , _0≤z≤1 ; Further, it can be an AlGaInN material layer or a GaInN material layer.

Preferably, the deep well layer and the shallow well layer include material layers with graded forbidden band widths, and the forbidden band width of the shallow well layer is always larger than that of the potential well layer, and the deep well layer The local forbidden band width of is smaller than the forbidden band width of the potential well layer.

Preferably, the heating layer and the cooling layer respectively include undoped material layers, the deep well layer and the shallow well layer respectively include P-type doped material layers, and the doping concentration is not higher than 5*10 ¹⁷ cm ^-3 .

Preferably, the heating layer and the cooling layer respectively include an Al _a Ga _b N material layer, wherein 0≤a≤1, 0≤b≤1; further, it may be an AlGaN material layer or a GaN material layer.

Preferably, the thickness of the potential well layer is 3 times or more than the thickness of the deep well layer or the shallow well layer.

Preferably, the thicknesses of the deep well layer and the shallow well layer are both 0-10 nm.

Preferably, the thickness of the barrier layer is 4 times or more than the thickness of the heating layer or the cooling layer.

Preferably, the thicknesses of the heating layer and the cooling layer are both 0-20 nm.

Preferably, the barrier layer is doped with n-type impurities.

The present invention also provides a method for fabricating a semiconductor epitaxial structure, the fabrication method comprising the following steps:

Step S01, providing a substrate;

Step S02, growing a first-type semiconductor layer, an active region, and a second-type semiconductor layer on the surface of the substrate in sequence;

The active region includes alternately stacked barrier layers and potential well layers, and at least one side surface of the barrier layer close to the first type semiconductor layer is sequentially provided with a cooling layer and a deep well layer, and at least one side surface of the barrier layer is provided with a cooling layer and a deep well layer. A shallow well layer and a temperature rise layer are arranged on the surface of the barrier layer close to the second type semiconductor layer in sequence; wherein, the temperature drop layer and the temperature rise layer are used for the growth temperature transition between the barrier layer and the potential well layer ; The deep well layer and the shallow well layer are used for electron confinement to the barrier layer;

Further, the deep well layer and the shallow well layer respectively comprise _AlxGayInzN material layers with graded In composition, wherein 0≤x≤1, _0≤y≤1 , _0≤z≤1 ; The heating layer and the cooling layer respectively comprise Al _a Ga _b N material layers, wherein 0≤a≤1, 0≤b≤1.

The present invention also provides an LED chip, comprising an epitaxial layer, an N-type electrode and a P-type electrode, wherein the epitaxial layer includes the semiconductor epitaxial structure described in any one of the above.

It can be seen from the above technical solutions that, in the semiconductor epitaxial structure provided by the present invention, at least one barrier layer is provided with a cooling layer and a deep well layer in sequence on the side surface of at least one barrier layer close to the first type semiconductor layer. A shallow well layer and a heating layer are sequentially arranged on the surface of one side close to the second type semiconductor layer; wherein, the cooling layer and the heating layer are used for the growth temperature transition between the potential barrier layer and the potential well layer; so The deep well layer and the shallow well layer are used for electron confinement for the barrier layer; further, during the growth process of the deep well layer, the growth temperature of the deep well layer is reduced from the growth temperature of the cooling layer to a temperature lower than the temperature of the cooling layer. The growth temperature of the potential well layer; during the growth process of the shallow well layer, the growth temperature of the shallow well layer is increased from the growth temperature of the potential well layer to the growth temperature of the elevated temperature layer. By controlling the growth temperature, the stress between the barrier layer and the potential well layer can be effectively released; at the same time, well-like structures are further formed at the front and rear ends of the potential well layer, which is beneficial to strengthen the electron confinement of the barrier layer, thereby improving its performance. Internal quantum efficiency.

Secondly, through: the heating layer and the cooling layer respectively include non-doped material layers, the deep well layer and the shallow well layer respectively include P-type doped material layers, and the doping concentration is not higher than 5*10 ¹⁷ cm ⁻³ The deep well layer and the shallow well layer respectively include P-type doped material layers, and the doping concentration is not higher than 5*10 ¹⁷ cm ⁻³ ; on the one hand, the active region is grown The formed V-pits structure combines the micro-doped P-type impurities in the deep well layer and the shallow well layer, which can effectively deal with different crystal interface energies, and effectively release the potential well layer and the potential barrier layer during the growth process of the deep well layer and the shallow well layer. On the other hand, it can effectively increase the number of holes in the active region, and avoid the newly formed built-in electric field in the active region, thereby effectively improving the internal quantum efficiency of the active region.

Furthermore, the thickness of the potential well layer is 3 times or more than the thickness of the deep well layer or the shallow well layer, and the thickness of the potential barrier layer is 4 times or more than the thickness of the heating layer or the cooling layer. ; While avoiding the poor crystal quality of the active region as a whole due to the too small thickness of the barrier layer; effectively release the stress between the potential well layer and the barrier layer during the growth process of the deep well layer and the shallow well layer , and increase the number of holes in the active region.

It can be known from the above technical solutions that the manufacturing method of the semiconductor epitaxial structure provided by the present invention achieves the beneficial effects of the above semiconductor epitaxial structure, and at the same time, the manufacturing process is simple and convenient, and it is convenient for production.

It can be seen from the above technical solutions that the LED chip provided by the present invention is obtained on the basis of the above-mentioned semiconductor epitaxial structure. Therefore, it has the beneficial effects of the above-mentioned semiconductor epitaxial structure, and at the same time, its process is simple and convenient, and it is convenient for production.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

FIG. 1 is a schematic structural diagram of a semiconductor epitaxial structure provided by an embodiment of the present invention;

2 is a schematic structural diagram of an active region of a semiconductor epitaxial structure provided by an embodiment of the present invention;

3 is a schematic diagram showing the relationship between the growth temperatures of each constituent layer in the active region according to an embodiment of the present invention;

4 is a schematic diagram illustrating the relationship between the potential barrier heights of each constituent layer in the active region according to an embodiment of the present invention;

Description of symbols in the figure: 1, substrate, 2, first-type semiconductor layer, 3, active region, 31, cooling layer, 32, deep well layer, 33, potential well layer, 34, shallow well layer, 35, temperature rise layer, 36, barrier layer, 4, second type semiconductor layer, 5, buffer layer, Q1, barrier height of well layer, Q2, barrier height of barrier layer, T1, growth temperature of well layer, T2, the growth temperature of the barrier layer.

Detailed ways

In order to make the content of the present invention clearer, the content of the present invention will be further described below with reference to the accompanying drawings. The present invention is not limited to this specific embodiment. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in Figure 1 and Figure 2, a semiconductor epitaxial structure includes:

substrate 1;

A first-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer 4 stacked in sequence on the surface of the substrate 1;

The active region 3 includes alternately stacked barrier layers 36 and potential well layers 33, and at least one side surface of the barrier layer 36 close to the first-type semiconductor layer 2 is sequentially provided with a cooling layer 31 and a deep well layer 32, at least A shallow well layer 34 and a heating layer 35 are sequentially provided on a surface of the barrier layer 36 near the second-type semiconductor layer 4; wherein, the cooling layer 31 and the heating layer 35 are used for the connection between the barrier layer 36 and the potential well layer 33. The growth temperature transition between the two; the deep well layer 32 and the shallow well layer 34 are used for electron confinement on the barrier layer 36 .

It is worth mentioning that the type of the substrate 11 is not limited in the semiconductor epitaxial structure of this embodiment. For example, the substrate 11 may be, but not limited to, a sapphire substrate 1, a silicon substrate 1, and the like. In addition, the specific material types of the first-type semiconductor layer 22, the active region 33, and the second-type semiconductor layer 45 may not be limited in the semiconductor epitaxial structure of this embodiment. For example, the first-type semiconductor layer 2 may be but not limited to Limited to the gallium nitride layer, correspondingly, the second type semiconductor layer 4 may be, but not limited to, the gallium nitride layer.

In this embodiment, a buffer layer 5 may also be provided between the substrate 1 and the first-type semiconductor layer 2 .

As shown in FIG. 3 , in this embodiment, during the growth process of the deep well layer 32 , the growth temperature of the deep well layer 32 is lowered from the growth temperature of the cooling layer 31 to lower than the growth temperature T1 of the potential well layer 33 ; the shallow well layer 34 is grown during the growth process. Among them, its growth temperature is raised from the growth temperature T1 of the potential well layer 33 to the growth temperature of the temperature rise layer 35 .

It should be noted that FIG. 3 is a schematic diagram showing the relationship between the growth temperature of each constituent layer in the active region 3 provided in this embodiment, which only illustrates the linear change of the growth temperature of each constituent layer in the active region 3 , this embodiment does not limit the specific temperature and its change trend in the growth process of the cooling layer 31, the deep well layer 32, the potential well layer 33, the shallow well layer 34, the heating layer 35, and the potential barrier layer 36, which can be linear or nonlinear. Meanwhile, the temperature difference between the growth temperature of the deep well layer 32 and the potential well layer 33 is not limited in this embodiment, as long as the temperature difference transition is realized and the stress between the potential barrier layer 36 and the potential well layer 33 is effectively released.

As shown in FIG. 3 , in this embodiment, the growth temperature of the heating layer 35 is lower than the growth temperature T2 of the barrier layer 36 . It should be noted that this embodiment does not limit the temperature difference between the growth temperatures of the heating layer 35 and the barrier layer 36, as long as the growth temperature transition between the two can be achieved while ensuring the growth quality.

In this embodiment, the deep well layer 32 and the shallow well layer 34 respectively include _AlxGayInzN material layers with graded In composition, wherein 0≤x≤1, _0≤y≤1 , _0≤z≤1 ; Further, it can be an AlGaInN material layer or a GaInN material layer.

As shown in FIG. 4 , in this embodiment, the deep well layer 32 and the shallow well layer 34 include material layers with gradual forbidden band widths, and the forbidden band width of the shallow well layer 34 is always larger than that of the potential well layer 33 . The local forbidden band width of the well layer 32 is smaller than that of the potential well layer 33 .

It should be noted that FIG. 4 is a schematic diagram showing the relationship between the potential barrier heights of each constituent layer in the active region 3 according to the embodiment of the present invention, which merely illustrates the linearity of the energy band relationship of each constituent layer in the active region 3 by way of example. This embodiment does not limit the specific energy band values and their changing trends during the growth of the cooling layer 31 , the deep well layer 32 , the potential well layer 33 , the shallow well layer 34 , the heating layer 35 , and the potential barrier layer 36 . , which can be linear or nonlinear.

In this embodiment, the heating layer 35 and the cooling layer 31 respectively include undoped material layers, the deep well layer 32 and the shallow well layer 34 respectively include P-type doped material layers, and the doping concentration is not higher than 5*10 ¹⁷ cm ^-3 .

In this embodiment, the heating layer 35 and the cooling layer 31 respectively include Al _a Ga _b N material layers, wherein 0≤a≤1, 0≤b≤1; further, they may be AlGaN material layers or GaN material layers.

In this embodiment, the thickness of the potential well layer 33 is three times or more the thickness of the deep well layer 32 or the shallow well layer 34 .

In this embodiment, the thicknesses of the deep well layer 32 and the shallow well layer 34 are both 0-10 nm.

In this embodiment, the thickness of the barrier layer 36 is 4 times or more than the thickness of the heating layer 35 or the cooling layer 31 .

In this embodiment, the thicknesses of the heating layer 35 and the cooling layer 31 are both 0-20 nm.

In this embodiment, the barrier layer 36 is doped with n-type impurities.

This embodiment also provides a method for fabricating a semiconductor epitaxial structure, and the fabrication method includes the following steps:

Step S01, providing a substrate 1;

Step S02, growing a buffer layer 5, a first-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer 4 on the surface of the substrate 1 in sequence;

The active region 3 includes alternately stacked barrier layers 36 and potential well layers 33, and at least one side surface of the barrier layer 36 close to the first-type semiconductor layer 2 is sequentially provided with a cooling layer 31 and a deep well layer 32, at least A shallow well layer 34 and a heating layer 35 are sequentially provided on a surface of the barrier layer 36 near the second-type semiconductor layer 4; wherein, the cooling layer 31 and the heating layer 35 are used for the connection between the barrier layer 36 and the potential well layer 33. The growth temperature transition between the deep well layer 32 and the shallow well layer 34 is used for electron confinement on the barrier layer 36;

Further, the deep well layer 32 and the shallow well layer 34 respectively comprise _AlxGayInzN material layers with graded In composition, wherein 0≤x≤1, _0≤y≤1 , _0≤z≤1 ; preferably The ground can be an AlGaInN material layer or a GaInN material layer;

The heating layer 35 and the cooling layer 31 respectively include an Al _a Ga _b N material layer, wherein 0≤a≤1, 0≤b≤1; preferably, it can be an AlGaN material layer or a GaN material layer;

In this embodiment, during the growth process of the deep well layer 32, the growth temperature is lowered from the growth temperature of the cooling layer 31 to lower than the growth temperature of the potential well layer 33; during the growth process of the shallow well layer 34, the growth temperature is reduced from the potential well layer 33 to a lower temperature. The growth temperature of the well layer 33 is raised to the growth temperature of the temperature-raising layer 35 .

In this embodiment, the growth temperature of the heating layer 35 is lower than the growth temperature of the barrier layer 36 .

This embodiment also provides an LED chip, which includes an epitaxial layer, an N-type electrode and a P-type electrode, and the epitaxial layer includes any one of the semiconductor epitaxial structures described above.

It can be seen from the above technical solutions that the semiconductor epitaxial structure provided in this embodiment is provided with a cooling layer 31 and a deep well layer 32 in sequence on at least one side surface of the barrier layer 36 close to the first-type semiconductor layer 2, at least one The side surface of the barrier layer 36 close to the second type semiconductor layer 4 is sequentially provided with a shallow well layer 34 and a heating layer 35; The growth temperature transitions; the deep well layer 32 and the shallow well layer 34 are used for electron confinement of the barrier layer 36; further, during the growth process of the deep well layer 32, the growth temperature of the deep well layer 32 is reduced from the growth temperature of the cooling layer 31 to lower than The growth temperature of the potential well layer 33 ; during the growth process of the shallow well layer 34 , the growth temperature thereof increases from the growth temperature of the potential well layer 33 to the growth temperature of the temperature-raising layer 35 . By controlling the growth temperature, the stress between the barrier layer 36 and the potential well layer 33 can be effectively released; at the same time, well structures are further formed at the front and rear ends of the potential well layer 33 , which is beneficial to strengthen the electron confinement of the barrier layer 36 , thereby increasing its internal quantum efficiency.

Secondly, through: the heating layer 35 and the cooling layer 31 respectively include non-doped material layers, the deep well layer 32 and the shallow well layer 34 respectively include P-type doped material layers, and the doping concentration is not higher than 5*10 ¹⁷ cm ^-3 The deep well layer 32 and the shallow well layer 34 respectively include P-type doped material layers, and the doping concentration is not higher than 5*10 ¹⁷ cm ^-3 ; The -pits structure combines the micro-doped P-type impurities of the deep well layer 32 and the shallow well layer 34, which can effectively deal with different crystal interface energies and effectively release the deep well layer 32 and the shallow well layer 34 during the growth process. The potential well layer 33, the potential On the other hand, the number of holes in the active region 3 can be effectively increased, and a built-in electric field can be prevented from being newly formed in the active region 3 , thereby effectively improving the internal quantum efficiency of the active region 3 .

Furthermore, the thickness of the potential well layer 33 is three times or more the thickness of the deep well layer 32 or the shallow well layer 34, and the thickness of the potential barrier layer 36 is four times or more the thickness of the heating layer 35 or the cooling layer 31; While avoiding that the thickness of the barrier layer 36 is too small to cause the overall crystal quality of the active region 3 to be poor; effectively release the deep well layer 32 and the shallow well layer 34 during the growth process of the potential well layer 33 and the barrier layer 36. stress between and increase the number of holes in the active region 3.

It can be seen from the above technical solutions that the manufacturing method of the semiconductor epitaxial structure provided by this embodiment not only achieves the beneficial effects of the above semiconductor epitaxial structure, but also has a simple and convenient manufacturing process and is convenient for production.

It can be seen from the above technical solutions that the LED chip provided in this embodiment is obtained on the basis of the above-mentioned semiconductor epitaxial structure. Therefore, while having the beneficial effects of the above-mentioned semiconductor epitaxial structure, the manufacturing process is simple and convenient, and is convenient for production.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

It should also be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply those entities or operations There is no such actual relationship or order between them. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that an article or device comprising a list of elements includes not only those elements, but also other elements not expressly listed, Or also include elements inherent to the article or equipment. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in an article or device that includes the above-mentioned element.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, this application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

A semiconductor epitaxial structure is characterized in that, comprising:

substrate;

A first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence on the surface of the substrate;

The active region includes alternately stacked barrier layers and potential well layers, and at least one side surface of the barrier layer close to the first type semiconductor layer is sequentially provided with a cooling layer and a deep well layer, and at least one side surface of the barrier layer is provided with a cooling layer and a deep well layer. A shallow well layer and a temperature rise layer are arranged on the surface of the barrier layer close to the second type semiconductor layer in sequence; wherein, the temperature drop layer and the temperature rise layer are used for the growth temperature transition between the barrier layer and the potential well layer ; The deep well layer and the shallow well layer are used for electron confinement of the barrier layer.
The semiconductor epitaxial structure according to claim 1, wherein, during the growth process of the deep well layer, the growth temperature of the deep well layer is reduced from the growth temperature of the cooling layer to a growth temperature lower than that of the potential well layer; During the growth process of the shallow well layer, the growth temperature of the shallow well layer is increased from the growth temperature of the potential well layer to the growth temperature of the elevated temperature layer.
The semiconductor epitaxial structure according to claim 1, wherein the growth temperature of the temperature rising layer is lower than the growth temperature of the barrier layer.
The semiconductor epitaxial structure according to claim 1, wherein the deep well layer and the shallow well layer respectively comprise AlxGayInzN material layers with graded In composition, wherein 0≤x≤1 , 0≤y≤1, 0≤z≤1.
The semiconductor epitaxial structure according to claim 1, wherein the deep well layer and the shallow well layer comprise material layers with graded forbidden band widths, and the forbidden band width of the shallow well layer is always larger than the potential band width. The forbidden band width of the well layer, the local forbidden band width of the deep well layer is smaller than the forbidden band width of the potential well layer.
The semiconductor epitaxial structure according to claim 1, wherein the heating layer and the cooling layer respectively comprise undoped material layers, and the deep well layer and the shallow well layer respectively comprise P-type doped material layers , and the doping concentration is not higher than 5*10 17 cm -3 .
The semiconductor epitaxial structure according to claim 1, wherein the heating layer and the cooling layer respectively comprise Al a Ga b N material layers, wherein 0≤a≤1, 0≤b≤1.
The semiconductor epitaxial structure according to claim 1, wherein the thickness of the potential well layer is three times or more than the thickness of the deep well layer or the shallow well layer.
The semiconductor epitaxial structure according to claim 1, wherein the thickness of the deep well layer and the shallow well layer are both 0-10 nm.
The semiconductor epitaxial structure according to claim 1, wherein the thickness of the barrier layer is 4 times or more than the thickness of the heating layer or the cooling layer.
The semiconductor epitaxial structure according to claim 1, wherein the heating layer and the cooling layer have thicknesses of 0-20 nm.
A fabrication method of a semiconductor epitaxial structure, characterized in that the fabrication method comprises the following steps:

Step S01, providing a substrate;

Step S02, growing a first-type semiconductor layer, an active region, and a second-type semiconductor layer on the surface of the substrate in sequence;

The active region includes alternately stacked barrier layers and potential well layers, and at least one side surface of the barrier layer close to the first type semiconductor layer is sequentially provided with a cooling layer and a deep well layer, and at least one side surface of the barrier layer is provided with a cooling layer and a deep well layer. A shallow well layer and a temperature rise layer are sequentially arranged on the surface of the barrier layer on one side close to the second type semiconductor layer; wherein, the temperature drop layer and the temperature rise layer are used for the growth temperature transition between the barrier layer and the potential well layer ; The deep well layer and the shallow well layer are used for electron confinement to the barrier layer;

Further, the deep well layer and the shallow well layer respectively comprise AlxGayInzN material layers with graded In composition, wherein 0≤x≤1, 0≤y≤1 , 0≤z≤1 ;;

The heating layer and the cooling layer respectively comprise Al a Ga b N material layers, wherein 0≤a≤1, 0≤b≤1.
The method for fabricating a semiconductor epitaxial structure according to claim 12, wherein during the growth process of the deep well layer, the growth temperature of the deep well layer is lowered from the growth temperature of the cooling layer to a temperature lower than that of the potential well layer. temperature; during the growth process of the shallow well layer, the growth temperature of the shallow well layer is increased from the growth temperature of the potential well layer to the growth temperature of the elevated temperature layer.
The method for fabricating a semiconductor epitaxial structure according to claim 13, wherein the growth temperature of the heating layer is lower than the growth temperature of the barrier layer.
An LED chip, comprising an epitaxial layer, an N-type electrode and a P-type electrode, wherein the epitaxial layer comprises the semiconductor epitaxial structure according to any one of claims 1-11.