KR20120013577A - Light emitting device having active region of multi-quantum well structure - Google Patents

Light emitting device having active region of multi-quantum well structure Download PDF

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KR20120013577A
KR20120013577A KR1020100075625A KR20100075625A KR20120013577A KR 20120013577 A KR20120013577 A KR 20120013577A KR 1020100075625 A KR1020100075625 A KR 1020100075625A KR 20100075625 A KR20100075625 A KR 20100075625A KR 20120013577 A KR20120013577 A KR 20120013577A
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barrier layer
barrier
compound semiconductor
type compound
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유홍재
이성남
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서울옵토디바이스주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

A light emitting device having an active region of a multi-quantum well structure is disclosed. The active region of the light emitting element is from the n-type compound semiconductor layer side to the p-type compound semiconductor layer side, in which a first barrier layer, a second barrier layer, a third barrier layer, a well layer and a fourth barrier layer are periodically stacked in this order. It has a multi-quantum well structure. The fourth barrier layers each include an undoped layer in contact with the well layer, and at least one of the fourth barrier layers includes a silicon doped layer on the undoped layer. By adjusting the silicon doping position in the fourth barrier layers it is possible to lower the forward voltage and improve the light output.

Description

LIGHT EMITTING DEVICE HAVING ACTIVE REGION OF MULTI-QUANTUM WELL STRUCTURE}

The present invention relates to a nitride semiconductor light emitting device, and a light emitting device having an active region of a multi-quantum well structure. More specifically, the present invention relates to a nitride-based semiconductor light emitting device that improves the forward voltage characteristics and / or light output characteristics by adjusting the silicon doping position in the active region.

In general, nitrides of Group III elements such as gallium nitride (GaN), aluminum nitride (AlN), and indium gallium nitride (InGaN) have excellent thermal stability and have a direct transition type energy band structure. It is attracting much attention as a material for light emitting devices in the green and ultraviolet region. The light emitting device using the gallium nitride-based compound semiconductor is widely used as a light emitting diode or a laser diode in various applications such as a large-scale color flat panel display, a backlight light source, a traffic light, an indoor light, a high density light source, a high resolution output system, and an optical communication.

The nitride-based light emitting device includes an active region of an InGaN-based multi-quantum well structure positioned between n-type and p-type nitride semiconductor layers, and electrons and holes recombine in the quantum well layer in the active region to generate light. Therefore, in the manufacture of nitride semiconductor light emitting devices, it is necessary to improve the emission recombination rate of electrons and holes in the quantum well layer in order to obtain high output.

On the other hand, when the barrier layer in the active region is used as an undoped layer, the resistivity in the active region is increased to increase the forward voltage, and the number of electron carriers is decreased, thereby reducing the emission recombination rate. In contrast, when the impurity is doped into the barrier layer in the active region, the forward voltage can be lowered, but the lifetime of the hole carrier can be shortened, thereby reducing the emission recombination rate and thus lowering the light output.

The problem to be solved by the present invention is to provide a light emitting device that can improve the light output while lowering the forward voltage.

Another object of the present invention is to improve the light output of the light emitting device by increasing the rate of light recombination.

The light emitting device according to the embodiments of the present invention, a gallium nitride-based n-type compound semiconductor layer; Gallium nitride-based p-type compound semiconductor layers; And an active region interposed between the n-type and p-type compound semiconductor layers. The active region is formed by periodically stacking a first barrier layer, a second barrier layer, a third barrier layer, a well layer and a fourth barrier layer in this order from the n-type compound semiconductor layer side to the p-type compound semiconductor layer side. It has a multi-quantum well structure. In addition, the second barrier layer has a narrower energy bandgap than the first barrier layer, the third barrier layer, and the fourth barrier layer. Further, the first barrier layer and the second barrier layer closest to the n-type compound semiconductor layer side include a silicon doping layer, the other first barrier layer and the second barrier layer are undoped layers, and the third barrier layer Are all undoped layers. Further, the fourth barrier layers each include an undoped layer in contact with a well layer, and at least one of the fourth barrier layers includes a silicon doped layer on the undoped layer.

Since the first barrier layer and the second barrier layer closest to the n-type compound semiconductor layer side include a silicon doping layer, it is possible to smoothly flow the electron carrier into the active region from the n-type compound semiconductor layer side. Further, the other first and second barrier layers and the third barrier layer are used as undoped layers, and the partial thickness region of the fourth barrier layer in contact with the well layer is defined as an undoped layer, and a partial thickness of the fourth barrier layer. By using the region as a doping layer, the recombination rate of electrons and holes can be improved while maintaining the number of electron carriers in the active region.

The thickness of the silicon doped layer in the fourth barrier layer is preferably not more than 70% of the thickness of the fourth barrier layer, more preferably not more than 50%. Preferably, the thickness of the silicon doped layer in the fourth barrier layer may be in the range of 30 to 70% of the thickness of the fourth barrier layer.

Meanwhile, the third barrier layer and the fourth barrier layer may have a relatively wide energy band gap to confine the carrier in the well layer. Furthermore, since the second barrier layer has a relatively narrow bandgap compared to the third barrier layer, stress applied to the well layer by the third barrier layer can be alleviated and thus strain in the well layer can be alleviated. have. Furthermore, the first barrier layer may have a narrower bandgap than the fourth barrier layer, and may have a relatively wider bandgap than the second barrier layer.

Meanwhile, the fourth barrier layer may be relatively thicker than the third barrier layer. Therefore, electrons introduced into the well layer through the third barrier layer are not easily escaped through the fourth barrier layer. On the other hand, the fourth barrier layer is preferably relatively thin compared to the well layer. The fourth barrier layer may, for example, have a thickness in the range of 1.5-2 nm. Furthermore, the third barrier layer may have a thickness at which electron tunneling may occur. For example, the thickness of the third barrier layer may be 1 to 1.5 nm. In addition, when the thickness of the second barrier layer is thick, electron-hole recombination may occur in the second barrier layer, and may absorb light generated in the well layer. Therefore, the thickness of the second barrier layer is preferably formed relatively thin in the range that can alleviate the strain applied to the well layer, it may be a thickness similar to the third barrier layer, for example, 1 ~ 1.5nm.

Preferably, the fourth barrier layers including the silicon doped layer may be located closer to the n-type compound semiconductor layer side than to the p-type compound semiconductor layer side. That is, in the active region, the fourth barrier layers in the region closer to the n-type compound semiconductor layer side than the p-type compound semiconductor layer side have the silicon doped layer, and the fourth barrier layers in the region closer to the p-type compound semiconductor layer side are the silicon doped layer. It may be an undoped layer that does not include.

The first barrier layer and the second barrier layer may be formed of InGaN, the third barrier layer and the fourth barrier layer may be formed of GaN, and the In composition ratio of the first barrier layer may be In composition ratio of the second barrier layer. It can be relatively smaller than. As the In composition ratio increases in the order of the first barrier layer and the second barrier layer, the strain-in applied to the well layer may be further relaxed.

The first barrier layer may be a grading layer in which a band gap is reduced toward the p-type compound semiconductor layer. Further, the first barrier layer and the second barrier layer may be a gallium nitride-based semiconductor layer including In, and the third barrier layer and the fourth barrier layer may be AlInGaN or GaN. By using the four-component nitride compound semiconductor layer, lattice mismatch between the well layer and the barrier layer can be alleviated.

In addition, the first barrier layer may be thicker than the second barrier layer, thus mitigating strain caused by the second barrier layer. Further, the first barrier layer may be relatively thicker than the well layer.

According to embodiments of the present invention, the barrier layer is divided into first to fourth barrier layers, and the first and second barrier layers and the third barrier layer are undoped layers, and the well layer of the fourth barrier layer is formed. By making some of the thickness regions in contact with the undoped layer and some of the thickness regions of the fourth barrier layer as the doping layer, the recombination rate of electrons and holes can be improved while maintaining the number of electron carriers in the active region. In addition, it is possible to reduce the strain applied to the well layer by controlling the composition and thickness of the first to fourth barrier layers. Accordingly, a light emitting device capable of improving forward voltage characteristics and / or light output characteristics can be provided.

1 is a cross-sectional view illustrating a light emitting device according to an embodiment of the present invention.
FIG. 2 is an enlarged cross-sectional view for describing the active region of FIG. 1.
3 is a schematic band diagram for describing a light emitting device according to an embodiment of the present invention.
4 is a schematic band diagram for explaining various experimental examples according to an embodiment of the present invention.
5 is a schematic band diagram for explaining comparative examples.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention to those skilled in the art will fully convey. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view illustrating a light emitting device according to an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view of a portion of the active region of FIG. 1, and FIG. 3 is a schematic band diagram. Only the conduction band Ec is shown in FIG. 3.

Referring to FIG. 1, the light emitting device includes a substrate 21, an n-type GaN-based compound semiconductor layer 27, an active region 30, and a p-type GaN-based compound semiconductor layer 43. In addition, the light emitting device may include a low temperature buffer layer 23 and a high temperature buffer layer 25 between the substrate 21 and the n-type compound semiconductor layer 27, and the p-type compound semiconductor layer 43 and the active region. It may include a p-type cladding layer 41 between the (30).

The substrate 21 is not particularly limited, and may be, for example, a conductive substrate such as sapphire, spinel, silicon carbide substrate, or metal. Meanwhile, the low temperature buffer layer 23 may be generally formed of Al x Ga 1 - x N (0 ≦ x ≦ 1), and the high temperature buffer layer 25 may be, for example, an n type doped with undoped GaN or n type impurities. GaN.

A p-type compound semiconductor layer 43 is positioned on the n-type compound semiconductor layer 27, and an active region 30 is interposed between the n-type compound semiconductor layer 27 and the p-type compound semiconductor layer 43. . The n-type compound semiconductor layer and the p-type compound semiconductor layer may be formed of a group III nitride semiconductor layer of (Al, In, Ga) N series. For example, the n-type compound semiconductor layer 27 and the p-type compound semiconductor layer 43 may be n-type and p-type GaN, or n-type and p-type AlGaN, respectively. In addition, a p-type cladding layer 41 may be interposed between the p-type compound semiconductor layer 43 and the active region 30. The p-type cladding layer 41 may also be formed of a Group III nitride semiconductor layer of (Al, In, Ga) N series, for example, AlGaN. In addition, an n-type cladding layer (not shown) may be interposed between the n-type compound semiconductor layer 27 and the active region 30.

2 and 3, the active region 30 has a multi-quantum well structure in which the barrier layer 31, the well layer 33, and the fourth barrier layer 35 are periodically stacked. The barrier layer 31 includes a first barrier layer 31a, a second barrier layer 31b, and a third barrier layer 31c. Meanwhile, the well layer 33 may be a single layer having a single band gap, but is not limited thereto, and may include layers in which the band gap is discontinuous. In addition, a buffer layer 37 may be interposed between the p-type cladding layer 41 and the fourth barrier layer 35.

The active region 30 has a first barrier layer 31a, a second barrier layer 31b, a third barrier layer 31c, a well layer 33, and a fourth from the n-type compound semiconductor layer 27 side. The barrier layer 35 has a multi-quantum well structure that is periodically stacked in this order.

The first barrier layer 31a may be formed of Al x In y Ga 1 -xy N (0 ≦ x <1, 0 <y <1, 0 <x + y <1). The first barrier layer 31a has an energy band gap capable of supplying electrons to the well layer 33. That is, the first barrier layer 31a may have a narrower bandgap than the n-type compound semiconductor layer 27, and have a wider bandgap than the well layer 33. When the first barrier layer 31a is formed of a four-component system, the first barrier layer 31a may have a relatively good crystallinity, and when the n-type compound semiconductor layer 27 is GaN, the well of the n-type compound semiconductor layer 27 and the InGaN series The lattice mismatch between the layers 33 can be alleviated. In addition, the first barrier layer 31a may be a grading layer having a band gap reduced toward the p-type compound semiconductor layer 43. The composition of the first barrier layer 31a can be inclined from the composition of the n-type compound semiconductor layer 27 or the composition having a narrower bandgap than the n-type compound semiconductor layer 27 to the composition of the second barrier layer 32a. have. Meanwhile, the growth temperature of the first barrier layer 31a is lower than that of the n-type compound semiconductor layer 27, and the third barrier layer 31c, the well layer 33, and the fourth barrier layer 35 are formed. It may be higher than the growth temperature. In addition, the gradient composition in which the band gap decreases toward the p-type compound semiconductor layer 43 in the first barrier layer 31a gradually increases the flow rate of In from 22 cc to 70 cc at the same growth temperature. Can be adjusted.

The first barrier layer 31a closest to the n-type compound semiconductor layer 27 side of the first barrier layers 31a includes a silicon doping layer, and the other first barrier layers 31a are undoped. It is preferable that it is a layer. By doping silicon in the first barrier layer 31a closest to the n-type compound semiconductor layer 27 side, it is possible to facilitate the inflow of electrons into the active region 30, and the other first barrier layer 31a. By making the undoped layer, non-luminescence recombination of electrons and holes can be prevented.

The thickness t1 of the first barrier layer 31a is relatively thicker than the other barrier layers 31b, 31c, and 35, and is also relatively thicker than the well layer 33.

On the other hand, the second barrier layer 31b is Al x In y Ga 1 -xy N (0 ≦ x <1, 0 <y <1, 0 <x + y <1) on the first barrier layer 31a. And an energy band gap narrower than that of the first barrier layer 31a. In addition, the second barrier layer 31b has a wider energy bandgap than the well layer 33. Further, the thickness t2 of the second barrier layer 31b is preferably thinner than the first barrier layer 31a, and is generally similar to that of the third barrier layer 31c, for example, a thickness in the range of 1 to 1.5 nm. It can have The second barrier layer 31b may be a gradient composition layer, but preferably has a substantially uniform composition throughout the layer. The growth temperature of the second barrier layer 31b may be the same growth temperature as that of the first barrier layer 31a, and its composition may be controlled by In flow rate.

The second barrier layer 31b closest to the n-type compound semiconductor layer 27 side of the second barrier layers 31b includes a silicon doping layer, and the other second barrier layers 31b are undoped. It is preferable that it is a layer. By doping silicon in the second barrier layer 31b closest to the n-type compound semiconductor layer 27 side, it is possible to facilitate the inflow of electrons into the active region 30, and the other second barrier layer 31b. By making the undoped layer, non-luminescence recombination of electrons and holes can be prevented.

The third barrier layer 31c is formed of Al x In y Ga 1 -xy N (0 <x <1, 0 <y <1, 0 <x + y <1) or GaN on the second barrier layer 31b. It may be formed, and has a wider energy bandgap than the second barrier layer 31b. The third barrier layer 31c may have a thickness through which electrons supplied through the first barrier layer 31a and the second barrier layer 31b can tunnel. For example, the third barrier layer 31c may have a thickness t3 of 1.0-1.5 nm and the growth temperature of the third barrier layer 31c may be the first barrier layer 31a and the second. It may be lower than or equal to the growth temperature of the barrier layer 31b. Typically, after the formation of the second barrier layer 31b, the temperature is ramped to about 45 ° C and then grown at a relatively low temperature.

It is preferable that all the 3rd barrier layers 31c are undoped layers. By using the third barrier layer 31c as an undoped layer, the crystallinity of the well layer 33 can be improved to increase the recombination rate of light emission in the well layer.

The well layer 33 may be a single layer or multiple layers, and may be located between and in contact with the third barrier layer 31c and the fourth barrier layer 35. The well layer 33 may be formed of In x Ga 1- x N (0 <x <1), and is preferably an undoped layer. The thickness t4 of the well layer 33 may be in a range of about 2 nm to about 2.5 nm.

When the well layer 33 includes multiple layers, for example, the first well layer and the second well layer, the first and second well layers may have different band gaps and have intermittent structures. In detail, the conventional general quantum well layer is not intermittent but consists of a single layer (including 15 to 16% In), whereas the In content of the first and second well layers is ~ 12%. It can be adjusted to have an average In content of ~ 19%. Further, the first well layer and the second well layer may each be a gradient composition layer.

Meanwhile, the fourth barrier layer 35 is in contact with the well layer 33 and has a wider energy band gap than the well layer 33. The fourth barrier layer 35 may be formed of Al x In y Ga 1 -xy N (0 <x <1, 0 <y <1, 0 <x + y <1) or GaN. In addition, the thickness t5 of the fourth barrier layer 35 is preferably thicker than the third barrier layer 31c so as to reduce the speed at which electrons move in the active region 33. It is preferable that it is relatively thin compared with (t4). For example, the thickness t5 of the fourth barrier layer 35 may be within a range of 1.5 nm to 2 nm. Meanwhile, the fourth barrier layer 35 may grow at the same temperature as the temperature at which the well layer 33 is formed. The first to third barrier layers 31a to 31c, the well layer 33, and the fourth barrier layer 35 are repeatedly grown on the fourth barrier layer 35.

The fourth barrier layer 35 each includes an undoped layer in contact with the well layer 33. By making the portion in contact with the well layer 33 an undoped layer, it is possible to increase the light recombination rate in the well layer 33 to improve the light output. In addition, at least one of the fourth barrier layers may include a silicon doped layer on the undoped layer. The silicon doped layer in the fourth barrier layer can increase the number of electron carriers to lower the forward voltage.

The thickness of the silicon doped layer in the fourth barrier layer 35 preferably does not exceed 70% of the thickness of the fourth barrier layer 35, and more preferably, does not exceed 50%. The thickness of the silicon doped layer in the yarn barrier layer 35 may be, for example, in the range of 30 to 70% of the thickness of the fourth barrier layer 35. If it exceeds 70%, the light emitting recombination rate of electrons and holes may increase, thereby decreasing the light output.

Furthermore, the fourth barrier layer 35 including the silicon doped layer is preferably located closer to the n-type compound semiconductor layer 27 side than the p-type compound semiconductor layer 43 side. That is, the fourth barrier layer 35 including the silicon doped layer may be located on the n-type compound semiconductor layer 27 side at an intermediate point of the active region 30. Accordingly, while doping silicon into the fourth barrier layer 35 to reduce the forward voltage, the lifetime of the hole carriers flowing from the p-type compound semiconductor layer 41 side can be increased to increase the recombination rate of electrons and holes. As a result, the light output can be further improved.

On the other hand, the buffer layer 37 preferably has a larger lattice constant than the fourth barrier layer 35 and a smaller lattice constant than the p-type compound semiconductor layer 43 or the p-type cladding layer 41. The buffer layer 37 mitigates lattice mismatch between the active region 30 and the p-type compound semiconductor layer 43, which is equal to or equal to the sum of the thicknesses of the first barrier layer 31a and the second barrier layer 31b. It is grown to a thickness 20% thicker, and the growth temperature at that time can be the same temperature as the growth temperature of the first barrier layer 31a and the second barrier layer 31b.

Experimental Example

4 (a) to (c) is a schematic band diagram for explaining various experimental examples (Examples 1 to 3) according to an embodiment of the present invention, Figures 5 (a) and (b) is a comparison A schematic band diagram for illustrating examples (Comparative Examples 1 and 2). In FIGS. 4 and 5, portions doped with silicon are indicated by diagonal lines. Except for the silicon-doped portions, the well layer and the barrier layer were grown under the same conditions, and the well layers 33 were all five. In addition, in Examples and Comparative Examples, silicon doping was all performed under the same process conditions.

Examples 1 to 3 of FIGS. 4 (a) to (c) and Comparative Examples 1 and 2 of FIGS. 5 (a) and (b) all have the first and the closest to the n-type compound semiconductor layer 27 side. Silicon was doped into the second barrier layers 31a and 31b, and the other first and second barrier layers were undoped layers. In addition, all the 3rd barrier layers 31c were undoped layers.

Meanwhile, in Example 1, after the undoped layer was formed on all of the fourth barrier layers 35, the silicon doped layer was formed, and the thickness of the silicon doped layer corresponds to 30% of the thickness of the fourth barrier layer 35. (FIG. 4 (a)). In Embodiment 2, the silicon doped layers are formed on the first and second fourth barrier layers 35 in the order close to the n-type compound semiconductor layer 27 side, and the remaining fourth barrier layers 35 are all undoped. The thickness of the silicon doped layer corresponds to 70% of the thickness of the fourth barrier layer 35 (Fig. 4 (b)). In the third embodiment, the silicon doped layer is formed on the same fourth barrier layers 35 as in the second embodiment, except that the silicon doped layer corresponds to 30% of the thickness of the fourth barrier layer 35. (FIG. 4 (c)).

In Comparative Example 1, except that the first and second barrier layers 31a and 31b closest to the n-type compound semiconductor layer 27 were doped with silicon, all of the remaining barrier layers were undoped layers ( 5 (a)). In Comparative Example 2, all of the fourth barrier layers 35 were formed of a silicon doped layer.

The forward voltage and light output of the light emitting diodes according to Examples 1 to 3 and Comparative Examples 1 and 2 were measured at a forward current of 20 mA, and the average values thereof were summarized in Table 1 in terms of percentages based on Comparative Example 1.

Forward voltage (%) Light output (%) Example 1 95.4 92.4 Example 2 97.3 93.6 Example 3 95.7 102.7 Comparative Example 1 100 100 Comparative Example 2 94.2 79.6

Referring to Table 1, in Comparative Example 2 in which all of the fourth barrier layers 35 were doped with silicon, the forward voltage was relatively decreased, but the light output was reduced to less than 80% compared to Comparative Example 1. As silicon is doped over the entire thickness of the fourth barrier layer, the number of electron carriers increases and the forward voltage decreases, but the light output is expected to decrease due to an increase in the non-emitting recombination rate of electrons and holes.

On the other hand, Examples 1 to 2, the forward voltage was reduced, the light output was maintained at 90% or more compared to Comparative Example 1. Although the light output decreases slightly, it is expected that the decrease is not so large that the light output can be improved while lowering the forward voltage by adjusting the doping concentration.

On the other hand, in Example 3, the forward voltage is reduced and the light output is improved compared to Comparative Example 1. Further, in Example 3, the silicon doped layer was formed to about 30% of the thickness of the fourth barrier layer while the silicon doped layer was formed on the fourth barrier layer at the same position as compared with the second embodiment. Therefore, it can be seen that the forward voltage and the light output characteristics can be improved by adjusting the thickness of the silicon doped layer formed on the fourth barrier layer.

21: substrate, 23: low temperature buffer layer, 25: high temperature buffer layer,
27: n-type GaN compound semiconductor layer, 30: active region,
31: barrier layer, 31a: first barrier layer, 31b: second barrier layer,
31c: third barrier layer, 33: well layer, 35: fourth barrier layer,
37: buffer layer, 41: p-type cladding layer,
43: p-type GaN compound semiconductor layer
t1, t2, t3: thickness of the first to third barriers
t4: thickness of the well layer
t5: thickness of the fourth barrier layer

Claims (9)

Gallium nitride-based n-type compound semiconductor layers;
Gallium nitride-based p-type compound semiconductor layers; And
An active region interposed between the n-type and p-type compound semiconductor layers,
The active region is formed by periodically stacking a first barrier layer, a second barrier layer, a third barrier layer, a well layer and a fourth barrier layer in this order from the n-type compound semiconductor layer side to the p-type compound semiconductor layer side. Has a multi-quantum well structure,
The second barrier layer has a narrower energy bandgap than the first barrier layer, the third barrier layer, and the fourth barrier layer,
The first barrier layer and the second barrier layer closest to the n-type compound semiconductor layer side include a silicon doping layer, the other first barrier layer and the second barrier layer are undoped layers,
The third barrier layers are all undoped layers,
The fourth barrier layers each include an undoped layer in contact with the well layer,
At least one of the fourth barrier layers includes a silicon doped layer on the undoped layer. The method according to claim 1,
The thickness of the silicon doped layer in the fourth barrier layer does not exceed 70% of the thickness of the fourth barrier layer. The method according to claim 1,
The thickness of the silicon doped layer in the fourth barrier layer does not exceed 50% of the thickness of the fourth barrier layer. The method according to claim 1,
The fourth barrier layers including the silicon doped layer are located closer to the n-type compound semiconductor layer side than the p-type compound semiconductor layer side. The method of claim 4,
The thickness of the silicon doped layer in the fourth barrier layer does not exceed 70% of the thickness of the fourth barrier layer. The method of claim 4,
The thickness of the silicon doped layer in the fourth barrier layer does not exceed 50% of the thickness of the fourth barrier layer. The method according to claim 1,
Wherein the first barrier layer and the second barrier layer are gallium nitride-based semiconductor layers including In, and the third barrier layer and the fourth barrier layer are AlInGaN or GaN. The method according to claim 7,
Wherein the first barrier layer is thicker than the second barrier layer. The method according to claim 8,
The second to fourth barrier layers are relatively thinner than the well layer, and the first barrier layer is relatively thicker than the well layer.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160044638A (en) * 2014-10-15 2016-04-26 삼성전자주식회사 Semiconductor light emitting device
CN109755362A (en) * 2019-01-14 2019-05-14 江西兆驰半导体有限公司 A kind of iii-nitride light emitting devices of high-luminous-efficiency
JP2021010038A (en) * 2020-10-30 2021-01-28 日機装株式会社 Nitride semiconductor light-emitting element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160044638A (en) * 2014-10-15 2016-04-26 삼성전자주식회사 Semiconductor light emitting device
CN109755362A (en) * 2019-01-14 2019-05-14 江西兆驰半导体有限公司 A kind of iii-nitride light emitting devices of high-luminous-efficiency
CN109755362B (en) * 2019-01-14 2021-10-01 江西兆驰半导体有限公司 Nitride light-emitting diode with high luminous efficiency
JP2021010038A (en) * 2020-10-30 2021-01-28 日機装株式会社 Nitride semiconductor light-emitting element

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