KR20130063378A - Nitride semiconductor device and method of fabricating the same - Google Patents

Nitride semiconductor device and method of fabricating the same Download PDF

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KR20130063378A
KR20130063378A KR1020110129865A KR20110129865A KR20130063378A KR 20130063378 A KR20130063378 A KR 20130063378A KR 1020110129865 A KR1020110129865 A KR 1020110129865A KR 20110129865 A KR20110129865 A KR 20110129865A KR 20130063378 A KR20130063378 A KR 20130063378A
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nitride semiconductor
semiconductor layer
type nitride
pit
layer
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KR1020110129865A
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Korean (ko)
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고미소
모토노부 타케야
최효식
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서울옵토디바이스주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

A nitride semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first n-type nitride semiconductor layer having a top surface and a V-pit, and a second n-type nitride semiconductor layer located on the first n-type nitride semiconductor layer and filling the V-pit. The 2 n-type nitride semiconductor layer has a wider bandgap than the first n-type nitride semiconductor layer. As a result, electrostatic discharge through the actual potential can be suppressed, and current dispersing performance in the first n-type nitride semiconductor layer is improved.

Description

Nitride semiconductor device and its manufacturing method {NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nitride semiconductor devices, and more particularly to nitride semiconductor devices having improved electrostatic discharge characteristics and methods of manufacturing the same.

AlGaInN-based nitride semiconductors are widely used in ultraviolet, blue / green light emitting diodes, or laser diodes as light sources for full-color displays, traffic lights, general lighting and optical communication devices, and also heterojunction bipolar transistors. (HBT) and high electron mobility transistors (HEMT).

In general, nitride semiconductors are grown on substrates where lattice mismatch occurs, such as sapphire, silicon carbide or silicon, because it is difficult to obtain a lattice matched substrate. Accordingly, nitride semiconductor layers grown on these substrates have a significantly higher threading dislocation density (TDD) of about 1E9 / cm 2 or more.

The actual potential provides electron trap sites to cause non-luminescent recombination, and also provides a current leakage path. Accordingly, when overvoltage such as static electricity is applied to the semiconductor device, current is concentrated through the real potential, and damage due to electrostatic discharge is easily generated. Furthermore, the current is evenly distributed over a wide range in a relatively thin nitride semiconductor layer. Difficult to disperse

Because of the poor electrostatic discharge characteristics of the nitride semiconductor element, a zener diode is usually used together with the nitride semiconductor element. However, Zener diodes are relatively expensive and also require a process and space for mounting Zener diodes.

On the other hand, although a substrate that lattice-matches with a nitride semiconductor, such as a GaN substrate, may be used, the manufacturing cost of the GaN substrate is quite high, and there is a limit in applying it except for a specific device such as a laser.

Meanwhile, in order to improve the electrostatic discharge characteristics of the nitride light emitting device, a growth temperature is controlled to grow a nitride semiconductor layer having a V-pit, and thereafter, a p-type nitride semiconductor layer is grown at a high temperature to fill the V-pit. There is this. This technique improves the electrostatic discharge characteristics by using less doped Mg in the V-pit when growing the p-type nitride semiconductor layer. However, since the V-pit penetrates the active layer, there is a problem in that the light emitting area of the active layer is reduced, and the p-type nitride semiconductor layer for filling the V-pit has a small margin for the growth process, and thus leakage current is increased depending on the Mg doping conditions. Can increase.

On the other hand, a part of the light generated in the active layer proceeds to the substrate side and is absorbed and lost in the semiconductor element or is absorbed and lost by the mounting member mounting the substrate. In order to solve this problem, a technique of arranging a mirror under the substrate is used, but since light propagates through the substrate, it is not possible to prevent light loss due to light absorption generated in the region between the active layer and the mirror.

The problem to be solved by the present invention is to provide a nitride semiconductor device having an improved electrostatic discharge characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a nitride semiconductor device having an improved current dispersion performance and a method of manufacturing the same.

Another object of the present invention is to reduce the loss due to light absorption generated inside the semiconductor device to improve the luminous efficiency of the light emitting diode.

Another problem to be solved by the present invention is to improve the electrostatic discharge characteristics of the nitride semiconductor device while preventing the reduction of the light emitting area by V-pits.

According to an aspect of the present invention, a nitride semiconductor device includes: a first n-type nitride semiconductor layer having a V-pit and an upper surface surrounding the V-pit; And a second n-type nitride semiconductor layer disposed on the first n-type nitride semiconductor layer and filling the V-pit. Here, the second n-type nitride semiconductor layer has a wider bandgap than the first n-type nitride semiconductor layer.

In addition, the second n-type nitride semiconductor layer may have a higher specific resistance than the first n-type nitride semiconductor layer, the thickness of the second n-type nitride semiconductor layer in the V-pit is the first n-type nitride It may be thicker than the thickness of the second n-type nitride semiconductor layer located on the top surface of the semiconductor layer.

The V-pit is located on the path where the actual potential is transferred. By placing the second n-type nitride semiconductor layer having a wider band gap on the path of the real potential, the current through the real potential can be suppressed, thereby improving the electrostatic discharge characteristics. Further, by forming the second n-type nitride semiconductor layer having a wide band gap in the V-pit formed in the first n-type nitride semiconductor layer, carrier traps due to actual potentials can be prevented, and thus, in the first n-type nitride semiconductor layer Current dispersion characteristics are enhanced.

On the other hand, the first n-type nitride semiconductor layer may be an InAlGaN-based bicomponent, quarter-based or tetracomponent nitride layer, the second n-type nitride semiconductor layer has a wider bandgap than the first n-type nitride semiconductor layer It may be an InAlGaN-based bicomponent, tri- or tetracomponent nitride layer having. In particular, the first n-type nitride semiconductor layer is Al x Ga 1-x N (0≤x <1), and the second n-type nitride semiconductor layer is Al y Ga 1- y N (0 <y <1) Can be. Where x <y.

The second n-type nitride semiconductor layer may be a semiconductor layer having a lower impurity doping concentration than that of the first n-type nitride semiconductor layer or an undoped layer which is not intentionally doped with impurities.

The first n-type nitride semiconductor layer may be a layer grown at a temperature at which a V-pit is formed, and the second n-type nitride semiconductor layer may be a layer grown at a temperature that fills the V-pit to planarize a surface thereof. The first n-type nitride semiconductor layer may be grown in a temperature range of 800 ° C. or more and less than 1000 ° C., and the second n-type nitride semiconductor layer may be grown in a temperature range of 1000 ° C. to 1200 ° C. FIG.

The V-pit may be formed by growth conditions, and thus, the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer may be grown in-situ. Alternatively, after growing an n-type nitride semiconductor layer having a real potential, the semiconductor layer may be etched to form a V-pit at a portion where the real potential is located.

In some embodiments, two or more pairs of the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer may be stacked. Accordingly, current may be dispersed in the first n-type nitride semiconductor layers, thereby further improving the electrostatic discharge characteristics. In addition, the laminate of the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer may be a distributed Bragg reflector.

The semiconductor device may further include a p-type nitride semiconductor layer positioned on the second n-type nitride semiconductor layer, and further, an active layer located between the second n-type nitride semiconductor layer and the p-type nitride semiconductor layer. It may further include.

In some embodiments, the semiconductor device comprises a substrate; And a lower n-type nitride semiconductor layer. In this case, the first n-type nitride semiconductor layer is located on the lower n-type nitride semiconductor layer.

The semiconductor device may be a nitride semiconductor device such as a light emitting diode, an HBT, or an HEMT.

In a method of manufacturing a semiconductor device according to another aspect of the present invention, a lower n-type nitride semiconductor layer is formed on a substrate, and a first n-type nitride semiconductor layer having V-pits is formed on the lower n-type nitride semiconductor layer. And forming a second n-type nitride semiconductor layer filling the V-pit on the first n-type nitride semiconductor layer. Here, the second n-type nitride semiconductor layer has a wider bandgap than the first n-type nitride semiconductor layer.

In addition, the second n-type nitride semiconductor layer may have a higher specific resistance than the first n-type nitride semiconductor layer. Furthermore, the thickness of the second n-type nitride semiconductor layer in the V-pit may be thicker than the thickness of the second n-type nitride semiconductor layer located on the top surface of the first n-type nitride semiconductor layer.

In addition, the first n-type nitride semiconductor layer may be grown at a temperature at which the V-pit is formed, and the second n-type nitride semiconductor layer may be grown at a temperature that fills the V-pit to planarize the surface. Particularly, the first n-type nitride semiconductor layer may be grown in a temperature range of 800 ° C. or more and less than 1000 ° C., and the second n-type nitride semiconductor layer may be grown in a temperature range of 1000 ° C. or more and 1200 ° C. or less.

Meanwhile, the first n-type nitride semiconductor layer may be formed of an InAlGaN-based binary, quarter-, or tetra-component nitride layer, and the second n-nitride semiconductor layer may be wider than the first n-type nitride semiconductor layer. It may be formed of an InAlGaN-based bicomponent, semi-branched or tetracomponent nitride layer having a band gap. In particular, the first n-type nitride semiconductor layer is Al x Ga 1- x N (0 ≦ x <1), and the second n-type nitride semiconductor layer is Al y Ga 1- y N (0 <y <1). Can be. Where x <y.

According to the present invention, the second n-type nitride semiconductor layer having a wider band gap on the path of the real potential can be placed to suppress current through the real potential and to prevent carrier traps due to the real potential. Accordingly, it is possible to provide a nitride semiconductor device having improved static discharge characteristics and current dispersion performance. Furthermore, the semiconductor layers can be continuously grown by an in-situ process by controlling the growth temperature of the nitride semiconductor to grow a nitride semiconductor layer having V-pits and a nitride semiconductor layer filling the V-pits.

Furthermore, the light loss inside the light emitting diode can be reduced by alternately stacking a nitride semiconductor layer having V-pits and a nitride semiconductor layer filling V-pits to form a distributed Bragg reflector.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.
2 is a schematic perspective view for describing current dispersion in a semiconductor device according to an exemplary embodiment of the present invention.
3 is a cross-sectional view illustrating a semiconductor device in accordance with still another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of constituent elements can be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. Here, a nitride light emitting diode will be described as an example of a semiconductor device.

Referring to FIG. 1, the light emitting diode includes a substrate 21, a buffer layer 23, a lower n-type nitride semiconductor layer 25, a first n-type nitride semiconductor layer 27, and a second n-type nitride semiconductor layer 28. ), An active layer 29, a p-type nitride semiconductor layer 31, a transparent electrode 33, a first electrode 35, and a second electrode 37.

The substrate 21 is a substrate for growing a gallium nitride based semiconductor layer, and is not particularly limited, such as sapphire, SiC, Si, spinel, and the like. The substrate 21 is a heterogeneous substrate that lattice mismatches with a semiconductor layer to be grown thereon. The substrate 21 may have protrusions (not shown) on an upper surface thereof, and may be, for example, a patterned sapphire substrate.

The buffer layer 23 usually includes a low temperature buffer layer (nuclear layer) and a high temperature buffer layer. The low temperature buffer layer may be formed of (Al, Ga) N at a low temperature of 400 ~ 600 ℃ on the substrate 21, preferably formed of GaN or AlN. The low temperature buffer layer may be formed to a thickness of about 25nm. The high temperature buffer layer is a layer for alleviating defects such as dislocations between the substrate 21 and the lower n-type semiconductor layer 25 and is grown at a relatively high temperature. For example, the high temperature buffer layer may be formed of undoped GaN or GaN doped with n-type impurities. While the buffer layer 23 is formed, the real potential D is generated by lattice mismatch between the substrate 21 and the buffer layer 23.

The lower n-type nitride semiconductor layer 25 is formed of a gallium nitride-based semiconductor layer doped with n-type impurities, such as Si. The lower n-type nitride semiconductor layer 25 may include a GaN layer, an AlGaN layer, or an InAlGaN layer, and may be formed as a single layer or multiple layers. The Si doping concentration doped in the lower n-type nitride semiconductor layer may be in the range of 5 × 10 17 / cm 3 to 5 × 10 19 / cm 3. The lower n-type nitride semiconductor layer 25 may be grown at, for example, 1000 ° C. to 1200 ° C. by supplying a metal source gas into the chamber using a MOCVD technique.

The lower n-type nitride semiconductor layer 25 may be continuously formed on the buffer layer 23, and the actual potential D formed in the buffer layer 23 is transferred to the lower n-type nitride semiconductor layer 25.

The first n-type nitride semiconductor layer 27 is positioned on the lower n-type nitride semiconductor layer 25. The first n-type nitride semiconductor layer 27 may be grown to an InAlGaN-based semiconductor layer, such as n-Al x Ga 1- x N (0 ≦ x <1). The first n-type nitride semiconductor layer 27 is grown to a thickness of about 100 to 500 nm in a temperature range of 800 ° C. to 1000 ° C., thus forming a V-pit V surrounded by a relatively flat top surface. The growth temperature of the first n-type nitride semiconductor layer 27 may vary depending on the source flow rate and the pressure in the chamber.

When the nitride semiconductor layer is grown at a relatively low temperature, the vertical growth rate is faster than the horizontal growth, and thus V-pits V are formed on the path where the actual potential D is transferred.

The second n-type nitride semiconductor layer 28 is positioned on the first n-type nitride semiconductor layer 27. The second n-type nitride semiconductor layer 28 fills the V-pit V of the first n-type nitride semiconductor layer 27 and covers the upper surface of the first n-type nitride semiconductor layer 27. The thickness of the second n-type nitride semiconductor layer 28 inside the V-pit V is thicker than the thickness of the second n-type nitride semiconductor layer 28 on the top surface of the first n-type nitride semiconductor layer 27. In addition, the second n-type nitride semiconductor layer 28 may have a relatively wide band gap and may have a high specific resistance than the first n-type nitride semiconductor layer 27. For example, the second n-type nitride semiconductor layer 28 may be an InAlGaN-based semiconductor layer having a wider band gap than the first n-type nitride semiconductor layer 27, for example, Al y Ga 1 -y N (0 <y <1). , x <y).

In addition, the second n-type nitride semiconductor layer 28 may be a layer doped with a lower concentration of n-type impurities than the first n-type nitride semiconductor layer 27 or an undoped layer formed without intentional doping of impurities. It is well known that gallium nitride compound semiconductor layers exhibit n-type semiconductor characteristics even without intentionally doping impurities.

 The second n-type nitride semiconductor layer 28 is grown to a thickness of about 50 to 300 nm at a relatively high temperature, for example, 1000 ℃ to 1200 ℃. As it is grown at a high temperature of 1000 ° C. or higher, the second n-type nitride semiconductor layer 28 has a predominantly horizontal growth to fill the V-pit V and has a relatively flat surface.

Meanwhile, the active layer 29 is located on the second n-type nitride semiconductor layer 28. The active layer 29 may have a single quantum well structure or a multi-quantum well structure in which a barrier layer and a quantum well layer are alternately stacked. The barrier layer may be formed of a gallium nitride based semiconductor layer having a wider band gap than that of the quantum well layer, for example, GaN, InGaN, AlGaN, or AlInGaN. The quantum well layer may be formed of a gallium nitride based semiconductor layer, such as InGaN, and the In composition ratio is determined by the desired light wavelength. The active layer 29 may be in contact with the second n-type nitride semiconductor layer 28, but is not limited thereto, and the n-type nitride semiconductor layer between the active layer 29 and the second n-type nitride semiconductor layer 28 ( Not shown) may be interposed.

The barrier layer and the quantum well layer of the active region 29 may be formed of an undoped layer which is not doped with impurities to improve crystal quality of the active region, but impurities may be formed in some or all of the active region to lower the forward voltage. It may be doped.

The p-type nitride semiconductor layer 31 is positioned on the active layer 29. The p-type nitride semiconductor layer 31 is formed of a semiconductor layer doped with p-type impurities such as Mg. The p-type nitride semiconductor layer 31 may be a single layer or multiple layers, for example, may include a p-type cladding layer and a p-type contact layer.

A transparent electrode 33 such as ITO may be disposed on the p-type nitride semiconductor layer 31. Meanwhile, the p-type nitride semiconductor layer 31 and the active layer 29 are partially removed to form a first electrode 35 on the exposed n-layer portion, and the second electrode 37 is formed on the transparent electrode 33. ) Is formed to complete the light emitting diode. The first electrode 35 may contact the first n-type nitride semiconductor layer 27, but is not limited thereto. The second n-type nitride semiconductor layer 28 or the lower n-type nitride semiconductor layer 25 may be used. You can also contact

2 is a schematic perspective view for describing current dispersion in a semiconductor device according to an exemplary embodiment of the present invention. Here, (a) shows a first n-type nitride semiconductor layer 27 having a real potential formed according to the prior art, and (b) shows a first n-type nitride semiconductor layer 27 having a V-pit according to the present invention. Indicates.

Referring to FIG. 2A, when a real potential is formed in the first n-type nitride semiconductor layer 27, the carriers e are easily trapped in the real potential D. Referring to FIG. The trapped carriers easily move along the actual potential D by the voltage applied to the semiconductor device, and thus the electrostatic discharge characteristics are poor.

Referring to FIG. 2B, a V-pit V is formed in the first n-type nitride semiconductor layer 27, and the V-pit V is compared with the first n-type nitride semiconductor layer 27. The second n-type nitride semiconductor layer 28 having a wide band gap is filled. Since the second n-type nitride semiconductor layer 28 has a wider bandgap than the first n-type nitride semiconductor layer 27, carriers e in the first n-type nitride semiconductor layer 27 form an energy barrier. It is difficult to move into the V-pit V by. Thus, the carriers e are better dispersed in the first n-type nitride semiconductor layer 27.

Further, since the second n-type nitride semiconductor layer 28 is formed on the upper surface of the first n-type nitride semiconductor layer 27, a two-dimensional electron gas layer is formed at the boundary of these layers, further improving current dispersion performance.

According to this embodiment, since the movement of the carrier into the V-pit is suppressed, the current can be easily dispersed in the first n-type nitride semiconductor layer 27. In addition, by preventing the carrier from moving into the V-pit, current flow through the real potential can be suppressed, thus improving the electrostatic discharge characteristics of the semiconductor element.

The first n-type nitride semiconductor layer 27 having V-pits (V) may be formed by growing an n-type semiconductor layer having a real potential D and etching the n-type semiconductor layer. However, when the growth conditions are controlled to form the V-pits (V), the first and second n-type nitride semiconductor layers 27 and 28 may be grown by an in-situ process, thereby simplifying the process. good.

3 is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 3, the semiconductor device according to the present embodiment is generally similar to the light emitting diode described with reference to FIG. 1, but the light emitting diode of FIG. 1 includes a pair of first n-type nitride semiconductor layers 27 and second n. In contrast to having the type nitride semiconductor layer 28, the semiconductor element according to the present embodiment has two pairs of the first n-type nitride semiconductor layers 27a and 27b and the second n-type nitride semiconductor layers 28a and 28b. There is a difference.

That is, as described with reference to FIG. 1, after the first n-type nitride semiconductor layer 27a and the second n-type nitride semiconductor layer 28a are formed, on the second n-type nitride semiconductor layer 28a. The first n-type nitride semiconductor layer 27b having the V-pit V is grown again, and the second n-type nitride semiconductor layer 28b filling the V-pit V is grown.

As described above, by alternately stacking the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer, the current through the real potential can be further suppressed.

In the present embodiment, it has been described that two pairs of the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer are formed. However, the present invention is not limited thereto, and more pairs may be formed. Furthermore, since the first n-type nitride semiconductor layers 27a and 27b and the second n-type nitride semiconductor layers 28a and 28b have different compositions, refractive indices are also different from each other. Therefore, the distribution Bragg reflector can be formed by controlling the thicknesses of the first n-type nitride semiconductor layers 27a and 27b and the second n-type nitride semiconductor layers 28a and 28b. This distributed Bragg reflector reflects light generated in the active region 29 and proceeds toward the substrate 21 to improve luminous efficiency.

Although the foregoing embodiments have described light emitting diodes as an example, the present invention is not limited to the light emitting diodes, and may be adopted to improve electrostatic discharge characteristics in various devices employing nitride semiconductors such as HBT and HEMT.

Claims (19)

A first n-type nitride semiconductor layer having a V-pit and an upper surface surrounding the V-pit; And
A second n-type nitride semiconductor layer on the first n-type nitride semiconductor layer and filling the V-pit;
The second n-type nitride semiconductor layer has a wider band gap than the first n-type nitride semiconductor layer. The method according to claim 1,
And the thickness of the second n-type nitride semiconductor layer in the V-pit is thicker than the thickness of the second n-type nitride semiconductor layer located on the top surface of the first n-type nitride semiconductor layer. The method according to claim 1,
The first n-type nitride semiconductor layer is Al x Ga 1- x N (0≤x <1),
The second n-type nitride semiconductor layer is Al y Ga 1 -y N (0 <y <1),
A semiconductor device in which x <y. The method according to claim 1,
And at least two pairs of the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer. The method of claim 4,
The stack of the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer is a distributed Bragg reflector. The method according to claim 1,
And the first n-type nitride semiconductor layer is grown at a temperature at which a V-pit is formed, and the second n-type nitride semiconductor layer is grown at a temperature to fill a V-pit and planarize a surface thereof. The method according to claim 1,
And the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer are grown in-situ. The method according to claim 1,
The first n-type nitride semiconductor layer has a lower specific resistance than the second n-type nitride semiconductor layer. The method according to claim 1,
The semiconductor device further comprises a p-type nitride semiconductor layer positioned on the second n-type nitride semiconductor layer. The method according to claim 9,
And an active layer disposed between the second n-type nitride semiconductor layer and the p-type nitride semiconductor layer. The method according to any one of claims 1 to 10,
Board; And
Further comprising a lower n-type nitride semiconductor layer,
And the first n-type nitride semiconductor layer is on the lower n-type nitride semiconductor layer. Forming a lower n-type nitride semiconductor layer on the substrate,
Forming a first n-type nitride semiconductor layer having a V-pit on the lower n-type nitride semiconductor layer,
Forming a second n-type nitride semiconductor layer filling the V-pit on the first n-type nitride semiconductor layer,
The second n-type nitride semiconductor layer has a wider band gap than the first n-type nitride semiconductor layer. The method of claim 12,
And the thickness of the second n-type nitride semiconductor layer in the V-pit is thicker than the thickness of the second n-type nitride semiconductor layer located on the top surface of the first n-type nitride semiconductor layer. The method of claim 12,
The first n-type nitride semiconductor layer is grown at a temperature at which the V-pit is formed, the second n-type nitride semiconductor layer is grown at a temperature to fill the V-pit to planarize the surface. The method according to claim 14,
The first n-type nitride semiconductor layer is grown in a temperature range of 800 ℃ or more, less than 1000 ℃, the second n-type nitride semiconductor layer is grown in a temperature range of 1000 ℃ or more, 1200 ℃ or less. The method of claim 12,
The first n-type nitride semiconductor layer is Al x Ga 1- x N (0≤x <1),
The second n-type nitride semiconductor layer is Al y Ga 1 -y N (0 <y <1),
A semiconductor device manufacturing method wherein x <y. The method of claim 12,
The lower n-type nitride semiconductor layer, the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer is formed in-situ. The method of claim 12, wherein two or more pairs of the first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer are stacked. 19. The method of claim 18,
The first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer are stacked in two or more pairs to form a distributed Bragg reflector.
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KR20160008749A (en) * 2014-07-15 2016-01-25 엘지이노텍 주식회사 Light emitting device, Method for fabricating the same and Lighting system
CN105633230A (en) * 2016-03-31 2016-06-01 厦门市三安光电科技有限公司 Nitride light emitting diode with AIN quantum dots and manufacturing method thereof
KR20160121837A (en) * 2015-04-13 2016-10-21 엘지이노텍 주식회사 Light emitting device and lighting system
WO2018076901A1 (en) * 2016-10-31 2018-05-03 厦门三安光电有限公司 Thin-film light-emitting diode chip and manufacturing method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160008749A (en) * 2014-07-15 2016-01-25 엘지이노텍 주식회사 Light emitting device, Method for fabricating the same and Lighting system
KR20160121837A (en) * 2015-04-13 2016-10-21 엘지이노텍 주식회사 Light emitting device and lighting system
CN105633230A (en) * 2016-03-31 2016-06-01 厦门市三安光电科技有限公司 Nitride light emitting diode with AIN quantum dots and manufacturing method thereof
CN105633230B (en) * 2016-03-31 2018-08-14 厦门市三安光电科技有限公司 A kind of iii-nitride light emitting devices and preparation method thereof with AlN quantum dots
WO2018076901A1 (en) * 2016-10-31 2018-05-03 厦门三安光电有限公司 Thin-film light-emitting diode chip and manufacturing method therefor

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