WO2022165894A1 - Semiconductor epitaxial structure and manufacturing method therefor, and led chip - Google Patents

Abstract

A semiconductor epitaxial structure and a manufacturing method therefor, and an LED chip. A potential well layer (32) close to a P-type semiconductor layer (4) is configured to: comprise an AlxGayInzN material layer in which component In gradually decreases in a growth direction, wherein 0≤x≤1, 0≤y≤1, 0≤z≤1, and certain holes can be provided at edges of an active region (3) to facilitate the subsequent migration of holes to the active region (3), thereby improving recombination efficiency of electrons and holes in the space of the active region (3).

Description

A kind of semiconductor epitaxial structure and its manufacturing method, LED chip

This application claims the priority of the Chinese patent application filed on February 7, 2021 with the application number 202110177793.4 and the invention-creation title of "a semiconductor epitaxial structure and its manufacturing method, LED chip", the entire content of which is approved by Reference is incorporated in this application.

technical field

The invention relates to the field of light emitting diodes, in particular to a semiconductor epitaxial structure, a manufacturing method thereof, and an LED chip.

Background technique

Light Emitting Diode (English: Light Emitting Diode, referred to as: LED) is a semiconductor electronic component that can emit light. LED has the advantages of high efficiency, long life, small size, low power consumption, etc., and can be used in indoor and outdoor white light lighting, screen display, backlight and other fields. In the development of the LED industry, gallium nitride (GaN)-based materials are typical representatives of V-III compound semiconductors, and improving the optoelectronic properties of GaN-based LEDs has become the key to the semiconductor lighting industry.

The internal quantum efficiency of the LED structure has a decisive influence on its brightness and luminous efficiency. However, due to the bipolar input of carriers, electrons and holes are concentrated in the quantum near the N-type doped region and the P-type doped region, respectively. In the wells, the carriers are not uniformly distributed among the quantum wells, especially for the holes with low mobility and high effective mass, this inhomogeneity is more obvious. In addition, due to the inherent polarization effect of GaN-based materials, the transition probability decreases and the carrier radiation recombination probability decreases.

At present, the preparation technology of blue-green LEDs is relatively mature. The output wavelength of LEDs using InGaN-based multiple quantum wells can be changed by changing the width, composition, number of quantum wells, or the thickness and composition of the barrier layer. to adjust. Traditional InGaN-based multi-quantum well structure light-emitting diodes, due to the influence of built-in polarization electric field and other factors, the radiative recombination probability of carriers in the InGaN-based multi-quantum well structure is low, and the luminous internal quantum of the InGaN-based multi-quantum well structure is low. The efficiency is low, resulting in low luminous efficiency of the light-emitting diode based on the InGaN-based multiple quantum well structure.

In view of this, the inventor specially designed a semiconductor epitaxial structure, a method for manufacturing the same, and an LED chip, and this case came into being.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a semiconductor epitaxial structure, a manufacturing method thereof, and an LED chip to solve the problem of low quantum efficiency in the active region.

In order to achieve the above object, the technical scheme adopted in the present invention is as follows:

A semiconductor epitaxial structure, comprising a substrate, an N-type semiconductor layer, an active region and a P-type semiconductor layer;

The active region includes alternately stacked potential barrier layers and potential well layers, and the potential well layer close to the P-type semiconductor layer includes an AlxGayInzN material layer whose In composition gradually decreases along the growth direction, wherein 0≤x≤1 , 0≤y≤1, 0≤z≤1; the growth direction is perpendicular to the substrate, and points to the first-type semiconductor layer from the substrate.

Preferably, the potential well layer closest to the P-type semiconductor layer is the last potential well layer, and the last potential well layer includes a P-type doped AlxGayInzN material layer with a gradually decreasing In composition along the growth direction.

Preferably, in the potential well layer, each In composition value corresponds to a sub-AlxGayInzN material layer, and the thickness of each of the sub-AlxGayInzN material layers gradually increases along the growth direction.

Preferably, the last potential well layer includes a first AlGaInN material layer and a second AlGaInN material layer stacked in sequence along the growth direction, and the In composition of the first AlGaInN material layer is larger than that of the second AlGaInN In composition of the material layer.

Preferably, the thickness of the second AlGaInN material layer is 5 times or more than the thickness of the first AlGaInN material layer.

Preferably, the barrier layer closest to the P-type semiconductor layer is the last barrier layer, and the last barrier layer includes an undoped AlaGabN material layer whose Al composition is graded along the growth direction, wherein , 0≤a≤1, 0≤b≤1.

Preferably, the Al composition value gradually decreases toward both ends along the center position of the last barrier layer; further, the Al composition value at both ends of the last barrier layer may be infinitely close to 0.

Preferably, the last barrier layer includes a first AlGaN material layer, a second AlGaN material layer and a third AlGaN material layer stacked in sequence along the growth direction, and the Al composition of the second AlGaN material layer is are higher than the Al composition of the first AlGaN material layer and/or the third AlGaN material layer.

Preferably, in the active region, except for the potential well layer whose In composition is graded, each of the other potential well layers has a constant composition and is not doped.

Preferably, in the active region, except for the last barrier layer, the components of the other barrier layers are constant and N-type doped.

The present invention also provides a method for fabricating a semiconductor epitaxial structure, the fabrication method comprising the following steps:

Step S01, providing a substrate;

Step S02, growing an N-type semiconductor layer, an active region, and a P-type semiconductor layer on the surface of the substrate in sequence;

The active region includes alternately stacked potential barrier layers and potential well layers, and the potential well layer close to the P-type semiconductor layer includes an AlxGayInzN material layer whose In composition gradually decreases along the growth direction, wherein 0≤x≤1 , 0≤y≤1, 0≤z≤1; the growth direction is perpendicular to the substrate, and points to the first-type semiconductor layer from the substrate;

Further, the potential well layer closest to the P-type semiconductor layer is the last potential well layer, and the last potential well layer includes a P-type doped AlxGayInzN material layer whose In composition is gradually reduced along the growth direction; each An In composition value corresponds to a sub-AlxGayInzN material layer, and the thickness of each of the sub-AlxGayInzN material layers is gradually thickened along the growth direction;

Further, the barrier layer closest to the P-type semiconductor layer is the last barrier layer, and the last barrier layer includes a non-doped AlaGabN material layer whose Al composition is graded along the growth direction, wherein , 0≤a≤1, 0≤b≤1; the Al composition value gradually decreases toward both ends along the center position of the last barrier layer;

Moreover, in the active region, except for the potential well layer with graded In composition, the other potential well layers have constant and undoped components; except for the last barrier layer, the rest The composition of each of the barrier layers is constant and N-type doped.

Preferably, the growth temperature of the potential well layer with graded In composition is T2, and the growth temperature of the other potential well layers is T1, 0≤T2-T1≤50°C.

Preferably, the growth temperature of the last barrier layer is T3, and the growth temperature of the remaining barrier layers is T4, 0≤T4-T3≤100°C.

The present invention also provides an LED chip, comprising an epitaxial layer, an N-type electrode and a P-type electrode, wherein the epitaxial layer includes the semiconductor epitaxial structure described in any one of the above.

It can be seen from the above technical solutions that, in the semiconductor epitaxial structure provided by the present invention, the potential well layer close to the P-type semiconductor layer is set to include an AlxGayInzN material layer with a gradually decreasing In composition along the growth direction, wherein 0≤x ≤1, 0≤y≤1, 0≤z≤1; further, the last potential well layer along the growth direction includes a P-type doped AlxGayInzN material layer whose In composition is gradually reduced along the growth direction; A certain amount of holes are stored at the edge of the active region, which facilitates the migration of subsequent holes to the active region, thereby improving the recombination efficiency of electrons and holes in the space of the active region.

Secondly, by: setting the potential well layer close to the P-type semiconductor layer to include an AlxGayInzN material layer with a gradually decreasing In composition along the growth direction; and each In composition value corresponds to a sub-AlxGayInzN material layer, each The thickness of the AlxGayInzN material layer is gradually thickened along the growth direction; on the one hand, it is beneficial to better retain In in the active region and avoid the phenomenon of a large amount of In desorption and escape caused by subsequent high-temperature growth; The thickness of the AlxGayInzN material layer is gradually increased along the growth direction, which is also beneficial to improve the hole storage capacity of the active region.

Furthermore, the last barrier layer along the growth direction includes a non-doped AlaGabN material layer whose Al composition is graded along the growth direction, wherein 0≤a≤1, 0≤b≤1; the Al composition The value gradually decreases toward both ends along the center position of the last barrier layer; and except for the last barrier layer, the components of the other barrier layers are constant and N-type doped. It can effectively reduce the diffusion of electrons to the P-type semiconductor layer caused by N-type doping in the active region.

It can be known from the above technical solutions that the manufacturing method of the semiconductor epitaxial structure provided by the present invention achieves the beneficial effects of the above semiconductor epitaxial structure, and at the same time, the manufacturing process is simple and convenient, and it is convenient for production.

It can be seen from the above technical solutions that the LED chip provided by the present invention is obtained on the basis of the above-mentioned semiconductor epitaxial structure. Therefore, while having the beneficial effects of the above-mentioned semiconductor epitaxial structure, the process is simple and convenient, and is convenient for production.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, for those of ordinary skill in the art,

On the premise of paying creative work, other drawings can also be obtained based on the provided drawings.

FIG. 1 is a schematic structural diagram of a semiconductor epitaxial structure provided by an embodiment of the present invention;

2 is a schematic structural diagram of the last barrier layer and the last potential well layer of the active region according to an embodiment of the present invention;

3 is a schematic diagram showing the relationship between the growth temperatures of each constituent layer in the active region according to an embodiment of the present invention;

Description of symbols in the figure: 1, substrate, 2, N-type semiconductor layer, 3, active region, 31, barrier layer, 31.1, first AlGaN material layer, 31.2, second AlGaN material layer, 31.3, third AlGaN Material layer, 32, potential well layer, 32.1, first AlGaInN material layer, 32.2, second AlGaInN material layer, 4, P-type semiconductor layer, 5, buffer layer.

Detailed ways

In order to make the content of the present invention clearer, the content of the present invention will be further described below with reference to the accompanying drawings. The present invention is not limited to this specific embodiment. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in FIG. 1 and FIG. 2 , a semiconductor epitaxial structure includes a substrate 1, an N-type semiconductor layer 2, an active region 3 and a P-type semiconductor layer 4;

The active region 3 includes alternately stacked potential barrier layers 31 and potential well layers 32, and the potential well layer 32 close to the P-type semiconductor layer 4 includes an AlxGayInzN material layer whose In composition is gradually reduced along the growth direction, wherein 0≤x≤ 1, 0≤y≤1, 0≤z≤1; the growth direction is perpendicular to the substrate 1, and the substrate 1 points to the first-type semiconductor layer.

It is worth mentioning that the type of the substrate 1 is not limited in the semiconductor epitaxial structure of this embodiment. For example, the substrate 1 may be, but not limited to, a sapphire substrate 1, a silicon substrate 1, and the like. In addition, the specific material types of the N-type semiconductor layer 2, the active region 3, and the P-type semiconductor layer 4 may not be limited in the semiconductor epitaxial structure of this embodiment. For example, the N-type semiconductor layer 2 may be, but not limited to, nitridation. The gallium layer, correspondingly, the P-type semiconductor layer 4 may be, but not limited to, a gallium nitride layer.

In this embodiment, the potential well layer 32 closest to the P-type semiconductor layer 4 is the last potential well layer 32 , and the last potential well layer 32 includes P-type doping and AlxGayInzN whose In composition gradually decreases along the growth direction material layer.

In this embodiment, in the potential well layer 32, each In composition value corresponds to a sub-AlxGayInzN material layer, and the thickness of each sub-AlxGayInzN material layer gradually increases along the growth direction.

In this embodiment, the last potential well layer 32 includes a first AlGaInN material layer 32.1 and a second AlGaInN material layer 32.2 stacked in sequence along the growth direction, and the In composition of the first AlGaInN material layer 32.1 is larger than that of the second AlGaInN material layer In composition of 32.2. It should be noted that this embodiment only illustrates two sub-AlxGayInzN material layers with different In compositions. In other embodiments of the present invention, there may be multiple sub-AlxGayInzN material layers with different In compositions, which will not be described in detail here. limit. At the same time, this embodiment does not limit the specific indium composition value of each sub-AlxGayInzN material layer, as long as the In is better retained in the active region according to the specific material and its thickness, so as to avoid the subsequent high temperature growth causing In The phenomenon of a large number of desorption escapes is sufficient.

In this embodiment, the thickness of the second AlGaInN material layer 32.2 is 5 times or more than the thickness of the first AlGaInN material layer 32.1.

In this embodiment, the barrier layer 31 closest to the P-type semiconductor layer 4 is the last barrier layer 31, and the last barrier layer 31 includes an undoped AlaGabN material layer with graded Al composition along the growth direction, wherein , 0≤a≤1, 0≤b≤1.

In this embodiment, the Al composition value gradually decreases toward both ends along the center position of the last barrier layer 31 ; further, the Al composition value at both ends of the last barrier layer 31 can be infinitely close to 0.

In this embodiment, the last barrier layer 31 includes a first AlGaN material layer 31.1, a second AlGaN material layer 31.2 and a third AlGaN material layer 31.3 stacked in sequence along the growth direction, and the Al group of the second AlGaN material layer 31.2 The fraction is higher than the Al composition of the first AlGaN material layer 31.1 and/or the third AlGaN material layer 31.3. It should be noted that this embodiment only illustrates three sub-AlaGabN material layers with graded Al composition. In other embodiments of the present invention, there may be multiple sub-AlxGayInzN material layers with graded Al composition, which will not be described in detail here. limit.

In this embodiment, in the active region 3, except for the potential well layer 32 whose In composition is graded, the composition of the other potential well layers 32 is constant and not doped.

In this embodiment, in the active region 3 , except the last barrier layer 31 , the components of the other barrier layers 31 are constant and N-type doped.

In this embodiment, a buffer layer 5 may also be provided between the substrate 1 and the first-type semiconductor layer 2 .

This embodiment also provides a method for fabricating a semiconductor epitaxial structure, and the fabrication method includes the following steps:

Step S01, providing a substrate 1;

Step S02, growing an N-type semiconductor layer 2, an active region 3, and a P-type semiconductor layer 4 on the surface of the substrate 1 in sequence;

The active region 3 includes alternately stacked potential barrier layers 31 and potential well layers 32, and the potential well layer 32 close to the P-type semiconductor layer 4 includes an AlxGayInzN material layer whose In composition is gradually reduced along the growth direction, wherein 0≤x≤ 1, 0≤y≤1, 0≤z≤1; the growth direction is perpendicular to the substrate 1, and the substrate 1 points to the first-type semiconductor layer;

Further, the potential well layer 32 closest to the P-type semiconductor layer 4 is the last potential well layer 32, and the last potential well layer 32 includes a P-type doped AlxGayInzN material layer whose In composition gradually decreases along the growth direction. ; Each In composition value corresponds to a sub-AlxGayInzN material layer, and the thickness of each sub-AlxGayInzN material layer gradually increases along the growth direction;

Further, the barrier layer 31 closest to the P-type semiconductor layer 4 is the last barrier layer 31, and the last barrier layer 31 includes a non-doped AlaGabN material layer with graded Al composition along the growth direction, wherein 0 ≤a≤1, 0≤b≤1; the Al composition value gradually decreases toward both ends along the center position of the last barrier layer 31;

Moreover, in the active region 3, except for the potential well layer 32 whose In composition is graded, the components of the other potential well layers are constant and undoped; except for the last barrier layer 31, the remaining potential barriers The composition of the layers is constant and N-type doped.

As shown in FIG. 3 , in this embodiment, the growth temperature of the well layer 32 with graded In composition is T2, and the growth temperature of the other well layers 32 is T1, 0≤T2-T1≤50°C.

In this embodiment, the growth temperature of the last barrier layer 31 is T3, and the growth temperature of the remaining barrier layers 31 is T4, 0≤T4-T3≤100°C.

It should be noted that FIG. 3 is a schematic diagram showing the relationship between the growth temperature of each constituent layer in the active region 3 provided in this embodiment, which only illustrates the linear change of the growth temperature of each constituent layer in the active region 3 , this embodiment does not limit the barrier layer 31, the first AlGaN material layer 31.1, the second AlGaN material layer 31.2, the third AlGaN material layer 31.3, the potential well layer 32, the first AlGaInN material layer 32.1, the second AlGaInN material layer 32.2 The specific temperature and its variation trend during the growth process, which can be linear or non-linear.

This embodiment also provides an LED chip, which includes an epitaxial layer, an N-type electrode and a P-type electrode, wherein the epitaxial layer includes any one of the semiconductor epitaxial structures described above.

It can be seen from the above technical solutions that the semiconductor epitaxial structure provided by the present invention is formed by setting the potential well layer 32 close to the P-type semiconductor layer 4 to include an AlxGayInzN material layer with a gradually decreasing In composition along the growth direction, wherein 0≤x ≤1, 0≤y≤1, 0≤z≤1; further, the last potential well layer 32 along the growth direction includes an AlxGayInzN material layer with P-type doping and gradually decreasing In composition along the growth direction; The edge of the active region 3 stores a certain amount of holes, which facilitates the subsequent migration of holes to the active region 3 , thereby improving the recombination efficiency of electrons and holes in the space of the active region 3 .

Secondly, by: setting the potential well layer 32 close to the P-type semiconductor layer 4 to include an AlxGayInzN material layer whose In composition gradually decreases along the growth direction; and each In composition value corresponds to a sub-AlxGayInzN material layer, and each sub-AlxGayInzN material layer The thickness of the layer is gradually thickened along the growth direction; on the one hand, it is beneficial to better retain In in the active region 3 to avoid the phenomenon of a large amount of In desorption and escape caused by subsequent high temperature growth; on the other hand, each sub-AlxGayInzN material layer The thickness gradually increases along the growth direction, which is also beneficial to improve the hole storage capacity of the active region 3 .

Furthermore, the last barrier layer 31 along the growth direction includes a non-doped AlaGabN material layer whose Al composition is graded along the growth direction, wherein 0≤a≤1, 0≤b≤1; The center position of one barrier layer 31 gradually decreases toward both ends; and except for the last barrier layer 31 , the components of the other barrier layers are constant and N-type doped. The phenomenon of electrons diffusing to the P-type semiconductor layer 4 caused by N-type doping in the active region 3 can be effectively reduced.

It can be known from the above technical solutions that the manufacturing method of the semiconductor epitaxial structure provided by the present invention achieves the beneficial effects of the above semiconductor epitaxial structure, and at the same time, the manufacturing process is simple and convenient, and it is convenient for production.

It can be seen from the above technical solutions that the LED chip provided by the present invention is obtained on the basis of the above-mentioned semiconductor epitaxial structure. Therefore, while having the beneficial effects of the above-mentioned semiconductor epitaxial structure, the process is simple and convenient, and is convenient for production.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the points that are different from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

It should also be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply those entities or operations There is no such actual relationship or order between them. Furthermore, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that an article or device comprising a list of elements includes not only those elements, but also other elements not expressly listed, Or also include elements inherent to the article or equipment. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in an article or device that includes the above-mentioned element.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, this application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (14)

1. A semiconductor epitaxial structure, comprising a substrate, an N-type semiconductor layer, an active region and a P-type semiconductor layer, characterized in that:

   The active region includes alternately stacked potential barrier layers and potential well layers, and the potential well layer close to the _P -type semiconductor layer includes an _AlxGayInzN material layer whose In composition _is gradually reduced along a growth direction, wherein , 0≤x≤1, 0≤y≤1, 0≤z≤1.
2. The semiconductor epitaxial structure according to claim 1, wherein the potential well layer closest to the P-type semiconductor layer is the last potential well layer, and the last potential well layer comprises P-type doping and is grown along the _AlxGayInzN material layer with gradually _decreasing In _composition in the direction.
3. The semiconductor epitaxial structure according to claim 1 or 2, wherein, in the potential well layer, each In composition _value corresponds to a _sub - _AlxGayInzN material layer, and each of the sub-Al The thickness of the _{xGayInzN material} layer _gradually increases along the growth direction.
4. The semiconductor epitaxial structure according to claim 2, wherein the last potential well layer comprises a first AlGaInN material layer and a second AlGaInN material layer stacked in sequence along the growth direction, and the first AlGaInN material layer The In composition of the material layer is larger than the In composition of the second AlGaInN material layer.
5. The semiconductor epitaxial structure according to claim 4, wherein the thickness of the second AlGaInN material layer is 5 times or more than the thickness of the first AlGaInN material layer.
6. The semiconductor epitaxial structure according to claim 1, wherein the barrier layer closest to the P-type semiconductor layer is the last barrier layer, and the last barrier layer comprises undoped and along the The Al _a Ga _b N material layer with graded Al composition in the growth direction, wherein 0≤a≤1, 0≤b≤1.
7. The semiconductor epitaxial structure according to claim 6, wherein the Al composition value gradually decreases toward both ends along the center position of the last barrier layer.
8. The semiconductor epitaxial structure according to claim 6, wherein the last barrier layer comprises a first AlGaN material layer, a second AlGaN material layer and a third AlGaN material layer stacked in sequence along the growth direction, And the Al composition of the second AlGaN material layer is higher than the Al composition of the first AlGaN material layer and/or the third AlGaN material layer.
9. The semiconductor epitaxial structure according to claim 1, wherein, in the active region, except for the potential well layer whose In composition is graded, the composition of each of the remaining potential well layers is constant and Not doped.
10. The semiconductor epitaxial structure according to claim 6, wherein, in the active region, except for the last barrier layer, the components of the other barrier layers are constant and N-type doped.
11. A fabrication method of a semiconductor epitaxial structure, characterized in that the fabrication method comprises the following steps:

    Step S01, providing a substrate;

    Step S02, growing an N-type semiconductor layer, an active region, and a P-type semiconductor layer on the surface of the substrate in sequence;

    The active region includes alternately stacked potential barrier layers and potential well layers, and the potential well layer close to the _P -type semiconductor layer includes an _AlxGayInzN material layer whose In composition _is gradually reduced along a growth direction, wherein , 0≤x≤1, 0≤y≤1, 0≤z≤1;

    Further, the potential well layer closest to the P-type semiconductor layer is the last potential well layer, and the last potential well layer includes P-type doping and _{AlxGayIn whose} In composition gradually decreases along the growth direction _{zN material} layer; each In _composition value corresponds to a sub- _{AlxGayInzN material} layer, and the thickness of each sub _{- AlxGayInzN} material layer gradually increases along the growth direction;

    Further, the barrier layer closest to the P-type semiconductor layer is the last barrier layer, and the last barrier layer includes Al _a Ga _b N that is not doped and whose Al composition is graded along the growth direction. a material layer, wherein 0≤a≤1, 0≤b≤1; the Al composition value gradually decreases toward both ends along the center position of the last barrier layer;

    Moreover, in the active region, except for the potential well layer with graded In composition, the other potential well layers have constant and undoped components; except for the last barrier layer, the rest The composition of each of the barrier layers is constant and N-type doped.
12. The method for fabricating a semiconductor epitaxial structure according to claim 11, wherein the growth temperature of the potential well layer with graded In composition is T2, and the growth temperature of the other potential well layers is T1, 0≤T2 -T1≤50℃.
13. The method for fabricating a semiconductor epitaxial structure according to claim 11, wherein the growth temperature of the last barrier layer is T3, and the growth temperature of the remaining barrier layers is T4, 0≤T4-T3 ≤100℃.
14. An LED chip comprising an epitaxial layer, an N-type electrode and a P-type electrode, wherein the epitaxial layer comprises the semiconductor epitaxial structure according to any one of claims 1-10.

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