JP5709899B2 - Light emitting diode and manufacturing method thereof - Google Patents

Description

  The present invention relates to a light emitting diode and a method for manufacturing the same, and more particularly to a reliable light emitting diode with improved electrostatic discharge characteristics and / or luminous efficiency and a method for manufacturing the same.

  In general, gallium nitride based semiconductors are widely used for ultraviolet light, blue / green light emitting diodes or laser diodes as light sources for full color displays, traffic signal lights, general lighting, and optical communication equipment. Such a gallium nitride-based light emitting device has an active layer of an InGaN-based multiple quantum well structure positioned between n-type and p-type gallium nitride semiconductor layers, and electrons and holes are regenerated in the quantum well layer in the active layer. Light is generated and emitted by the coupling principle.

  FIG. 1 is a cross-sectional view for explaining a conventional light emitting diode.

  Referring to FIG. 1, the light emitting diode includes a substrate 11, a low temperature buffer layer or core layer 13, an undoped GaN layer 15, an n-type contact layer 17, an active region 25, and a p-type contact layer 27.

  Such a conventional light emitting diode has an active region 25 having a multiple quantum well structure between the n-type contact layer 17 and the p-type contact layer 27 to improve the light emission efficiency. By adjusting the In content of the InGaN well layer, light having a desired wavelength can be emitted.

The n-type contact layer 17 usually has a doping concentration in the range of 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ and serves to supply electrons. The current distribution performance in the light emitting diode greatly affects the light emission efficiency of the light emitting diode. The n-type contact layer 17 and p-type contact layer 27, respectively n ^- when forming an electrode (not shown), n ^{- -} electrode and p electrode and p ^- electrode area in contact with the contact layer 17 and 27 Depending on the size and position, a current concentration phenomenon occurs. When a high voltage such as electrostatic discharge is applied to the light emitting diode, the light emitting diode is easily destroyed due to current concentration. In addition, threading dislocation generated in the low-temperature buffer layer 13 is transferred to the undoped GaN layer 15, the n-type contact layer 17, the active region 25, and the p-type contact layer 27, and current is passed through these threading dislocations. Since it flows intensively, the electrostatic discharge characteristics are further deteriorated.

  In addition, since approximately 11% of lattice mismatch exists between GaN and InN, in the InGaN-based multiple quantum well structure, a strong strain is generated at the interface between the quantum well and the quantum barrier. Such strain causes a piezoelectric field in the quantum well, leading to a decrease in internal quantum efficiency. In particular, in the case of a green light emitting diode, since the amount of In contained in the quantum well increases, the internal quantum efficiency is further reduced by the piezoelectric field.

  In an InGaN light emitting diode, an active region having a multiple quantum well structure is generally formed by alternately laminating InGaN well layers and InGaN barrier layers. The well layer is formed of a semiconductor layer having a smaller band gap than the barrier layer, and recombination of electrons and holes occurs in the well layer. Further, the barrier layer may be doped with Si in order to reduce the drive voltage Vf. However, Si doping adversely affects the crystalline quality of the active region. Further, due to the limitation of the epitaxial growth technique, there is a problem that the active region of the multiple quantum well structure becomes relatively thick by doping Si. In particular, when Si is doped into the active region containing In, many crystal defects are generated on the surface and inside of the active region, and a space charge separation phenomenon occurs due to the polarization electric field, and a wavelength shift tends to occur.

  On the other hand, an external quantum efficiency is increased by increasing the injection current under a low current, but a phenomenon in which the external quantum efficiency is decreased by increasing the injection current under a high current. Such a phenomenon is called efficiency droop, and particularly limits the increase in efficiency of high-power light-emitting diodes.

  The causes of the efficiency droop include thermal vibration, Auger recombination, internal electric field in the multiple quantum well structure, non-recombination rate due to crystal structure, and the like.

  Due to thermal vibration caused by heat or Joule heating, electrons and holes do not stay in the active layer region for a long time, resulting in a decrease in efficiency. When high current injection is performed, efficiency may decrease due to Auger recombination due to an increase in carrier concentration. . In addition, due to an electron overflow due to application of a high voltage, the non-recombination rate increases, thereby causing a decrease in efficiency, and an increase in the non-light-emitting recombination rate due to defects in the semiconductor crystal causes a decrease in efficiency.

  On the other hand, an AlGaN electron blocking layer (EBL) is formed on the active layer in order to prevent electrons from being emitted to the outside of the active layer. However, an internal electric field can be generated by spontaneous polarization and piezoelectric polarization in the active layer and the electron blocking layer. A high applied voltage is required for electrons to pass through the active layer having a multiple quantum well structure due to an internal electric field in the active layer and the electron blocking layer. In particular, in a 350 mA high-power diode, when the applied voltage is larger than the built-in voltage, the conduction band on the n side has a higher energy level than the conduction band on the p side with the active layer as the center, and the electron block layer As a result, the energy level becomes lower and the leakage current increases. In order to increase the energy level of the electron block layer, the Al composition in the electron block layer may be increased, but such a method lowers the crystallinity.

  The present invention has been made in view of the above problems, and an object thereof is to provide a light emitting diode having improved electrostatic discharge characteristics.

  Another object is to provide a light emitting diode with low current leakage.

  Another object of the present invention is to provide a method for manufacturing a light emitting diode with improved current dispersion performance.

  Another object of the present invention is to provide a light emitting diode that can reduce the generation of an internal electric field and lower the driving voltage.

  Still another object is to provide a light emitting diode capable of reducing the efficiency droop.

In order to achieve the above object, a light emitting diode according to an aspect of the present invention includes an n-type contact layer doped with silicon, a p-type contact layer, and an n-type contact layer interposed between the n-type contact layer and the p-type contact layer. An active region, a superlattice layer interposed between the n-type contact layer and the active region, an undoped intermediate layer interposed between the superlattice layer and the n-type contact layer, and the undoped An electron reinforcing layer interposed between the layer and the superlattice layer. Further, the superlattice layer, the mini-silicon closest final layer to the active region is doped, except the final layer is undoped, silicon doping concentration of the final layer is of the n-type contact layer Higher than silicon doping concentration. Almost all of the superlattice layers located close to the active region are not intentionally doped with silicon, so leakage current can be reduced and the final layer closest to the active region is doped with a high concentration of silicon. As a result, it is possible to prevent the bonding characteristics from deteriorating and to improve the electrostatic discharge characteristics. In particular, the final layer of the superlattice layer can be in contact with the active region.

  Meanwhile, the electron reinforcing layer may be doped with silicon, and in this case, the silicon doping concentration of the electron reinforcing layer is preferably higher than the silicon doping concentration of the n-type contact layer. Furthermore, the electronic reinforcing layer can be in contact with the superlattice layer. The electron reinforcing layer may be formed of GaN, and the superlattice layer may be formed by alternately stacking GaN and InGaN. At this time, the final layer of the superlattice layer is formed of GaN. Meanwhile, the silicon doping concentration of the final layer of the superlattice layer may be substantially the same as the silicon doping concentration of the electron reinforcing layer.

  Meanwhile, the n-type contact layer may include a GaN layer. The undoped intermediate layer may be formed of GaN. The undoped intermediate layer has a relatively high specific resistance compared to the n-type contact layer. Therefore, by arranging the undoped intermediate layer on the n-type contact layer, electrons can be uniformly dispersed in the n-type contact layer.

According to another aspect of the present invention, a method for manufacturing a light emitting diode is provided. In this method, a buffer layer is formed on a substrate, an n-type contact layer doped with silicon is formed on the buffer layer, an undoped intermediate layer is formed on the n-type contact layer, and the intermediate layer is formed on the intermediate layer. Forming an electron reinforcing layer, forming a superlattice layer on the electron reinforcing layer, and forming an active region on the superlattice layer. Here, in the superlattice layer, only the final layer is doped with silicon , and other than the final layer is undoped, and the silicon doping concentration of the final layer is higher than the silicon doping concentration of the n-type contact layer.

  Further, the method supplies a nitrogen source gas and a metal source gas into the chamber, grows the electron reinforcing layer of the gallium nitride based semiconductor layer at a first temperature, interrupts the supply of the metal source gas, The grown n-side gallium nitride based semiconductor layer is maintained on the substrate at the first temperature for a first time, and after the first time has elapsed, the temperature of the substrate is lowered to a second temperature, The superlattice layer can be grown at the second temperature by supplying a metal source gas into the chamber. The first time may be in the range of 3 minutes to 10 minutes.

  In addition, after the active layer is grown on the superlattice layer, the supply of the metal source gas is interrupted, and the temperature of the substrate is raised to a third temperature for a second time, and the active temperature is increased at the third temperature. A p-type gallium nitride based semiconductor layer can be grown on the layer. The second time may be in the range of 5 to 15 minutes.

  Before the electron reinforcing layer is lowered to the growth temperature of the superlattice layer, it is maintained in the chamber for a first time at a temperature suitable for the growth of the electron reinforcing layer or at a temperature in the vicinity thereof. While the remaining metal source gas is discharged to the outside and the substrate temperature is lowered to the superlattice layer growth temperature, it is possible to prevent the formation of a nitride layer with poor crystal quality on the electron reinforcing layer. Further, the n-side gallium nitride based semiconductor layer grown on the substrate is heat-treated during the first time, so that the crystal quality is improved.

The light emitting diode according to another aspect of the present invention includes an n-type contact layer doped with silicon, a p-type contact layer, an active region interposed between the n-type contact layer and the p-type contact layer, and the n-type contact layer. A superlattice layer interposed between the type contact layer and the active region, an undoped intermediate layer interposed between the superlattice layer and the n-type contact layer, the undoped layer and the superlattice layer, And an electronic reinforcing layer interposed therebetween. Further, in the superlattice layer, silicon is doped only in the final layer closest to the active region, the silicon other than the final layer is undoped, and the silicon doping concentration of the final layer is the silicon of the n-type contact layer. Higher than doping concentration. The n-type contact layer includes an n-type GaN layer and an n-type AlGaN layer interposed between the n-type GaN layers.

  The light emitting diode may further include a substrate, a low-temperature buffer layer located on the substrate, and an undoped GaN layer interposed between the low-temperature buffer layer and the n-type contact layer.

  By inserting an n-type AlGaN layer between the n-type GaN layers, the threading dislocation generated in the low-temperature buffer layer is blocked from being transferred to the active region, thereby reducing leakage current and improving electrostatic discharge characteristics. Can do.

  The superlattice layer may be intentionally doped with silicon only in a final layer closest to the active region, and a silicon doping concentration of the final layer may be higher than a silicon doping concentration of the n-type contact layer. . Almost all of the superlattice layers located near the active region are not intentionally doped with silicon, so that leakage current can be reduced and the final layer closest to the active region is doped with a high concentration of silicon. By doing so, it is possible to prevent the bonding characteristics from deteriorating and to improve the electrostatic discharge characteristics. In particular, the final layer of the superlattice layer may be in contact with the active region.

  Meanwhile, the electron reinforcing layer may be doped with silicon, and in this case, the silicon doping concentration of the electron reinforcing layer is preferably higher than the silicon doping concentration of the n-type contact layer. Furthermore, the electronic reinforcing layer can be in contact with the superlattice layer. The electron reinforcing layer may be formed of GaN, and the superlattice layer may be formed by alternately stacking GaN and InGaN. At this time, the final layer of the superlattice layer is formed of GaN. Meanwhile, the silicon doping concentration of the final layer of the superlattice layer may be substantially the same as the silicon doping concentration of the electron reinforcing layer.

  Meanwhile, the undoped intermediate layer may be formed of GaN. The undoped intermediate layer has a relatively high specific resistance compared to the n-type contact layer. Therefore, by arranging the undoped intermediate layer on the n-type contact layer, electrons can be uniformly dispersed in the n-type contact layer.

According to another aspect of the present invention, an n-type contact layer, a p-type contact layer formed on the n-type contact layer, and a multiple interposed between the n-type contact layer and the p-type contact layer An active region having a quantum well structure; and a spacer layer interposed between the n-type contact layer and the active region, wherein the spacer layer has a superlattice layer laminated alternately, and the active layer At least one layer adjacent to the region is doped with an n-type impurity, except for the at least one layer, the n-type impurity is undoped, and the doping concentration of the n-type impurity is the n-type contact. A diode is provided that is relatively higher than the impurity doping concentration of the layer and wherein the active region is undoped with n-type impurities.

The spacer layer comprises In, the In content is the higher than the In content in the barrier layer of the active region, may be rather low than In content in the well layer.

  The active region may have a multiple quantum well structure having an InGaN layer.

The spacer layer may have an InGaN layer, in which In _x Ga _1-x N (0 ≦ x <1) and In _y Ga _1-y N (0 ≦ y <1) are alternately stacked. It may be. The spacer layer may include superlattice layers stacked alternately.

  The spacer layer includes a plurality of layers, and at least one layer adjacent to the active region is doped with n-type impurities, and the remaining layers are undoped with n-type impurities. The doping concentration of the n-type impurity may be relatively higher than the impurity doping concentration of the n-type contact layer.

The light emitting diode further includes an intermediate layer formed between the spacer layer and the n-type contact layer, and the intermediate layer is relatively higher than an impurity doping concentration of the n-type contact layer, than the impurity doping concentration of the layer n-type impurity of the spacer layer is doped is relatively low, may have a layer n-type impurity is doped.

  The intermediate layer may have an n-type AlGaN layer. The closer the n-type AlGaN layer is to the active region, the lower the composition of Al gradually or stepwise. The n-type AlGaN layer may be formed of an AlGaN / GaN or AlGaN / InGaN multilayer structure. The intermediate layer may further include an n-GaN layer between the spacer layer and the n-type AlGaN layer. The intermediate layer may further include at least one of an undoped GaN layer and a low-doped n-GaN layer between the n-type AlGaN layer and the n-type contact layer.

  The light emitting diode may further include a p-type cladding layer formed between the active region and the p-type contact layer. The p-type cladding layer may have a p-type AlGaN layer. The p-type AlGaN layer may be formed of an AlGaN / GaN or AlGaN / InGaN multilayer structure. In the p-type AlGaN layer, a layer adjacent to the active region may be formed of AlGaN. In the p-type AlGaN layer, the AlGaN layer adjacent to the active region may be thinner than other layers in the p-type cladding layer. In the p-type AlGaN layer, the composition of Al may gradually or gradually decrease toward the p-type contact layer.

  The light emitting diode may further include an InAlN layer between the active region and the p-type cladding layer. The InAlN layer may be formed with an InN / AlN superlattice structure. The InAlN layer may have an InN / AlN superlattice structure, and the InN layer may be doped with a p-type impurity.

  In accordance with the present invention, the leakage current characteristics and the majority of the region in the superlattice layer located near the active region is not intentionally doped with impurities and its final layer is doped with a high concentration of silicon. Electrostatic discharge characteristics can be improved. Further, by interposing an undoped intermediate layer and an electron reinforcing layer between the superlattice layer and the n-type contact layer, it is possible to disperse current and prevent an increase in forward voltage.

  Furthermore, after growing the electron reinforcing layer, by maintaining the growth temperature of the electron reinforcing layer for a predetermined time, the crystal quality of the electron reinforcing layer can be improved, and after growing the active layer, Leakage current can be lowered by interrupting the supply of the metal source gas and relatively increasing the time for raising the substrate temperature to a temperature suitable for growing the p-side gallium nitride based semiconductor layer.

  Also, by inserting an n-type AlGaN layer between the n-type GaN layers, the penetration potential generated in the low-temperature buffer layer is blocked from being transferred to the active region, the leakage current is lowered, and the electrostatic discharge characteristics are improved. can do.

  In addition, the crystallinity of the active region can be improved and the recombination of carriers can be increased in the active region. In addition, by forming a spacer layer composed of a plurality of layers between the contact layer and the active region, strain generated in the active region can be reduced. In addition, the driving voltage in the active region can be lowered through the spacer layer in which the n-type impurity is selectively doped only in the layer adjacent to the active region. Furthermore, the role of the electron blocking layer can be increased, and the carrier recombination rate in the active region can be increased.

It is sectional drawing for demonstrating the conventional light emitting diode. 1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention. FIG. 5 is a schematic view illustrating a silicon doping profile of a light emitting diode according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention. 3 is a schematic temperature profile for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention, showing a silicon doping profile and a structure of a spacer layer. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention, showing a silicon doping profile and a structure of a spacer layer. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention, showing a silicon doping profile and a structure of a spacer layer. FIG. 4 is a cross-sectional view and a silicon doping profile for explaining a light emitting diode according to another embodiment of the present invention. FIG. 4 is a cross-sectional view and a silicon doping profile for explaining a light emitting diode according to another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided as examples in order to fully convey the idea of the present invention to those skilled in the art. Therefore, this invention is not limited to the Example mentioned later, It can be embodied in another form. In the drawings, the width, length, thickness, and the like of components may be exaggerated for convenience of explanation. Throughout the specification, identical reference numbers indicate identical components.

  FIG. 2 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention, and FIG. 3 illustrates a schematic silicon doping profile of the light emitting diode.

  Referring to FIGS. 2 and 3, the light emitting diode includes an n-type contact layer 57, an undoped intermediate layer 59, an electron reinforcing layer 61, a superlattice layer 63, an active region 65, and a p-type contact layer 69. The light emitting diode may include a substrate 51, a low temperature buffer layer, or a core layer 53 and a buffer layer 55, and may include a p-type cladding layer 67.

  The substrate 51 is a substrate for growing a gallium nitride based semiconductor layer, and is not particularly limited, such as sapphire, SiC, sfinnel, etc. For example, it may be a patterned sapphire substrate (PSS).

  In order to grow the buffer layer 55 on the substrate 51, the core layer 53 may be formed of (Al, Ga) N at a low temperature of 400 to 600 ° C., and is preferably formed of GaN or AlN. . The core layer may be formed with a thickness of about 25 nm. The buffer layer 55 is a layer for reducing the occurrence of defects such as potential between the substrate 51 and the n-type contact layer 57, and is grown at a relatively high temperature. The buffer layer 55 may be made of undoped GaN, for example.

The n-type contact layer 57 is formed of a gallium nitride based semiconductor layer doped with an n-type impurity, for example, Si. The n-type contact layer 57 may have a GaN layer and may be formed of a single layer or multiple layers. As shown in FIG. 4, the n-type contact layer 57 may include an n-type first GaN layer 57a, an n-type AlGaN layer 57b, and a second GaN layer 57c. That is, the AlGaN layer 57b is interposed between the GaN layers 57a and 57c. The Si doping concentration doped in the n-type contact layer may be in the range of 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ .

  For example, as shown in FIG. 4, when the n-type AlGaN layer 57b is grown after the first n-type GaN layer 57a is grown, biaxial stress is generated by the n-type AlGaN layer 57b. When the second GaN layer 57c is further grown thereon, the biaxial stress is relaxed by the compressive stress, and the penetration potential can be reduced due to such a stress change. Therefore, by disposing the n-type AlGaN layer 57b between the n-type GaN layers 57a and 57c, the through potential transferred through the core layer 53 and the high-temperature buffer layer 55 is prevented from being transferred to the active region 65 side. be able to.

  The undoped intermediate layer 59 is a GaN layer that is not intentionally doped with impurities, and may be formed to a thickness of 100 to 5000 mm. Since the undoped intermediate layer 59 is not doped with impurities, the specific resistance is relatively higher than that of the n-type contact layer. Therefore, electrons flowing from the n-type contact layer 57 into the active region 65 can be uniformly dispersed in the n-type contact layer 57 before passing through the undoped intermediate layer 59.

  An electron reinforcing layer 61 is formed on the undoped intermediate layer 59. The electron reinforcing layer 61 may be a GaN layer doped with Si at a high concentration and having a thickness of 10 to 2000 mm, and lowers the forward voltage of the light emitting diode. As shown in FIG. 3, the doping concentration of Si doped in the electron reinforcing layer 61 is higher than the silicon doping concentration of the n-type contact layer 57. The silicon doping concentration in the electron reinforcing layer 61 may be four times or more the silicon doping concentration of the n-type contact layer 57.

  The n-type contact layer 57, the undoped intermediate layer 59, and the electron reinforcing layer 61 may be continuously grown by supplying a metal source gas into the chamber. As a raw material for the metal source gas, an organic substance such as Al, Ga, or In, for example, TMA, TMG, and / or TMI is used. These layers may be grown at a first temperature, eg, 1050 ° C. to 1150 ° C.

  A superlattice layer 63 is formed on the electron reinforcing layer 61. The superlattice layer 63 may be formed by alternately stacking GaN layers and InGaN layers, for example, with a thickness of 20 mm, respectively. The first layer of the superlattice layer 63 may be formed of GaN or InGaN, but the final layer is preferably formed of GaN. The final layer of the superlattice layer 63 is doped with Si at a high concentration. The doping concentration of Si doped in the final layer may be, for example, about 4 to 5 times higher than the concentration of Si doped in the n-type contact layer 57. Further, the Si concentration doped in the final layer of the superlattice layer 63 may be substantially the same as the doping concentration of the electron reinforcing layer 61. Accordingly, the final layer of the superlattice layer 63 and the electron reinforcing layer 61 below the superlattice layer 63 are formed of a highly doped layer, and the remaining layers of the superlattice layer 63 positioned therebetween are undoped. Formed in layers.

  Since most of the superlattice layer 63 is formed of an undoped layer, the leakage current of the light emitting diode can be reduced. Also, the junction characteristics between the superlattice layer 63 and the active region can be improved by doping the final layer of the superlattice layer 63 with a high concentration.

Meanwhile, the superlattice layer 63 may be grown at a temperature relatively lower than that of the electron reinforcing layer 61. As shown in FIG. 5, before the superlattice layer 63 is grown, after the electron reinforcing layer 61 is grown, the supply of the metal source gas is interrupted, and the grown electron reinforcing layer 61 is moved to the first layer. on the substrate 5 first temperature T1, it is maintained during the first time t1. The first time t1 is a time for sufficiently discharging the metal source gas remaining in the chamber, and may be about 3 to 10 minutes, preferably about 5 to 7 minutes. Further, during the first time t1, the n-type contact layer 57 and the intermediate layer 59 including the electron reinforcing layer 61 are heat-treated, and the crystal quality of the n-side semiconductor layer is improved.

Then, lowering the temperature of the substrate 5 1 from a first temperature T1 to a second temperature T2. The second temperature T2 is set to a temperature suitable for growing the superlattice layer 63. The second temperature T2 may be within a range of 650 to 800 ° C., for example.

  After the growth of the superlattice layer 63 is completed, an active region 65 is grown on the superlattice layer 63. The active region 65 may be grown at the same or relatively lower temperature than the superlattice layer 63, for example, in the range of 650 to 750 ° C. In order to simplify the illustration, FIG. 5 shows that the active region 65 is grown at the second temperature T <b> 2 that is the growth temperature of the superlattice layer 63.

  The active region 65 may have a multiple quantum well structure in which barrier layers and InGaN quantum well layers are alternately stacked. The barrier layer may be formed of a gallium nitride based semiconductor layer having a wider band gap than the quantum well layer, for example, GaN, InGaN, AlGaN, or AlInGaN. The In composition ratio in the InGaN quantum well layer is determined by a desired light wavelength. The active region 65 may be in contact with the final layer of the superlattice layer 63. The barrier layer and the quantum well layer of the active region 65 may be formed of an undoped layer that is not doped with impurities in order to improve the crystal quality of the active region, but in order to reduce the forward voltage, Impurities may be doped in part or all of the active region.

  A p-type contact layer 69 may be positioned on the active region 65, and a p-type cladding layer 67 may be interposed between the active region 65 and the p-type contact layer 69. For example, after the growth of the active region 65 is completed, the supply of the metal source gas is interrupted, and the temperature of the substrate 51 is raised to the third temperature T3 for the second time t2. The second time t2 is set to a time for sufficiently discharging the metal source gas remaining in the chamber. For example, the second time t2 may be within a range of 5 minutes to 15 minutes. Alternatively, after the growth of the active region 65 is completed, the supply of the metal source gas is interrupted, and the temperature of the substrate 51 is maintained for a third time at the active region growth temperature, eg, the second time t2, for a third time. May be. The third time may be, for example, the same time as the first time, that is, within a range of 3 minutes to 10 minutes. Maintaining the second temperature for a third time after the growth of the active region 65 is completed, and raising the second temperature to the third temperature for the second time t2 are alternatives to each other. However, the present invention is not limited to this, and they may be used complementing each other.

  Next, at the third temperature T3, a metal source gas is supplied into the chamber, and a p-side gallium nitride based semiconductor layer, for example, the p-type cladding layer 67 or the p-type contact layer 69 is grown. The p-type cladding layer 67 may be AlGaN. The p-type contact layer 69 may have a single layer of GaN or a multilayer structure having a GaN layer.

  After the growth of the epitaxial layer of the light emitting diode is completed, individual light emitting diode chips are manufactured using the epitaxial layer.

(Experimental example 1)
Using the MOCVD equipment, the epitaxial layer having the structure described above was grown with reference to FIGS. Here, all other conditions were the same, and the Si doping position in the GaN / InGaN superlattice layer was varied. On the undoped GaN buffer layer 55, an n-type contact layer 57, an undoped intermediate layer 59, and a highly doped GaN electron reinforcing layer 61 are sequentially grown, and the superlattice layer is grown on the electron reinforcing layer 61. Then, an active region 65 having a multiple quantum well structure, a p-type AlGaN cladding layer 67, and a p-type GaN contact layer 69 were sequentially grown on the superlattice layer.

  In the comparative example, all GaN layers in the superlattice layer are doped with Si, and in the example, only the GaN layer that is the final layer of the superlattice layer is doped with Si at the same high concentration as the electron reinforcing layer 61. . The grown epitaxial layer was divided together with the substrate, and optical properties and electrical properties were measured. The results are shown in Table 1. Here, the electrostatic discharge (ESD) characteristics confirmed the occurrence of defects after performing an electrostatic discharge test on a good light emitting diode manufactured on the same wafer using a reverse voltage of 1000 V. The ESD path ratio is shown, and the light output and electrical characteristic values are values measured before the ESD test, expressed as percentages based on the comparative example.

  Referring to Table 1, according to the embodiment of the present invention, the peak wavelength is slightly decreased, the forward voltage is slightly increased, and the light output is slightly decreased in comparison with the comparative example. Not shown. However, the example shows that the leakage current is drastically reduced as compared with the comparative example, and shows that the ESD characteristics are extremely improved.

(Experimental example 2)
With reference to FIGS. 3 and 4, an epitaxial layer having the structure described above was grown using an MOCVD equipment. Here, all other conditions are the same, and the n-type contact layer is formed of only n-type GaN (comparative example) and the n-type AlGaN layer is interposed between n-type GaN layers (example). And compared.

  The grown epitaxial layer was divided together with the substrate, and optical characteristics and electrical characteristics were measured. The results are shown in Table 2. Here, the electrostatic discharge (ESD) characteristics confirmed the occurrence of defects after performing an electrostatic discharge test on a good light emitting diode manufactured on the same wafer using a reverse voltage of 1000 V. The ESD path ratio was shown, and the light output and leakage current were measured in good light-emitting diodes after the ESD test, and expressed as a percentage based on the comparative example.

  Referring to Table 2, the embodiment according to the present invention was shown to have a slightly reduced peak wavelength and a slightly reduced light output as compared with the comparative example. However, in the example, it was shown that the ESD characteristics were considerably improved as compared with the comparative example, and the leakage current of the light emitting diode that passed through the ESD was not different between the comparative example and the example.

  6 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention, FIG. 7 illustrates a schematic silicon doping profile of the light emitting diode, and FIG. 8 illustrates a spacer layer of the light emitting diode. FIG.

  6 to 8, the light emitting diode includes a substrate 121, an n-type contact layer 126, a spacer layer 128, an active region 129 having a multiple quantum well structure, and a p-type contact layer 133. A core layer 123 and an undoped GaN layer (u-GaN) 125 may be interposed between the substrate 121 and the n-type contact layer 126.

  The substrate 121 is a substrate for growing a gallium nitride based semiconductor layer, and is not particularly limited, such as sapphire, SiC, sfinnel, etc. For example, it may be a patterned sapphire substrate (PSS).

  In order to grow the u-GaN layer 125 on the substrate 121, the core layer 123 may be formed of (Al, Ga) N at a low temperature of 400 to 600 ° C., and is preferably formed of AlN. . The core layer may be formed with a thickness of about 25 nm.

  The u-GaN layer 125 is a layer for reducing the occurrence of defects such as potential between the substrate 121 and the n-type contact layer 126, and is grown at a relatively high temperature, for example, 900 to 1200 ° C. .

The n-type contact layer 126 is a layer on which an n ^- electrode 139 is formed, and may be doped with an n-type impurity such as Si or Ge. For example, the impurity concentration of the n-type contact layer 126 may be 5 × 10 ¹⁸ atm / cm ³ , for example, at a relatively high temperature, a first temperature T1, for example, 900 to 1200 ° C. It may be u-GaN grown to 2 μm or less.

The spacer layer 128 may be made of an (Al, In, Ga) N-based group III nitride semiconductor layer having a smaller band gap than the barrier layer of the active region 129 and a larger band gap than the well layer. For example, the spacer layer 1 28 _may include _{In x Ga 1-x N (} 0 ≦ x <1).

  The spacer layer 128 is doped with an n-type impurity at a high concentration to lower the forward voltage of the light emitting diode. As shown in FIG. 7, the doping concentration of the n-type impurity doped in the spacer layer 128 is higher than the doping concentration of the n-type impurity in the n-type contact layer 126.

  The In composition ratio of the spacer layer 128 is preferably smaller than the In composition ratio in the InGaN quantum well layer, but in this case, charges can be taken into the active region, and the light emission efficiency can be improved.

At this time, when the growth direction of the spacer layer 128 is used as a reference, a part of the thickness adjacent to the active region 129 is doped with an n-type impurity. Further, the remaining thickness regions except for the thickness region doped with n-type impurities are undoped with n-type impurities. In the region of the entire thickness of the spacer layer 128, the n-type impurity is doped only in a part of the thickness region adjacent to the active region 129, so that electrons are smoothly transferred from the spacer layer 128 into the active region 129. Can be injected. The doping concentration in the region doped with the n-type impurity may be relatively higher than the impurity doping concentration of the n-type contact layer 126, for example, 9 × 10 ¹⁹ atm / cm ³ . As a result, an increase in resistance of the spacer layer 128 can be prevented, and the efficiency of electron injection into the active region 129 can be increased by the electrons generated therein. On the other hand, as shown in FIG. 8, the spacer layer 128 has a smaller band gap than the barrier layer of the active region 129 and a larger band gap than the well layer (Al, In, Ga) N-based group III nitride. The semiconductor layers 128a and 128b may be alternately stacked. For example, the spacer layer 128 may be formed by alternately stacking In _x Ga _1-x N (0 ≦ x <1) 128a and In _y Ga _1-y N (0 ≦ y <1) 128b having different compositions. In _x Ga _1-x N (0 ≦ x <1) 1 28a is, for example, 30 to 40 mm thick, and In _y Ga _1-y N (0 ≦ y <1) 1 28b is 15 to 20 mm. It may be formed with a thickness.

The spacer layer 128 having a stacked structure of In _x Ga _1-x N (0 ≦ x <1) 128 a and In _y Ga _1-y N (0 ≦ y <1) 128 b is an active layer formed on the spacer layer 128. The crystallinity of the region 129 can be improved and distortion can be reduced. The spacer layer 128 may be formed in 7 to 15 periods. However, if the period is less than 7 periods, the effect of the spacer layer 128 to relieve strain caused in the active region is weak. Increase is not preferable.

At this time, in the spacer layer 128, at least one layer 128a and 128b adjacent to the active region 129 is doped with an n-type impurity. The remaining layers except for the layer doped with n-type impurities are undoped with n-type impurities. Of the spacer layer 128, only the InGaN layer 128a and / or the InGaN layer 128b adjacent to the active region 129 are doped with n-type impurities, so that electrons are smoothly injected from the spacer layer 128 into the active region 129. Can do. Further, the doping concentration of the n-type impurity doped InGaN layer 128a may be relatively higher than the impurity doping concentration of the n-type contact layer 126, for example, 9 × 10 ¹⁹ atm / cm ³ . As a result, an increase in resistance of the spacer layer 128 can be prevented, and the efficiency of electron injection into the active region 129 can be increased by the electrons generated therein.

  Since most of the spacer layer 128 is formed of an undoped layer, the leakage current of the light emitting diode can be reduced. Further, the junction characteristics between the spacer layer 128 and the active region 129 can be improved by doping the n-type impurity with high concentration only in at least one of the layers 128a and 128b adjacent to the active region 129.

  On the other hand, the spacer layer 128c adjacent to the active region 129 can be an InGaN layer further containing In than other semiconductor layers constituting the spacer layer 128. At this time, the amount of In contained in the spacer layer 128c adjacent to the active region 129 may be higher than that of the quantum well layer of the active region 129. In this case, the doping of the n-type impurity is performed in the n-type contact. It is preferable to dope to the doping concentration of the layer 126 and to the n-type contact layer 126 side in the spacer layer 128c.

  The active region 129 has a multiple quantum well structure in which quantum barrier layers and quantum well layers are alternately stacked, and the quantum well layer includes an InGaN layer. The barrier layer may be formed of a gallium nitride based semiconductor layer having a wider band gap than the quantum well layer, for example, GaN, InGaN, AlGaN, or AlInGaN. The In composition ratio in the InGaN quantum well layer is determined by a desired light wavelength. The active region 129 is not doped with an n-type impurity such as Si or Ge.

  A p-type contact layer 133 is located on the active region 129. The p-type contact layer 133 may be formed on the active region 129, for example, with GaN.

Also, a transparent electrode (not shown) such as Ni / Au or indium tin oxide film (ITO) is formed on the p-type contact layer 133, and the p ^- electrode 134 is formed thereon by, for example, a lift-off process. It may be formed. Further, an n ^- electrode 135 such as Ti / Al may be formed on the n-type contact layer 126 by a lift-off process.

In the embodiment described above, in the active region 129, the quantum barrier layer and the quantum well layer are not doped with n-type impurities, and the active region 129 is substantially free of n-type impurities. In _x Ga _1-x N The layer is grown on the spacer layer 128 having a stacked structure of (0 ≦ x <1) 128a and In _y Ga _1-y N (0 ≦ y <1) 128b. Therefore, the crystallinity of the active region 129 is improved and distortion is reduced. In addition, the n-type impurity is doped only in the InGaN layer 128a and / or the InGaN layer 128b adjacent to the active region 129 in the spacer layer 128, so that electrons are smoothly injected into the active region 129 from the spacer layer 128. The recombination rate of carriers in the active region 129 can be increased. As a result, the light emission efficiency of the light emitting diode is improved.

  9 and 10 are a cross-sectional view and a silicon doping profile for explaining a light emitting diode according to another embodiment of the present invention, respectively.

  Referring to FIGS. 9 and 10, the light emitting diode according to the present embodiment is almost the same as the stacked structure of the light emitting diodes described with reference to FIGS. 6 to 8, and simply the spacer layer 128 and the n-type contact layer 126. And an intermediate layer 127 doped with n-type impurities, and a p-type cladding layer 131 is interposed between the active region 129 and the p-type contact layer 133.

As shown in FIG. 10, the intermediate layer 127 is relatively higher than the impurity doping concentration of the n-type contact layer 126 and relatively lower than the n-type impurity concentration in the spacer layer 128, for example, 2 It may be doped with n-type impurities at a concentration of .5 × 10 ¹⁹ atm / cm ³ and may have, for example, an n-AlGaN layer.

  The closer the n-AlGaN layer is to the active region 129, the lower the Al composition, or the lower the Al composition step by step. At this time, the composition range of Al is 10 to 15%, and is laminated with a thickness of 10 to 100 nm, preferably 30 to 60 nm. By setting the composition of Al in the n-AlGaN layer to be gradually or lower step by step, the energy level of the intermediate layer 127 becomes lower as it is closer to the active region 129, and the intermediate layer 127 and the spacer layer 128 are reduced. Can have the lowest value at the interface.

  The n-AlGaN layer may be formed with a multilayer structure. For example, the n-AlGaN layer may be formed of an AlGaN / GaN or AlGaN / InGaN multilayer film. When the n-AlGaN layer is formed of a multilayer film, it has an object to improve the crystallinity of the AlGaN layer. For example, the composition of Al in the n-AlGaN layer may gradually or gradually decrease toward the active region 129.

On the other hand, the intermediate layer 127, as shown in FIG. 11, may have a n-GaN 1 27a which are laminated in a thickness of 200~300Å between the n-AlGaN layer 127b and the spacer layer 128.

  Further, as shown in FIG. 12, the intermediate layer 127 may include an undoped GaN layer 127c and a low-doped n-GaN layer 127d, and the intermediate layer 127 includes an n-AlGaN layer 127b and an n-type contact layer 126. For example, the layers may be stacked with a thickness of 1000 to 2000 mm. In the drawing, it is shown that an undoped GaN layer 127c is formed on a low-doped n-GaN layer 127d. However, the present invention is not limited to this, and the undoped GaN layer 127c is formed as necessary. An n-GaN layer 127d may be formed on the GaN layer 127c. Further, only one of the undoped GaN layer 127c and the low-doped n-GaN layer 127d may be formed.

As shown in FIG. 13, the intermediate layer 127 includes an n-GaN 127a, an n-AlGaN layer 127b, an undoped GaN layer 127c, and a low-doped n between the spacer layer 128 and the n-type contact layer 126. -You may have GaN layer 127d. The undoped GaN layer 127c is GaN not intentionally doped with impurities, and may be formed to a thickness of 100 to 5000 mm. Since the undoped GaN layer 127 c is not doped with impurities, the specific resistance is relatively higher than that of the n-type contact layer 126. Therefore, electrons flowing from the n-type contact layer 126 into the active region 129 can be uniformly dispersed in the n-type contact layer 126 before passing through the undoped GaN layer 127c.

The low-doped n-GaN layer 127 d is doped with a lower concentration of impurities than the n-type contact layer 126, and therefore has a relatively higher specific resistance than the n-type contact layer 126. Therefore, electrons flowing from the n-type contact layer 126 into the active region 129 can be uniformly dispersed in the n-type contact layer 126 before passing through the low-doped n-GaN layer 127 d .

  Meanwhile, the p-type cladding layer 131 functions as an electron blocking layer and may be formed of AlGaN or a multilayer structure. For example, the p-type cladding layer 131 may be formed of a multilayer film of AlGaN / GaN or AlGaN / InGaN. When the p-type cladding layer 131 is formed of a multilayer film, the crystallinity of the AlGaN layer can be improved. For example, the p-type cladding layer 131 may be formed of AlGaN in a layer adjacent to the active region 129, and the Al composition may gradually decrease as the AlGaN layer goes to the p-type contact layer 133. This is to reduce the polarization phenomenon at the interface between the p-type cladding layer 131 and the p-type contact layer 133. In addition, the first AlGaN layer adjacent to the active region 129 is preferably thinner than the other layers in the p-type cladding layer 131. Meanwhile, the AlGaN layer of the p-type cladding layer 131 preferably has a higher energy level than the n-AlGaN layer 127b. That is, in the Al composition, the AlGaN layer of the p-type cladding layer 131 is set higher than the n-AlGaN layer 127b. Since the AlGaN layer of the p-type cladding layer 131 has a higher Al composition than the n-AlGaN layer 127b, the conduction band on the n side with the active layer as the center when a forward voltage is applied. Is higher than the conduction band on the p side, and is intended to alleviate this.

Further, an InGaN layer may be further included between the active region 129 and the p-type cladding layer 131. In this case, in the InAlN layer, the In composition is about 0.10 to 0.20, and the In composition may be about 0.17 to 0.18. At this time, the growth temperature of the InAlN layer may be, for example, 845 ° C., or may be formed of an InN / AlN superlattice structure. The thickness of the InAlN layer is about 10 to 30 nm, and preferably about 18 to 22 nm. The p-type cladding layer 131 may be formed thinner than the thickness of the AlGaN layer. For example, the thickness of the InAlN layer can be reduced to a thickness of about 3: 2 compared to the AlGaN layer that forms the p-type cladding layer 131. The doping concentration of the p-type impurity in the InAlN layer is about 8 × 10 ¹⁷ / cm ³ , and it is preferable to dope InN with a superlattice structure of InN / AlN. In this case, the InAlN layer serves to increase the hole concentration. The InAlN layer formed between the active region 129 and the p-type cladding layer 131 can reduce the influence of temperature on the active region 129 when growing the p-type cladding layer 131 functioning as an electron block.

  In the embodiment of the present invention described above, the number of layers doped with n-type impurities in the spacer layer 128, the doping concentration of n-type impurities, the stacking thickness, the number of stacking, the intermediate layer 127, the undoped layer, n The thickness of the mold cladding layer is related to each other and is adjusted as necessary.

As described above, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention defined in the appended claims.

Claims (39)

An n-type contact layer doped with silicon;
a p-type contact layer;
An active region interposed between the n-type contact layer and the p-type contact layer;
A superlattice layer interposed between the n-type contact layer and the active region;
An undoped intermediate layer interposed between the superlattice layer and the n-type contact layer;
An electron reinforcing layer interposed between the undoped intermediate layer and the superlattice layer,
The superlattice layer, the mini-silicon closest final layer to the active region is doped, except the final layer is undoped,
The light emitting diode according to claim 1, wherein a silicon doping concentration of the final layer is higher than a silicon doping concentration of the n-type contact layer.   The light emitting diode according to claim 1, wherein a final layer of the superlattice layer is in contact with an active region.   The light emitting diode according to claim 1, wherein the electron reinforcing layer is doped with silicon, and a silicon doping concentration of the electron reinforcing layer is higher than a silicon doping concentration of the n-type contact layer.   The light emitting diode according to claim 3, wherein the electron reinforcing layer is in contact with the superlattice layer.   5. The electron reinforcing layer is formed of GaN, the superlattice layer is formed by alternately stacking GaN and InGaN, and the final layer of the superlattice layer is formed of GaN. Light emitting diode.   6. The light emitting diode according to claim 5, wherein the n-type contact layer has a GaN layer, and the undoped intermediate layer is made of GaN.   The light emitting diode according to claim 1, wherein a silicon doping concentration of a final layer of the superlattice layer is the same as a silicon doping concentration of the electron reinforcing layer. Forming a buffer layer on the substrate;
Forming an n-type contact layer doped with silicon on the buffer layer;
Forming an undoped intermediate layer on the n-type contact layer;
Forming an electron reinforcing layer on the intermediate layer;
Forming a superlattice layer on the electron reinforcing layer;
Forming an active region on the superlattice layer,
The superlattice layer is doped with silicon only in the final layer, and other than the final layer is undoped,
A method of manufacturing a light emitting diode, wherein a silicon doping concentration of the final layer is higher than a silicon doping concentration of an n-type contact layer. A nitrogen source gas and a metal source gas are supplied into the chamber, and an electron reinforcing layer of a gallium nitride based semiconductor layer is grown at a first temperature,
Interrupting the supply of the metal source gas, and maintaining the grown n-side gallium nitride based semiconductor layer on the first temperature substrate for a first time;
After the first time has elapsed, the temperature of the substrate is lowered to a second temperature,
The method according to claim 8, further comprising supplying a metal source gas into the chamber and growing the superlattice layer at the second temperature.   The method of manufacturing a light emitting diode according to claim 9, wherein the first time is in a range of 3 minutes to 10 minutes. After growing the active layer on the superlattice layer, the supply of the metal source gas is interrupted,
Raising the temperature of the substrate to a third temperature for a second time;
The method of manufacturing a light emitting diode according to claim 9, further comprising growing a p-type gallium nitride based semiconductor layer on the active layer at the third temperature.   12. The method of manufacturing a light emitting diode according to claim 11, wherein the second time is in a range of 5 minutes to 15 minutes. An n-type contact layer doped with silicon;
a p-type contact layer;
An active region interposed between the n-type contact layer and the p-type contact layer;
A superlattice layer interposed between the n-type contact layer and the active region;
An undoped intermediate layer interposed between the superlattice layer and the n-type contact layer;
An electron reinforcing layer interposed between the undoped intermediate layer and the superlattice layer,
The superlattice layer is doped with silicon only in the final layer closest to the active region, and other than the final layer is undoped,
A silicon doping concentration of the final layer is higher than a silicon doping concentration of the n-type contact layer;
The light emitting diode, wherein the n-type contact layer has an n-type GaN layer and an n-type AlGaN layer interposed between the n-type GaN layers. A substrate,
A low temperature buffer layer located on the substrate;
The light emitting diode according to claim 13, further comprising an undoped GaN layer interposed between the low-temperature buffer layer and the n-type contact layer. The final layer of the superlattice layer, the light emitting diode according to claim 1 3, characterized in that in contact with the active region. The superlattice layer, are formed by laminating GaN and InGaN are alternately light-emitting diode according to claim 1 5, characterized in that the final layer of the superlattice layer is formed by GaN.   The light emitting diode according to claim 13, wherein the silicon doping concentration of the final layer of the superlattice layer is the same as the silicon doping concentration of the electron reinforcing layer.   The light emitting diode according to claim 13, wherein the silicon doping concentration of the final layer of the superlattice layer is the same as the silicon doping concentration of the electron reinforcing layer.   The light emitting diode according to claim 13, wherein the electron reinforcing layer is in contact with the superlattice layer. an n-type contact layer;
A p-type contact layer formed on the n-type contact layer;
An active region having a multiple quantum well structure interposed between the n-type contact layer and the p-type contact layer;
A spacer layer interposed between the n-type contact layer and the active region,
The spacer layer has superlattice layers alternately stacked on each other, and at least one layer adjacent to the active region is doped with an n-type impurity, and other than the at least one layer is an n-type. Impurities are undoped,
A doping concentration of the n-type impurity is relatively higher than an impurity doping concentration of the n-type contact layer;
The light emitting diode is characterized in that the active region is undoped with n-type impurities. 21. The light emitting device according to claim 20 , wherein the spacer layer includes In, and the In content is higher than an In content in the barrier layer of the active region and lower than an In content in the well layer. diode. 21. The light emitting diode according to claim 20 , wherein the active region has a multiple quantum well structure having an InGaN layer. The light emitting diode according to claim 20 , wherein the spacer layer includes an InGaN layer. The spacer layer _is, the _{In x Ga 1-x N (} 0 ≦ x <1) and _{In y Ga 1-y N (} 0 ≦ y <1) according to claim 2 3, wherein a stacked alternately The light emitting diode as described. An intermediate layer formed between the spacer layer and the n-type contact layer;
The intermediate layer is doped with n-type impurities relatively higher than the impurity doping concentration of the n-type contact layer and relatively lower than the impurity doping concentration of the spacer layer doped with the n-type impurity. 21. The light emitting diode according to claim 20 , further comprising a layer. The light emitting diode according to claim 25 , wherein the intermediate layer includes an n-type AlGaN layer. The light emitting diode according to claim 26 , wherein the closer the n-type AlGaN layer is to the active region, the lower the composition of Al gradually or stepwise. 27. The light emitting diode according to claim 26 , wherein the n-type AlGaN layer is formed of an AlGaN / GaN or AlGaN / InGaN multilayer structure. The light emitting diode according to claim 26 , wherein the intermediate layer further includes an n-GaN layer between the spacer layer and the n-type AlGaN layer. The intermediate layer, between the n-type AlGaN layer and the n-type contact layer, GaN layer of undoped to claim 2 6, characterized in that it further comprises at least one of the n-GaN layer of Rodopu The light emitting diode as described. 21. The light emitting diode of claim 20 , further comprising a p-type cladding layer formed between the active region and the p-type contact layer. The p-type cladding layer, the light emitting diode of claim 3 1, characterized in that it comprises a p-type AlGaN layer. The p-type AlGaN layer, AlGaN / GaN or AlGaN / InGaN light emitting diode according to claim 3 2, characterized in that it is formed of a multilayer film structure. The p-type AlGaN layer, the light emitting diode of claim 3 3, wherein the layer adjacent to the active region is formed by AlGaN. The p-type AlGaN layer, the AlGaN layer adjacent to the active region, the light emitting diode of claim 3 3, wherein the thin compared to other layers of the p-type cladding layer. The p-type AlGaN layer, the light emitting diode of claim 3 2, characterized in that the composition of Al toward the p-type contact layer is gradually or stepwise reduced. The light emitting diode of claim 3 1, further comprising a InAlN layer between the active region and the p-type cladding layer. 38. The light emitting diode according to claim 37 , wherein the InAlN layer is formed of an InN / AlN superlattice structure. 39. The light emitting diode according to claim 38 , wherein the InAlN layer has an InN / AlN superlattice structure, and the InN layer is doped with a p-type impurity.