WO2022165884A1 - 一种新型增强型GaN HEMT器件结构 - Google Patents

一种新型增强型GaN HEMT器件结构 Download PDF

Info

Publication number
WO2022165884A1
WO2022165884A1 PCT/CN2021/078370 CN2021078370W WO2022165884A1 WO 2022165884 A1 WO2022165884 A1 WO 2022165884A1 CN 2021078370 W CN2021078370 W CN 2021078370W WO 2022165884 A1 WO2022165884 A1 WO 2022165884A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
layer
gan
junction
etching
Prior art date
Application number
PCT/CN2021/078370
Other languages
English (en)
French (fr)
Inventor
翁加付
周炳
Original Assignee
宁波海特创电控有限公司
桂林理工大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 宁波海特创电控有限公司, 桂林理工大学 filed Critical 宁波海特创电控有限公司
Publication of WO2022165884A1 publication Critical patent/WO2022165884A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Definitions

  • the invention relates to the technical field of electronic component manufacturing, in particular to a novel enhancement mode GaN HEMT (Gallium Nitride High Electron Mobility Transistor) device structure.
  • GaN HEMT Gallium Nitride High Electron Mobility Transistor
  • Enhancement-mode GaN-based High Electron Mobility Transistor (HEMT) devices have always been a hot spot in the research of nitride devices.
  • p-GaN is used as the gate cap layer to realize enhancement-mode GaN.
  • HEMT device technology has great potential in interface quality, device on-state characteristics, GaN high-power applications, etc., and has received extensive attention in recent years.
  • the forward gate breakdown voltage produced by p-GaN gate HEMTs is greater than 10 V, the gate/gate leakage due to gate leakage at high electric fields The p-GaN interface degrades and the maximum gate bias voltage allowed for reliable long-term operation will be significantly reduced.
  • the threshold voltage of Schottky-type p-GaN gate power HEMTs is relatively small, which in turn imposes high requirements on gate ringing and false turn-on suppression. Therefore, it is highly desirable to develop a device structure that can further reduce gate leakage and increase forward gate breakdown voltage, so that larger gate drive bias can be obtained to ensure safe operation.
  • the purpose of the present invention is to provide a new type of enhanced GaN HEMT device structure.
  • a PN junction gate type GaN HEMT is designed, and a layer of n-GaN is added on the p-GaN to form a PN junction.
  • the PN junction is applied with voltage at the gate, the PN junction is reverse biased, which increases the gate breakdown voltage Vg and has a large gate voltage swing, which is very suitable for the application of power switches and can obtain a larger gate drive bias. to ensure safe operation.
  • a novel enhancement mode GaN HEMT device structure is prepared by the following steps.
  • AlN nucleation layer, GaN buffer layer, AlN insertion layer, AlGaN barrier layer, and GaN layer are grown from bottom to top on Si substrate by metal organic chemical vapor deposition (MOCVD) to form Si base GaN epitaxial wafers.
  • MOCVD metal organic chemical vapor deposition
  • PN junction gate stack growth The PN junction gate stack is grown by metal organic chemical vapor deposition, which consists of a 100nm thick p-GaN layer and a 30nm thick n-GaN layer from bottom to top.
  • the Mg doping concentration was 3 ⁇ 10 19 cm ⁇ 3
  • the Si doping concentration of the n-GaN layer was 1 ⁇ 10 19 cm ⁇ 3 .
  • Etching the PN junction stack aligning the sample with AZ6130 glue, rotating at 6000 rpm, and baking on a hot plate at 95°C for 2 minutes; and the first alignment mark overlay photolithography, developing and fixing to form a grid Electrode window; the n-GaN/p-GaN stack outside the gate region was removed by dry etching using low-damage BCl 3 /Cl 2 based inductively coupled plasma (ICP); after that, annealed at 850°C in N 2 atmosphere 25min to reactivate the n-GaN/p-GaN stack, the stack is 3 ⁇ m away from the source, the gate-source spacing is 15 ⁇ m, and the length is 2 ⁇ m.
  • ICP inductively coupled plasma
  • Source and drain ohmic contact swipe AZ6130 on the sample, rotate at 6000 rpm, and bake on a hot plate at 95°C for 2 minutes; overlay photolithography with the alignment marks in step 3), develop, and fix to form a source/ Drain electrode window; then use electron beam evaporation equipment to complete metal stack deposition to form Ti/Al/Ni/Au metal layer; Rapid thermal annealing at 850°C for 30s to form ohmic contact electrodes with source and drain electrodes.
  • Passivation layer deposition by plasma-enhanced chemical vapor deposition (PECVD) method, the gas flow rate is 600 sccm SiH 4 , 1960 sccm N 2 and 20 sccm NH 3 as chemical reaction sources, the temperature is 250 °C, and the radio frequency power is A 160 nm thick Si 3 N 4 passivation layer was deposited at 60 W in a plasma-enhanced chemical vapor deposition chamber with a pressure of 500 Torr.
  • PECVD plasma-enhanced chemical vapor deposition
  • Gate groove etching throw polymethyl methacrylate (PMMA) electron beam glue on the sample, rotate at 2000 rpm, bake on a hot plate at 180 °C for 10 min; use electron beam exposure at a distance of 3 ⁇ m from the source electrode, The gate groove pattern was exposed at a position with a gate-source spacing of 15 ⁇ m, and the length of the gate groove pattern was 2 ⁇ m; the gate groove window was formed after developing for 25 s and fixing for 5 s; using RIE technology, under the power of 50 W for 2 min, through the CF 4 plasma dry method The Si 3 N 4 layer in the gate region is removed by etching to form a gate trench.
  • PMMA polymethyl methacrylate
  • Gate metal deposition the sample is spun double-layer electron beam glue, the lower layer is the copolymer glue, the speed is 3000 rpm, bake on a hot plate at 150 °C for 15 minutes, the upper layer is PMMA glue, the speed is 3000 Rotation/min, bake on a hot plate at 180°C for 10min; at the position of the grid groove, use electron beam exposure to overwrite the grid electrode pattern, set the grid electrode size to 2 ⁇ m, after exposure, develop for 25s and fix for 5s to form a grid electrode pattern window; A Ni/Au metal layer was grown on the dielectric layer forming the gate pattern window by electron beam evaporation, and Schottky contact was formed between the dielectric layer and the dielectric layer, and then the photoresist was removed with acetone ; Rapid thermal annealing was performed for 30 s to form Schottky gate electrodes.
  • Protective layer deposition by plasma-enhanced chemical vapor deposition method, with gas flow of 1420 sccm of N 2 O, 150 sccm of SiH 4 and 392 sccm of N 2 as chemical reaction sources, the temperature is 300 °C, the radio frequency power is 15 W, A 200-nm-thick SiO2 protective layer was deposited in a plasma-enhanced chemical vapor deposition chamber at a pressure of 0.9 Torr.
  • the thickness of the AlN nucleation layer is 20 nm
  • the thickness of the GaN buffer layer is 2 ⁇ m
  • the thickness of the AlN insertion layer is 1 nm
  • the thickness of the AlGaN barrier layer is 20 nm
  • the thickness of the GaN layer is 2 ⁇ m. The thickness is 2nm.
  • the wavelength of photolithography in the steps 4), 6) and 12) is all 435nm
  • the developing solution is 2.38% tetramethylammonium hydroxide (TMAH)
  • the fixing solution is water .
  • the dry etching in step 5) lasted for 2 min at a power of 50 W, and the etching depth was 280 nm.
  • the width of the source electrode and the drain electrode are both 2 ⁇ m, and the distance between the source electrode and the drain electrode is 20 ⁇ m.
  • the developer in the steps 9) and 10) is a mixed solution with a volume ratio of methyl isobutyl ketone and isopropanol (MIBK:IPA) of 1:3, and the fixing solution is IPA.
  • the beneficial effects of the present invention are as follows: 1) The present invention designs a PN junction gate type GaN HEMT based on the p-type gate. A layer of n-GaN is added on the p-GaN to form a PN junction, and the PN junction is used to add a layer of n-GaN to the gate. When the voltage is high, the PN junction is reverse biased, which increases the gate breakdown voltage Vg and has a large gate voltage swing, which is very suitable for power switch applications.
  • the PN junction of the present invention can withstand a higher gate breakdown voltage, because the breakdown voltage of the Schottky mainly depends on the Schottky junction, Schottky junction is a sudden junction, which belongs to unilateral depletion, while PN junction is bidirectional depletion, so the overall depletion layer width is much higher than the Schottky gate, so this device improves the gate breakdown voltage .
  • FIG. 1 is a schematic view of the structure of the workpiece during substrate cleaning of the present invention.
  • FIG. 2 is a schematic view of the structure of the workpiece when the table is isolated according to the present invention.
  • FIG. 3 is a schematic view of the structure of the workpiece during the etching of the PN junction of the present invention.
  • FIG. 4 is a schematic view of the structure of the workpiece in the ohmic contact of the present invention.
  • FIG. 5 is a schematic view of the workpiece structure during the deposition of the passivation layer of the present invention.
  • FIG. 6 is a schematic view of the workpiece structure during gate trench etching of the present invention.
  • FIG. 7 is a schematic diagram of the workpiece structure during the deposition of the gate metal of the present invention.
  • FIG. 8 is a schematic diagram of the structure of the workpiece during the protective deposition of the present invention.
  • FIG. 9 is a schematic diagram of the structure of the workpiece during the deposition of the hole and interconnection metal of the present invention.
  • Example 1 see Fig. 1 to figure 9 .
  • the present invention provides a novel enhanced GaN HEMT device structure, which is prepared by the following steps.
  • a 20nm-thick AlN nucleation layer, a 2- ⁇ m-thick GaN buffer layer, and a 1nm-thick AlN layer were grown from bottom to top by metal organic chemical vapor deposition (MOCVD) on a 6-inch (111) Si substrate. Insertion layer, 20 nm thick AlGaN barrier layer and 2 nm thick GaN capping layer form Si-based GaN epitaxial wafer.
  • MOCVD metal organic chemical vapor deposition
  • PN junction gate stack growth The PN junction gate stack is grown by metal organic chemical vapor deposition, which consists of a 100nm thick p-GaN layer and a 30nm thick n-GaN layer from bottom to top.
  • the Mg doping concentration was 3 ⁇ 10 19 cm ⁇ 3
  • the Si doping concentration of the n-GaN layer was 1 ⁇ 10 19 cm ⁇ 3 .
  • Photolithography and alignment mark formation S9912 was applied to the sample at a rotational speed of 6000 rpm, baked on a hot plate at 100°C for 5 minutes, and then passed through UV lithography (wavelength 435nm) and development (developer with a mass concentration of 2.38 % TMAH)/fixing (fixing solution is water) to form etching windows and at the same time to form alignment marks on the photoresist.
  • UV lithography wavelength 435nm
  • development developer with a mass concentration of 2.38 % TMAH
  • fixing solution is water
  • Etching the PN junction stack aligning the sample with AZ6130, rotating at 6000 rpm, and baking on a hot plate at 95°C for 2 minutes; and the first alignment mark overlay lithography (wavelength 435nm), developing (The developer is TMAH with a mass concentration of 2.38%) and fixing (the fixer is water) to form the gate electrode window; use low-damage BCl 3 /Cl 2 based inductively coupled plasma (ICP) dry etching to remove the n- outside the gate region.
  • ICP inductively coupled plasma
  • GaN/p-GaN stack after that, the n-GaN/p-GaN stack was reactivated by annealing at 850°C for 25min in N atmosphere, the stack was 3 ⁇ m from the source and the gate-source spacing was 15 ⁇ m position, length is 2 ⁇ m (see Figure 3).
  • Source and drain ohmic contact put the glue AZ6130 on the sample, the rotation speed is 6000 rpm, and bake on a hot plate at 95°C for 2 minutes; and the alignment mark is overlaid with photolithography (wavelength 435nm), and developed (the developer is the quality TMAH with a concentration of 2.38%) and fixing (fixing solution is water) to form source-drain electrode windows; then electron beam evaporation equipment is used to complete metal stack deposition to form Ti/Al/Ni/Au (20 nm/50 nm/ 40nm/50 nm) ) metal layer; rapid thermal annealing at 850 °C for 30 s to form ohmic contact electrodes with both source/drain electrode widths of 2 ⁇ m and source-drain spacing of 20 ⁇ m (see Figure 4).
  • Passivation layer deposition by plasma-enhanced chemical vapor deposition (PECVD) method, the gas flow rate is 600 sccm SiH 4 , 1960 sccm N 2 and 20 sccm NH 3 as chemical reaction sources, the temperature is 250 °C, and the radio frequency power is A 160-nm-thick Si 3 N 4 passivation layer was deposited at 60 W in a plasma-enhanced chemical vapor deposition chamber with a pressure of 500 Torr (see Figure 5).
  • PECVD plasma-enhanced chemical vapor deposition
  • Gate metal deposition throw double-layer electron beam glue on the sample, the lower layer is Copolymer glue, the rotation speed is 3000 rpm, bake on a hot plate at 150 °C for 15 minutes, the upper layer is PMMA glue, the speed is 3000 rpm, 180 °C At the position of the grid groove, the grid electrode pattern is overwritten by electron beam exposure, and the grid electrode size is set to 2 ⁇ m.
  • the gate electrode pattern window is formed for IPA) 5s; the metal layer of Ni/Au (30 nm/50 nm) is grown on the dielectric layer forming the gate pattern window by electron beam evaporation, and a Schottky contact is formed between the dielectric layer and the dielectric layer. , and then use acetone to remove the photoresist; then in a N 2 atmosphere, perform rapid thermal annealing at 400 °C for 30 s to form a Schottky gate electrode (see Figure 7).
  • Protective layer deposition by PECVD method, the gas flow rate is 1420sccm of N2O , 150sccm of SiH4 and 392sccm of N2 as chemical reaction sources, the temperature is 300 °C, the radio frequency power is 15 W, and the PECVD chamber pressure is A 200 nm thick SiO 2 protective layer was deposited at 0.9 Torr (see Figure 8).

Abstract

本发明提供一种新型增强型GaN HEMT器件结构，由如下步骤制备而成：外延生长；PN结栅叠层生长；Si基GaN外延晶片清洗；光刻及对准标记形成；台面隔离；刻蚀PN结叠层；源、漏欧姆接触；钝化层沉积；栅槽刻蚀；栅金属沉积；保护层沉积；开孔及金属互联。本发明以p型栅为基础设计了PN结栅型GaN HEMT，通过在p-GaN上面加了一层n-GaN，形成PN结，利用PN结在栅加电压时，PN结反向偏置，增大栅极击穿电压Vg，具有大的栅压摆幅，非常适合于功率开关的应用，可以获得更大的栅极驱动偏置以确保安全操作。

Description

一种新型增强型GaN HEMT器件结构 技术领域
本发明涉及电子元器件制造技术领域，具体涉及一种新型增强型GaNHEMT（氮化镓高电子迁移率晶体管）器件结构。
 背景技术
增强型GaN基高电子迁移率晶体管（HEMT）器件一直是氮化物器件研究中的热点，已报道的几种主流实现增强型应用的方法中，以p-GaN作为栅帽层实现了增强型GaN HEMT器件技术在界面质量、器件开态特性、GaN大功率应用中等方面具有极大的潜力，近年来受到广泛关注。
尽管p-GaN栅极HEMT产生的正向栅极击穿电压大于10 V，但由于高电场下的栅极泄漏引起的栅极/ p-GaN界面退化，长期可靠运行所允许的最大栅极偏置电压将明显降低。导致高功率电源开关应用中，肖特基型p-GaN栅极功率HEMT的阈值电压相对较小，这又对抑制栅极振铃和误导通产生了较高要求。因此，非常需要开发一种能够进一步减少栅极泄漏并提高正向栅极击穿电压的器件结构，从而可以获得更大的栅极驱动偏置以确保安全操作。
 技术问题
本发明的目的是提供一种新型增强型GaN HEMT器件结构，以p型栅为基础设计了PN结栅型GaN HEMT，通过在p-GaN上面加了一层n-GaN，形成PN结，利用PN结在栅加电压时，PN结反向偏置，增大栅极击穿电压Vg，具有大的栅压摆幅，非常适合于功率开关的应用，可以获得更大的栅极驱动偏置以确保安全操作。
 技术解决方案
为了实现上述目的，本发明采用的技术方案如下。
一种新型增强型GaN HEMT器件结构，由如下步骤制备而成。
1）外延生长：在Si衬底上通过金属有机化学气相沉积（MOCVD）自下而上分别生长AlN成核层、GaN缓冲层、AlN插入层、AlGaN势垒层、GaN冒层，形成Si基GaN外延晶片。
2）PN结栅叠层生长：通过金属有机化学气相沉积生长PN结栅叠层，自下而上由100nm厚的p-GaN层和30nm厚的n-GaN层组成，其中p-GaN层的Mg掺杂浓度为3×10 19cm -3，而n-GaN层的Si掺杂浓度为1×10 19cm -3。
3）Si基GaN外延晶片清洗：将外延衬底依次放入MOS级丙酮和MOS级乙醇中超声3 min，用流动的去离子水清洗样片2min并用氮气枪吹干；接着将器件浸入HF:HCl:H 2O体积比为1:4:20的溶液1min，去除表面上的天然氧化物，然后用去离子水冲洗2min并用氮气枪吹干，完成样品清洗。
4）光刻及对准标记形成：对样品甩正胶S9912，转速6000转/min，在100℃的热板上烘5min，通过紫外光刻、显影、定影，形成腐蚀窗口，同时在光刻胶上形成对准标记。
5）台面隔离：采用反应离子刻蚀（RIE）法，利用Cl 2作为反应刻蚀气体，干法刻蚀GaN冒层、AlGaN势垒层、AlN插入层和部分GaN缓冲层；将有源区以外的异质结二维电子气刻蚀掉，形成器件有源区之间的隔离。
6）刻蚀PN结叠层：对样品甩正胶AZ6130，转速为6000转/min，95℃的热板上烘2min；与第一次的对准标记套刻光刻，显影、定影形成栅电极窗口；使用低损伤BCl 3/Cl 2基电感耦合等离子体（ICP）干法蚀刻去除栅区外部的n-GaN/p-GaN叠层；之后，在N 2气氛中于850°C进行退火25min，以重新激活n-GaN/p-GaN叠层，叠层在距离源极3 μm，栅源间距为15 μm的位置，长度为2μm。
7）源、漏欧姆接触：对样品甩正胶AZ6130，转速为6000转/min，95℃的热板上烘2min；与步骤3）的对准标记套刻光刻，显影、定影形成源/漏电极窗口；然后采用电子束蒸发设备完成金属堆栈沉积，形成Ti/Al/Ni/Au金属层；在850℃下快速热退火30s，形成有源极与漏极的欧姆接触电极。
8）钝化层沉积：通过等离子体增强化学气相沉积（PECVD）法，以气体流量为600sccm的SiH 4、1960sccm的N 2和20sccm的NH 3作为化学反应源，温度为250 ℃，射频功率为60 W，等离子体增强化学气相沉积的腔室压力为500Torr的条件下沉积160 nm厚的Si 3N 4钝化层。
9）栅槽刻蚀：对样品甩聚甲基丙烯酸甲酯（PMMA）电子束胶，转速为2000转/min，180℃的热板上烘10min；采用电子束曝光在距离源极3 μm，栅源间距为15 μm的位置曝光栅槽图形，栅槽图形长度为2μm；经显影25s、定影5s形成栅槽窗口；利用RIE技术，在50W 的功率下持续2min，通过CF 4等离子体干法刻蚀去除栅极区域的Si 3N 4层，形成栅槽。
10）栅金属沉积：对样品甩双层电子束胶，下层为下层为共聚物（Copolymer）胶，转速为3000转/min，150℃的热板上烘15min，上层为PMMA胶，转速为3000转/min，180℃的热板上烘10min；在栅槽位置处，采用电子束曝光套刻栅电极图形，设置栅电极尺寸2μm，曝光后经显影25s、定影5s形成栅电极图形窗口；采用电子束蒸发法在形成栅极图形窗口的介质层上生长Ni/Au金属层，与介质层之间形成肖特基接触，再使用丙酮将光刻胶去除；之后在N 2气氛中，400℃下进行快速热退火30 s形成肖特基栅电极。
11）保护层沉积：通过等离子体增强化学气相沉积法，以气体流量为1420sccm的N 2O、150sccm的SiH 4和392sccm的N 2作为化学反应源，温度为300 ℃，射频功率为15 W，等离子体增强化学气相沉积的腔室压力为0.9Torr的条件下沉积200 nm厚的SiO 2保护层。
12）开孔及金属互联：对样品甩正胶S9912，转速6000转/min，在100℃的热板上烘5min，通过紫外光刻、显影、定影形成光刻窗口；最后利用反应离子刻蚀技术将欧姆接触电极和肖特基栅电极表面覆盖的Si 3N 4保护层材料移除，刻蚀反应气体采用CF 4和O 2，射频功率为50 W完成开孔；互联金属采用粘附性好的Ti/Au金属叠层，利用电子束蒸发和剥离工艺完成。
根据以上方案，所述步骤1）中AlN成核层的厚度为20nm、GaN缓冲层的厚度为2 μm、AlN插入层的厚度为1nm、AlGaN势垒层的厚度为20 nm、GaN冒层的厚度为2nm。
根据以上方案，所述步骤4）、步骤6）与步骤12）中光刻的波长均为435nm，显影液均为质量浓度2.38%的四甲基氢氧化铵（TMAH），定影液均为水。
根据以上方案，所述步骤5）中干刻时在50 W的功率下持续2 min，刻蚀深度为280 nm。
根据以上方案，所述步骤7）中源极与漏极的宽度均为2 μm，源极与漏极间距为20 μm。
根据以上方案，所述步骤9）与步骤10）中的显影液为甲基异丁基酮与异丙醇（MIBK:IPA）体积比为1:3的混合溶液，定影液为IPA。
 有益效果
本发明的有益效果是：1）本发明以p型栅为基础设计了PN结栅型GaN HEMT，通过在p-GaN上面加了一层n-GaN，形成PN结，利用PN结在栅加电压时，PN结反向偏置，增大栅极击穿电压Vg，具有大的栅压摆幅，非常适合于功率开关的应用。
2）与传统的p增强型GaN HEMT相比，在相同的峰值电场情况下，本发明的PN结可以承受更高的栅极击穿电压，因为肖特基的击穿电压主要靠肖特基结，肖特基结是一个突变结，属于单边耗尽，而PN结是双向耗尽，所以整体耗尽层宽度比肖特基栅高得多，因此本器件提高了栅极击穿电压。
 附图说明
图1是本发明的衬底清洗时的工件结构示意图。
图2是本发明的台面隔离时的工件结构示意图。
图3是本发明的PN结刻蚀时的工件结构示意图。
图4是本发明的欧姆接触时的工件结构示意图。
图5是本发明的钝化层沉积时的工件结构示意图。
图6是本发明的栅槽刻蚀时的工件结构示意图。
图7是本发明的栅金属沉积时的工件结构示意图。
图8是本发明的保护沉积时的工件结构示意图。
图9是本发明的开孔及互联金属沉积时的工件结构示意图。
 本发明的实施方式
下面结合附图与实施例对本发明的技术方案进行说明。
实施例 1 ，见图 1 至图 9 。
本发明提供一种新型增强型GaN HEMT器件结构，由如下步骤制备而成。
1）外延生长：在6英寸（111）Si衬底上通过金属有机化学气相沉积（MOCVD）自下而上分别生长20nm厚的AlN成核层、2 μm厚的GaN缓冲层、1nm厚的AlN插入层、20 nm厚的AlGaN势垒层和2nm厚的GaN冒层，形成Si基GaN外延晶片。
2）PN结栅叠层生长：通过金属有机化学气相沉积生长PN结栅叠层，自下而上由100nm厚的p-GaN层和30nm厚的n-GaN层组成，其中p-GaN层的Mg掺杂浓度为3×10 19cm -3，而n-GaN层的Si掺杂浓度为1×10 19cm -3。
3）Si基GaN外延晶片清洗：将外延衬底依次放入MOS级丙酮和MOS级乙醇中超声3 min，用流动的去离子水清洗样片2min并用氮气枪吹干；接着将器件浸入HF:HCl:H 2O体积比为1:4:20的溶液1min，去除表面上的天然氧化物，然后用去离子水冲洗2min并用氮气枪吹干，完成样品清洗（见图1）。
4）光刻及对准标记形成：对样品甩正胶S9912，转速6000转/min，在100℃的热板上烘5min，通过紫外光刻（波长435nm）及显影（显影液为质量浓度2.38%的TMAH）/定影（定影液为水）形成腐蚀窗口，同时在光刻胶上形成对准标记。
5）台面隔离：采用反应离子刻蚀（RIE）法，利用氯气（Cl 2）作为反应刻蚀气体，在50 W 的功率下持续2 min，刻蚀深度为280 nm，干法刻蚀GaN冒层、AlGaN势垒层、AlN插入层和部分GaN缓冲层；将有源区以外的异质结二维电子气刻蚀掉，形成器件有源区之间的隔离（见图2）。
6）刻蚀PN结叠层：对样品甩正胶AZ6130，转速为6000转/min，95℃的热板上烘2min；与第一次的对准标记套刻光刻（波长 435nm），显影（显影液为质量浓度2.38%的TMAH）、定影（定影液为水）形成栅电极窗口；使用低损伤BCl 3/Cl 2基电感耦合等离子体（ICP）干法蚀刻去除栅区外部的n-GaN/p-GaN叠层；之后，在N 2气氛中于850°C进行退火25min，以重新激活n-GaN/p-GaN叠层，叠层在距离源极3 μm，栅源间距为15 μm的位置，长度为2μm（见图3）。
7）源、漏欧姆接触：对样品甩正胶AZ6130，转速为6000转/min，95℃的热板上烘2min；与对准标记套刻光刻（波长 435nm），显影（显影液为质量浓度2.38%的TMAH）、定影（定影液为水）形成源漏电极窗口；然后采用电子束蒸发设备完成金属堆栈沉积，形成Ti/Al/Ni/Au（20 nm/50 nm/ 40nm/50 nm）金属层；在850℃下快速热退火30s，形成欧姆接触电极，源/漏电极宽度都为2 μm，源漏间距为20 μm（见图4）。
8）钝化层沉积：通过等离子体增强化学气相沉积（PECVD）法，以气体流量为600sccm的SiH 4、1960sccm的N 2和20sccm的NH 3作为化学反应源，温度为250 ℃，射频功率为60 W，等离子体增强化学气相沉积的腔室压力为500Torr的条件下沉积160 nm厚的Si 3N 4钝化层（见图5）。
9）栅槽刻蚀：对样品甩PMMA胶，转速为2000转/min，180℃的热板上烘10min；采用电子束曝光在距离源极2μm，栅槽图形长度为2μm；经显影（显影液MIBK:IPA=1：3）25s、定影（定影液为IPA）5s形成栅槽窗口；利用RIE技术，在50W 的功率下持续2min，通过CF 4等离子体干法刻蚀去除栅极区域的Si 3N 4层，形成栅槽（见图6）。
10）栅金属沉积：对样品甩双层电子束胶，下层为Copolymer胶，转速为3000转/min，150℃的热板上烘15min，上层为PMMA胶，转速为3000转/min，180℃的热板上烘10min；在栅槽位置处，采用电子束曝光套刻栅电极图形，设置栅电极尺寸2μm，曝光后经显影（显影液MIBK:IPA=1：3）25s、定影（定影液为IPA）5s形成栅电极图形窗口；采用电子束蒸发法在形成栅极图形窗口的介质层上生长Ni/Au (30 nm/50 nm)的金属层，与介质层之间形成肖特基接触，再使用丙酮将光刻胶去除；之后在N 2气氛中，400℃下进行快速热退火30 s形成肖特基栅电极（见图7）。
11）保护层沉积：通过PECVD法，以气体流量为1420sccm的N 2O、150sccm的SiH 4和392sccm的N 2作为化学反应源，温度为300 ℃，射频功率为15 W，PECVD腔室压力为0.9Torr的条件下沉积200 nm厚的SiO 2保护层（见图8）。
12）开孔及金属互联：对样品甩正胶S9912，转速6000转/min，在100℃的热板上烘5min，通过紫外光刻（波长435nm）及显影（显影液为质量浓度2.38%的TMAH）/定影（定影液为水）形成光刻窗口；最后利用RIE刻蚀技术将欧姆接触电极和肖特基栅电极表面覆盖的Si 3N 4保护层材料移除，刻蚀反应气体采用CF 4和O 2，射频功率为50 W完成开孔；互联金属采用粘附性较好的Ti/Au（20 nm/200 nm）金属叠层，利用电子束蒸发和剥离工艺完成（见图9）。
以上实施例仅用以说明而非限制本发明的技术方案，尽管上述实施例对本发明进行了详细说明，本领域的相关技术人员应当理解：可以对本发明进行修改或者同等替换，但不脱离本发明精神和范围的任何修改和局部替换均应涵盖在本发明的权利要求范围内。

Claims (6)

  1. 一种新型增强型GaN HEMT器件结构，其特征在于，由如下步骤制备而成：
    1）外延生长：在Si衬底上通过金属有机化学气相沉积自下而上分别生长AlN成核层、GaN缓冲层、AlN插入层、AlGaN势垒层、GaN冒层，形成Si基GaN外延晶片；
    2）PN结栅叠层生长：通过金属有机化学气相沉积生长PN结栅叠层，自下而上由100nm厚的p-GaN层和30nm厚的n-GaN层组成，其中p-GaN层的Mg掺杂浓度为3×10 19cm -3，而n-GaN层的Si掺杂浓度为1×10 19cm -3；
    3）Si基GaN外延晶片清洗：将外延衬底依次放入MOS级丙酮和MOS级乙醇中超声3min，用流动的去离子水清洗样片2min并用氮气枪吹干；接着将器件浸入HF:HCl:H 2O体积比为1:4:20的溶液1min，去除表面上的天然氧化物，然后用去离子水冲洗2min并用氮气枪吹干，完成样品清洗；
    4）光刻及对准标记形成：对样品甩正胶S9912，转速6000转/min，在100℃的热板上烘5min，通过紫外光刻、显影、定影，形成腐蚀窗口，同时在光刻胶上形成对准标记；
    5）台面隔离：采用反应离子刻蚀法，利用氯气作为反应刻蚀气体，干法刻蚀GaN冒层、AlGaN势垒层、AlN插入层和部分GaN缓冲层；将有源区以外的异质结二维电子气刻蚀掉，形成器件有源区之间的隔离；
    6）刻蚀PN结叠层：对样品甩正胶AZ6130，转速为6000转/min，95℃的热板上烘2min与第一次的对准标记套刻光刻，显影、定影形成栅电极窗口；使用低损伤BCl 3/Cl 2基电感耦合等离子体干法蚀刻去除栅区外部的n-GaN/p-GaN叠层；之后，在N 2气氛中于850°C进行退火25min，以重新激活n-GaN/p-GaN叠层，叠层在距离源极3 μm，栅源间距为15 μm的位置，长度为2μm；
    7）源、漏欧姆接触：对样品甩正胶AZ6130，转速为6000转/min，95℃的热板上烘2min；与对准标记套刻光刻，显影、定影形成源/漏电极窗口；然后采用电子束蒸发设备完成金属堆栈沉积，形成Ti/Al/Ni/Au金属层；在850℃下快速热退火30s，形成有源极与漏极的欧姆接触电极；
    8）钝化层沉积：通过等离子体增强化学气相沉积法，以气体流量为600sccm的SiH 4、1960sccm的N 2和20sccm的NH 3作为化学反应源，温度为250 ℃，射频功率为60 W，等离子体增强化学气相沉积的腔室压力为500Torr的条件下沉积160 nm厚的Si 3N 4钝化层；
    9）栅槽刻蚀：对样品甩聚甲基丙烯酸甲酯电子束胶，转速为2000转/min，180℃的热板上烘10min；采用电子束曝光在距离源极3 μm，栅源间距为15 μm的位置曝光栅槽图形，栅槽图形长度为2μm；经显影25s、定影5s形成栅槽窗口；利用RIE技术，在50W 的功率下持续2min，通过CF 4等离子体干法刻蚀去除栅极区域的Si 3N 4层，形成栅槽；
    10）栅金属沉积：对样品甩双层电子束胶，下层为共聚物胶，转速为3000转/min，150℃的热板上烘15min，上层为聚甲基丙烯酸甲酯电子束胶，转速为3000转/min，180℃的热板上烘10min；在栅槽位置处，采用电子束曝光套刻栅电极图形，设置栅电极尺寸2μm，曝光后经显影25s、定影5s形成栅电极图形窗口；采用电子束蒸发法在形成栅极图形窗口的介质层上生长Ni/Au金属层，与介质层之间形成肖特基接触，再使用丙酮将光刻胶去除；之后在N 2气氛中，400℃下进行快速热退火30 s形成肖特基栅电极；
    11）保护层沉积：通过等离子体增强化学气相沉积法，以气体流量为1420sccm的N 2O、150sccm的SiH 4和392sccm的N 2作为化学反应源，温度为300 ℃，射频功率为15 W，等离子体增强化学气相沉积的腔室压力为0.9Torr的条件下沉积200 nm厚的SiO 2保护层；
    12）开孔及金属互联：对样品甩正胶S9912，转速6000转/min，在100℃的热板上烘5min，通过紫外光刻、显影、定影形成光刻窗口；最后利用反应离子刻蚀技术将欧姆接触电极和肖特基栅电极表面覆盖的Si 3N 4保护层材料移除，刻蚀反应气体采用CF 4和O 2，射频功率为50 W完成开孔；互联金属采用粘附性好的Ti/Au金属叠层，利用电子束蒸发和剥离工艺完成。
  2. 根据权利要求1所述的新型增强型GaN HEMT器件结构，其特征在于，所述步骤1）中AlN成核层的厚度为20nm、GaN缓冲层的厚度为2 μm、AlN插入层的厚度为1nm、AlGaN势垒层的厚度为20 nm、GaN冒层的厚度为2nm。
  3. 根据权利要求1所述的新型增强型GaN HEMT器件结构，其特征在于，所述步骤4）、步骤6）与步骤12）中光刻的波长均为435nm，显影液均为质量浓度2.38%的四甲基氢氧化铵，定影液均为水。
  4. 根据权利要求1所述的新型增强型GaN HEMT器件结构，其特征在于，所述步骤5）中干刻时在50 W的功率下持续2 min，刻蚀深度为280 nm。
  5. 根据权利要求1所述的新型增强型GaN HEMT器件结构，其特征在于，所述步骤7）中源极与漏极的宽度均为2 μm，源极与漏极间距为20 μm。
  6. 根据权利要求1所述的新型增强型GaN HEMT器件结构，其特征在于，所述步骤9）与步骤10）中的显影液为甲基异丁基酮与异丙醇的体积比为1:3的混合溶液，定影液为异丙醇。
PCT/CN2021/078370 2021-02-04 2021-03-01 一种新型增强型GaN HEMT器件结构 WO2022165884A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110154220.XA CN112968059B (zh) 2021-02-04 2021-02-04 一种新型增强型GaN HEMT器件结构
CN202110154220.X 2021-02-04

Publications (1)

Publication Number Publication Date
WO2022165884A1 true WO2022165884A1 (zh) 2022-08-11

Family

ID=76275491

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/078370 WO2022165884A1 (zh) 2021-02-04 2021-03-01 一种新型增强型GaN HEMT器件结构

Country Status (2)

Country Link
CN (1) CN112968059B (zh)
WO (1) WO2022165884A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114334650B (zh) * 2021-12-30 2024-04-16 桂林理工大学 一种p-GaN HEMT中的新结构
CN115663024A (zh) * 2022-10-28 2023-01-31 上海百功微电子有限公司 一种阈值可调节的GaN器件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130062614A1 (en) * 2011-09-09 2013-03-14 Texas Instruments Incorporated Group iii-v enhancement mode transistor with thyristor gate
CN106981423A (zh) * 2017-04-12 2017-07-25 成都海威华芯科技有限公司 基于Si衬底外延SiC基GaN HEMT的工艺方法
CN107680998A (zh) * 2017-10-24 2018-02-09 江苏华功半导体有限公司 一种GaN基p型栅HFET器件及其制备方法
CN109786442A (zh) * 2019-01-29 2019-05-21 南方科技大学 一种高电子迁移率晶体管及其制作方法
CN109860290A (zh) * 2019-01-29 2019-06-07 南方科技大学 一种高电子迁移率晶体管及其制作方法
US10573734B1 (en) * 2018-12-28 2020-02-25 Vanguard International Semiconductor Corporation High electron mobility transistor and method for forming the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130062614A1 (en) * 2011-09-09 2013-03-14 Texas Instruments Incorporated Group iii-v enhancement mode transistor with thyristor gate
CN106981423A (zh) * 2017-04-12 2017-07-25 成都海威华芯科技有限公司 基于Si衬底外延SiC基GaN HEMT的工艺方法
CN107680998A (zh) * 2017-10-24 2018-02-09 江苏华功半导体有限公司 一种GaN基p型栅HFET器件及其制备方法
US10573734B1 (en) * 2018-12-28 2020-02-25 Vanguard International Semiconductor Corporation High electron mobility transistor and method for forming the same
CN109786442A (zh) * 2019-01-29 2019-05-21 南方科技大学 一种高电子迁移率晶体管及其制作方法
CN109860290A (zh) * 2019-01-29 2019-06-07 南方科技大学 一种高电子迁移率晶体管及其制作方法

Also Published As

Publication number Publication date
CN112968059A (zh) 2021-06-15
CN112968059B (zh) 2022-04-19

Similar Documents

Publication Publication Date Title
US11888052B2 (en) Semiconductor device and manufacturing method thereof employing an etching transition layer
CN102629624B (zh) 基于GaN的MIS栅增强型HEMT器件及制作方法
JP2009088097A (ja) 化合物半導体装置とその製造方法
WO2022165884A1 (zh) 一种新型增强型GaN HEMT器件结构
CN102637726A (zh) MS栅GaN基增强型高电子迁移率晶体管及制作方法
CN112086362A (zh) 一种氮化镓增强型hemt器件及其制备方法
WO2022116915A1 (zh) 一种半导体器件及其应用与制造方法
CN112635544A (zh) 具有偶极子层的增强型AlGaN-GaN垂直型超结HEMT及其制备方法
CN110429127B (zh) 一种氮化镓晶体管结构及其制备方法
WO2022165885A1 (zh) 一种提高槽栅GaN MIS FET器件可靠性的方法
CN111785776B (zh) 垂直结构Ga2O3金属氧化物半导体场效应晶体管的制备方法
CN102646705A (zh) MIS栅GaN基增强型HEMT器件及制作方法
CN111682064B (zh) 高性能MIS栅增强型GaN基高电子迁移率晶体管及其制备方法
CN112993029B (zh) 一种提高GaN HEMT界面质量的方法
CN114121655B (zh) 一种基于增强型器件的自终止刻蚀方法及器件
CN102916043B (zh) Mos-hemt器件及其制作方法
US11682713B2 (en) Methods of fabricating semiconductor structures with two-step etching
CN113257901A (zh) 栅极空气腔结构射频hemt器件及其制备方法
CN113257896A (zh) 多场板射频hemt器件及其制备方法
CN105552108A (zh) GaN HEMT器件非合金欧姆接触的制作方法
CA3093906A1 (en) Semiconductor device and manufacturing method thereof
CN113257911B (zh) 含Sc掺杂的源空气桥结构GaN射频HEMT及其制备方法
CN117080255B (zh) 一种具有冲击能量释放能力的GaN HEMT晶体管及其制作方法
CN114446892B (zh) 一种N面GaN基CMOS器件及其制备方法
CN113540229B (zh) 半导体器件及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21923894

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21923894

Country of ref document: EP

Kind code of ref document: A1