WO2022165670A1 - Procédé de fabrication de puce, procédé de remplissage avec du métal redondant, puce et support de stockage lisible par ordinateur - Google Patents

Procédé de fabrication de puce, procédé de remplissage avec du métal redondant, puce et support de stockage lisible par ordinateur Download PDF

Info

Publication number
WO2022165670A1
WO2022165670A1 PCT/CN2021/075075 CN2021075075W WO2022165670A1 WO 2022165670 A1 WO2022165670 A1 WO 2022165670A1 CN 2021075075 W CN2021075075 W CN 2021075075W WO 2022165670 A1 WO2022165670 A1 WO 2022165670A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
inductor
redundant
redundant metal
strip
Prior art date
Application number
PCT/CN2021/075075
Other languages
English (en)
Chinese (zh)
Inventor
吴亮
康泽辉
Original Assignee
香港中文大学（深圳）
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 香港中文大学（深圳） filed Critical 香港中文大学（深圳）
Priority to CN202180003222.7A priority Critical patent/CN113853674B/zh
Priority to PCT/CN2021/075075 priority patent/WO2022165670A1/fr
Publication of WO2022165670A1 publication Critical patent/WO2022165670A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors

Definitions

  • the invention relates to a method for manufacturing a chip, a method for filling redundant metal and a chip.
  • Redundant metal filling is a technology used in the manufacture of integrated circuits (Integrated Circuit, IC) to improve surface planarization; The flatness of the surface of the chip of the integrated circuit after chemical mechanical polishing (CMP), thereby improving the reliability and yield of the product.
  • the integrated circuit manufacturing technology develops at a rate of doubling the integration level every 18 months according to Moore's Law, but when the feature size of integrated circuits falls below, for example, 90 nanometers, the integrated circuit manufacturing technology encounters unprecedented challenges, and the surface is not flat. The performance and stability of the device have been seriously affected by the stability of the device, and redundant metal filling has become an indispensable step.
  • redundant metal needs to be filled to meet the requirements of the production process for the metal density of each metal layer of the chip. Filling of redundant metal, however, introduces other problems.
  • the present invention provides a method for manufacturing a chip, a method for filling redundant metal, and a chip to solve one or more of several problems introduced by the filling of redundant metal.
  • an embodiment provides a method for manufacturing a chip, including:
  • the silicon wafer is wet-etched to remove silicon dioxide to form a well region injection hole;
  • Ion implantation is performed on the silicon wafer to form a well
  • the polysilicon is removed by dry etching to form the gate and the injection hole in the active region;
  • Ion implantation is performed on the silicon wafer to form source and drain;
  • Borophosphosilicate glass is formed on the surface of the silicon wafer by chemical vapor deposition process, and through-hole lithography is carried out according to the circuit design on the mask;
  • the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by the physical vapor deposition process;
  • a metal layer is formed on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: one or more wires outside the inductor device of the metal layer Strip redundant metal;
  • Silicon wafers are tested and packaged.
  • the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
  • the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
  • an embodiment provides a chip manufactured according to the manufacturing method described in any of the embodiments herein.
  • an embodiment provides a method for filling redundant metal, including:
  • the integrated circuit layout includes one or more metal layers
  • At least one of the metal layers is filled with redundant metal according to a preset rule; wherein the preset rule includes: identifying the inductance device existing in the metal layer to be filled, and filling one or Multiple strips of redundant metal.
  • the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
  • the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
  • an embodiment provides a chip fabricated according to the filling method described in any of the embodiments herein.
  • an embodiment provides an integrated circuit chip, comprising one or more metal layers, wherein at least one metal layer is provided with an inductance device, and one or more metal layers are filled outside the inductance device Root strip redundant metal.
  • the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
  • the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
  • an embodiment provides a computer-readable storage medium, the computer-readable storage medium stores a program, and the program can be executed by a processor to implement the method described in any of the embodiments herein.
  • Fig. 1 is a schematic diagram of a metal block array
  • Fig. 2 is the schematic diagram of filling redundant metal in the form of metal block array outside and inside the inductor;
  • Fig. 3 is a schematic diagram of metal strip arrangement
  • Fig. 4 is a schematic diagram of metal strips arranged around the outside of the inductor and can meet the requirements of the process for metal density;
  • Fig. 5 is a schematic diagram showing the direction in which the alternating magnetic field generated by the inductance produces an induced current in the outer conductor parallel to the inductance coil;
  • Fig. 6 is a schematic diagram of the strip-shaped redundant metal filled around the outside of the inductor and not placed along the direction of the inductor coil or the induced current;
  • Figure 7(a) and Figure 7(b) are two schematic diagrams of strip-shaped redundant metal
  • FIG. 8 is a flowchart of a method for manufacturing a chip according to an embodiment
  • FIG. 9 is a flowchart of a method for filling redundant metal according to an embodiment
  • FIG. 10 is a schematic diagram of a partial area of a metal layer of a chip of a collector circuit according to an embodiment
  • Figure 11(a) is a schematic diagram of inductor A without any redundant metal filling
  • Figure 11(b) is a schematic diagram of filling inductor A with redundant metal or bulk redundant metal in a block array manner
  • Figure 11 (c) is a schematic diagram of radially filling the strip-shaped redundant metal for the inductor A
  • Figure 12 shows the corresponding simulation results for these three cases
  • Figure 13(a) shows that inductor B is not filled with any redundant metal.
  • Figure 13(b) shows that inductor B is filled with redundant metal or bulk redundant metal according to the block array method.
  • Figure 13(c) is a Fill the strip-shaped redundant metal radially for the inductor B;
  • Figure 14 shows the corresponding simulation results for these three cases;
  • Figure 15(a) shows that the coupled inductors are not filled with any redundant metal.
  • Figure 15(b) shows that the coupled inductors are filled with redundant metal or bulk redundant metal according to the block array method.
  • Figure 15(c) is a The coupled inductors are radially filled with strips of redundant metal;
  • Figure 16 shows the corresponding simulation results for the primary coil quality factor for these three cases, and
  • Figure 17 shows the corresponding simulation results for the secondary coil quality factor for these three cases.
  • connection and “connection” mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).
  • each metal layer to be filled with redundant metal to ensure the flatness of the surface after chemical mechanical polishing to obtain a higher yield; however, the filling of the redundant metal will also increase the Some problems that you want to avoid when the chip is introduced into the circuit design, such as the filling of the redundant metal will also introduce the parasitic capacitance that you want to avoid when the circuit design is introduced into the chip.
  • chip manufacturers have also provided a method to avoid filling redundant metal in consideration of the actual needs of circuit design - using the INDDMY layer in the layout design process;
  • the software use the INDDMY layer to frame the desired area, and the frame-selected area will not be checked for metal density, so there is no need to add redundant metals; the inductance model provided in the manufacturing process generally comes with the INDDMY layer.
  • Designers can also manually add INDDMY layers to their designed inductors to skip metal density checks.
  • the advantage of this is that it can avoid placing redundant metal around the inductor, and prevent the quality factor of the inductor from decreasing due to the interference of the redundant metal to the magnetic field around the inductor; but understandably, the INDDMY layer is only a virtual structural layer on the software. It does not exist in the physical process of actual production. The role of the INDDMY layer is to artificially make the selected area skip the metal density check, so naturally it will not further consider filling this area with redundant metal to meet the metal density. 's checked.
  • the function of the INDDMY layer is to artificially make the area selected by the frame skip the metal density check, due to the limitation of the production process, the area occupied by the INDDMY layer must be less than a certain proportion relative to the overall chip area, so as to ensure the actual production.
  • the flatness of each metal layer of the chip during the process In the general digital chip design, if the inductor is hardly used, the proportion of the INDDMY layer to the total chip area specified by the process is sufficient for the designer to use.
  • the quality factor of the inductor can generally be represented by the symbol Q; the quality factor Q of the inductor plays a key role in various analog RF circuits.
  • the phase noise of the oscillator is proportional to 1/Q 2 , and for example
  • the voltage gain of the tuned amplifier is proportional to Q.
  • the quality factor Q of the inductor often limits the performance of the circuit.
  • the highest value of the FoM (figure of merit) of the oscillator is limited by the highest quality factor of the inductor under this process. .
  • the quality factor Q of the inductor is a very important concept; those skilled in the art quantify the loss level of the inductor through the quality factor Q of the inductor.
  • the quality factor Q of the inductor is defined as the maximum energy storage value of the system and the system in one cycle. Ratio of energy loss. Therefore, a key factor affecting the Q value is the amount of energy loss when the current flows through the inductor, and the loss of the inductor mainly comes from the metal structure of the inductor itself and the equivalent resistance presented by the surrounding space. According to the definition of the quality factor Q of the inductance, if the inductance is L, the equivalent series resistance is R s , and the operating frequency is ⁇ , the Q value has the following expression:
  • the following will introduce several mechanisms that cause the loss of the inductor—specifically, metal ohmic loss and dielectric loss.
  • the figure of merit can be improved by reducing the metal resistance of the inductance.
  • the equivalent resistance can be reduced by increasing the width of the inductor; however, a wider metal line will show lower resistance, but on the other hand, it will also have a larger parasitic capacitance relative to the substrate, which will will reduce the self-resonant frequency of the inductor. Therefore, designers often need to trade off between the Q value and the parasitic capacitance in the actual circuit design.
  • f is the frequency
  • ⁇ is the magnetic permeability
  • ⁇ is the electrical conductivity
  • the divergent electric field passes through the dielectric layer between the substrate and each layer of metal to form a displacement current. Because the resistivity of the substrate is not ideal, it is unavoidable that a portion of the current flowing through the substrate will be converted into losses during each cycle of voltage change. The loss that occurs when the electric field passes through these media is called dielectric loss, which further reduces the quality factor of the inductor.
  • the redundant metal is currently filled in the form of a metal block array.
  • Figure 1 is an example of a metal block array; due to the limitation of the process, the redundant metal has inter-metal spacing. Limitation, which makes redundant metal filling in the form of metal block array, only filling the redundant metal outside the inductor can not well meet the requirements of the process for metal density, often it is also necessary to fill the redundant metal inside the inductor.
  • Fig. 2 is an example of filling redundant metals in the form of metal block arrays outside and inside an inductor or an inductor device.
  • FIG. 3 is an example of the arrangement in the form of metal strips
  • FIG. 4 is an example of the arrangement in the form of metal strips around the outside of the inductor and can meet the requirements for metal density in the process.
  • the present application improves the filling method of the redundant metal, and replaces the bulk redundant metal with a strip redundant metal.
  • the redundant metal occupies the same space, the spatial density of the strip redundant metal is much larger than that of the bulk redundant metal, so this makes it only necessary to fill a small amount of redundant metal inside the inductor, and even does not need to fill the redundant metal inside the inductor.
  • metal it can also meet the requirements of the process for metal density.
  • the filling of the redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved.
  • the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced.
  • the quality factor of the inductor - the dashed line in Figure 5 shows the direction in which the alternating magnetic field generated by the inductor will induce a current in the outer conductor parallel to the inductor coil. Considering this situation, the strip-shaped redundant metal filled outside the inductor is not placed along the direction of the inductor coil or the induced current, which can further reduce the loss of the induced current in the filler metal.
  • Figure 6 is a Example; further, when the strip-shaped redundant metal is placed along the vertical inductor coil or the direction of the induced current, the gap between the strips cuts off the current flow path, which can further significantly reduce the induced current in the metal.
  • the loss in , Figure 4 above is such an example.
  • the present patent proposes to fill the outside of the inductor with strip-shaped redundant metal, so as to meet the metal density and reduce the influence on the quality factor of the inductor due to the filling of the redundant metal. Further, the strip-shaped redundancy The metal is placed radially around the outside of the inductor in the direction perpendicular to the induced current generated by the inductor to reduce the ohmic loss of the current as much as possible, thereby further reducing the influence of the redundant metal filling on the quality factor of the inductor.
  • the "strip shape" is used to define that the redundant metal is in the shape of a strip or a strip as a whole, and this shape can be a rectangle as shown in Figure 7(a), As shown in Fig. 7(b), both ends are arc-shaped, such as semi-circular shapes.
  • the direction of the strip-shaped redundant metal arrangement in the present invention it is defined by the long axis direction of the strip-shaped redundant metal.
  • the long axis direction of the residual metal is perpendicular to the direction of the inductor coil or the induced current.
  • the specific size and quantity of the strip-shaped redundant metal can be determined according to metal density requirements and the like.
  • Some embodiments of the present invention disclose a method for manufacturing a chip.
  • the chip is the carrier of the integrated circuit, and the manufacturing method of the chip is a method of miniaturizing the circuit and manufacturing it on the surface of the semiconductor wafer; CMP and other process technologies are used to make components such as MOSFETs or BJTs, and then thin-film and CMP processes are used to make wires to complete the production of chips.
  • the complete process of chip fabrication includes several links such as chip design, wafer fabrication, packaging fabrication and testing, among which the wafer fabrication process is particularly complex.
  • a method for manufacturing a chip includes the following steps:
  • Step 101 cleaning and drying the silicon wafer.
  • the silicon wafer or silicon wafer is first cleaned to remove various impurities on its surface.
  • Various semiconductor devices are generally made by doping appropriate impurities in the silicon wafer (usually the doping concentration is at the level of one millionth), depositing a suitable thin film on the surface of the silicon wafer, photolithography, etching specific patterns, etc. It is manufactured by a series of process steps, so only when the contamination level of various unrelated impurities is controlled in advance without affecting the device characteristics and chip yield, can the above-mentioned process steps be truly producible. In practical applications, this requires us to control the concentration of various irrelevant impurities below one part per million, or even one part per billion, and at the same time, we must effectively remove the influence of various stray particles.
  • washing and drying can be performed again.
  • Step 103 Oxidize the cleaned silicon wafer.
  • silicon dioxide is produced on the surface of a smooth silicon wafer by an oxidizing agent and a gradual temperature rise. This process can be called oxidation or thermal oxidation.
  • silicon dioxide formed by oxidizing silicon wafers has many functions, such as surface passivation, doping barrier layer, surface insulator and device insulator.
  • silicon dioxide can protect the surface and interior of the device;
  • the role of the doping barrier layer means that silicon dioxide can form a blocking protective layer to prevent dopants from invading the silicon surface;
  • the role of the surface insulator refers to the role of the dioxide
  • the oxide layer of silicon can prevent short circuits between adjacent upper and lower metal layers, and at the same time, a sufficiently thick oxide layer can also be used to prevent induction from the metal, that is, field oxide;
  • the role of the device insulator is that the oxide layer can It acts as a dielectric and can induce an induced current in the gate electrode under the oxide layer.
  • Step 105 performing well region lithography on the oxidized silicon wafer according to the circuit design on the mask.
  • Lithography is the cornerstone of modern IC manufacturing, capable of printing sub-micron-sized patterns on silicon wafers.
  • the principle of lithography is to spin-coat a light-sensitive photoresist onto a silicon wafer, form a thin film on the surface, and then use a lithography plate, which contains the graphic information of the specific layer to be made - this is the step
  • the light source irradiates the photoresist through the photoresist, so that the photoresist is selectively exposed; then the photoresist is developed, and the pattern transfer from the plate to the silicon wafer is completed.
  • the photoresist can be used as a masking film in the step of etching the underlying thin film layer, or in the step of ion implantation and doping.
  • Step 107 after the photolithography is completed, wet etching is performed on the silicon wafer to remove silicon dioxide to form a well region injection hole.
  • wet etching is an etching method. It is a technique of immersing the etching material in an etching solution for etching. It is a pure chemical etching with excellent selectivity. After etching the current film, it will stop. without damaging the underlying film of other materials.
  • Step 109 Perform ion implantation on the silicon wafer to form a well.
  • Ion implantation is a technique that combines ion sorting, acceleration, and dose measurement to introduce precise impurity atoms into a silicon substrate. quantity method.
  • Step 111 performing rapid thermal annealing on the silicon wafer after ion implantation.
  • Rapid Thermal Annealing is a process in the chip manufacturing process, which is generally used to activate doping elements in semiconductor materials and restore the amorphous structure caused by ion implantation to a complete lattice structure.
  • the rapid thermal annealing process may be to rapidly heat the silicon wafer from ambient temperature to about 1000-1500K, hold the silicon wafer at this temperature for a few seconds, and then complete the quenching.
  • Step 113 use a shallow trench isolation process for isolation.
  • Shallow Trench Isolation is to form a trench by depositing, patterning, and etching silicon using a silicon nitride mask, and filling the trench with a deposition oxide for isolation from silicon. craft.
  • Step 115 Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area photolithography according to the circuit design on the mask.
  • Step 117 after the photolithography is completed, the polysilicon is removed by dry etching to form a gate electrode and an injection hole in the active region.
  • Dry etching is a thin-film etching technique using plasma.
  • the gas exists in the form of plasma, it has two characteristics: on the one hand, the chemical activity of these gases in the plasma is much stronger than that in the normal state. Reacts with the material to achieve the purpose of etching and removal; on the other hand, the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy.
  • the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy.
  • it bombards the surface of the object to be etched it will be etched.
  • the atoms of the material are knocked out, so as to achieve the purpose of using physical energy transfer to achieve the purpose of etching. Therefore, dry etching is the result of a balance between the physical and chemical processes on the wafer surface. Dry etching can be divided into three types: physical etching, chemical etching, and physical-chemical etching.
  • Step 119 Perform ion implantation on the silicon wafer to form source and drain electrodes.
  • Step 121 performing rapid thermal annealing on the silicon wafer after ion implantation.
  • Step 123 using a chemical vapor deposition process to form borophosphosilicate glass on the surface of the silicon wafer, and perform photolithography of through holes (ie, lead holes) according to the circuit design on the mask.
  • the thin film process refers to the process of forming the required thin film on the surface of the silicon wafer. These specific films include insulators, semiconductors or conductors.
  • the main thin film technologies include chemical vapor deposition (Chemical Vapor Deposition, CVD) and physical vapor deposition (Physical Vapor Deposition, PVD) and so on.
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • the vast majority of thin films in integrated circuit fabrication are deposited by CVD techniques.
  • the principle of CVD is to mix the chemical components containing the required atoms or molecules in the reaction chamber and react in the gaseous state, so that the atoms or molecules are deposited on the surface of the silicon wafer, thereby forming a specific type of thin film.
  • the chemical reactions used are generally divided into pyrolysis, reduction, oxidation, and nitridation.
  • Pyrolysis refers to chemical reactions that rely solely on heat.
  • Reduction is a chemical reaction of molecules, hydrogen.
  • Oxidation is a chemical reaction of atoms, molecules and oxygen.
  • Nitriding mainly refers to a chemical reaction that forms a silicon nitride film on the surface of a silicon wafer.
  • Step 125 after the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by a physical vapor deposition process.
  • PVD technology is more used in every aspect than CVD method, because it can do the deposition of almost any material.
  • the chips of general integrated circuits are composed of multi-layer metal layers, and the metal layers and the metal layers are connected by vias (VIAs).
  • Step 127 use a physical vapor deposition process to form a metal layer on the surface of the silicon wafer; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: a metal layer outside the inductance device of the metal layer or multiple strips of redundant metal.
  • the strip-shaped redundant metal filled outside the inductor is not arranged along the direction of the induced current, which can further reduce the loss of the induced current in the filled metal. Furthermore, when the strip-shaped redundant metal is placed along the direction perpendicular to the induced current, the gaps between the strips cut off the flow path of the current, which can further significantly reduce the loss of the induced current in the metal.
  • Step 129 chemical mechanical polishing is performed on the metal layer filled with the redundant metal to planarize it.
  • CMP Chemical Mechanical Polish
  • Step 131 Test and package the silicon wafer.
  • Packaging is mainly to achieve the connection and protection between the internal and external circuits of the chip.
  • the testing of silicon wafers is to use various testing methods to detect whether the silicon wafers or chips have design defects or physical defects caused by the manufacturing process. In order to ensure that the chip can be used normally, the last two processes that must be passed before delivery to the complete machine manufacturer: packaging and testing.
  • the manufacturing method of the chip disclosed in the present invention chips manufactured according to the method for manufacturing a chip disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured by the chip manufacturing method disclosed in the present invention will have a specific structure, for example, the outside of the inductor device is filled with one or more strip-shaped redundant metals.
  • the redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the chip manufacturing method disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.
  • a method for filling redundant metal is disclosed.
  • the filling of redundant metal is completed in the wafer fab or chip manufacturing stone.
  • the filling of redundant metal is located in the final stage of layout physical design, timing, layout logic verification (Layout Versus Schematics, LVS), design rule verification (Design Rule Check, DRC), etc. have been passed, and the layout design has been basically finalized.
  • FIG. 9 another embodiment of the present invention discloses a method for filling redundant metal, including the following steps:
  • Step 191 Obtain an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers.
  • Step 193 Fill at least one metal layer with redundant metal according to a preset rule; wherein the preset rule includes: filling one or more strip-shaped redundant metals on the outside of the inductance device of the metal layer.
  • redundant metal filling is a process of layout post-processing.
  • Step 193 proposes a rule for filling redundant metal in the metal layer, that is, filling one or more strips outside the inductor device of the metal layer. Shape redundant metal.
  • the filling of redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved.
  • the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced.
  • step 193 The quality factor of the inductor. Considering this situation, the strip-shaped redundant metal filled outside the inductor in step 193 is not placed along the direction of the induced current, which can further reduce the loss of the induced current in the filler metal; further, step 193 is in The strip-shaped redundant metal is filled outside the inductor. The strip-shaped redundant metal is placed along the direction of the vertical induced current. Since the gap between the strips cuts off the current flow path, this can further significantly reduce the loss of the induced current in the metal. .
  • the above are some descriptions of the method for filling the redundant metal disclosed in the present invention.
  • chips fabricated according to the method for filling redundant metal disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured according to the method for filling redundant metal disclosed in the present invention will have a specific structure. , the strip-shaped redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the method for filling redundant metal disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.
  • some embodiments of the present invention further disclose an integrated circuit chip, the chip includes one or more metal layers, at least one metal layer is provided with an inductance device 11, and is filled outside the inductance device There are one or more strip-shaped redundant metals 12 , wherein FIG. 10 is a schematic diagram of a partial area of the metal layer provided with the inductance device 11 , and 13 is a metal wire or a signal wire.
  • the strip-shaped redundant metal 12 is not parallel to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 are generated in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. The directions of the induced currents are not parallel.
  • the strip-shaped redundant metal 12 is perpendicular to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 generate an induced current in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. direction is vertical.
  • This application proposes a technical solution for radially filling strip-shaped redundant metal around an inductor.
  • this solution is easier to meet the requirements of the metal density of the process, thereby avoiding filling the redundant metal inside the inductor.
  • placing radial metal strips perpendicular to the induced current direction of the inductor around the outside of the inductor can effectively suppress the loss of the quality factor of the inductor caused by the redundant metal under the premise of meeting the requirements of the process production. In this way, an inductor with a higher quality factor can be obtained.
  • the simulation results show that the method can be applied to inductors operating from 15GHz to 70GHz, and the quality factor is improved by 7% to 17%, which will be explained in detail below.
  • the present invention uses simulation software (such as HFSS electromagnetic simulation software) to carry out quality factor simulation of two different inductors A, B and a coupled inductor respectively; wherein when performing quality factor simulation of each inductor, it is performed without adding any Redundant metal, filled in the form of an array of redundant metal blocks around the inductor, and filled with strips of redundant metal in a radial pattern around the inductor were simulated, as described below.
  • simulation software such as HFSS electromagnetic simulation software
  • FIG. 11(a), Figure 11(b), and Figure 11(c) show that inductor A is not filled with any redundant metal.
  • Figure 11(b) shows that inductor A is filled with redundant metal or bulk redundant metal according to the block array method.
  • Figure 11(c) is a Inductor A is filled with strip-shaped redundant metal in a radial shape, and electromagnetic field simulations are carried out for these three cases. According to the calculation formula of inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 12. Show.
  • the inductance value is 0.26nH and the inner diameter is 23um.
  • the two-round inductance B is simulated.
  • the inductance design and the filling method of redundant metal are shown in Figure 13(a), Figure 13(b), and Figure 13(c).
  • Figure 13(c) 13(a) does not fill the inductor B with any redundant metal.
  • Figure 13(b) fills the inductor B with redundant metal or bulk redundant metal according to the block array method.
  • Inductor B is filled with strip-shaped redundant metal in a radial shape.
  • the electromagnetic field simulation is carried out for these three cases. According to the calculation formula of the inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 14. .
  • the maximum value of the quality factor Q of the inductor is 17.45 when no redundant metal is filled, and the maximum value of the quality factor Q of the inductor when the redundant metal is filled in the block array method is 15.82, which is lower than the ideal condition.
  • the maximum value of the inductance quality factor Q is 16.92.
  • the quality factor is only reduced by 3.0%.
  • the quality factor is improved by 6.9%.
  • the present invention can be applied not only to single-port inductors, but also to coupled inductors.
  • Fig. 15(a), Fig. 15(b), Fig. 15(c) the 3D modeling and electromagnetic simulation under the above three different filling conditions were carried out for a coupled inductor with a turns ratio of 2:1.
  • Fig. 15(a) shows that the coupled inductor is not filled with any redundant metal
  • Fig. 15(b) shows that the coupled inductor is filled with redundant metal or bulk redundant metal according to the block array method.
  • Fig. 15( c) is to fill the strip-shaped redundant metal in a radial shape for the coupled inductor; wherein the bulk array and the radial strip-shaped redundant metal are filled around the inductor to meet the requirements for the metal density of the process.
  • the quality factor Q of the primary coil is obtained according to the calculation formula of the inductance quality factor Q above to obtain the relationship between the inductance quality factor and the frequency.
  • the result is shown in Figure 16. It can be seen from Figure 16 that the maximum value of the quality factor Q of the primary coil when no redundant metal is filled is 19.86; when the redundant metal is filled in the block array mode, the maximum value of the quality factor Q of the primary coil is 15.89, which is lower than the ideal condition.
  • the maximum value of the quality factor Q of the primary coil is 18.69, which is only 5.9% lower than the ideal condition, and Compared with the original block array filling method, the quality factor is improved by 17.6%.
  • the relationship between the quality factor Q of the secondary coil and the frequency is shown in Figure 17. It can be seen from Figure 17 that the maximum value of the quality factor Q of the secondary coil is 11.07 when no redundant metal is filled; The quality factor is reduced by 8.9%; and according to the method for filling strip-shaped redundant metal in a radial shape proposed in an embodiment of the present invention, the maximum value of the quality factor Q of the secondary coil is 10.81. Compared with the ideal situation, the quality factor is only reduced. 2.3%, and compared with the original uniform block array filling method, the quality factor is improved by 7.2%.
  • the present invention can effectively prevent the reduction of the inductance quality factor due to the addition of redundant metals; in the case of satisfying the metal density required by the process, the redundant metal filling scheme proposed by the present invention obtains Compared with the general redundant metal filling method, the quality factor of the inductor is improved by about 7%, and the present invention can also be applied to coupled inductors.
  • a filling technology of placing radial strips of metal perpendicular to the direction of the induced electric field is proposed; This technology alleviates the problem that the allowable area of the INDDMY layer in the design of analog and RF circuits is not enough for design due to process limitations. Simulations show that this technique not only meets the metal density required by the process, but also cuts off the induced current path and avoids metal filling inside the inductor coil without using the INDDMY layer to ignore the metal density check.
  • the electromagnetic full-wave simulation shows that, compared with the conventional method of uniformly filling the redundant metal of the block array, this technology can effectively reduce the loss caused by the redundant metal to the inductor, which is extremely beneficial for the design of high-Q single-port inductors and coupled inductors. .
  • any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CD to ROM, DVD, Blu Ray disks, etc.), flash memory, and/or the like .
  • These computer program instructions may be loaded on a general purpose computer, special purpose computer or other programmable data processing apparatus to form a machine, such that the instructions executed on the computer or other programmable data processing apparatus may generate means for carrying out the specified functions.
  • These computer program instructions may also be stored in a computer-readable memory that instructs a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable memory form a piece of Articles of manufacture, including implementing means for implementing specified functions.
  • Computer program instructions may also be loaded on a computer or other programmable data processing device to perform a series of operational steps on the computer or other programmable device to produce a computer-implemented process such that a process executed on the computer or other programmable device Instructions may provide steps for implementing specified functions.
  • the term “comprising” and any other variations thereof are non-exclusive inclusion, such that a process, method, article or device including a list of elements includes not only those elements, but also not expressly listed or included in the process , method, system, article or other elements of a device.
  • the term “coupled” and any other variations thereof refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.

Abstract

L'invention concerne un procédé de fabrication de puce, un procédé de remplissage avec du métal redondant, une puce et un support de stockage lisible par ordinateur. Un ou plusieurs métaux redondants en forme de barre (12) sont disposés à l'extérieur d'un dispositif inductif (11) d'une couche métallique. En outre, les métaux redondants en forme de barre (12) ne sont pas parallèles à la direction de bobine du dispositif inductif (11), et les métaux redondants en forme de barre (12) sont perpendiculaires à la direction de bobine du dispositif inductif (11). Par comparaison avec la technologie de remplissage avec du métal redondant classique visant une zone de dispositif inducteur, la présente invention peut améliorer efficacement le facteur de qualité d'une inductance.
PCT/CN2021/075075 2021-02-03 2021-02-03 Procédé de fabrication de puce, procédé de remplissage avec du métal redondant, puce et support de stockage lisible par ordinateur WO2022165670A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180003222.7A CN113853674B (zh) 2021-02-03 2021-02-03 芯片及其制造方法、冗余金属填充方法、计算机可读存储介质
PCT/CN2021/075075 WO2022165670A1 (fr) 2021-02-03 2021-02-03 Procédé de fabrication de puce, procédé de remplissage avec du métal redondant, puce et support de stockage lisible par ordinateur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/075075 WO2022165670A1 (fr) 2021-02-03 2021-02-03 Procédé de fabrication de puce, procédé de remplissage avec du métal redondant, puce et support de stockage lisible par ordinateur

Publications (1)

Publication Number Publication Date
WO2022165670A1 true WO2022165670A1 (fr) 2022-08-11

Family

ID=78982727

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/075075 WO2022165670A1 (fr) 2021-02-03 2021-02-03 Procédé de fabrication de puce, procédé de remplissage avec du métal redondant, puce et support de stockage lisible par ordinateur

Country Status (2)

Country Link
CN (1) CN113853674B (fr)
WO (1) WO2022165670A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116404006B (zh) * 2023-06-09 2023-08-25 合肥晶合集成电路股份有限公司 一种芯片版图

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020036335A1 (en) * 2000-09-28 2002-03-28 Kabushiki Kaisha Toshiba Spiral inductor and method for fabricating semiconductor integrated circuit device having same
CN1734767A (zh) * 2004-08-03 2006-02-15 三星电子株式会社 包括无源器件屏蔽结构的集成电路器件及其形成方法
US20070228515A1 (en) * 2006-03-30 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with spiral inductors
CN102543853A (zh) * 2011-12-31 2012-07-04 中国科学院微电子研究所 冗余金属填充方法和集成电路版图结构
CN104011860A (zh) * 2011-12-29 2014-08-27 英特尔公司 具有金属伪特征的电感器设计
CN104051435A (zh) * 2013-03-11 2014-09-17 台湾积体电路制造股份有限公司 具有伪金属部件的电感器结构及方法
US20140284763A1 (en) * 2013-03-25 2014-09-25 Realtek Semiconductor Corp. Integrated inductor and integrated inductor fabricating method
CN104810244A (zh) * 2014-01-26 2015-07-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法、半导体器件和电子装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236033A (ja) * 2004-02-19 2005-09-02 Mitsubishi Electric Corp 半導体装置
US7652348B1 (en) * 2006-07-27 2010-01-26 National Semiconductor Corporation Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits
CN102082143B (zh) * 2009-12-01 2013-06-19 中芯国际集成电路制造(上海)有限公司 插入在电感器周围的图形填充物结构
JP5494214B2 (ja) * 2010-05-14 2014-05-14 ルネサスエレクトロニクス株式会社 半導体装置
JP2018026475A (ja) * 2016-08-10 2018-02-15 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020036335A1 (en) * 2000-09-28 2002-03-28 Kabushiki Kaisha Toshiba Spiral inductor and method for fabricating semiconductor integrated circuit device having same
CN1734767A (zh) * 2004-08-03 2006-02-15 三星电子株式会社 包括无源器件屏蔽结构的集成电路器件及其形成方法
US20070228515A1 (en) * 2006-03-30 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with spiral inductors
CN104011860A (zh) * 2011-12-29 2014-08-27 英特尔公司 具有金属伪特征的电感器设计
CN102543853A (zh) * 2011-12-31 2012-07-04 中国科学院微电子研究所 冗余金属填充方法和集成电路版图结构
CN104051435A (zh) * 2013-03-11 2014-09-17 台湾积体电路制造股份有限公司 具有伪金属部件的电感器结构及方法
US20140284763A1 (en) * 2013-03-25 2014-09-25 Realtek Semiconductor Corp. Integrated inductor and integrated inductor fabricating method
CN104810244A (zh) * 2014-01-26 2015-07-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法、半导体器件和电子装置

Also Published As

Publication number Publication date
CN113853674B (zh) 2022-08-05
CN113853674A (zh) 2021-12-28

Similar Documents

Publication Publication Date Title
US8946049B2 (en) Replacement gate structures and methods of manufacturing
US9230725B2 (en) Methods of designing an inductor having opening enclosed within conductive line
US8470682B2 (en) Methods and structures for increased thermal dissipation of thin film resistors
US8912630B2 (en) Integrated circuit including thermal gate, related method and design structure
US20180323158A1 (en) Magnetic inductor stack including insulating material having multiple thicknesses
WO2022165670A1 (fr) Procédé de fabrication de puce, procédé de remplissage avec du métal redondant, puce et support de stockage lisible par ordinateur
US8518773B2 (en) Method of fabricating semiconductor capacitor
US9257519B2 (en) Semiconductor device including graded gate stack, related method and design structure
US8809998B2 (en) Semiconductor device including in wafer inductors, related method and design structure
US20120122315A1 (en) Self-aligned devices and methods of manufacture
US10438803B2 (en) Semiconductor structures having low resistance paths throughout a wafer
CN102437089B (zh) 一种铜后道互连工艺
US8853076B2 (en) Self-aligned contacts
US20140203280A1 (en) Electrical test structure for devices employing high-k dielectrics or metal gates
CN107871706B (zh) 浅沟槽隔离结构及其制作方法
US8637403B2 (en) Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics
US11031250B2 (en) Semiconductor structures of more uniform thickness
US8822993B2 (en) Integrated circuit including sensor structure, related method and design structure
US20130234138A1 (en) Electrical test structure for determining loss of high-k dielectric material and/or metal gate material
US8916932B2 (en) Semiconductor device including FINFET structures with varied epitaxial regions, related method and design structure
US8815733B2 (en) Isolated wire structures with reduced stress, methods of manufacturing and design structures
CN114256064A (zh) 一种改善回刻光刻胶工艺窗口的方法
CN117320443A (zh) 半导体元件的制备方法
JP2003086697A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21923698

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21923698

Country of ref document: EP

Kind code of ref document: A1