WO2022165670A1

WO2022165670A1 - Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium

Info

Publication number: WO2022165670A1
Application number: PCT/CN2021/075075
Authority: WO
Inventors: 吴亮; 康泽辉
Original assignee: 香港中文大学（深圳）
Priority date: 2021-02-03
Filing date: 2021-02-03
Publication date: 2022-08-11
Also published as: CN113853674A; CN113853674B

Abstract

A chip manufacturing method, a redundant metal filling method, a chip and a computer readable storage medium. One or more bar-shaped redundant metals (12) are arranged outside an inductive device (11) of a metal layer. Furthermore, the bar-shaped redundant metals (12) are not parallel to the coil direction of the inductive device (11), and the bar-shaped redundant metals (12) are perpendicular to the coil direction of the inductive device (11). Compared with the traditional redundant metal filling technology aiming at an inductor device area, the present invention can effectively improve the quality factor of an inductor.

Description

[Title of invention made by ISA pursuant to Rule 37.2] Method of manufacturing a chip, method of filling redundant metal, chip and computer-readable storage medium

technical field

The invention relates to a method for manufacturing a chip, a method for filling redundant metal and a chip.

Background technique

Redundant metal filling (Dummy Fill) is a technology used in the manufacture of integrated circuits (Integrated Circuit, IC) to improve surface planarization; The flatness of the surface of the chip of the integrated circuit after chemical mechanical polishing (CMP), thereby improving the reliability and yield of the product. The integrated circuit manufacturing technology develops at a rate of doubling the integration level every 18 months according to Moore's Law, but when the feature size of integrated circuits falls below, for example, 90 nanometers, the integrated circuit manufacturing technology encounters unprecedented challenges, and the surface is not flat. The performance and stability of the device have been seriously affected by the stability of the device, and redundant metal filling has become an indispensable step.

Therefore, in the layout design, redundant metal needs to be filled to meet the requirements of the production process for the metal density of each metal layer of the chip. Filling of redundant metal, however, introduces other problems.

SUMMARY OF THE INVENTION

The present invention provides a method for manufacturing a chip, a method for filling redundant metal, and a chip to solve one or more of several problems introduced by the filling of redundant metal.

According to a first aspect, an embodiment provides a method for manufacturing a chip, including:

Clean and dry the silicon wafer;

Oxidize the cleaned silicon wafer;

Perform well region lithography on the oxidized silicon wafer according to the circuit design on the mask;

After the photolithography is completed, the silicon wafer is wet-etched to remove silicon dioxide to form a well region injection hole;

Ion implantation is performed on the silicon wafer to form a well;

Rapid thermal annealing of ion implanted silicon wafers;

Isolation by shallow trench isolation process;

Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area lithography according to the circuit design on the mask;

After the photolithography is completed, the polysilicon is removed by dry etching to form the gate and the injection hole in the active region;

Ion implantation is performed on the silicon wafer to form source and drain;

Rapid thermal annealing of ion implanted silicon wafers;

Borophosphosilicate glass is formed on the surface of the silicon wafer by chemical vapor deposition process, and through-hole lithography is carried out according to the circuit design on the mask;

After the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by the physical vapor deposition process;

A metal layer is formed on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: one or more wires outside the inductor device of the metal layer Strip redundant metal;

chemical mechanical polishing of the metal layer filled with redundant metal to planarize it;

Silicon wafers are tested and packaged.

In one embodiment, the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.

In one embodiment, the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.

According to a second aspect, an embodiment provides a chip manufactured according to the manufacturing method described in any of the embodiments herein.

According to a third aspect, an embodiment provides a method for filling redundant metal, including:

obtaining an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers;

At least one of the metal layers is filled with redundant metal according to a preset rule; wherein the preset rule includes: identifying the inductance device existing in the metal layer to be filled, and filling one or Multiple strips of redundant metal.

According to a fourth aspect, an embodiment provides a chip fabricated according to the filling method described in any of the embodiments herein.

According to a fifth aspect, an embodiment provides an integrated circuit chip, comprising one or more metal layers, wherein at least one metal layer is provided with an inductance device, and one or more metal layers are filled outside the inductance device Root strip redundant metal.

According to a sixth aspect, an embodiment provides a computer-readable storage medium, the computer-readable storage medium stores a program, and the program can be executed by a processor to implement the method described in any of the embodiments herein.

Description of drawings

Fig. 1 is a schematic diagram of a metal block array;

Fig. 2 is the schematic diagram of filling redundant metal in the form of metal block array outside and inside the inductor;

Fig. 3 is a schematic diagram of metal strip arrangement;

Fig. 4 is a schematic diagram of metal strips arranged around the outside of the inductor and can meet the requirements of the process for metal density;

Fig. 5 is a schematic diagram showing the direction in which the alternating magnetic field generated by the inductance produces an induced current in the outer conductor parallel to the inductance coil;

Fig. 6 is a schematic diagram of the strip-shaped redundant metal filled around the outside of the inductor and not placed along the direction of the inductor coil or the induced current;

Figure 7(a) and Figure 7(b) are two schematic diagrams of strip-shaped redundant metal;

8 is a flowchart of a method for manufacturing a chip according to an embodiment;

FIG. 9 is a flowchart of a method for filling redundant metal according to an embodiment;

10 is a schematic diagram of a partial area of a metal layer of a chip of a collector circuit according to an embodiment;

Figure 11(a) is a schematic diagram of inductor A without any redundant metal filling, Figure 11(b) is a schematic diagram of filling inductor A with redundant metal or bulk redundant metal in a block array manner, Figure 11 (c) is a schematic diagram of radially filling the strip-shaped redundant metal for the inductor A; Figure 12 shows the corresponding simulation results for these three cases;

Figure 13(a) shows that inductor B is not filled with any redundant metal. Figure 13(b) shows that inductor B is filled with redundant metal or bulk redundant metal according to the block array method. Figure 13(c) is a Fill the strip-shaped redundant metal radially for the inductor B; Figure 14 shows the corresponding simulation results for these three cases;

Figure 15(a) shows that the coupled inductors are not filled with any redundant metal. Figure 15(b) shows that the coupled inductors are filled with redundant metal or bulk redundant metal according to the block array method. Figure 15(c) is a The coupled inductors are radially filled with strips of redundant metal; Figure 16 shows the corresponding simulation results for the primary coil quality factor for these three cases, and Figure 17 shows the corresponding simulation results for the secondary coil quality factor for these three cases.

Detailed ways

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments have used associated similar element numbers. In the following embodiments, many details are described so that the present application can be better understood. However, those skilled in the art will readily recognize that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application from being overwhelmed by excessive description, and for those skilled in the art, these are described in detail. The relevant operations are not necessary, and they can fully understand the relevant operations according to the descriptions in the specification and general technical knowledge in the field.

Additionally, the features, acts, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in order in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary order unless otherwise stated, a certain order must be followed.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).

As described in the background art, in the actual production process of the chip, the process requires each metal layer to be filled with redundant metal to ensure the flatness of the surface after chemical mechanical polishing to obtain a higher yield; however, the filling of the redundant metal will also increase the Some problems that you want to avoid when the chip is introduced into the circuit design, such as the filling of the redundant metal will also introduce the parasitic capacitance that you want to avoid when the circuit design is introduced into the chip. These parasitic capacitances increase the signal delay, interference noise and energy loss; The effect of filling redundant metal in a suitable way to reduce the interference of parasitic effects on the circuit has also become a part of the integrated circuit layout design; for example, the Chinese patent publication number CN102456080A proposes a redundancy that reduces parasitic capacitance Metal filled.

In the prior art, there are many studies on the parasitic capacitance caused by the redundant metal filling, and then the redundant metal also interferes with the electromagnetic field, resulting in a decrease in the quality factor of the inductance in the integrated circuit. Specifically, in an integrated circuit chip, especially a radio frequency chip, there are high-frequency devices such as inductors. Generally speaking, the pattern density of these high-frequency devices is very low. Therefore, redundant metal filling is generally required in these areas.

In view of the problems caused by redundant metal filling, chip manufacturers have also provided a method to avoid filling redundant metal in consideration of the actual needs of circuit design - using the INDDMY layer in the layout design process; In the software, use the INDDMY layer to frame the desired area, and the frame-selected area will not be checked for metal density, so there is no need to add redundant metals; the inductance model provided in the manufacturing process generally comes with the INDDMY layer. In addition, Designers can also manually add INDDMY layers to their designed inductors to skip metal density checks. The advantage of this is that it can avoid placing redundant metal around the inductor, and prevent the quality factor of the inductor from decreasing due to the interference of the redundant metal to the magnetic field around the inductor; but understandably, the INDDMY layer is only a virtual structural layer on the software. It does not exist in the physical process of actual production. The role of the INDDMY layer is to artificially make the selected area skip the metal density check, so naturally it will not further consider filling this area with redundant metal to meet the metal density. 's checked. Since the function of the INDDMY layer is to artificially make the area selected by the frame skip the metal density check, due to the limitation of the production process, the area occupied by the INDDMY layer must be less than a certain proportion relative to the overall chip area, so as to ensure the actual production. The flatness of each metal layer of the chip during the process. In the general digital chip design, if the inductor is hardly used, the proportion of the INDDMY layer to the total chip area specified by the process is sufficient for the designer to use. However, due to the widespread use of inductors in analog and RF circuits, in these chip designs, if each inductor avoids redundant metal surrounding by using an INDMMY layer, the proportion of the INDMMY layer to the total chip area tends to be smaller Process limits will be exceeded. Therefore, how to fill the inductor with redundant metal in an appropriate way in the layout, and to minimize the loss of the redundant metal to the inductor quality factor under the condition of satisfying the metal density, is still a problem that needs to be considered and worth studying.

Before describing the solution of the present application, the inductance quality factor and inductance loss will be described first.

The quality factor of the inductor can generally be represented by the symbol Q; the quality factor Q of the inductor plays a key role in various analog RF circuits. For example, the phase noise of the oscillator is proportional to 1/Q ² , and for example The voltage gain of the tuned amplifier is proportional to Q. In addition, the quality factor Q of the inductor often limits the performance of the circuit. For example, the highest value of the FoM (figure of merit) of the oscillator is limited by the highest quality factor of the inductor under this process. .

Therefore, the quality factor Q of the inductor is a very important concept; those skilled in the art quantify the loss level of the inductor through the quality factor Q of the inductor. The quality factor Q of the inductor is defined as the maximum energy storage value of the system and the system in one cycle. Ratio of energy loss. Therefore, a key factor affecting the Q value is the amount of energy loss when the current flows through the inductor, and the loss of the inductor mainly comes from the metal structure of the inductor itself and the equivalent resistance presented by the surrounding space. According to the definition of the quality factor Q of the inductance, if the inductance is L, the equivalent series resistance is R _s , and the operating frequency is ω, the Q value has the following expression:

Q=Lω/R _s ;

Under certain other conditions, the greater the overall loss of the inductor, the greater the equivalent series resistance R _s . The following will introduce several mechanisms that cause the loss of the inductor—specifically, metal ohmic loss and dielectric loss.

(1) Metal ohmic loss

Due to the limited conductivity of the metal used to make the inductor itself, a part of the energy will be dissipated in the form of heat when the current flows through the metal. This part of the loss is called the ohmic loss of the metal wire. From the expression for the Q value above, we can see that for a given inductance, the figure of merit can be improved by reducing the metal resistance of the inductance. In general, the equivalent resistance can be reduced by increasing the width of the inductor; however, a wider metal line will show lower resistance, but on the other hand, it will also have a larger parasitic capacitance relative to the substrate, which will will reduce the self-resonant frequency of the inductor. Therefore, designers often need to trade off between the Q value and the parasitic capacitance in the actual circuit design.

At high frequencies, the current components in the inductor tend to repel each other and move away from each other, and eventually the current tends to flow on the metal surface, a phenomenon known as the skin effect. The actual distribution of the current follows an exponential decay from the surface of the metal inwards:

J(s)=J ₀ exp(-x/δ);

where J0 is the current density _at the surface, δ is the skin depth, and the value of δ is given by:

where f is the frequency, μ is the magnetic permeability, and σ is the electrical conductivity.

Due to the smaller skin depth at high frequencies, the equivalent cross-sectional area through which the current flows is reduced, which further increases its equivalent resistance from increasing ohmic losses.

(2) Dielectric loss

Due to the capacitance between the inductor and the substrate, when the voltage of each part of the inductor changes with time, the divergent electric field passes through the dielectric layer between the substrate and each layer of metal to form a displacement current. Because the resistivity of the substrate is not ideal, it is unavoidable that a portion of the current flowing through the substrate will be converted into losses during each cycle of voltage change. The loss that occurs when the electric field passes through these media is called dielectric loss, which further reduces the quality factor of the inductor.

Studying and understanding the quality factor Q of the inductor, metal ohmic loss, and dielectric loss play an important role in understanding the deficiencies of the prior art and the improvement scheme of the present application. The following is a description of the existing redundant metal filling technology and the improvement scheme of the present application. illustrate.

In the layout design process of the integrated circuit, the redundant metal is currently filled in the form of a metal block array. Figure 1 is an example of a metal block array; due to the limitation of the process, the redundant metal has inter-metal spacing. Limitation, which makes redundant metal filling in the form of metal block array, only filling the redundant metal outside the inductor can not well meet the requirements of the process for metal density, often it is also necessary to fill the redundant metal inside the inductor. , Fig. 2 is an example of filling redundant metals in the form of metal block arrays outside and inside an inductor or an inductor device.

Considering the above situation, the applicant proposes to use long strips of metal to fill the periphery of the inductor. The metal density after the metal strips is arranged is greater than that of the metal block array, so this can reduce or avoid the internal impact of the inductor. Fill redundant metal. FIG. 3 is an example of the arrangement in the form of metal strips, and FIG. 4 is an example of the arrangement in the form of metal strips around the outside of the inductor and can meet the requirements for metal density in the process.

The following is a comparison of this metal filling method.

Let the side length of the redundant metal blocks in Figure 1 be 1um, and the spacing between the redundant metal blocks is also 1um. %. Taking Figure 3 as an example, when strip-shaped redundant metals with a length of 9um and a width of 1um or strip-shaped redundant metals are placed at the same spacing, that is, 1um, if this arrangement goes down infinitely, The spatial density occupied by the redundant metal is then 50%. It can be seen that compared with the former, the latter filling method is easier to meet the requirements of the process for metal density in the case of the same area.

It can be seen from the above analysis that because the metal block array itself only occupies 25% of the space density, it is difficult to meet the minimum metal density requirements of the process in the case of occupying a small area. Therefore, filling the redundant metal with the metal array often requires More area to meet the requirements of process metal density, such as the need to fill the redundant metal inside the inductor; and because the magnetic flux density inside the inductor is larger, the redundant metal inside the inductor is compared with the outside surrounding of the inductor under the alternating magnetic field. Metals will generate larger induced currents and will reduce the quality factor of the inductor more significantly.

After considering this situation, the present application improves the filling method of the redundant metal, and replaces the bulk redundant metal with a strip redundant metal. When the redundant metal occupies the same space, the spatial density of the strip redundant metal is much larger than that of the bulk redundant metal, so this makes it only necessary to fill a small amount of redundant metal inside the inductor, and even does not need to fill the redundant metal inside the inductor. When using metal, it can also meet the requirements of the process for metal density.

By replacing the block-shaped redundant metal with the strip-shaped redundant metal, the filling of the redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved.

Further, although the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced. The quality factor of the inductor - the dashed line in Figure 5 shows the direction in which the alternating magnetic field generated by the inductor will induce a current in the outer conductor parallel to the inductor coil. Considering this situation, the strip-shaped redundant metal filled outside the inductor is not placed along the direction of the inductor coil or the induced current, which can further reduce the loss of the induced current in the filler metal. For example, Figure 6 is a Example; further, when the strip-shaped redundant metal is placed along the vertical inductor coil or the direction of the induced current, the gap between the strips cuts off the current flow path, which can further significantly reduce the induced current in the metal. The loss in , Figure 4 above is such an example.

Therefore, in some embodiments, the present patent proposes to fill the outside of the inductor with strip-shaped redundant metal, so as to meet the metal density and reduce the influence on the quality factor of the inductor due to the filling of the redundant metal. Further, the strip-shaped redundancy The metal is placed radially around the outside of the inductor in the direction perpendicular to the induced current generated by the inductor to reduce the ohmic loss of the current as much as possible, thereby further reducing the influence of the redundant metal filling on the quality factor of the inductor.

It should be noted that, in the strip-shaped redundant metal of the present invention, the "strip shape" is used to define that the redundant metal is in the shape of a strip or a strip as a whole, and this shape can be a rectangle as shown in Figure 7(a), As shown in Fig. 7(b), both ends are arc-shaped, such as semi-circular shapes. When discussing the direction of the strip-shaped redundant metal arrangement in the present invention, it is defined by the long axis direction of the strip-shaped redundant metal. The long axis direction of the residual metal is perpendicular to the direction of the inductor coil or the induced current. When the strip-shaped redundant metal is filled, the specific size and quantity of the strip-shaped redundant metal can be determined according to metal density requirements and the like.

Some embodiments of the present invention disclose a method for manufacturing a chip. The chip is the carrier of the integrated circuit, and the manufacturing method of the chip is a method of miniaturizing the circuit and manufacturing it on the surface of the semiconductor wafer; CMP and other process technologies are used to make components such as MOSFETs or BJTs, and then thin-film and CMP processes are used to make wires to complete the production of chips. The complete process of chip fabrication includes several links such as chip design, wafer fabrication, packaging fabrication and testing, among which the wafer fabrication process is particularly complex.

Referring to FIG. 8 , a method for manufacturing a chip according to some embodiments includes the following steps:

Step 101 : cleaning and drying the silicon wafer.

During the manufacturing process, the silicon wafer or silicon wafer is first cleaned to remove various impurities on its surface. Various semiconductor devices are generally made by doping appropriate impurities in the silicon wafer (usually the doping concentration is at the level of one millionth), depositing a suitable thin film on the surface of the silicon wafer, photolithography, etching specific patterns, etc. It is manufactured by a series of process steps, so only when the contamination level of various unrelated impurities is controlled in advance without affecting the device characteristics and chip yield, can the above-mentioned process steps be truly producible. In practical applications, this requires us to control the concentration of various irrelevant impurities below one part per million, or even one part per billion, and at the same time, we must effectively remove the influence of various stray particles.

It can be understood that at the end of each of the other steps shown in FIG. 8 , washing and drying can be performed again.

It is understandable that some preliminary preparations need to be done before starting to manufacture, such as selecting silicon wafer specifications and doping ion types according to the needs of designing circuits.

Step 103: Oxidize the cleaned silicon wafer.

In the chip manufacturing process, silicon dioxide is produced on the surface of a smooth silicon wafer by an oxidizing agent and a gradual temperature rise. This process can be called oxidation or thermal oxidation. In the entire chip manufacturing process, silicon dioxide formed by oxidizing silicon wafers has many functions, such as surface passivation, doping barrier layer, surface insulator and device insulator. The formation of very high-density silicon dioxide can protect the surface and interior of the device; the role of the doping barrier layer means that silicon dioxide can form a blocking protective layer to prevent dopants from invading the silicon surface; the role of the surface insulator refers to the role of the dioxide The oxide layer of silicon can prevent short circuits between adjacent upper and lower metal layers, and at the same time, a sufficiently thick oxide layer can also be used to prevent induction from the metal, that is, field oxide; the role of the device insulator is that the oxide layer can It acts as a dielectric and can induce an induced current in the gate electrode under the oxide layer.

Step 105 : performing well region lithography on the oxidized silicon wafer according to the circuit design on the mask.

Lithography is the cornerstone of modern IC manufacturing, capable of printing sub-micron-sized patterns on silicon wafers. The principle of lithography is to spin-coat a light-sensitive photoresist onto a silicon wafer, form a thin film on the surface, and then use a lithography plate, which contains the graphic information of the specific layer to be made - this is the step For the mask involved in 110, the light source irradiates the photoresist through the photoresist, so that the photoresist is selectively exposed; then the photoresist is developed, and the pattern transfer from the plate to the silicon wafer is completed. Next, the photoresist can be used as a masking film in the step of etching the underlying thin film layer, or in the step of ion implantation and doping.

Step 107 : after the photolithography is completed, wet etching is performed on the silicon wafer to remove silicon dioxide to form a well region injection hole.

Wet etching is an etching method. It is a technique of immersing the etching material in an etching solution for etching. It is a pure chemical etching with excellent selectivity. After etching the current film, it will stop. without damaging the underlying film of other materials.

Step 109: Perform ion implantation on the silicon wafer to form a well.

Ion implantation is a technique that combines ion sorting, acceleration, and dose measurement to introduce precise impurity atoms into a silicon substrate. quantity method.

Step 111 : performing rapid thermal annealing on the silicon wafer after ion implantation.

Rapid Thermal Annealing (RTA) is a process in the chip manufacturing process, which is generally used to activate doping elements in semiconductor materials and restore the amorphous structure caused by ion implantation to a complete lattice structure. Specifically, the rapid thermal annealing process may be to rapidly heat the silicon wafer from ambient temperature to about 1000-1500K, hold the silicon wafer at this temperature for a few seconds, and then complete the quenching.

Step 113: use a shallow trench isolation process for isolation.

Shallow Trench Isolation (STI) is to form a trench by depositing, patterning, and etching silicon using a silicon nitride mask, and filling the trench with a deposition oxide for isolation from silicon. craft.

Step 115: Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area photolithography according to the circuit design on the mask.

Step 117 : after the photolithography is completed, the polysilicon is removed by dry etching to form a gate electrode and an injection hole in the active region.

Dry etching is a thin-film etching technique using plasma. When the gas exists in the form of plasma, it has two characteristics: on the one hand, the chemical activity of these gases in the plasma is much stronger than that in the normal state. Reacts with the material to achieve the purpose of etching and removal; on the other hand, the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy. When it bombards the surface of the object to be etched, it will be etched. The atoms of the material are knocked out, so as to achieve the purpose of using physical energy transfer to achieve the purpose of etching. Therefore, dry etching is the result of a balance between the physical and chemical processes on the wafer surface. Dry etching can be divided into three types: physical etching, chemical etching, and physical-chemical etching.

Step 119: Perform ion implantation on the silicon wafer to form source and drain electrodes.

Step 121 : performing rapid thermal annealing on the silicon wafer after ion implantation.

Step 123 : using a chemical vapor deposition process to form borophosphosilicate glass on the surface of the silicon wafer, and perform photolithography of through holes (ie, lead holes) according to the circuit design on the mask.

The thin film process refers to the process of forming the required thin film on the surface of the silicon wafer. These specific films include insulators, semiconductors or conductors. The main thin film technologies include chemical vapor deposition (Chemical Vapor Deposition, CVD) and physical vapor deposition (Physical Vapor Deposition, PVD) and so on. The vast majority of thin films in integrated circuit fabrication are deposited by CVD techniques. The principle of CVD is to mix the chemical components containing the required atoms or molecules in the reaction chamber and react in the gaseous state, so that the atoms or molecules are deposited on the surface of the silicon wafer, thereby forming a specific type of thin film. The chemical reactions used are generally divided into pyrolysis, reduction, oxidation, and nitridation. Pyrolysis refers to chemical reactions that rely solely on heat. Reduction is a chemical reaction of molecules, hydrogen. Oxidation is a chemical reaction of atoms, molecules and oxygen. Nitriding mainly refers to a chemical reaction that forms a silicon nitride film on the surface of a silicon wafer.

Step 125 : after the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by a physical vapor deposition process.

Unlike chemical vapor deposition, which relies on chemical reactions to generate reactive particles to form thin films, physical vapor deposition methods mainly use physical processes to deposit thin films, that is, use physical processes to transfer atoms or molecules from a gas source to the surface of a silicon wafer. PVD technology is more used in every aspect than CVD method, because it can do the deposition of almost any material.

The chips of general integrated circuits are composed of multi-layer metal layers, and the metal layers and the metal layers are connected by vias (VIAs).

Step 127 : use a physical vapor deposition process to form a metal layer on the surface of the silicon wafer; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: a metal layer outside the inductance device of the metal layer or multiple strips of redundant metal.

In some embodiments, the strip-shaped redundant metal filled outside the inductor is not arranged along the direction of the induced current, which can further reduce the loss of the induced current in the filled metal. Furthermore, when the strip-shaped redundant metal is placed along the direction perpendicular to the induced current, the gaps between the strips cut off the flow path of the current, which can further significantly reduce the loss of the induced current in the metal.

Step 129 : chemical mechanical polishing is performed on the metal layer filled with the redundant metal to planarize it.

After the growth of the metal layer is completed, uneven metal thickness and etching concentration differences are formed on the surface of the silicon wafer. The purpose of chemical mechanical polishing (Chemical Mechanical Polish, CMP) is to remove the excess metal to make them the same height. When CMP planarizes the metal layer, it combines chemical and mechanical effects. Through the polishing liquid containing chemical components, the mechanical and chemical effects simultaneously act on the polishing layer.

Step 131: Test and package the silicon wafer.

Packaging is mainly to achieve the connection and protection between the internal and external circuits of the chip. The testing of silicon wafers is to use various testing methods to detect whether the silicon wafers or chips have design defects or physical defects caused by the manufacturing process. In order to ensure that the chip can be used normally, the last two processes that must be passed before delivery to the complete machine manufacturer: packaging and testing.

The above are some descriptions of the manufacturing method of the chip disclosed in the present invention. In other embodiments of the present invention, chips manufactured according to the method for manufacturing a chip disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured by the chip manufacturing method disclosed in the present invention will have a specific structure, for example, the outside of the inductor device is filled with one or more strip-shaped redundant metals. The redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the chip manufacturing method disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.

In other embodiments of the present invention, a method for filling redundant metal is disclosed. Generally, the filling of redundant metal is completed in the wafer fab or chip manufacturing stone. The filling of redundant metal is located in the final stage of layout physical design, timing, layout logic verification (Layout Versus Schematics, LVS), design rule verification (Design Rule Check, DRC), etc. have been passed, and the layout design has been basically finalized.

Referring to FIG. 9 , another embodiment of the present invention discloses a method for filling redundant metal, including the following steps:

Step 191: Obtain an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers.

Step 193 : Fill at least one metal layer with redundant metal according to a preset rule; wherein the preset rule includes: filling one or more strip-shaped redundant metals on the outside of the inductance device of the metal layer.

In the layout design of integrated circuits, redundant metal filling is a process of layout post-processing. Step 193 proposes a rule for filling redundant metal in the metal layer, that is, filling one or more strips outside the inductor device of the metal layer. Shape redundant metal. By filling with strip-shaped redundant metal, the filling of redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved. Further, although the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced. The quality factor of the inductor. Considering this situation, the strip-shaped redundant metal filled outside the inductor in step 193 is not placed along the direction of the induced current, which can further reduce the loss of the induced current in the filler metal; further, step 193 is in The strip-shaped redundant metal is filled outside the inductor. The strip-shaped redundant metal is placed along the direction of the vertical induced current. Since the gap between the strips cuts off the current flow path, this can further significantly reduce the loss of the induced current in the metal. .

In addition, there are various methods for identifying and locating inductive devices in an integrated circuit layout. In some methods, according to the identification layer provided by the designer, usually special devices such as inductors will have a corresponding identification layer. If the chip factory needs it, the designer can be required to retain the identification layer when providing the original design data. The conversion is passed to the chip factory; in other methods, these designs have a fixed shape, such as an inductor device, whose metal layer pattern is a plurality of parallel metal loops, which exist as inductor coils.

The above are some descriptions of the method for filling the redundant metal disclosed in the present invention. In other embodiments of the present invention, chips fabricated according to the method for filling redundant metal disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured according to the method for filling redundant metal disclosed in the present invention will have a specific structure. , the strip-shaped redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the method for filling redundant metal disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.

Referring to FIG. 10, some embodiments of the present invention further disclose an integrated circuit chip, the chip includes one or more metal layers, at least one metal layer is provided with an inductance device 11, and is filled outside the inductance device There are one or more strip-shaped redundant metals 12 , wherein FIG. 10 is a schematic diagram of a partial area of the metal layer provided with the inductance device 11 , and 13 is a metal wire or a signal wire. In some embodiments, the strip-shaped redundant metal 12 is not parallel to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 are generated in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. The directions of the induced currents are not parallel. In some embodiments, the strip-shaped redundant metal 12 is perpendicular to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 generate an induced current in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. direction is vertical.

This application proposes a technical solution for radially filling strip-shaped redundant metal around an inductor. Compared with filling the redundant metal in the form of a metal block array, this solution is easier to meet the requirements of the metal density of the process, thereby avoiding filling the redundant metal inside the inductor. For example, placing radial metal strips perpendicular to the induced current direction of the inductor around the outside of the inductor can effectively suppress the loss of the quality factor of the inductor caused by the redundant metal under the premise of meeting the requirements of the process production. In this way, an inductor with a higher quality factor can be obtained. The simulation results show that the method can be applied to inductors operating from 15GHz to 70GHz, and the quality factor is improved by 7% to 17%, which will be explained in detail below.

The present invention uses simulation software (such as HFSS electromagnetic simulation software) to carry out quality factor simulation of two different inductors A, B and a coupled inductor respectively; wherein when performing quality factor simulation of each inductor, it is performed without adding any Redundant metal, filled in the form of an array of redundant metal blocks around the inductor, and filled with strips of redundant metal in a radial pattern around the inductor were simulated, as described below.

(1) Simulation of inductance A

A two-turn inductor A with an inductance value of 0.38nH and an inner diameter of 35um is simulated. The inductor design and the filling method of redundant metal are shown in Figure 11(a), Figure 11(b), and Figure 11(c). Figure 11(a) shows that inductor A is not filled with any redundant metal. Figure 11(b) shows that inductor A is filled with redundant metal or bulk redundant metal according to the block array method. Figure 11(c) is a Inductor A is filled with strip-shaped redundant metal in a radial shape, and electromagnetic field simulations are carried out for these three cases. According to the calculation formula of inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 12. Show. It can be seen from Fig. 12 that the maximum value of the quality factor Q of the inductor is 16.04 when no redundant metal is filled; Without filling any redundant metal), the quality factor is reduced by (16.04-14.93)/16.04=6.9%; according to the method of filling strip-shaped redundant metal in a radial shape proposed by an embodiment of the present invention, the quality factor Q of the inductor is the largest The value is 15.97. Compared with the ideal situation, the quality factor is only reduced by (15.97-16.04)/16.04=0.44%. Compared with the original block array filling method, the quality factor Q is (15.97-14.93)/14.93 =7.0% improvement. In addition, it can be seen in the figure that the frequencies corresponding to the maximum value of the inductance quality factor Q after the three filling methods are different, which is caused by the parasitic capacitance introduced by the redundant metal.

(2) Simulation of inductance B

The inductance value is 0.26nH and the inner diameter is 23um. The two-round inductance B is simulated. The inductance design and the filling method of redundant metal are shown in Figure 13(a), Figure 13(b), and Figure 13(c). Figure 13(c) 13(a) does not fill the inductor B with any redundant metal. Figure 13(b) fills the inductor B with redundant metal or bulk redundant metal according to the block array method. Inductor B is filled with strip-shaped redundant metal in a radial shape. The electromagnetic field simulation is carried out for these three cases. According to the calculation formula of the inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 14. . It can be seen from Figure 14 that the maximum value of the quality factor Q of the inductor is 17.45 when no redundant metal is filled, and the maximum value of the quality factor Q of the inductor when the redundant metal is filled in the block array method is 15.82, which is lower than the ideal condition. According to the method of filling strip-shaped redundant metal in a radial shape proposed in an embodiment of the present invention, the maximum value of the inductance quality factor Q is 16.92. Compared with the ideal situation, the quality factor is only reduced by 3.0%. Compared with the original block array filling method, the quality factor is improved by 6.9%.

(3) Simulation of coupled inductors

The present invention can be applied not only to single-port inductors, but also to coupled inductors. As shown in Fig. 15(a), Fig. 15(b), Fig. 15(c), the 3D modeling and electromagnetic simulation under the above three different filling conditions were carried out for a coupled inductor with a turns ratio of 2:1. Specifically, Fig. 15(a) shows that the coupled inductor is not filled with any redundant metal, and Fig. 15(b) shows that the coupled inductor is filled with redundant metal or bulk redundant metal according to the block array method. Fig. 15( c) is to fill the strip-shaped redundant metal in a radial shape for the coupled inductor; wherein the bulk array and the radial strip-shaped redundant metal are filled around the inductor to meet the requirements for the metal density of the process.

After the simulation, when the secondary coil port is connected to a 50Ω load, the quality factor Q of the primary coil is obtained according to the calculation formula of the inductance quality factor Q above to obtain the relationship between the inductance quality factor and the frequency. The result is shown in Figure 16. It can be seen from Figure 16 that the maximum value of the quality factor Q of the primary coil when no redundant metal is filled is 19.86; when the redundant metal is filled in the block array mode, the maximum value of the quality factor Q of the primary coil is 15.89, which is lower than the ideal condition. According to the method of filling strip-shaped redundant metal radially proposed in an embodiment of the present invention, the maximum value of the quality factor Q of the primary coil is 18.69, which is only 5.9% lower than the ideal condition, and Compared with the original block array filling method, the quality factor is improved by 17.6%. The relationship between the quality factor Q of the secondary coil and the frequency is shown in Figure 17. It can be seen from Figure 17 that the maximum value of the quality factor Q of the secondary coil is 11.07 when no redundant metal is filled; The quality factor is reduced by 8.9%; and according to the method for filling strip-shaped redundant metal in a radial shape proposed in an embodiment of the present invention, the maximum value of the quality factor Q of the secondary coil is 10.81. Compared with the ideal situation, the quality factor is only reduced. 2.3%, and compared with the original uniform block array filling method, the quality factor is improved by 7.2%.

The following table summarizes the inductance quality factor simulation results of inductors A, B and coupled inductors, where method 1 refers to the filling method of the block array, and method 2 refers to the radial filling strip redundancy proposed by an embodiment of the present invention As can be seen from the table below, the present invention can effectively prevent the reduction of the inductance quality factor due to the addition of redundant metals; in the case of satisfying the metal density required by the process, the redundant metal filling scheme proposed by the present invention obtains Compared with the general redundant metal filling method, the quality factor of the inductor is improved by about 7%, and the present invention can also be applied to coupled inductors.

Aiming at the situation that redundant metal needs to be filled around the inductor due to the requirement of metal density in the chip production process, in some embodiments, a filling technology of placing radial strips of metal perpendicular to the direction of the induced electric field is proposed; This technology alleviates the problem that the allowable area of the INDDMY layer in the design of analog and RF circuits is not enough for design due to process limitations. Simulations show that this technique not only meets the metal density required by the process, but also cuts off the induced current path and avoids metal filling inside the inductor coil without using the INDDMY layer to ignore the metal density check. The electromagnetic full-wave simulation shows that, compared with the conventional method of uniformly filling the redundant metal of the block array, this technology can effectively reduce the loss caused by the redundant metal to the inductor, which is extremely beneficial for the design of high-Q single-port inductors and coupled inductors. .

Descriptions are made herein with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps, and components for performing operational steps, may be implemented in different ways depending on the particular application or considering any number of cost functions associated with the operation of the system (eg, one or more steps may be deleted, modified or incorporated into other steps).

In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. Additionally, as understood by those skilled in the art, the principles herein may be reflected in a computer program product on a computer-readable storage medium preloaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CD to ROM, DVD, Blu Ray disks, etc.), flash memory, and/or the like . These computer program instructions may be loaded on a general purpose computer, special purpose computer or other programmable data processing apparatus to form a machine, such that the instructions executed on the computer or other programmable data processing apparatus may generate means for carrying out the specified functions. These computer program instructions may also be stored in a computer-readable memory that instructs a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable memory form a piece of Articles of manufacture, including implementing means for implementing specified functions. Computer program instructions may also be loaded on a computer or other programmable data processing device to perform a series of operational steps on the computer or other programmable device to produce a computer-implemented process such that a process executed on the computer or other programmable device Instructions may provide steps for implementing specified functions.

Although the principles herein have been shown in various embodiments, many modifications may be made in structure, arrangement, proportions, elements, materials and components as are particularly suited to particular environmental and operating requirements without departing from the principles and scope of the present disclosure use. The above modifications and other changes or corrections are intended to be included within the scope of this document.

The foregoing Detailed Description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Accordingly, this disclosure is to be considered in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within its scope. Likewise, the advantages, other advantages, and solutions to problems of the various embodiments have been described above. However, the benefits, advantages, solutions to the problems, and any elements that give rise to them, or make them more explicit, should not be construed as critical, necessary, or essential. As used herein, the term "comprising" and any other variations thereof are non-exclusive inclusion, such that a process, method, article or device including a list of elements includes not only those elements, but also not expressly listed or included in the process , method, system, article or other elements of a device. Furthermore, as used herein, the term "coupled" and any other variations thereof refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.

Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined only by the claims.

Claims

A method for manufacturing a chip, comprising:

Wash and dry the silicon wafer;

Oxidize the cleaned silicon wafer;

Perform well region lithography on the oxidized silicon wafer according to the circuit design on the mask;

After the photolithography is completed, the silicon wafer is wet-etched to remove silicon dioxide to form a well region injection hole;

Ion implantation is performed on the silicon wafer to form a well;

Rapid thermal annealing of ion implanted silicon wafers;

Isolation by shallow trench isolation process;

Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area lithography according to the circuit design on the mask;

After the photolithography is completed, the polysilicon is removed by dry etching to form the gate and the injection hole in the active region;

Ion implantation is performed on the silicon wafer to form source and drain;

Rapid thermal annealing of ion implanted silicon wafers;

Borophosphosilicate glass is formed on the surface of the silicon wafer by chemical vapor deposition process, and through-hole lithography is performed according to the circuit design on the mask;

After the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by the physical vapor deposition process;

A metal layer is formed on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: one or more wires outside the inductor device of the metal layer Strip redundant metal;

chemical mechanical polishing of the metal layer filled with redundant metal to planarize it;

Silicon wafers are tested and packaged.
The manufacturing method of claim 1, wherein the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
The manufacturing method of claim 1, wherein the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
A chip manufactured according to the manufacturing method of any one of claims 1 to 3.
A method for filling redundant metal, comprising:

obtaining an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers;

At least one of the metal layers is filled with redundant metal according to a preset rule; wherein the preset rule includes: identifying the inductance device existing in the metal layer to be filled, and filling one or Multiple strips of redundant metal.
The filling method according to claim 4, wherein the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
The filling method according to claim 5, wherein the strip-shaped redundant metal is perpendicular to the coil direction of the inductance device.
A chip manufactured according to the filling method of any one of claims 5 to 7.
An integrated circuit chip is characterized by comprising one or more metal layers, wherein at least one metal layer is provided with an inductance device, and the outside of the inductance device is filled with one or more strip-shaped redundant metals.
The chip of claim 9, wherein the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
The chip of claim 10, wherein the strip-shaped redundant metal is perpendicular to the coil direction of the inductance device.
A computer-readable storage medium, characterized in that the computer-readable storage medium has a program, and the program can be executed by a processor to implement the method according to any one of claims 1 to 3 or 5 to 7 .