WO2022165670A1 - Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium - Google Patents
Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium Download PDFInfo
- Publication number
- WO2022165670A1 WO2022165670A1 PCT/CN2021/075075 CN2021075075W WO2022165670A1 WO 2022165670 A1 WO2022165670 A1 WO 2022165670A1 CN 2021075075 W CN2021075075 W CN 2021075075W WO 2022165670 A1 WO2022165670 A1 WO 2022165670A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal
- inductor
- redundant
- redundant metal
- strip
- Prior art date
Links
- 239000002184 metal Substances 0.000 title claims abstract description 307
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 307
- 238000000034 method Methods 0.000 title claims abstract description 121
- 238000011049 filling Methods 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 238000003860 storage Methods 0.000 title claims abstract description 10
- 150000002739 metals Chemical class 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 60
- 229910052710 silicon Inorganic materials 0.000 claims description 60
- 239000010703 silicon Substances 0.000 claims description 60
- 235000012431 wafers Nutrition 0.000 claims description 60
- 230000008569 process Effects 0.000 claims description 49
- 238000013461 design Methods 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000206 photolithography Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000005240 physical vapour deposition Methods 0.000 claims description 11
- 239000000126 substance Substances 0.000 claims description 11
- 238000001459 lithography Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 abstract description 11
- 230000001939 inductive effect Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 65
- 238000004088 simulation Methods 0.000 description 17
- 238000005530 etching Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 239000010409 thin film Substances 0.000 description 12
- 230000002829 reductive effect Effects 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000004907 flux Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000004590 computer program Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005672 electromagnetic field Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000197 pyrolysis Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002925 chemical effect Effects 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000002500 effect on skin Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
Definitions
- the invention relates to a method for manufacturing a chip, a method for filling redundant metal and a chip.
- Redundant metal filling is a technology used in the manufacture of integrated circuits (Integrated Circuit, IC) to improve surface planarization; The flatness of the surface of the chip of the integrated circuit after chemical mechanical polishing (CMP), thereby improving the reliability and yield of the product.
- the integrated circuit manufacturing technology develops at a rate of doubling the integration level every 18 months according to Moore's Law, but when the feature size of integrated circuits falls below, for example, 90 nanometers, the integrated circuit manufacturing technology encounters unprecedented challenges, and the surface is not flat. The performance and stability of the device have been seriously affected by the stability of the device, and redundant metal filling has become an indispensable step.
- redundant metal needs to be filled to meet the requirements of the production process for the metal density of each metal layer of the chip. Filling of redundant metal, however, introduces other problems.
- the present invention provides a method for manufacturing a chip, a method for filling redundant metal, and a chip to solve one or more of several problems introduced by the filling of redundant metal.
- an embodiment provides a method for manufacturing a chip, including:
- the silicon wafer is wet-etched to remove silicon dioxide to form a well region injection hole;
- Ion implantation is performed on the silicon wafer to form a well
- the polysilicon is removed by dry etching to form the gate and the injection hole in the active region;
- Ion implantation is performed on the silicon wafer to form source and drain;
- Borophosphosilicate glass is formed on the surface of the silicon wafer by chemical vapor deposition process, and through-hole lithography is carried out according to the circuit design on the mask;
- the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by the physical vapor deposition process;
- a metal layer is formed on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: one or more wires outside the inductor device of the metal layer Strip redundant metal;
- Silicon wafers are tested and packaged.
- the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
- the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
- an embodiment provides a chip manufactured according to the manufacturing method described in any of the embodiments herein.
- an embodiment provides a method for filling redundant metal, including:
- the integrated circuit layout includes one or more metal layers
- At least one of the metal layers is filled with redundant metal according to a preset rule; wherein the preset rule includes: identifying the inductance device existing in the metal layer to be filled, and filling one or Multiple strips of redundant metal.
- the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
- the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
- an embodiment provides a chip fabricated according to the filling method described in any of the embodiments herein.
- an embodiment provides an integrated circuit chip, comprising one or more metal layers, wherein at least one metal layer is provided with an inductance device, and one or more metal layers are filled outside the inductance device Root strip redundant metal.
- the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
- the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
- an embodiment provides a computer-readable storage medium, the computer-readable storage medium stores a program, and the program can be executed by a processor to implement the method described in any of the embodiments herein.
- Fig. 1 is a schematic diagram of a metal block array
- Fig. 2 is the schematic diagram of filling redundant metal in the form of metal block array outside and inside the inductor;
- Fig. 3 is a schematic diagram of metal strip arrangement
- Fig. 4 is a schematic diagram of metal strips arranged around the outside of the inductor and can meet the requirements of the process for metal density;
- Fig. 5 is a schematic diagram showing the direction in which the alternating magnetic field generated by the inductance produces an induced current in the outer conductor parallel to the inductance coil;
- Fig. 6 is a schematic diagram of the strip-shaped redundant metal filled around the outside of the inductor and not placed along the direction of the inductor coil or the induced current;
- Figure 7(a) and Figure 7(b) are two schematic diagrams of strip-shaped redundant metal
- FIG. 8 is a flowchart of a method for manufacturing a chip according to an embodiment
- FIG. 9 is a flowchart of a method for filling redundant metal according to an embodiment
- FIG. 10 is a schematic diagram of a partial area of a metal layer of a chip of a collector circuit according to an embodiment
- Figure 11(a) is a schematic diagram of inductor A without any redundant metal filling
- Figure 11(b) is a schematic diagram of filling inductor A with redundant metal or bulk redundant metal in a block array manner
- Figure 11 (c) is a schematic diagram of radially filling the strip-shaped redundant metal for the inductor A
- Figure 12 shows the corresponding simulation results for these three cases
- Figure 13(a) shows that inductor B is not filled with any redundant metal.
- Figure 13(b) shows that inductor B is filled with redundant metal or bulk redundant metal according to the block array method.
- Figure 13(c) is a Fill the strip-shaped redundant metal radially for the inductor B;
- Figure 14 shows the corresponding simulation results for these three cases;
- Figure 15(a) shows that the coupled inductors are not filled with any redundant metal.
- Figure 15(b) shows that the coupled inductors are filled with redundant metal or bulk redundant metal according to the block array method.
- Figure 15(c) is a The coupled inductors are radially filled with strips of redundant metal;
- Figure 16 shows the corresponding simulation results for the primary coil quality factor for these three cases, and
- Figure 17 shows the corresponding simulation results for the secondary coil quality factor for these three cases.
- connection and “connection” mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).
- each metal layer to be filled with redundant metal to ensure the flatness of the surface after chemical mechanical polishing to obtain a higher yield; however, the filling of the redundant metal will also increase the Some problems that you want to avoid when the chip is introduced into the circuit design, such as the filling of the redundant metal will also introduce the parasitic capacitance that you want to avoid when the circuit design is introduced into the chip.
- chip manufacturers have also provided a method to avoid filling redundant metal in consideration of the actual needs of circuit design - using the INDDMY layer in the layout design process;
- the software use the INDDMY layer to frame the desired area, and the frame-selected area will not be checked for metal density, so there is no need to add redundant metals; the inductance model provided in the manufacturing process generally comes with the INDDMY layer.
- Designers can also manually add INDDMY layers to their designed inductors to skip metal density checks.
- the advantage of this is that it can avoid placing redundant metal around the inductor, and prevent the quality factor of the inductor from decreasing due to the interference of the redundant metal to the magnetic field around the inductor; but understandably, the INDDMY layer is only a virtual structural layer on the software. It does not exist in the physical process of actual production. The role of the INDDMY layer is to artificially make the selected area skip the metal density check, so naturally it will not further consider filling this area with redundant metal to meet the metal density. 's checked.
- the function of the INDDMY layer is to artificially make the area selected by the frame skip the metal density check, due to the limitation of the production process, the area occupied by the INDDMY layer must be less than a certain proportion relative to the overall chip area, so as to ensure the actual production.
- the flatness of each metal layer of the chip during the process In the general digital chip design, if the inductor is hardly used, the proportion of the INDDMY layer to the total chip area specified by the process is sufficient for the designer to use.
- the quality factor of the inductor can generally be represented by the symbol Q; the quality factor Q of the inductor plays a key role in various analog RF circuits.
- the phase noise of the oscillator is proportional to 1/Q 2 , and for example
- the voltage gain of the tuned amplifier is proportional to Q.
- the quality factor Q of the inductor often limits the performance of the circuit.
- the highest value of the FoM (figure of merit) of the oscillator is limited by the highest quality factor of the inductor under this process. .
- the quality factor Q of the inductor is a very important concept; those skilled in the art quantify the loss level of the inductor through the quality factor Q of the inductor.
- the quality factor Q of the inductor is defined as the maximum energy storage value of the system and the system in one cycle. Ratio of energy loss. Therefore, a key factor affecting the Q value is the amount of energy loss when the current flows through the inductor, and the loss of the inductor mainly comes from the metal structure of the inductor itself and the equivalent resistance presented by the surrounding space. According to the definition of the quality factor Q of the inductance, if the inductance is L, the equivalent series resistance is R s , and the operating frequency is ⁇ , the Q value has the following expression:
- the following will introduce several mechanisms that cause the loss of the inductor—specifically, metal ohmic loss and dielectric loss.
- the figure of merit can be improved by reducing the metal resistance of the inductance.
- the equivalent resistance can be reduced by increasing the width of the inductor; however, a wider metal line will show lower resistance, but on the other hand, it will also have a larger parasitic capacitance relative to the substrate, which will will reduce the self-resonant frequency of the inductor. Therefore, designers often need to trade off between the Q value and the parasitic capacitance in the actual circuit design.
- f is the frequency
- ⁇ is the magnetic permeability
- ⁇ is the electrical conductivity
- the divergent electric field passes through the dielectric layer between the substrate and each layer of metal to form a displacement current. Because the resistivity of the substrate is not ideal, it is unavoidable that a portion of the current flowing through the substrate will be converted into losses during each cycle of voltage change. The loss that occurs when the electric field passes through these media is called dielectric loss, which further reduces the quality factor of the inductor.
- the redundant metal is currently filled in the form of a metal block array.
- Figure 1 is an example of a metal block array; due to the limitation of the process, the redundant metal has inter-metal spacing. Limitation, which makes redundant metal filling in the form of metal block array, only filling the redundant metal outside the inductor can not well meet the requirements of the process for metal density, often it is also necessary to fill the redundant metal inside the inductor.
- Fig. 2 is an example of filling redundant metals in the form of metal block arrays outside and inside an inductor or an inductor device.
- FIG. 3 is an example of the arrangement in the form of metal strips
- FIG. 4 is an example of the arrangement in the form of metal strips around the outside of the inductor and can meet the requirements for metal density in the process.
- the present application improves the filling method of the redundant metal, and replaces the bulk redundant metal with a strip redundant metal.
- the redundant metal occupies the same space, the spatial density of the strip redundant metal is much larger than that of the bulk redundant metal, so this makes it only necessary to fill a small amount of redundant metal inside the inductor, and even does not need to fill the redundant metal inside the inductor.
- metal it can also meet the requirements of the process for metal density.
- the filling of the redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved.
- the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced.
- the quality factor of the inductor - the dashed line in Figure 5 shows the direction in which the alternating magnetic field generated by the inductor will induce a current in the outer conductor parallel to the inductor coil. Considering this situation, the strip-shaped redundant metal filled outside the inductor is not placed along the direction of the inductor coil or the induced current, which can further reduce the loss of the induced current in the filler metal.
- Figure 6 is a Example; further, when the strip-shaped redundant metal is placed along the vertical inductor coil or the direction of the induced current, the gap between the strips cuts off the current flow path, which can further significantly reduce the induced current in the metal.
- the loss in , Figure 4 above is such an example.
- the present patent proposes to fill the outside of the inductor with strip-shaped redundant metal, so as to meet the metal density and reduce the influence on the quality factor of the inductor due to the filling of the redundant metal. Further, the strip-shaped redundancy The metal is placed radially around the outside of the inductor in the direction perpendicular to the induced current generated by the inductor to reduce the ohmic loss of the current as much as possible, thereby further reducing the influence of the redundant metal filling on the quality factor of the inductor.
- the "strip shape" is used to define that the redundant metal is in the shape of a strip or a strip as a whole, and this shape can be a rectangle as shown in Figure 7(a), As shown in Fig. 7(b), both ends are arc-shaped, such as semi-circular shapes.
- the direction of the strip-shaped redundant metal arrangement in the present invention it is defined by the long axis direction of the strip-shaped redundant metal.
- the long axis direction of the residual metal is perpendicular to the direction of the inductor coil or the induced current.
- the specific size and quantity of the strip-shaped redundant metal can be determined according to metal density requirements and the like.
- Some embodiments of the present invention disclose a method for manufacturing a chip.
- the chip is the carrier of the integrated circuit, and the manufacturing method of the chip is a method of miniaturizing the circuit and manufacturing it on the surface of the semiconductor wafer; CMP and other process technologies are used to make components such as MOSFETs or BJTs, and then thin-film and CMP processes are used to make wires to complete the production of chips.
- the complete process of chip fabrication includes several links such as chip design, wafer fabrication, packaging fabrication and testing, among which the wafer fabrication process is particularly complex.
- a method for manufacturing a chip includes the following steps:
- Step 101 cleaning and drying the silicon wafer.
- the silicon wafer or silicon wafer is first cleaned to remove various impurities on its surface.
- Various semiconductor devices are generally made by doping appropriate impurities in the silicon wafer (usually the doping concentration is at the level of one millionth), depositing a suitable thin film on the surface of the silicon wafer, photolithography, etching specific patterns, etc. It is manufactured by a series of process steps, so only when the contamination level of various unrelated impurities is controlled in advance without affecting the device characteristics and chip yield, can the above-mentioned process steps be truly producible. In practical applications, this requires us to control the concentration of various irrelevant impurities below one part per million, or even one part per billion, and at the same time, we must effectively remove the influence of various stray particles.
- washing and drying can be performed again.
- Step 103 Oxidize the cleaned silicon wafer.
- silicon dioxide is produced on the surface of a smooth silicon wafer by an oxidizing agent and a gradual temperature rise. This process can be called oxidation or thermal oxidation.
- silicon dioxide formed by oxidizing silicon wafers has many functions, such as surface passivation, doping barrier layer, surface insulator and device insulator.
- silicon dioxide can protect the surface and interior of the device;
- the role of the doping barrier layer means that silicon dioxide can form a blocking protective layer to prevent dopants from invading the silicon surface;
- the role of the surface insulator refers to the role of the dioxide
- the oxide layer of silicon can prevent short circuits between adjacent upper and lower metal layers, and at the same time, a sufficiently thick oxide layer can also be used to prevent induction from the metal, that is, field oxide;
- the role of the device insulator is that the oxide layer can It acts as a dielectric and can induce an induced current in the gate electrode under the oxide layer.
- Step 105 performing well region lithography on the oxidized silicon wafer according to the circuit design on the mask.
- Lithography is the cornerstone of modern IC manufacturing, capable of printing sub-micron-sized patterns on silicon wafers.
- the principle of lithography is to spin-coat a light-sensitive photoresist onto a silicon wafer, form a thin film on the surface, and then use a lithography plate, which contains the graphic information of the specific layer to be made - this is the step
- the light source irradiates the photoresist through the photoresist, so that the photoresist is selectively exposed; then the photoresist is developed, and the pattern transfer from the plate to the silicon wafer is completed.
- the photoresist can be used as a masking film in the step of etching the underlying thin film layer, or in the step of ion implantation and doping.
- Step 107 after the photolithography is completed, wet etching is performed on the silicon wafer to remove silicon dioxide to form a well region injection hole.
- wet etching is an etching method. It is a technique of immersing the etching material in an etching solution for etching. It is a pure chemical etching with excellent selectivity. After etching the current film, it will stop. without damaging the underlying film of other materials.
- Step 109 Perform ion implantation on the silicon wafer to form a well.
- Ion implantation is a technique that combines ion sorting, acceleration, and dose measurement to introduce precise impurity atoms into a silicon substrate. quantity method.
- Step 111 performing rapid thermal annealing on the silicon wafer after ion implantation.
- Rapid Thermal Annealing is a process in the chip manufacturing process, which is generally used to activate doping elements in semiconductor materials and restore the amorphous structure caused by ion implantation to a complete lattice structure.
- the rapid thermal annealing process may be to rapidly heat the silicon wafer from ambient temperature to about 1000-1500K, hold the silicon wafer at this temperature for a few seconds, and then complete the quenching.
- Step 113 use a shallow trench isolation process for isolation.
- Shallow Trench Isolation is to form a trench by depositing, patterning, and etching silicon using a silicon nitride mask, and filling the trench with a deposition oxide for isolation from silicon. craft.
- Step 115 Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area photolithography according to the circuit design on the mask.
- Step 117 after the photolithography is completed, the polysilicon is removed by dry etching to form a gate electrode and an injection hole in the active region.
- Dry etching is a thin-film etching technique using plasma.
- the gas exists in the form of plasma, it has two characteristics: on the one hand, the chemical activity of these gases in the plasma is much stronger than that in the normal state. Reacts with the material to achieve the purpose of etching and removal; on the other hand, the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy.
- the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy.
- it bombards the surface of the object to be etched it will be etched.
- the atoms of the material are knocked out, so as to achieve the purpose of using physical energy transfer to achieve the purpose of etching. Therefore, dry etching is the result of a balance between the physical and chemical processes on the wafer surface. Dry etching can be divided into three types: physical etching, chemical etching, and physical-chemical etching.
- Step 119 Perform ion implantation on the silicon wafer to form source and drain electrodes.
- Step 121 performing rapid thermal annealing on the silicon wafer after ion implantation.
- Step 123 using a chemical vapor deposition process to form borophosphosilicate glass on the surface of the silicon wafer, and perform photolithography of through holes (ie, lead holes) according to the circuit design on the mask.
- the thin film process refers to the process of forming the required thin film on the surface of the silicon wafer. These specific films include insulators, semiconductors or conductors.
- the main thin film technologies include chemical vapor deposition (Chemical Vapor Deposition, CVD) and physical vapor deposition (Physical Vapor Deposition, PVD) and so on.
- CVD chemical Vapor Deposition
- PVD Physical Vapor Deposition
- the vast majority of thin films in integrated circuit fabrication are deposited by CVD techniques.
- the principle of CVD is to mix the chemical components containing the required atoms or molecules in the reaction chamber and react in the gaseous state, so that the atoms or molecules are deposited on the surface of the silicon wafer, thereby forming a specific type of thin film.
- the chemical reactions used are generally divided into pyrolysis, reduction, oxidation, and nitridation.
- Pyrolysis refers to chemical reactions that rely solely on heat.
- Reduction is a chemical reaction of molecules, hydrogen.
- Oxidation is a chemical reaction of atoms, molecules and oxygen.
- Nitriding mainly refers to a chemical reaction that forms a silicon nitride film on the surface of a silicon wafer.
- Step 125 after the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by a physical vapor deposition process.
- PVD technology is more used in every aspect than CVD method, because it can do the deposition of almost any material.
- the chips of general integrated circuits are composed of multi-layer metal layers, and the metal layers and the metal layers are connected by vias (VIAs).
- Step 127 use a physical vapor deposition process to form a metal layer on the surface of the silicon wafer; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: a metal layer outside the inductance device of the metal layer or multiple strips of redundant metal.
- the strip-shaped redundant metal filled outside the inductor is not arranged along the direction of the induced current, which can further reduce the loss of the induced current in the filled metal. Furthermore, when the strip-shaped redundant metal is placed along the direction perpendicular to the induced current, the gaps between the strips cut off the flow path of the current, which can further significantly reduce the loss of the induced current in the metal.
- Step 129 chemical mechanical polishing is performed on the metal layer filled with the redundant metal to planarize it.
- CMP Chemical Mechanical Polish
- Step 131 Test and package the silicon wafer.
- Packaging is mainly to achieve the connection and protection between the internal and external circuits of the chip.
- the testing of silicon wafers is to use various testing methods to detect whether the silicon wafers or chips have design defects or physical defects caused by the manufacturing process. In order to ensure that the chip can be used normally, the last two processes that must be passed before delivery to the complete machine manufacturer: packaging and testing.
- the manufacturing method of the chip disclosed in the present invention chips manufactured according to the method for manufacturing a chip disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured by the chip manufacturing method disclosed in the present invention will have a specific structure, for example, the outside of the inductor device is filled with one or more strip-shaped redundant metals.
- the redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the chip manufacturing method disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.
- a method for filling redundant metal is disclosed.
- the filling of redundant metal is completed in the wafer fab or chip manufacturing stone.
- the filling of redundant metal is located in the final stage of layout physical design, timing, layout logic verification (Layout Versus Schematics, LVS), design rule verification (Design Rule Check, DRC), etc. have been passed, and the layout design has been basically finalized.
- FIG. 9 another embodiment of the present invention discloses a method for filling redundant metal, including the following steps:
- Step 191 Obtain an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers.
- Step 193 Fill at least one metal layer with redundant metal according to a preset rule; wherein the preset rule includes: filling one or more strip-shaped redundant metals on the outside of the inductance device of the metal layer.
- redundant metal filling is a process of layout post-processing.
- Step 193 proposes a rule for filling redundant metal in the metal layer, that is, filling one or more strips outside the inductor device of the metal layer. Shape redundant metal.
- the filling of redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved.
- the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced.
- step 193 The quality factor of the inductor. Considering this situation, the strip-shaped redundant metal filled outside the inductor in step 193 is not placed along the direction of the induced current, which can further reduce the loss of the induced current in the filler metal; further, step 193 is in The strip-shaped redundant metal is filled outside the inductor. The strip-shaped redundant metal is placed along the direction of the vertical induced current. Since the gap between the strips cuts off the current flow path, this can further significantly reduce the loss of the induced current in the metal. .
- the above are some descriptions of the method for filling the redundant metal disclosed in the present invention.
- chips fabricated according to the method for filling redundant metal disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured according to the method for filling redundant metal disclosed in the present invention will have a specific structure. , the strip-shaped redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the method for filling redundant metal disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.
- some embodiments of the present invention further disclose an integrated circuit chip, the chip includes one or more metal layers, at least one metal layer is provided with an inductance device 11, and is filled outside the inductance device There are one or more strip-shaped redundant metals 12 , wherein FIG. 10 is a schematic diagram of a partial area of the metal layer provided with the inductance device 11 , and 13 is a metal wire or a signal wire.
- the strip-shaped redundant metal 12 is not parallel to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 are generated in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. The directions of the induced currents are not parallel.
- the strip-shaped redundant metal 12 is perpendicular to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 generate an induced current in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. direction is vertical.
- This application proposes a technical solution for radially filling strip-shaped redundant metal around an inductor.
- this solution is easier to meet the requirements of the metal density of the process, thereby avoiding filling the redundant metal inside the inductor.
- placing radial metal strips perpendicular to the induced current direction of the inductor around the outside of the inductor can effectively suppress the loss of the quality factor of the inductor caused by the redundant metal under the premise of meeting the requirements of the process production. In this way, an inductor with a higher quality factor can be obtained.
- the simulation results show that the method can be applied to inductors operating from 15GHz to 70GHz, and the quality factor is improved by 7% to 17%, which will be explained in detail below.
- the present invention uses simulation software (such as HFSS electromagnetic simulation software) to carry out quality factor simulation of two different inductors A, B and a coupled inductor respectively; wherein when performing quality factor simulation of each inductor, it is performed without adding any Redundant metal, filled in the form of an array of redundant metal blocks around the inductor, and filled with strips of redundant metal in a radial pattern around the inductor were simulated, as described below.
- simulation software such as HFSS electromagnetic simulation software
- FIG. 11(a), Figure 11(b), and Figure 11(c) show that inductor A is not filled with any redundant metal.
- Figure 11(b) shows that inductor A is filled with redundant metal or bulk redundant metal according to the block array method.
- Figure 11(c) is a Inductor A is filled with strip-shaped redundant metal in a radial shape, and electromagnetic field simulations are carried out for these three cases. According to the calculation formula of inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 12. Show.
- the inductance value is 0.26nH and the inner diameter is 23um.
- the two-round inductance B is simulated.
- the inductance design and the filling method of redundant metal are shown in Figure 13(a), Figure 13(b), and Figure 13(c).
- Figure 13(c) 13(a) does not fill the inductor B with any redundant metal.
- Figure 13(b) fills the inductor B with redundant metal or bulk redundant metal according to the block array method.
- Inductor B is filled with strip-shaped redundant metal in a radial shape.
- the electromagnetic field simulation is carried out for these three cases. According to the calculation formula of the inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 14. .
- the maximum value of the quality factor Q of the inductor is 17.45 when no redundant metal is filled, and the maximum value of the quality factor Q of the inductor when the redundant metal is filled in the block array method is 15.82, which is lower than the ideal condition.
- the maximum value of the inductance quality factor Q is 16.92.
- the quality factor is only reduced by 3.0%.
- the quality factor is improved by 6.9%.
- the present invention can be applied not only to single-port inductors, but also to coupled inductors.
- Fig. 15(a), Fig. 15(b), Fig. 15(c) the 3D modeling and electromagnetic simulation under the above three different filling conditions were carried out for a coupled inductor with a turns ratio of 2:1.
- Fig. 15(a) shows that the coupled inductor is not filled with any redundant metal
- Fig. 15(b) shows that the coupled inductor is filled with redundant metal or bulk redundant metal according to the block array method.
- Fig. 15( c) is to fill the strip-shaped redundant metal in a radial shape for the coupled inductor; wherein the bulk array and the radial strip-shaped redundant metal are filled around the inductor to meet the requirements for the metal density of the process.
- the quality factor Q of the primary coil is obtained according to the calculation formula of the inductance quality factor Q above to obtain the relationship between the inductance quality factor and the frequency.
- the result is shown in Figure 16. It can be seen from Figure 16 that the maximum value of the quality factor Q of the primary coil when no redundant metal is filled is 19.86; when the redundant metal is filled in the block array mode, the maximum value of the quality factor Q of the primary coil is 15.89, which is lower than the ideal condition.
- the maximum value of the quality factor Q of the primary coil is 18.69, which is only 5.9% lower than the ideal condition, and Compared with the original block array filling method, the quality factor is improved by 17.6%.
- the relationship between the quality factor Q of the secondary coil and the frequency is shown in Figure 17. It can be seen from Figure 17 that the maximum value of the quality factor Q of the secondary coil is 11.07 when no redundant metal is filled; The quality factor is reduced by 8.9%; and according to the method for filling strip-shaped redundant metal in a radial shape proposed in an embodiment of the present invention, the maximum value of the quality factor Q of the secondary coil is 10.81. Compared with the ideal situation, the quality factor is only reduced. 2.3%, and compared with the original uniform block array filling method, the quality factor is improved by 7.2%.
- the present invention can effectively prevent the reduction of the inductance quality factor due to the addition of redundant metals; in the case of satisfying the metal density required by the process, the redundant metal filling scheme proposed by the present invention obtains Compared with the general redundant metal filling method, the quality factor of the inductor is improved by about 7%, and the present invention can also be applied to coupled inductors.
- a filling technology of placing radial strips of metal perpendicular to the direction of the induced electric field is proposed; This technology alleviates the problem that the allowable area of the INDDMY layer in the design of analog and RF circuits is not enough for design due to process limitations. Simulations show that this technique not only meets the metal density required by the process, but also cuts off the induced current path and avoids metal filling inside the inductor coil without using the INDDMY layer to ignore the metal density check.
- the electromagnetic full-wave simulation shows that, compared with the conventional method of uniformly filling the redundant metal of the block array, this technology can effectively reduce the loss caused by the redundant metal to the inductor, which is extremely beneficial for the design of high-Q single-port inductors and coupled inductors. .
- any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CD to ROM, DVD, Blu Ray disks, etc.), flash memory, and/or the like .
- These computer program instructions may be loaded on a general purpose computer, special purpose computer or other programmable data processing apparatus to form a machine, such that the instructions executed on the computer or other programmable data processing apparatus may generate means for carrying out the specified functions.
- These computer program instructions may also be stored in a computer-readable memory that instructs a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable memory form a piece of Articles of manufacture, including implementing means for implementing specified functions.
- Computer program instructions may also be loaded on a computer or other programmable data processing device to perform a series of operational steps on the computer or other programmable device to produce a computer-implemented process such that a process executed on the computer or other programmable device Instructions may provide steps for implementing specified functions.
- the term “comprising” and any other variations thereof are non-exclusive inclusion, such that a process, method, article or device including a list of elements includes not only those elements, but also not expressly listed or included in the process , method, system, article or other elements of a device.
- the term “coupled” and any other variations thereof refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A chip manufacturing method, a redundant metal filling method, a chip and a computer readable storage medium. One or more bar-shaped redundant metals (12) are arranged outside an inductive device (11) of a metal layer. Furthermore, the bar-shaped redundant metals (12) are not parallel to the coil direction of the inductive device (11), and the bar-shaped redundant metals (12) are perpendicular to the coil direction of the inductive device (11). Compared with the traditional redundant metal filling technology aiming at an inductor device area, the present invention can effectively improve the quality factor of an inductor.
Description
本发明涉及一种芯片的制造方法、冗余金属的填充方法和芯片。The invention relates to a method for manufacturing a chip, a method for filling redundant metal and a chip.
冗余金属填充(Dummy Fill)是集成电路(Integrated Circuit,IC)制造中所应用的改善表面平坦化的技术;具体地,集成电路制造过程中借助冗余金属来提高版图密度的均匀性,改善集成电路的芯片在化学机械研磨(Chemical Mechanical Polishing,CMP)后表面的平坦性,进而提高产品的可靠性和良率。集成电路制造技术按照摩尔定律以每18个月集成度提高一倍的速度发展,但当集成电路的特征尺寸降到例如90纳米以下的时候,集成电路制造技术遇到了空前的挑战,表面不平坦性已经严重影响到了器件的性能和稳定性,冗余金属填充已经成为不可或缺的步骤。Redundant metal filling (Dummy Fill) is a technology used in the manufacture of integrated circuits (Integrated Circuit, IC) to improve surface planarization; The flatness of the surface of the chip of the integrated circuit after chemical mechanical polishing (CMP), thereby improving the reliability and yield of the product. The integrated circuit manufacturing technology develops at a rate of doubling the integration level every 18 months according to Moore's Law, but when the feature size of integrated circuits falls below, for example, 90 nanometers, the integrated circuit manufacturing technology encounters unprecedented challenges, and the surface is not flat. The performance and stability of the device have been seriously affected by the stability of the device, and redundant metal filling has become an indispensable step.
因此在版图设计中,需要填充冗余金属来满足生产工艺对芯片各金属层的金属密度的要求。然而冗余金属的填充会引入其他问题。Therefore, in the layout design, redundant metal needs to be filled to meet the requirements of the production process for the metal density of each metal layer of the chip. Filling of redundant metal, however, introduces other problems.
发明内容SUMMARY OF THE INVENTION
本发明提供一种芯片的制造方法、冗余金属的填充方法和芯片,以解决冗余金属的填充所引入的若干问题中一个或多个。The present invention provides a method for manufacturing a chip, a method for filling redundant metal, and a chip to solve one or more of several problems introduced by the filling of redundant metal.
根据第一方面,一种实施例中提供一种芯片的制造方法,包括:According to a first aspect, an embodiment provides a method for manufacturing a chip, including:
对硅片进行清洗并烘干;Clean and dry the silicon wafer;
对清洗完的硅片进行氧化;Oxidize the cleaned silicon wafer;
对氧化完成的硅片根据掩模版上电路设计进行阱区光刻;Perform well region lithography on the oxidized silicon wafer according to the circuit design on the mask;
光刻完成后对硅片进行湿法刻蚀去除二氧化硅,形成阱区注入孔;After the photolithography is completed, the silicon wafer is wet-etched to remove silicon dioxide to form a well region injection hole;
对硅片进行离子注入,形成阱;Ion implantation is performed on the silicon wafer to form a well;
对离子注入完成的硅片进行快速热退火;Rapid thermal annealing of ion implanted silicon wafers;
采用浅槽隔离工艺进行隔离;Isolation by shallow trench isolation process;
对硅片进行氧化,氧化完成后沉积多晶硅,根据掩模版上电路设计进行有源区光刻;Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area lithography according to the circuit design on the mask;
光刻完成后采用干法刻蚀去除多晶硅,形成栅极和有源区注入孔;After the photolithography is completed, the polysilicon is removed by dry etching to form the gate and the injection hole in the active region;
对硅片进行离子注入,形成源极漏极;Ion implantation is performed on the silicon wafer to form source and drain;
对离子注入完成的硅片进行快速热退火;Rapid thermal annealing of ion implanted silicon wafers;
利用化学气相沉积工艺在硅片表面形成硼磷硅玻璃,根据掩模版上电路设计进行通孔光刻;Borophosphosilicate glass is formed on the surface of the silicon wafer by chemical vapor deposition process, and through-hole lithography is carried out according to the circuit design on the mask;
光刻完成后通过干法刻蚀去除硼磷硅玻璃,并利用物理气相沉积工艺沉积通孔金属;After the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by the physical vapor deposition process;
利用物理气相沉积工艺在硅片表面形成金属层;其中所述金属层是按照预设规则被填充有冗余金属,所述预设规则包括:在金属层的电感器件的外部一根或多根 条形冗余金属;A metal layer is formed on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: one or more wires outside the inductor device of the metal layer Strip redundant metal;
对填充了冗余金属的金属层进行化学机械研磨,以使之平坦化;chemical mechanical polishing of the metal layer filled with redundant metal to planarize it;
对硅片进行测试和封装。Silicon wafers are tested and packaged.
一实施例中,所述条形冗余金属与电感器件的线圈方向不平行。In one embodiment, the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
一实施例中,所述条形冗余金属与电感器件的线圈方向垂直。In one embodiment, the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
根据第二方面,一种实施例中提供一种根据本文任一实施例所述的制造方法所制造的芯片。According to a second aspect, an embodiment provides a chip manufactured according to the manufacturing method described in any of the embodiments herein.
根据第三方面,一种实施例中提供一种冗余金属的填充方法,包括:According to a third aspect, an embodiment provides a method for filling redundant metal, including:
获取待填充的集成电路版图,其中所述集成电路版图包括一个或多个金属层;obtaining an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers;
至少对于其中一个金属层,按照预设规则填充冗余金属;其中所述预设规则包括:识别所述待填充的金属层所存在的电感器件,并在所述电感器件的外部填充一根或多根条形冗余金属。At least one of the metal layers is filled with redundant metal according to a preset rule; wherein the preset rule includes: identifying the inductance device existing in the metal layer to be filled, and filling one or Multiple strips of redundant metal.
一实施例中,所述条形冗余金属与电感器件的线圈方向不平行。In one embodiment, the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
一实施例中,所述条形冗余金属与电感器件的线圈方向垂直。In one embodiment, the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
根据第四方面,一种实施例中提供一种根据本文任一实施例所述的的填充方法而制造的芯片。According to a fourth aspect, an embodiment provides a chip fabricated according to the filling method described in any of the embodiments herein.
根据第五方面,一种实施例中提供一种集成电路的芯片,包括一个或多个金属层,其中至少有一个金属层设有电感器件,并在所述电感器件的外部填充有一根或多根条形冗余金属。According to a fifth aspect, an embodiment provides an integrated circuit chip, comprising one or more metal layers, wherein at least one metal layer is provided with an inductance device, and one or more metal layers are filled outside the inductance device Root strip redundant metal.
一实施例中,所述条形冗余金属与电感器件的线圈方向不平行。In one embodiment, the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
一实施例中,所述条形冗余金属与电感器件的线圈方向垂直。In one embodiment, the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
根据第六方面,一种实施例提供一种计算机可读存储介质,所述计算机可读存储介质存储有程序,所述程序能够被处理器执行以实现本文任一实施例所述的方法。According to a sixth aspect, an embodiment provides a computer-readable storage medium, the computer-readable storage medium stores a program, and the program can be executed by a processor to implement the method described in any of the embodiments herein.
图1为金属块状阵列的一个示意图;Fig. 1 is a schematic diagram of a metal block array;
图2为在电感的外部和内部以金属块状阵列方式填充冗余金属的示意图;Fig. 2 is the schematic diagram of filling redundant metal in the form of metal block array outside and inside the inductor;
图3为金属长条方式排布的一个示意图;Fig. 3 is a schematic diagram of metal strip arrangement;
图4为在电感的外部周围以金属长条方式排布并能够满足工艺对于金属密度要求的一个示意图;Fig. 4 is a schematic diagram of metal strips arranged around the outside of the inductor and can meet the requirements of the process for metal density;
图5为显示了电感产生的交变磁场会在外部的导体中产生与电感线圈平行的感应电流的方向的一个示意图;Fig. 5 is a schematic diagram showing the direction in which the alternating magnetic field generated by the inductance produces an induced current in the outer conductor parallel to the inductance coil;
图6为在电感外部周围填充的条形冗余金属,不沿着电感线圈或者说感应电流的方向摆放的一个示意图;Fig. 6 is a schematic diagram of the strip-shaped redundant metal filled around the outside of the inductor and not placed along the direction of the inductor coil or the induced current;
图7(a)和图7(b)为条形冗余金属的两个示意图;Figure 7(a) and Figure 7(b) are two schematic diagrams of strip-shaped redundant metal;
图8为一实施例的芯片的制造方法的流程图;8 is a flowchart of a method for manufacturing a chip according to an embodiment;
图9为一实施例的冗余金属的填充方法的流程图;FIG. 9 is a flowchart of a method for filling redundant metal according to an embodiment;
图10为一实施例的集电路的芯片的金属层的局部区域示意图;10 is a schematic diagram of a partial area of a metal layer of a chip of a collector circuit according to an embodiment;
图11(a)是对电感A不填充任何冗余金属的示意图,图11(b)是按照块状 阵列方式对电感A填充冗余金属或者说是填充块状冗余金属的示意图,图11(c)是对电感A以辐射状填充条形冗余金属的示意图;图12为针对这三种情况相应的仿真结果;Figure 11(a) is a schematic diagram of inductor A without any redundant metal filling, Figure 11(b) is a schematic diagram of filling inductor A with redundant metal or bulk redundant metal in a block array manner, Figure 11 (c) is a schematic diagram of radially filling the strip-shaped redundant metal for the inductor A; Figure 12 shows the corresponding simulation results for these three cases;
图13(a)是对电感B不填充任何冗余金属,图13(b)是按照块状阵列方式对电感B填充冗余金属或者说是填充块状冗余金属,图13(c)是对电感B以辐射状填充条形冗余金属;图14为针对这三种情况相应的仿真结果;Figure 13(a) shows that inductor B is not filled with any redundant metal. Figure 13(b) shows that inductor B is filled with redundant metal or bulk redundant metal according to the block array method. Figure 13(c) is a Fill the strip-shaped redundant metal radially for the inductor B; Figure 14 shows the corresponding simulation results for these three cases;
图15(a)是对耦合电感不填充任何冗余金属,图15(b)是按照块状阵列方式对耦合电感填充冗余金属或者说是填充块状冗余金属,图15(c)是对耦合电感以辐射状填充条形冗余金属;图16为针对这三种情况初级线圈品质因数的相应仿真结果,图17为针对这三种情况次级线圈品质因数的相应仿真结果。Figure 15(a) shows that the coupled inductors are not filled with any redundant metal. Figure 15(b) shows that the coupled inductors are filled with redundant metal or bulk redundant metal according to the block array method. Figure 15(c) is a The coupled inductors are radially filled with strips of redundant metal; Figure 16 shows the corresponding simulation results for the primary coil quality factor for these three cases, and Figure 17 shows the corresponding simulation results for the secondary coil quality factor for these three cases.
下面通过具体实施方式结合附图对本发明作进一步详细说明。其中不同实施方式中类似元件采用了相关联的类似的元件标号。在以下的实施方式中,很多细节描述是为了使得本申请能被更好的理解。然而,本领域技术人员可以毫不费力的认识到,其中部分特征在不同情况下是可以省略的,或者可以由其他元件、材料、方法所替代。在某些情况下,本申请相关的一些操作并没有在说明书中显示或者描述,这是为了避免本申请的核心部分被过多的描述所淹没,而对于本领域技术人员而言,详细描述这些相关操作并不是必要的,他们根据说明书中的描述以及本领域的一般技术知识即可完整了解相关操作。The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments have used associated similar element numbers. In the following embodiments, many details are described so that the present application can be better understood. However, those skilled in the art will readily recognize that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application from being overwhelmed by excessive description, and for those skilled in the art, these are described in detail. The relevant operations are not necessary, and they can fully understand the relevant operations according to the descriptions in the specification and general technical knowledge in the field.
另外,说明书中所描述的特点、操作或者特征可以以任意适当的方式结合形成各种实施方式。同时,方法描述中的各步骤或者动作也可以按照本领域技术人员所能显而易见的方式进行顺序调换或调整。因此,说明书和附图中的各种顺序只是为了清楚描述某一个实施例,并不意味着是必须的顺序,除非另有说明其中某个顺序是必须遵循的。Additionally, the features, acts, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in order in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary order unless otherwise stated, a certain order must be followed.
本文中为部件所编序号本身,例如“第一”、“第二”等,仅用于区分所描述的对象,不具有任何顺序或技术含义。而本申请所说“连接”、“联接”,如无特别说明,均包括直接和间接连接(联接)。The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).
如背景技术中所述,在芯片实际生产过程中,工艺要求各金属层填充冗余金属以保证表面化学机械抛光后的平坦度从而获得更高的良率;然而冗余金属的填充也会向芯片引入电路设计时想要避免的一些问题,例如冗余金属的填充也会向芯片引入电路设计时想要避免的寄生电容,这些寄生电容增加了信号延迟、干扰噪声和能量损耗;针对如何以合适的方式填充冗余金属以减少寄生效应对电路的干扰的效果,也成为了集成电路版图设计中所需要考虑的一部分;例如公开号为CN102456080A的中国专利就提出一种减少寄生电容的冗余金属填充。As described in the background art, in the actual production process of the chip, the process requires each metal layer to be filled with redundant metal to ensure the flatness of the surface after chemical mechanical polishing to obtain a higher yield; however, the filling of the redundant metal will also increase the Some problems that you want to avoid when the chip is introduced into the circuit design, such as the filling of the redundant metal will also introduce the parasitic capacitance that you want to avoid when the circuit design is introduced into the chip. These parasitic capacitances increase the signal delay, interference noise and energy loss; The effect of filling redundant metal in a suitable way to reduce the interference of parasitic effects on the circuit has also become a part of the integrated circuit layout design; for example, the Chinese patent publication number CN102456080A proposes a redundancy that reduces parasitic capacitance Metal filled.
现有技术对冗余金属填充所带来的寄生电容研究比较多,然后冗余金属也会对电磁场产生干扰,导致集成电路中电感的品质因数降低。具体地,在集成电路的芯片尤其是射频芯片中,会存在高频器件例如电感等,这些高频器件一般而言其图形密度非常低,因此普遍需要在这些区域进行冗余金属的填充。In the prior art, there are many studies on the parasitic capacitance caused by the redundant metal filling, and then the redundant metal also interferes with the electromagnetic field, resulting in a decrease in the quality factor of the inductance in the integrated circuit. Specifically, in an integrated circuit chip, especially a radio frequency chip, there are high-frequency devices such as inductors. Generally speaking, the pattern density of these high-frequency devices is very low. Therefore, redundant metal filling is generally required in these areas.
针对冗余金属填充所带来的问题,芯片制造厂商考虑到电路设计的实际需求也提供了一种避免填充冗余金属的方法——在版图设计过程中使用INDDMY层;具体地,通过在设计软件中用INDDMY层框选所需区域,被框选的区域则不会被进行金属密度的检查,从而也不需要添加冗余金属;制造工艺中提供的电感模型一般自带INDDMY层,此外,设计者也可对自己设计的电感手动添加INDDMY层,以跳过金属密度检查。这样的优势是可以避免在电感的周围放置冗余金属,防止因为冗余金属对电感周围磁场的干扰而导致电感品质因数的下降;但是可以理解地,INDDMY层只是软件上所虚拟的结构层,在实际生产的物理过程中不存在的,INDDMY层的作用是人为地使得被框选的区域跳过金属密度的检查,因此自然也不会进一步再考虑在该区域填充冗余金属来满足金属密度的检查了。由于INDDMY层的作用只是人为地使得被框选的区域跳过金属密度的检查,因此受于生产工艺的限制,INDDMY层所占据的面积相对于芯片整体面积必须小于一定比例,这样才能保证实际生产过程中芯片各金属层的平坦性。在一般的数字芯片设计中,如果几乎不使用电感,那么工艺规定的INDDMY层占总芯片面积的比例足够设计者使用。但是,由于在模拟和射频电路中电感被广泛使用,因此在这类芯片设计中,如果每个电感都通过使用INDMMY层来避免周围填充冗余金属,那么INDMMY层占总芯片面积的比例则往往会超过工艺的限制。因此,在版图中如何以恰当的方式用冗余金属填充电感周围,在满足金属密度的情况下,尽量减少冗余金属对电感品质因数的损耗仍然是一个需要考虑和值得研究的问题。In view of the problems caused by redundant metal filling, chip manufacturers have also provided a method to avoid filling redundant metal in consideration of the actual needs of circuit design - using the INDDMY layer in the layout design process; In the software, use the INDDMY layer to frame the desired area, and the frame-selected area will not be checked for metal density, so there is no need to add redundant metals; the inductance model provided in the manufacturing process generally comes with the INDDMY layer. In addition, Designers can also manually add INDDMY layers to their designed inductors to skip metal density checks. The advantage of this is that it can avoid placing redundant metal around the inductor, and prevent the quality factor of the inductor from decreasing due to the interference of the redundant metal to the magnetic field around the inductor; but understandably, the INDDMY layer is only a virtual structural layer on the software. It does not exist in the physical process of actual production. The role of the INDDMY layer is to artificially make the selected area skip the metal density check, so naturally it will not further consider filling this area with redundant metal to meet the metal density. 's checked. Since the function of the INDDMY layer is to artificially make the area selected by the frame skip the metal density check, due to the limitation of the production process, the area occupied by the INDDMY layer must be less than a certain proportion relative to the overall chip area, so as to ensure the actual production. The flatness of each metal layer of the chip during the process. In the general digital chip design, if the inductor is hardly used, the proportion of the INDDMY layer to the total chip area specified by the process is sufficient for the designer to use. However, due to the widespread use of inductors in analog and RF circuits, in these chip designs, if each inductor avoids redundant metal surrounding by using an INDMMY layer, the proportion of the INDMMY layer to the total chip area tends to be smaller Process limits will be exceeded. Therefore, how to fill the inductor with redundant metal in an appropriate way in the layout, and to minimize the loss of the redundant metal to the inductor quality factor under the condition of satisfying the metal density, is still a problem that needs to be considered and worth studying.
在说明本申请的方案之前,先对电感品质因数及电感损耗进行说明。Before describing the solution of the present application, the inductance quality factor and inductance loss will be described first.
电感的品质因数(Quality factor)一般可以以符号Q代表;电感的品质因数Q在各种模拟射频电路中都起着关键的作用,例如振荡器的相位噪声与1/Q
2成正比,再例如调谐放大器的电压增益和Q成正比,此外电感的品质因数Q往往限制了电路的性能,比如振荡器的FoM(figure of merit,品质因数)的最高值就受该工艺下电感最高品质因数的限制。
The quality factor of the inductor can generally be represented by the symbol Q; the quality factor Q of the inductor plays a key role in various analog RF circuits. For example, the phase noise of the oscillator is proportional to 1/Q 2 , and for example The voltage gain of the tuned amplifier is proportional to Q. In addition, the quality factor Q of the inductor often limits the performance of the circuit. For example, the highest value of the FoM (figure of merit) of the oscillator is limited by the highest quality factor of the inductor under this process. .
因此,电感的品质因数Q是一个非常重要的概念;本领技术人员通过电感的品质因数Q来量化电感的损耗水平,电感的品质因数Q定义为系统的最大储能值与系统在一个周期内的能量损耗的比值。因此影响Q值的一个关键因素就是电流流过电感时能量损耗的多少,而电感的损耗主要来源于电感金属结构本身以及周围空间呈现的等效电阻。根据电感的品质因数Q的定义,若电感量为L,等效串联电阻为R
s,工作频率为ω,则其Q值有如下表达式:
Therefore, the quality factor Q of the inductor is a very important concept; those skilled in the art quantify the loss level of the inductor through the quality factor Q of the inductor. The quality factor Q of the inductor is defined as the maximum energy storage value of the system and the system in one cycle. Ratio of energy loss. Therefore, a key factor affecting the Q value is the amount of energy loss when the current flows through the inductor, and the loss of the inductor mainly comes from the metal structure of the inductor itself and the equivalent resistance presented by the surrounding space. According to the definition of the quality factor Q of the inductance, if the inductance is L, the equivalent series resistance is R s , and the operating frequency is ω, the Q value has the following expression:
Q=Lω/R
s;
Q=Lω/R s ;
在其他条件一定的情况下,电感总体损耗越大,意味着其等效串联电阻R
s越大,以下将会介绍几种造成电感损耗的机制——具体地,为金属欧姆损耗和介质损耗。
Under certain other conditions, the greater the overall loss of the inductor, the greater the equivalent series resistance R s . The following will introduce several mechanisms that cause the loss of the inductor—specifically, metal ohmic loss and dielectric loss.
(1)金属欧姆损耗(1) Metal ohmic loss
由于用于制作电感的金属本身电导率有限,电流流过金属时将有一部分能量以热量形式散失,这部分损耗称为金属线的欧姆损耗。从上文的Q值的表达式中我们可以得到,对于给定的电感,可以通过降低电感的金属电阻来提高品质因数。一般来说可以通过增加电感的宽度来降低等效电阻;不过更宽的金属线虽然会表现出更 低的电阻,但另一方面也会相对于衬底有着更大的寄生电容,而这将会降低电感的自谐振频率。因此设计者在实际电路设计中往往需要在Q值和寄生电容之间权衡。Due to the limited conductivity of the metal used to make the inductor itself, a part of the energy will be dissipated in the form of heat when the current flows through the metal. This part of the loss is called the ohmic loss of the metal wire. From the expression for the Q value above, we can see that for a given inductance, the figure of merit can be improved by reducing the metal resistance of the inductance. In general, the equivalent resistance can be reduced by increasing the width of the inductor; however, a wider metal line will show lower resistance, but on the other hand, it will also have a larger parasitic capacitance relative to the substrate, which will will reduce the self-resonant frequency of the inductor. Therefore, designers often need to trade off between the Q value and the parasitic capacitance in the actual circuit design.
在高频时,电感内的电流分量趋向于相互排斥,从而逐渐远离,最终电流会趋向于在金属表面流动,这种现象被称之为趋肤效应。电流的实际分布从金属的表面向内遵循一个指数衰减:At high frequencies, the current components in the inductor tend to repel each other and move away from each other, and eventually the current tends to flow on the metal surface, a phenomenon known as the skin effect. The actual distribution of the current follows an exponential decay from the surface of the metal inwards:
J(s)=J
0exp(-x/δ);
J(s)=J 0 exp(-x/δ);
其中J
0为表面的电流密度,δ是趋肤深度,δ的值由下式给出:
where J0 is the current density at the surface, δ is the skin depth, and the value of δ is given by:
其中f表示频率,μ是磁导率,σ是电导率。where f is the frequency, μ is the magnetic permeability, and σ is the electrical conductivity.
由于高频时较小的趋肤深度导致电流流过的等效横截面积减小,这进一步增加了其等效电阻从增加了欧姆损耗。Due to the smaller skin depth at high frequencies, the equivalent cross-sectional area through which the current flows is reduced, which further increases its equivalent resistance from increasing ohmic losses.
(2)介质损耗(2) Dielectric loss
由于电感和衬底之间存在电容,因此当电感各个部分的电压随着时间发生变化的时候,发散的电场穿过衬底和各层金属之间的介质层,形成位移电流。因为衬底的电阻率非理想情况,这就不可避免的在每次电压变化的周期内,流经衬底的电流都有一部分会被转换成损耗。电场穿过这些介质时产生的损耗称为介质损耗,这会进一步降低电感的品质因数。Due to the capacitance between the inductor and the substrate, when the voltage of each part of the inductor changes with time, the divergent electric field passes through the dielectric layer between the substrate and each layer of metal to form a displacement current. Because the resistivity of the substrate is not ideal, it is unavoidable that a portion of the current flowing through the substrate will be converted into losses during each cycle of voltage change. The loss that occurs when the electric field passes through these media is called dielectric loss, which further reduces the quality factor of the inductor.
研究和理解电感的品质因素Q及金属欧姆损耗、介质损耗,对于理解现有技术的不足和本申请的改进方案有重要作用,下面对现有冗余金属填充技术和本申请的改进方案进行说明。Studying and understanding the quality factor Q of the inductor, metal ohmic loss, and dielectric loss play an important role in understanding the deficiencies of the prior art and the improvement scheme of the present application. The following is a description of the existing redundant metal filling technology and the improvement scheme of the present application. illustrate.
集成电路的版图设计过程中,目前是以金属块状阵列的方式来进行冗余金属的填充,图1是金属块状阵列的一个例子;由于冗余金属在工艺的限制下有着金属间间距的限制,这使得以金属块状阵列方式填充冗余金属时,仅仅在电感的外部填充冗余金属并不能很好地满足工艺对于金属密度的要求,往往还需要在电感的内部也填充冗余金属,图2是在电感或者说电感器件的外部和内部以金属块状阵列方式填充冗余金属的一个例子。In the layout design process of the integrated circuit, the redundant metal is currently filled in the form of a metal block array. Figure 1 is an example of a metal block array; due to the limitation of the process, the redundant metal has inter-metal spacing. Limitation, which makes redundant metal filling in the form of metal block array, only filling the redundant metal outside the inductor can not well meet the requirements of the process for metal density, often it is also necessary to fill the redundant metal inside the inductor. , Fig. 2 is an example of filling redundant metals in the form of metal block arrays outside and inside an inductor or an inductor device.
考虑到上述情况,申请人提出以长条状金属来对电感的周围进行填充,金属长条方式排布后的金属密度是大于金属块状阵列的方式,因此这可以减少或者避免在电感内部也填充冗余金属。图3是金属长条方式排布的一个例子,图4是在电感的外部周围以金属长条方式排布并能够满足工艺对于金属密度要求的一个例子。Considering the above situation, the applicant proposes to use long strips of metal to fill the periphery of the inductor. The metal density after the metal strips is arranged is greater than that of the metal block array, so this can reduce or avoid the internal impact of the inductor. Fill redundant metal. FIG. 3 is an example of the arrangement in the form of metal strips, and FIG. 4 is an example of the arrangement in the form of metal strips around the outside of the inductor and can meet the requirements for metal density in the process.
下面对比这种金属填充方式。The following is a comparison of this metal filling method.
不妨令图1中冗余金属块的边长为1um,并且冗余金属块之间的间距也为1um为例,如果这种排布方式无限拓展下去,则冗余金属占据的空间密度为25%。而以图3为例,当长为9um、宽为1um的条形冗余金属或者说条状冗余金属以同样间距即1um摆放的时候,如果这种排布方式无限往下拓展下去,则冗余金属占据的空间密度为50%。可以看出后者的填充方式相比于前者,在同样面积的情况下,更容易满足工艺对金属密度的要求。Let the side length of the redundant metal blocks in Figure 1 be 1um, and the spacing between the redundant metal blocks is also 1um. %. Taking Figure 3 as an example, when strip-shaped redundant metals with a length of 9um and a width of 1um or strip-shaped redundant metals are placed at the same spacing, that is, 1um, if this arrangement goes down infinitely, The spatial density occupied by the redundant metal is then 50%. It can be seen that compared with the former, the latter filling method is easier to meet the requirements of the process for metal density in the case of the same area.
通过上面的分析可知,因为金属块阵列本身只占据25%的空间密度,较难在占 据较小面积的情况下满足工艺对金属最低密度的要求,因此以金属阵列填充冗余金属的方式往往需要更多的面积来满足工艺金属密度要求,比如需要在电感内部填充冗余金属;而由于电感内部磁通密度更大,因此电感内部的冗余金属在交变磁场下相较于电感外部周围的金属会产生更大的感应电流,将会更显著地降低电感的品质因数。It can be seen from the above analysis that because the metal block array itself only occupies 25% of the space density, it is difficult to meet the minimum metal density requirements of the process in the case of occupying a small area. Therefore, filling the redundant metal with the metal array often requires More area to meet the requirements of process metal density, such as the need to fill the redundant metal inside the inductor; and because the magnetic flux density inside the inductor is larger, the redundant metal inside the inductor is compared with the outside surrounding of the inductor under the alternating magnetic field. Metals will generate larger induced currents and will reduce the quality factor of the inductor more significantly.
在考虑到这一情况后,本申请对冗余金属的填充方式进行了改进,用条形冗余金属代替了块状冗余金属。冗余金属占据同一空间的情况下,条状冗余金属的空间密度远大于块状冗余金属,因此这就使得只需要在电感内部填充少量冗余金属,甚至不需要在电感内部填充冗余金属时,也能达到工艺对金属密度的要求。After considering this situation, the present application improves the filling method of the redundant metal, and replaces the bulk redundant metal with a strip redundant metal. When the redundant metal occupies the same space, the spatial density of the strip redundant metal is much larger than that of the bulk redundant metal, so this makes it only necessary to fill a small amount of redundant metal inside the inductor, and even does not need to fill the redundant metal inside the inductor. When using metal, it can also meet the requirements of the process for metal density.
通过以条形冗余金属代替了块状冗余金属,从而减少甚至避免了在电感内部这一磁通密度更大的区域进行冗余金属的填充,有效地提高了电感的品质因数。By replacing the block-shaped redundant metal with the strip-shaped redundant metal, the filling of the redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved.
进一步地,虽然电感外部的磁通密度小于电感内部的磁通密度,但是电感产生的交变磁场仍然会在外部的导体中产生与电感线圈平行的感应电流,这部分电流的欧姆损耗将会降低电感的品质因数——图5中的虚线显示了电感产生的交变磁场会在外部的导体中产生与电感线圈平行的感应电流的方向。考虑到这种情况下,在电感外部填充的条形冗余金属,不沿着电感线圈或者说感应电流的方向摆放,这可以进一步降低感应电流在填充金属中的损耗,例如图6就是一个例子;更进一步地,当条形冗余金属沿着垂直电感的线圈或者说感应电流方向摆放的时候,条带间的空隙切断了电流的流动路径,这又能够进一步显著降低感应电流在金属中的损耗,上文中图4就是这样的一个例子。Further, although the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced. The quality factor of the inductor - the dashed line in Figure 5 shows the direction in which the alternating magnetic field generated by the inductor will induce a current in the outer conductor parallel to the inductor coil. Considering this situation, the strip-shaped redundant metal filled outside the inductor is not placed along the direction of the inductor coil or the induced current, which can further reduce the loss of the induced current in the filler metal. For example, Figure 6 is a Example; further, when the strip-shaped redundant metal is placed along the vertical inductor coil or the direction of the induced current, the gap between the strips cuts off the current flow path, which can further significantly reduce the induced current in the metal. The loss in , Figure 4 above is such an example.
因此,一些实施例中,本专利提出通过在电感的外部填充条形冗余金属,在满足金属密度的同时,减少因冗余金属的填充对电感品质因数的影响,进一步地,条形冗余金属以垂直于电感产生的感应电流的方向,呈辐射状摆放在电感外部周围以尽可能降低电流的欧姆损耗,从而进一步减少因冗余金属的填充对电感品质因数的影响。Therefore, in some embodiments, the present patent proposes to fill the outside of the inductor with strip-shaped redundant metal, so as to meet the metal density and reduce the influence on the quality factor of the inductor due to the filling of the redundant metal. Further, the strip-shaped redundancy The metal is placed radially around the outside of the inductor in the direction perpendicular to the induced current generated by the inductor to reduce the ohmic loss of the current as much as possible, thereby further reducing the influence of the redundant metal filling on the quality factor of the inductor.
需要说明的是,本发明的条形冗余金属中,“条形”是用于限定冗余金属整体呈条形或者说条状,这种形状可以是如图7(a)中的矩形,如图7(b)中两头是弧形例如半圆的形状。本发明在讨论条形冗余金属摆放的方向时,是以条形冗余金属的长轴方向来定义的,例如条形冗余金属与电感线圈或感应电流方向垂直,是指条形冗余金属的长轴方向与电感线圈或感应电流方向垂直。在填充条形冗余金属时,条形冗余金属的具体尺寸和数量,这可以根据金属密度要求等来确定。It should be noted that, in the strip-shaped redundant metal of the present invention, the "strip shape" is used to define that the redundant metal is in the shape of a strip or a strip as a whole, and this shape can be a rectangle as shown in Figure 7(a), As shown in Fig. 7(b), both ends are arc-shaped, such as semi-circular shapes. When discussing the direction of the strip-shaped redundant metal arrangement in the present invention, it is defined by the long axis direction of the strip-shaped redundant metal. The long axis direction of the residual metal is perpendicular to the direction of the inductor coil or the induced current. When the strip-shaped redundant metal is filled, the specific size and quantity of the strip-shaped redundant metal can be determined according to metal density requirements and the like.
本发明一些实施例中公开了一种芯片的制造方法。芯片是集成电路的载体,芯片的制造方法是将电路小型化并制造在半导体晶圆表面上的一种方法;具体地,一般是使用硅晶圆用作基层,然后使用光刻、掺杂、CMP等工艺技术制成MOSFET或BJT等组件,再利用薄膜和CMP等工艺制成导线,从而完成芯片的制作。芯片制作完整过程包括芯片设计、晶片制作、封装制作和测试等几个环节,其中晶片制作过程尤为复杂。Some embodiments of the present invention disclose a method for manufacturing a chip. The chip is the carrier of the integrated circuit, and the manufacturing method of the chip is a method of miniaturizing the circuit and manufacturing it on the surface of the semiconductor wafer; CMP and other process technologies are used to make components such as MOSFETs or BJTs, and then thin-film and CMP processes are used to make wires to complete the production of chips. The complete process of chip fabrication includes several links such as chip design, wafer fabrication, packaging fabrication and testing, among which the wafer fabrication process is particularly complex.
请参照图8,一些实施例的芯片的制造方法包括以下步骤:Referring to FIG. 8 , a method for manufacturing a chip according to some embodiments includes the following steps:
步骤101:对硅片进行清洗并烘干。Step 101 : cleaning and drying the silicon wafer.
在制造工艺过程中,首先要对硅晶圆或者说硅片进行清洗,以去除其表面的各种杂质。各种半导体器件一般是通过在硅片中掺入适当的杂质(通常掺杂浓度在百万分之一的水平)、在硅片表面沉积合适的薄膜并光刻、刻蚀出特定的图形等一系 列工艺步骤制造出来的,因此只有将各种无关杂质的玷污水平控制在不影响器件特性和芯片成品率的提前下,才能使上述这些工艺步骤真正具备实际的可生产性。在实际的应用中,这就要求我们必须将各种无关杂质的浓度控制在百万分一以下,甚至十亿分之一的水平上,同时还必须有效地去除各种杂散颗粒的影响。During the manufacturing process, the silicon wafer or silicon wafer is first cleaned to remove various impurities on its surface. Various semiconductor devices are generally made by doping appropriate impurities in the silicon wafer (usually the doping concentration is at the level of one millionth), depositing a suitable thin film on the surface of the silicon wafer, photolithography, etching specific patterns, etc. It is manufactured by a series of process steps, so only when the contamination level of various unrelated impurities is controlled in advance without affecting the device characteristics and chip yield, can the above-mentioned process steps be truly producible. In practical applications, this requires us to control the concentration of various irrelevant impurities below one part per million, or even one part per billion, and at the same time, we must effectively remove the influence of various stray particles.
可以理解地,在图8所示的其他的每个步骤结束时,都可以再进行清洗和烘干。It can be understood that at the end of each of the other steps shown in FIG. 8 , washing and drying can be performed again.
可以理解地,在开始制造前还需要进行一些前期的准备工作,例如根据设计电路需要选择硅片规格和掺杂离子类型等。It is understandable that some preliminary preparations need to be done before starting to manufacture, such as selecting silicon wafer specifications and doping ion types according to the needs of designing circuits.
步骤103:对清洗完的硅片进行氧化。Step 103: Oxidize the cleaned silicon wafer.
在芯片制造过程中,通过氧化剂及逐步升温的条件,在光洁的硅片表面生产二氧化硅,这个工艺可以称之为氧化或热氧化。在整个芯片制造过程中,对硅片进行氧化所形成的二氧化硅有许多作用,例如表面钝化、掺杂阻挡层、表面绝缘体和器件绝缘体,表面钝化的作用是指通过在硅片表面形成密度非常高的二氧化硅,可以保护器件的表面及内部;掺杂阻挡层的作用是指二氧化硅能够形成阻挡保护层,防止掺杂物入侵硅面;表面绝缘体的作用是指二氧化硅这一氧化层可使相邻的上下金属层之间不短路,同时足够厚的氧化层还可以用来防止从金属去产生的感应,即场氧化物;器件绝缘体的作用是指氧化层能够起到介电质的功能,可以让氧化层下面的栅电极产生感应电流。In the chip manufacturing process, silicon dioxide is produced on the surface of a smooth silicon wafer by an oxidizing agent and a gradual temperature rise. This process can be called oxidation or thermal oxidation. In the entire chip manufacturing process, silicon dioxide formed by oxidizing silicon wafers has many functions, such as surface passivation, doping barrier layer, surface insulator and device insulator. The formation of very high-density silicon dioxide can protect the surface and interior of the device; the role of the doping barrier layer means that silicon dioxide can form a blocking protective layer to prevent dopants from invading the silicon surface; the role of the surface insulator refers to the role of the dioxide The oxide layer of silicon can prevent short circuits between adjacent upper and lower metal layers, and at the same time, a sufficiently thick oxide layer can also be used to prevent induction from the metal, that is, field oxide; the role of the device insulator is that the oxide layer can It acts as a dielectric and can induce an induced current in the gate electrode under the oxide layer.
步骤105:对氧化完成的硅片根据掩模版上电路设计进行阱区光刻。Step 105 : performing well region lithography on the oxidized silicon wafer according to the circuit design on the mask.
光刻是现代IC制造业的基石,它能在硅片衬氏上印制出亚微米尺寸的图形。光刻的原理是将光敏感的光刻胶旋涂到硅片上,在表面形成一层薄膜,然后使用光刻版,版上包含着所要制作的特定层的图形信息——这也即步骤110所涉及的掩模,光源透过光刻版照射到光刻胶上,使得光刻胶选择地曝光;接着对光刻胶显影,于是就完成了从版到硅片的图形转移。光刻胶接下来,可以刻蚀其下面薄膜层的步骤中,或者在离子注入掺杂的步骤中,用做掩蔽膜。Lithography is the cornerstone of modern IC manufacturing, capable of printing sub-micron-sized patterns on silicon wafers. The principle of lithography is to spin-coat a light-sensitive photoresist onto a silicon wafer, form a thin film on the surface, and then use a lithography plate, which contains the graphic information of the specific layer to be made - this is the step For the mask involved in 110, the light source irradiates the photoresist through the photoresist, so that the photoresist is selectively exposed; then the photoresist is developed, and the pattern transfer from the plate to the silicon wafer is completed. Next, the photoresist can be used as a masking film in the step of etching the underlying thin film layer, or in the step of ion implantation and doping.
步骤107:光刻完成后对硅片进行湿法刻蚀去除二氧化硅,形成阱区注入孔。Step 107 : after the photolithography is completed, wet etching is performed on the silicon wafer to remove silicon dioxide to form a well region injection hole.
湿法刻蚀是一种刻蚀方法,是将刻蚀材料浸泡在腐蚀液内进行腐蚀的技术,它是一种纯化学刻蚀,具有优良的选择性,刻蚀完当前薄膜就会停止,而不会损坏下面一层其他材料的薄膜。Wet etching is an etching method. It is a technique of immersing the etching material in an etching solution for etching. It is a pure chemical etching with excellent selectivity. After etching the current film, it will stop. without damaging the underlying film of other materials.
步骤109:对硅片进行离子注入,形成阱。Step 109: Perform ion implantation on the silicon wafer to form a well.
离子注入是一项将离子分选、加速和剂量测量结合在一起,从而将精确的杂质原子引入硅衬底的技术,它提供了一种非常精确的、向硅中掺入特定杂质原子剂量或数量的方法。Ion implantation is a technique that combines ion sorting, acceleration, and dose measurement to introduce precise impurity atoms into a silicon substrate. quantity method.
步骤111:对离子注入完成的硅片进行快速热退火。Step 111 : performing rapid thermal annealing on the silicon wafer after ion implantation.
快速热退火(Rapid Thermal Annealing,RTA)是芯片制造工艺中的一种工艺,一般用来激活半导体材料中的掺杂元素和将由离子注入造成的非晶结构恢复为完整晶格结构。具体地,快速热退火工艺可以是将硅晶片从环境温度快速加热至约1000–1500K,硅晶片达到该温度后会保持几秒钟,然后完成淬火。Rapid Thermal Annealing (RTA) is a process in the chip manufacturing process, which is generally used to activate doping elements in semiconductor materials and restore the amorphous structure caused by ion implantation to a complete lattice structure. Specifically, the rapid thermal annealing process may be to rapidly heat the silicon wafer from ambient temperature to about 1000-1500K, hold the silicon wafer at this temperature for a few seconds, and then complete the quenching.
步骤113:采用浅槽隔离工艺进行隔离。Step 113: use a shallow trench isolation process for isolation.
浅槽隔离(Shallow Trench Isolation,STI)是通过利用氮化硅掩膜经过淀 积、图形化、刻蚀硅后形成槽,并在槽中填充淀积氧化物,用于与硅隔离的一种工艺。Shallow Trench Isolation (STI) is to form a trench by depositing, patterning, and etching silicon using a silicon nitride mask, and filling the trench with a deposition oxide for isolation from silicon. craft.
步骤115:对硅片进行氧化,氧化完成后沉积多晶硅,根据掩模版上电路设计进行有源区光刻。Step 115: Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area photolithography according to the circuit design on the mask.
步骤117:光刻完成后采用干法刻蚀去除多晶硅,形成栅极和有源区注入孔。Step 117 : after the photolithography is completed, the polysilicon is removed by dry etching to form a gate electrode and an injection hole in the active region.
干法刻蚀是用等离子体进行薄膜刻蚀的技术。当气体以等离子体形式存在时,它具备两个特点:一方面等离子体中的这些气体化学活性比常态下时要强很多,根据被刻蚀材料的不同,选择合适的气体,就可以更快地与材料进行反应,实现刻蚀去除的目的;另一方面,还可以利用电场对等离子体进行引导和加速,使其具备一定能量,当其轰击被刻蚀物的表面时,会将被刻蚀物材料的原子击出,从而达到利用物理上的能量转移来实现刻蚀的目的。因此,干法刻蚀是晶圆片表面物理和化学两种过程平衡的结果。干法刻蚀可以分为三种:物理性刻蚀、化学性刻蚀、物理化学性刻蚀。Dry etching is a thin-film etching technique using plasma. When the gas exists in the form of plasma, it has two characteristics: on the one hand, the chemical activity of these gases in the plasma is much stronger than that in the normal state. Reacts with the material to achieve the purpose of etching and removal; on the other hand, the electric field can also be used to guide and accelerate the plasma, so that it has a certain energy. When it bombards the surface of the object to be etched, it will be etched. The atoms of the material are knocked out, so as to achieve the purpose of using physical energy transfer to achieve the purpose of etching. Therefore, dry etching is the result of a balance between the physical and chemical processes on the wafer surface. Dry etching can be divided into three types: physical etching, chemical etching, and physical-chemical etching.
步骤119:对硅片进行离子注入,形成源极漏极。Step 119: Perform ion implantation on the silicon wafer to form source and drain electrodes.
步骤121:对离子注入完成的硅片进行快速热退火。Step 121 : performing rapid thermal annealing on the silicon wafer after ion implantation.
步骤123:利用化学气相沉积工艺在硅片表面形成硼磷硅玻璃,根据掩模版上电路设计进行通孔(即引线孔)光刻。Step 123 : using a chemical vapor deposition process to form borophosphosilicate glass on the surface of the silicon wafer, and perform photolithography of through holes (ie, lead holes) according to the circuit design on the mask.
薄膜工艺是指在硅片表面形成所需要薄膜的加工工艺。这些特定薄膜包括绝缘体、半导体或导体。主要的薄膜技术包括化学气相沉积(Chemical Vapor Deposition,CVD)和物理气相沉积(Physical Vapor Deposition,PVD)等。集成电路制造中绝大部分的薄膜是通过CVD技术淀积的。CVD的原理是通过含有所需要的原子或者分子的化学成分,在反应腔体内混合并且在气态下发生反应,使得其原子或者分子淀积在硅片的表面,从而形成特定种类的薄膜。采用的化学反应一般分为高温分解,还原,氧化,氮化。高温分解是指仅仅依靠热量进行的化学反应。还原是分子、氢气的化学反应。氧化是原子、分子和氧气进行的化学反应。氮化主要是指在硅片表面形成一层氮化硅薄膜的化学反应。The thin film process refers to the process of forming the required thin film on the surface of the silicon wafer. These specific films include insulators, semiconductors or conductors. The main thin film technologies include chemical vapor deposition (Chemical Vapor Deposition, CVD) and physical vapor deposition (Physical Vapor Deposition, PVD) and so on. The vast majority of thin films in integrated circuit fabrication are deposited by CVD techniques. The principle of CVD is to mix the chemical components containing the required atoms or molecules in the reaction chamber and react in the gaseous state, so that the atoms or molecules are deposited on the surface of the silicon wafer, thereby forming a specific type of thin film. The chemical reactions used are generally divided into pyrolysis, reduction, oxidation, and nitridation. Pyrolysis refers to chemical reactions that rely solely on heat. Reduction is a chemical reaction of molecules, hydrogen. Oxidation is a chemical reaction of atoms, molecules and oxygen. Nitriding mainly refers to a chemical reaction that forms a silicon nitride film on the surface of a silicon wafer.
步骤125:光刻完成后通过干法刻蚀去除硼磷硅玻璃,并利用物理气相沉积工艺沉积通孔金属。Step 125 : after the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by a physical vapor deposition process.
不同于化学气相沉积依靠化学反应产生反应粒子形成薄膜,物理气相沉积方法主要利用物理过程淀积薄膜,即利用物理过程,将原子或者分子由气体源转移到硅片表面。PVD技术比CVD方法更多地用于各个方面,因为它几乎可做任何材料的淀积。Unlike chemical vapor deposition, which relies on chemical reactions to generate reactive particles to form thin films, physical vapor deposition methods mainly use physical processes to deposit thin films, that is, use physical processes to transfer atoms or molecules from a gas source to the surface of a silicon wafer. PVD technology is more used in every aspect than CVD method, because it can do the deposition of almost any material.
一般的集成电路的芯片都有多层金属层组成,金属层和金属层之间是由通孔(VIA)来进行连接的。The chips of general integrated circuits are composed of multi-layer metal layers, and the metal layers and the metal layers are connected by vias (VIAs).
步骤127:利用物理气相沉积工艺在硅片表面形成金属层;其中所述金属层是按照预设规则被填充有冗余金属,所述预设规则包括:在金属层的电感器件的外部一根或多根条形冗余金属。Step 127 : use a physical vapor deposition process to form a metal layer on the surface of the silicon wafer; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: a metal layer outside the inductance device of the metal layer or multiple strips of redundant metal.
一些实施例中,在电感外部填充的条形冗余金属,不沿着感应电流的方向摆放,这可以进一步降低感应电流在填充金属中的损耗。更进一步地,当条形冗余金属沿 着垂直感应电流方向摆放的时候,条带间的空隙切断了电流的流动路径,这又能够进一步显著降低感应电流在金属中的损耗。In some embodiments, the strip-shaped redundant metal filled outside the inductor is not arranged along the direction of the induced current, which can further reduce the loss of the induced current in the filled metal. Furthermore, when the strip-shaped redundant metal is placed along the direction perpendicular to the induced current, the gaps between the strips cut off the flow path of the current, which can further significantly reduce the loss of the induced current in the metal.
步骤129:对填充了冗余金属的金属层进行化学机械研磨,以使之平坦化。Step 129 : chemical mechanical polishing is performed on the metal layer filled with the redundant metal to planarize it.
金属层生长完成后,在硅片表面形成了高低不平的金属厚度和刻蚀浓度的差异,化学机械研磨(Chemical Mechanical Polish,CMP)的目的就是将多余的金属去除以使得它们高低相同。CMP在对金属层进行平坦化时,结合了化学和机械两个作用,通过含有化学成分的研磨液,通过机械和化学效应同时对待研磨层发生作用。After the growth of the metal layer is completed, uneven metal thickness and etching concentration differences are formed on the surface of the silicon wafer. The purpose of chemical mechanical polishing (Chemical Mechanical Polish, CMP) is to remove the excess metal to make them the same height. When CMP planarizes the metal layer, it combines chemical and mechanical effects. Through the polishing liquid containing chemical components, the mechanical and chemical effects simultaneously act on the polishing layer.
步骤131:对硅片进行测试和封装。Step 131: Test and package the silicon wafer.
封装主要是为了实现芯片内部和外部电路之间的连接和保护作用。而硅片进行测试就是运用各种测试方法,检测硅片或者说芯片是否存在设计缺陷或者制造过程导致的物理缺陷。为了确保芯片能够正常使用,在交付给整机厂商前必须要经过的最后两道过程:封装与测试。Packaging is mainly to achieve the connection and protection between the internal and external circuits of the chip. The testing of silicon wafers is to use various testing methods to detect whether the silicon wafers or chips have design defects or physical defects caused by the manufacturing process. In order to ensure that the chip can be used normally, the last two processes that must be passed before delivery to the complete machine manufacturer: packaging and testing.
以上就是本发明所公开的芯片的制造方法的一些说明。本发明另一些实施例中还公开根据本发明所公开的芯片的制造方法所制造的芯片。可以预见地,由本发明所公开的芯片的制造方法所制造的芯片,其金属层会有特定的结构,例如电感器件的外部填充一根或多根条形冗余金属,进一步地,条形冗余金属的与电感器件的感应电流方向不平行,进一步地,条形冗余金属的与电感器件的感应电流方向垂直。因此,一个实施例中,本发明所公开的芯片的制造方法所制造的芯片,条形冗余金属呈辐射状摆放在电感外部周围。The above are some descriptions of the manufacturing method of the chip disclosed in the present invention. In other embodiments of the present invention, chips manufactured according to the method for manufacturing a chip disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured by the chip manufacturing method disclosed in the present invention will have a specific structure, for example, the outside of the inductor device is filled with one or more strip-shaped redundant metals. The redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the chip manufacturing method disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.
本发明另一些实施例中公开了一种冗余金属的填充方法。一般地,冗余金属的填充都在晶圆制造厂或者说芯片制造石完成,冗余金属的填充位于版图物理设计的最后阶段,时序、版图逻辑验证(Layout Versus Schematics,LVS)、设计规则验证(Design Rule Check,DRC)等都已经通过,版图设计已经基本定案。In other embodiments of the present invention, a method for filling redundant metal is disclosed. Generally, the filling of redundant metal is completed in the wafer fab or chip manufacturing stone. The filling of redundant metal is located in the final stage of layout physical design, timing, layout logic verification (Layout Versus Schematics, LVS), design rule verification (Design Rule Check, DRC), etc. have been passed, and the layout design has been basically finalized.
请参照图9,本发明另一些实施例中公开了一种冗余金属的填充方法,包括以下步骤:Referring to FIG. 9 , another embodiment of the present invention discloses a method for filling redundant metal, including the following steps:
步骤191:获取待填充的集成电路版图,其中集成电路版图包括一个或多个金属层。Step 191: Obtain an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers.
步骤193:至少对于其中一个金属层,按照预设规则填充冗余金属;其中所述预设规则包括:在金属层的电感器件的外部填充一根或多根条形冗余金属。Step 193 : Fill at least one metal layer with redundant metal according to a preset rule; wherein the preset rule includes: filling one or more strip-shaped redundant metals on the outside of the inductance device of the metal layer.
在集成电路的版图设计中,冗余金属填充是版图后期处理的一个过程,步骤193提出了在金属层填充冗余金属的规则,即在金属层的电感器件的外部填充一根或多根条形冗余金属。通过以条形冗余金属进行填充,从而减少甚至避免了在电感内部这一磁通密度更大的区域进行冗余金属的填充,有效地提高了电感的品质因数。进一步地,虽然电感外部的磁通密度小于电感内部的磁通密度,但是电感产生的交变磁场仍然会在外部的导体中产生与电感线圈平行的感应电流,这部分电流的欧姆损耗将会降低电感的品质因数。考虑到这种情况下,步骤193在电感外部填充的条形冗余金属,不沿着感应电流的方向摆放,这可以进一步降低感应电流在填充金属中的损耗;更进一步地,步骤193在电感外部填充的条形冗余金属,条形冗余金属 沿着垂直感应电流方向摆放,由于条带间的空隙切断了电流的流动路径,这又能够进一步显著降低感应电流在金属中的损耗。In the layout design of integrated circuits, redundant metal filling is a process of layout post-processing. Step 193 proposes a rule for filling redundant metal in the metal layer, that is, filling one or more strips outside the inductor device of the metal layer. Shape redundant metal. By filling with strip-shaped redundant metal, the filling of redundant metal in the area with higher magnetic flux density inside the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved. Further, although the magnetic flux density outside the inductor is smaller than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor will still generate an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will be reduced. The quality factor of the inductor. Considering this situation, the strip-shaped redundant metal filled outside the inductor in step 193 is not placed along the direction of the induced current, which can further reduce the loss of the induced current in the filler metal; further, step 193 is in The strip-shaped redundant metal is filled outside the inductor. The strip-shaped redundant metal is placed along the direction of the vertical induced current. Since the gap between the strips cuts off the current flow path, this can further significantly reduce the loss of the induced current in the metal. .
另外,在集成电路版图中可以有多种方法识别并定位出电感器件。一些方法中,可以根据设计者提供的标识层,通常电感这类特殊器件都会有对应的标识层,如果芯片厂需要,可以要求设计者在提供原始设计数据的时候保留该标识层,同时通过层次转换传递给芯片厂;另一些方法中,这些设计都有固定的形状,例如电感器件,其金属层图形是平行的多个金属回路,作为电感线圈存在。In addition, there are various methods for identifying and locating inductive devices in an integrated circuit layout. In some methods, according to the identification layer provided by the designer, usually special devices such as inductors will have a corresponding identification layer. If the chip factory needs it, the designer can be required to retain the identification layer when providing the original design data. The conversion is passed to the chip factory; in other methods, these designs have a fixed shape, such as an inductor device, whose metal layer pattern is a plurality of parallel metal loops, which exist as inductor coils.
以上就是本发明所公开的冗余金属的填充方法的一些说明。本发明另一些实施例中还公开根据本发明所公开的冗余金属的填充方法而制造的芯片。可以预见地,根据本发明所公开的冗余金属的填充方法而所制造的芯片,其金属层会有特定的结构,例如电感器件的外部填充一根或多根条形冗余金属,进一步地,条形冗余金属的与电感器件的感应电流方向不平行,进一步地,条形冗余金属的与电感器件的感应电流方向垂直。因此,一个实施例中,本发明所公开的冗余金属的填充方法所制造的芯片,条形冗余金属呈辐射状摆放在电感外部周围。The above are some descriptions of the method for filling the redundant metal disclosed in the present invention. In other embodiments of the present invention, chips fabricated according to the method for filling redundant metal disclosed in the present invention are also disclosed. It is foreseeable that the metal layer of the chip manufactured according to the method for filling redundant metal disclosed in the present invention will have a specific structure. , the strip-shaped redundant metal is not parallel to the induced current direction of the inductive device, and further, the strip-shaped redundant metal is perpendicular to the induced current direction of the inductive device. Therefore, in one embodiment, in the chip manufactured by the method for filling redundant metal disclosed in the present invention, the strip-shaped redundant metal is radially arranged around the outside of the inductor.
请参照图10,本发明一些实施例中还公开了一种集成电路的芯片,该芯片包括一个或多个金属层,其中至少有一个金属层设有电感器件11,并且在电感器件的外部填充有一根或多根条形冗余金属12,其中图10为设有电感器件11的金属层的局部区域示意图,13为金属线或者说信号线。一些实施例中,条形冗余金属12与电感器件11的线圈方向不平行,或者说,条形冗余金属12与电感器件11由于产生的交变磁场在条形冗余金属12中产生的感应电流的方向不平行。一些实施例中,条形冗余金属12与电感器件11线圈方向垂直,或者说,条形冗余金属12与电感器件11由于产生的交变磁场在条形冗余金属12中产生的感应电流的方向垂直。Referring to FIG. 10, some embodiments of the present invention further disclose an integrated circuit chip, the chip includes one or more metal layers, at least one metal layer is provided with an inductance device 11, and is filled outside the inductance device There are one or more strip-shaped redundant metals 12 , wherein FIG. 10 is a schematic diagram of a partial area of the metal layer provided with the inductance device 11 , and 13 is a metal wire or a signal wire. In some embodiments, the strip-shaped redundant metal 12 is not parallel to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 are generated in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. The directions of the induced currents are not parallel. In some embodiments, the strip-shaped redundant metal 12 is perpendicular to the coil direction of the inductance device 11 , or, in other words, the strip-shaped redundant metal 12 and the inductive device 11 generate an induced current in the strip-shaped redundant metal 12 due to the generated alternating magnetic field. direction is vertical.
本申请提出了一种在电感周围辐射状填充条状冗余金属的技术方案。该方案相比于以金属块阵列形式填充冗余金属,更容易满足工艺对金属密度的要求,从而避免了在电感内部填充冗余金属。例如在电感外部周围放置垂直于电感感应电流方向的辐射状金属条,在满足工艺生产需求的前提下,有效抑制了冗余金属对电感品质因数的损耗,相较于一般均匀填充冗余金属的方式,能获得更高品质因数的电感。仿真结果表明,该方法可以应用于工作在15GHz到70GHz的电感,品质因数改善7%ˉ17%,下面具体说明。This application proposes a technical solution for radially filling strip-shaped redundant metal around an inductor. Compared with filling the redundant metal in the form of a metal block array, this solution is easier to meet the requirements of the metal density of the process, thereby avoiding filling the redundant metal inside the inductor. For example, placing radial metal strips perpendicular to the induced current direction of the inductor around the outside of the inductor can effectively suppress the loss of the quality factor of the inductor caused by the redundant metal under the premise of meeting the requirements of the process production. In this way, an inductor with a higher quality factor can be obtained. The simulation results show that the method can be applied to inductors operating from 15GHz to 70GHz, and the quality factor is improved by 7% to 17%, which will be explained in detail below.
本发明使用仿真软件(例如HFSS电磁仿真软件)分别对两个不同的电感A、B和一个耦合电感进行了品质因数仿真;其中在对每个电感进行品质因数仿真时,是分别以不加任何冗余金属,在电感周围以冗余金属块阵列的形式填充和在电感周围用条形冗余金属以辐射状填充的情况进行了仿真,下面具体说明。The present invention uses simulation software (such as HFSS electromagnetic simulation software) to carry out quality factor simulation of two different inductors A, B and a coupled inductor respectively; wherein when performing quality factor simulation of each inductor, it is performed without adding any Redundant metal, filled in the form of an array of redundant metal blocks around the inductor, and filled with strips of redundant metal in a radial pattern around the inductor were simulated, as described below.
(1)关于电感A的仿真(1) Simulation of inductance A
对电感值为0.38nH,内径35um的一个两圈电感A进行了仿真,电感设计和冗余金属的填充方式如图11(a)、图11(b)、图11(c)所示,其中图11(a)是对电感A不填充任何冗余金属,图11(b)是按照块状阵列方式对电感A填充冗余金 属或者说是填充块状冗余金属,图11(c)是对电感A以辐射状填充条形冗余金属,针对这三种情况进行了电磁场仿真,根据上文电感品质因数Q的计算公式得出电感品质因数随频率变化的关系,该关系如图12所示。由图12可以得知,不填充任何冗余金属时该电感品质因数Q最大值为16.04;按照块状阵列方式填充冗余金属时电感品质因数Q最大值为14.93,相比于理想状况(即不填充任何冗余金属的情况),品质因数降低了(16.04-14.93)/16.04=6.9%;按照本发明一实施例提出的以辐射状填充条形冗余金属的方法,电感品质因数Q最大值为15.97,相较于理想状况,品质因数只降低了(15.97-16.04)/16.04=0.44%,而相较于原本的块状阵列填充方法,品质因数Q则有(15.97-14.93)/14.93=7.0%的提升。另外图中可以看到三种填充方式后电感品质因数Q最大值对应的频率不一样,这是由冗余金属引入的寄生电容导致的。A two-turn inductor A with an inductance value of 0.38nH and an inner diameter of 35um is simulated. The inductor design and the filling method of redundant metal are shown in Figure 11(a), Figure 11(b), and Figure 11(c). Figure 11(a) shows that inductor A is not filled with any redundant metal. Figure 11(b) shows that inductor A is filled with redundant metal or bulk redundant metal according to the block array method. Figure 11(c) is a Inductor A is filled with strip-shaped redundant metal in a radial shape, and electromagnetic field simulations are carried out for these three cases. According to the calculation formula of inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 12. Show. It can be seen from Fig. 12 that the maximum value of the quality factor Q of the inductor is 16.04 when no redundant metal is filled; Without filling any redundant metal), the quality factor is reduced by (16.04-14.93)/16.04=6.9%; according to the method of filling strip-shaped redundant metal in a radial shape proposed by an embodiment of the present invention, the quality factor Q of the inductor is the largest The value is 15.97. Compared with the ideal situation, the quality factor is only reduced by (15.97-16.04)/16.04=0.44%. Compared with the original block array filling method, the quality factor Q is (15.97-14.93)/14.93 =7.0% improvement. In addition, it can be seen in the figure that the frequencies corresponding to the maximum value of the inductance quality factor Q after the three filling methods are different, which is caused by the parasitic capacitance introduced by the redundant metal.
(2)关于电感B的仿真(2) Simulation of inductance B
对电感值为0.26nH,内径23um的两圈电感B进行了仿真,电感设计和冗余金属的填充方式如图13(a)、图13(b)、图13(c)所示,其中图13(a)是对电感B不填充任何冗余金属,图13(b)是按照块状阵列方式对电感B填充冗余金属或者说是填充块状冗余金属,图13(c)是对电感B以辐射状填充条形冗余金属,针对这三种情况进行了电磁场仿真,根据上文电感品质因数Q的计算公式得出电感品质因数随频率变化的关系,该关系如图14所示。由图14可知,不填充任何冗余金属时该电感品质因数Q最大值为17.45,按照块状阵列方式填充冗余金属时电感品质因数Q最大值为15.82,相比于理想状况,品质因数降低了9.3%;按照本发明一实施例提出的以辐射状填充条形冗余金属的方法,电感品质因数Q最大值为16.92,相较于理想状况,品质因数只降低了3.0%,而相较于原本的块状阵列填充方法,品质因数则有6.9%的提升。The inductance value is 0.26nH and the inner diameter is 23um. The two-round inductance B is simulated. The inductance design and the filling method of redundant metal are shown in Figure 13(a), Figure 13(b), and Figure 13(c). Figure 13(c) 13(a) does not fill the inductor B with any redundant metal. Figure 13(b) fills the inductor B with redundant metal or bulk redundant metal according to the block array method. Inductor B is filled with strip-shaped redundant metal in a radial shape. The electromagnetic field simulation is carried out for these three cases. According to the calculation formula of the inductance quality factor Q above, the relationship between the inductance quality factor and frequency is obtained. The relationship is shown in Figure 14. . It can be seen from Figure 14 that the maximum value of the quality factor Q of the inductor is 17.45 when no redundant metal is filled, and the maximum value of the quality factor Q of the inductor when the redundant metal is filled in the block array method is 15.82, which is lower than the ideal condition. According to the method of filling strip-shaped redundant metal in a radial shape proposed in an embodiment of the present invention, the maximum value of the inductance quality factor Q is 16.92. Compared with the ideal situation, the quality factor is only reduced by 3.0%. Compared with the original block array filling method, the quality factor is improved by 6.9%.
(3)关于耦合电感的仿真(3) Simulation of coupled inductors
本发明不仅可以应用于单端口电感,同样也可以用于耦合电感。如图15(a)、图15(b)、图15(c)所示,对一个匝数比为2:1的耦合电感进行了上述三种不同填充情况下的三维建模和电磁仿真,具体地,图15(a)是对耦合电感不填充任何冗余金属,图15(b)是按照块状阵列方式对耦合电感填充冗余金属或者说是填充块状冗余金属,图15(c)是对耦合电感以辐射状填充条形冗余金属;其中块状阵列和辐射条状冗余金属填充后电感周围都满足工艺对金属密度的要求。The present invention can be applied not only to single-port inductors, but also to coupled inductors. As shown in Fig. 15(a), Fig. 15(b), Fig. 15(c), the 3D modeling and electromagnetic simulation under the above three different filling conditions were carried out for a coupled inductor with a turns ratio of 2:1. Specifically, Fig. 15(a) shows that the coupled inductor is not filled with any redundant metal, and Fig. 15(b) shows that the coupled inductor is filled with redundant metal or bulk redundant metal according to the block array method. Fig. 15( c) is to fill the strip-shaped redundant metal in a radial shape for the coupled inductor; wherein the bulk array and the radial strip-shaped redundant metal are filled around the inductor to meet the requirements for the metal density of the process.
仿真后,在次级线圈端口接50Ω负载的情况下对初级线圈的品质因数Q根据上文电感品质因数Q的计算公式得出电感品质因数随频率变化的关系,结果如图16所示。由图16可知不填充任何冗余金属时初级线圈品质因数Q最大值为19.86;按照块状阵列方式填充冗余金属时初级线圈品质因数Q最大值为15.89,相比于理想状况,品质因数降低了20%;而按照本发明一实施例提出的以辐射状填充条形冗余金属的方法,初级线圈品质因数Q最大值为18.69,相较于理想状况,品质因数只降低了5.9%,而相较于原本的块状阵列填充方法,品质因数则有17.6%的提升。次级线圈品质因数Q随频率的变化关系如图17所示。由图17可知,不填充任何冗余金属时次级线圈品质因数Q最大值为11.07;按照块状阵列方式填充冗余金属时次 级线圈品质因数Q最大值为10.08,相比于理想状况,品质因数降低了8.9%;而按照本发明一实施例提出的以辐射状填充条形冗余金属的方法,次级线圈品质因数Q最大值为10.81,相较于理想状况,品质因数只降低了2.3%,而相较于原本的均匀块状阵列的填充方法,品质因数则有7.2%的提升。After the simulation, when the secondary coil port is connected to a 50Ω load, the quality factor Q of the primary coil is obtained according to the calculation formula of the inductance quality factor Q above to obtain the relationship between the inductance quality factor and the frequency. The result is shown in Figure 16. It can be seen from Figure 16 that the maximum value of the quality factor Q of the primary coil when no redundant metal is filled is 19.86; when the redundant metal is filled in the block array mode, the maximum value of the quality factor Q of the primary coil is 15.89, which is lower than the ideal condition. According to the method of filling strip-shaped redundant metal radially proposed in an embodiment of the present invention, the maximum value of the quality factor Q of the primary coil is 18.69, which is only 5.9% lower than the ideal condition, and Compared with the original block array filling method, the quality factor is improved by 17.6%. The relationship between the quality factor Q of the secondary coil and the frequency is shown in Figure 17. It can be seen from Figure 17 that the maximum value of the quality factor Q of the secondary coil is 11.07 when no redundant metal is filled; The quality factor is reduced by 8.9%; and according to the method for filling strip-shaped redundant metal in a radial shape proposed in an embodiment of the present invention, the maximum value of the quality factor Q of the secondary coil is 10.81. Compared with the ideal situation, the quality factor is only reduced. 2.3%, and compared with the original uniform block array filling method, the quality factor is improved by 7.2%.
下表对电感A、B和耦合电感的电感品质因数仿真结果进行汇总,其中方法1是指块状阵列的填充方法,方法2是指本发明一实施例提出的以辐射状填充条形冗余金属的方法,从下表可知,本发明可以有效地防止由于添加冗余金属导致的电感品质因数的降低;在满足工艺要求的金属密度的情况下,本发明提出的冗余金属填充方案获得的电感的品质因数,相较于一般的冗余金属填充方式,有7%左右的提升,并且本发明也可以应用于耦合电感当中。The following table summarizes the inductance quality factor simulation results of inductors A, B and coupled inductors, where method 1 refers to the filling method of the block array, and method 2 refers to the radial filling strip redundancy proposed by an embodiment of the present invention As can be seen from the table below, the present invention can effectively prevent the reduction of the inductance quality factor due to the addition of redundant metals; in the case of satisfying the metal density required by the process, the redundant metal filling scheme proposed by the present invention obtains Compared with the general redundant metal filling method, the quality factor of the inductor is improved by about 7%, and the present invention can also be applied to coupled inductors.
本文针对芯片生产过程中因为对金属密度的要求,需要在电感周围填充冗余金属这一状况,在一些实施例中,提出了一种垂直于感应电场方向放置辐射状条形金属的填充技术;该技术缓解了模拟和射频电路设计中INDDMY层因工艺限制,允许的使用面积不够设计使用的问题。仿真表明,该技术在不使用INDDMY层来忽略金属密度检查的情况下,不仅满足了工艺要求的金属密度,该方式切断了感应电流路径,并且避免了在电感线圈内部填充金属。经过电磁全波仿真表明,该技术相较于常规的均匀填充块状阵列冗余金属的方式,能够有效降低冗余金属对电感造成的损耗,对于设计高Q值单端口电感和耦合电感极为有利。Aiming at the situation that redundant metal needs to be filled around the inductor due to the requirement of metal density in the chip production process, in some embodiments, a filling technology of placing radial strips of metal perpendicular to the direction of the induced electric field is proposed; This technology alleviates the problem that the allowable area of the INDDMY layer in the design of analog and RF circuits is not enough for design due to process limitations. Simulations show that this technique not only meets the metal density required by the process, but also cuts off the induced current path and avoids metal filling inside the inductor coil without using the INDDMY layer to ignore the metal density check. The electromagnetic full-wave simulation shows that, compared with the conventional method of uniformly filling the redundant metal of the block array, this technology can effectively reduce the loss caused by the redundant metal to the inductor, which is extremely beneficial for the design of high-Q single-port inductors and coupled inductors. .
本文参照了各种示范实施例进行说明。然而,本领域的技术人员将认识到,在不脱离本文范围的情况下,可以对示范性实施例做出改变和修正。例如,各种操作步骤以及用于执行操作步骤的组件,可以根据特定的应用或考虑与系统的操作相关联的任何数量的成本函数以不同的方式实现(例如一个或多个步骤可以被删除、修改或结合到其他步骤中)。Descriptions are made herein with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps, and components for performing operational steps, may be implemented in different ways depending on the particular application or considering any number of cost functions associated with the operation of the system (eg, one or more steps may be deleted, modified or incorporated into other steps).
在上述实施例中,可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。另外,如本领域技术人员所理解的,本文的原理可以反映在计算机可读存储介质上的计算机程序产品中,该可读存储介质预装有计算机可读程序代码。任何有形的、非暂时性的计算机可读存储介质皆可被使用,包括磁存储设备(硬盘、软盘等)、光学存储设备(CD至ROM、DVD、Blu Ray盘等)、闪存和/或诸如此类。这些计算机程序指令可被加载到通用计算机、专用计算机或其他可编程数据处理设备上以形成机器,使得这些在计算机上或其他可编程数据处理装置上执行的指令可以生 成实现指定的功能的装置。这些计算机程序指令也可以存储在计算机可读存储器中,该计算机可读存储器可以指示计算机或其他可编程数据处理设备以特定的方式运行,这样存储在计算机可读存储器中的指令就可以形成一件制造品,包括实现指定功能的实现装置。计算机程序指令也可以加载到计算机或其他可编程数据处理设备上,从而在计算机或其他可编程设备上执行一系列操作步骤以产生一个计算机实现的进程,使得在计算机或其他可编程设备上执行的指令可以提供用于实现指定功能的步骤。In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. Additionally, as understood by those skilled in the art, the principles herein may be reflected in a computer program product on a computer-readable storage medium preloaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CD to ROM, DVD, Blu Ray disks, etc.), flash memory, and/or the like . These computer program instructions may be loaded on a general purpose computer, special purpose computer or other programmable data processing apparatus to form a machine, such that the instructions executed on the computer or other programmable data processing apparatus may generate means for carrying out the specified functions. These computer program instructions may also be stored in a computer-readable memory that instructs a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable memory form a piece of Articles of manufacture, including implementing means for implementing specified functions. Computer program instructions may also be loaded on a computer or other programmable data processing device to perform a series of operational steps on the computer or other programmable device to produce a computer-implemented process such that a process executed on the computer or other programmable device Instructions may provide steps for implementing specified functions.
虽然在各种实施例中已经示出了本文的原理,但是许多特别适用于特定环境和操作要求的结构、布置、比例、元件、材料和部件的修改可以在不脱离本披露的原则和范围内使用。以上修改和其他改变或修正将被包含在本文的范围之内。Although the principles herein have been shown in various embodiments, many modifications may be made in structure, arrangement, proportions, elements, materials and components as are particularly suited to particular environmental and operating requirements without departing from the principles and scope of the present disclosure use. The above modifications and other changes or corrections are intended to be included within the scope of this document.
前述具体说明已参照各种实施例进行了描述。然而,本领域技术人员将认识到,可以在不脱离本披露的范围的情况下进行各种修正和改变。因此,对于本披露的考虑将是说明性的而非限制性的意义上的,并且所有这些修改都将被包含在其范围内。同样,有关于各种实施例的优点、其他优点和问题的解决方案已如上所述。然而,益处、优点、问题的解决方案以及任何能产生这些的要素,或使其变得更明确的解决方案都不应被解释为关键的、必需的或必要的。本文中所用的术语“包括”和其任何其他变体,皆属于非排他性包含,这样包括要素列表的过程、方法、文章或设备不仅包括这些要素,还包括未明确列出的或不属于该过程、方法、系统、文章或设备的其他要素。此外,本文中所使用的术语“耦合”和其任何其他变体都是指物理连接、电连接、磁连接、光连接、通信连接、功能连接和/或任何其他连接。The foregoing Detailed Description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Accordingly, this disclosure is to be considered in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within its scope. Likewise, the advantages, other advantages, and solutions to problems of the various embodiments have been described above. However, the benefits, advantages, solutions to the problems, and any elements that give rise to them, or make them more explicit, should not be construed as critical, necessary, or essential. As used herein, the term "comprising" and any other variations thereof are non-exclusive inclusion, such that a process, method, article or device including a list of elements includes not only those elements, but also not expressly listed or included in the process , method, system, article or other elements of a device. Furthermore, as used herein, the term "coupled" and any other variations thereof refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.
具有本领域技术的人将认识到,在不脱离本发明的基本原理的情况下,可以对上述实施例的细节进行许多改变。因此,本发明的范围应仅由权利要求确定。Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined only by the claims.
Claims (12)
- 一种芯片的制造方法,其特征在于,包括:A method for manufacturing a chip, comprising:对硅片进行清洗并烘干;Wash and dry the silicon wafer;对清洗完的硅片进行氧化;Oxidize the cleaned silicon wafer;对氧化完成的硅片根据掩模版上电路设计进行阱区光刻;Perform well region lithography on the oxidized silicon wafer according to the circuit design on the mask;光刻完成后对硅片进行湿法刻蚀去除二氧化硅,形成阱区注入孔;After the photolithography is completed, the silicon wafer is wet-etched to remove silicon dioxide to form a well region injection hole;对硅片进行离子注入,形成阱;Ion implantation is performed on the silicon wafer to form a well;对离子注入完成的硅片进行快速热退火;Rapid thermal annealing of ion implanted silicon wafers;采用浅槽隔离工艺进行隔离;Isolation by shallow trench isolation process;对硅片进行氧化,氧化完成后沉积多晶硅,根据掩模版上电路设计进行有源区光刻;Oxidize the silicon wafer, deposit polysilicon after the oxidation is completed, and perform active area lithography according to the circuit design on the mask;光刻完成后采用干法刻蚀去除多晶硅,形成栅极和有源区注入孔;After the photolithography is completed, the polysilicon is removed by dry etching to form the gate and the injection hole in the active region;对硅片进行离子注入,形成源极漏极;Ion implantation is performed on the silicon wafer to form source and drain;对离子注入完成的硅片进行快速热退火;Rapid thermal annealing of ion implanted silicon wafers;利用化学气相沉积工艺在硅片表面形成硼磷硅玻璃,根据掩模版上电路设计进行通孔光刻;Borophosphosilicate glass is formed on the surface of the silicon wafer by chemical vapor deposition process, and through-hole lithography is performed according to the circuit design on the mask;光刻完成后通过干法刻蚀去除硼磷硅玻璃,并利用物理气相沉积工艺沉积通孔金属;After the photolithography is completed, the borophosphosilicate glass is removed by dry etching, and the through hole metal is deposited by the physical vapor deposition process;利用物理气相沉积工艺在硅片表面形成金属层;其中所述金属层是按照预设规则被填充有冗余金属,所述预设规则包括:在金属层的电感器件的外部一根或多根条形冗余金属;A metal layer is formed on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, and the preset rule includes: one or more wires outside the inductor device of the metal layer Strip redundant metal;对填充了冗余金属的金属层进行化学机械研磨,以使之平坦化;chemical mechanical polishing of the metal layer filled with redundant metal to planarize it;对硅片进行测试和封装。Silicon wafers are tested and packaged.
- 如权利要求1所述的制造方法,其特征在于,所述条形冗余金属与电感器件的线圈方向不平行。The manufacturing method of claim 1, wherein the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
- 如权利要求1所述的制造方法,其特征在于,所述条形冗余金属与电感器件的线圈方向垂直。The manufacturing method of claim 1, wherein the strip-shaped redundant metal is perpendicular to the coil direction of the inductor device.
- 一种根据如权利要求1至3中任一项所述的制造方法所制造的芯片。A chip manufactured according to the manufacturing method of any one of claims 1 to 3.
- 一种冗余金属的填充方法,其特征在于,包括:A method for filling redundant metal, comprising:获取待填充的集成电路版图,其中所述集成电路版图包括一个或多个金属层;obtaining an integrated circuit layout to be filled, wherein the integrated circuit layout includes one or more metal layers;至少对于其中一个金属层,按照预设规则填充冗余金属;其中所述预设规则包括:识别所述待填充的金属层所存在的电感器件,并在所述电感器件的外部填充一根或多根条形冗余金属。At least one of the metal layers is filled with redundant metal according to a preset rule; wherein the preset rule includes: identifying the inductance device existing in the metal layer to be filled, and filling one or Multiple strips of redundant metal.
- 如权利要求4所述的填充方法,其特征在于,所述条形冗余金属与电感器件的线圈方向不平行。The filling method according to claim 4, wherein the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
- 如权利要求5所述的填充方法,其特征在于,所述条形冗余金属与电感器件的线圈方向垂直。The filling method according to claim 5, wherein the strip-shaped redundant metal is perpendicular to the coil direction of the inductance device.
- 一种根据如权利要求5至7中任一项所述的填充方法而制造的芯片。A chip manufactured according to the filling method of any one of claims 5 to 7.
- 一种集成电路的芯片,其特征在于,包括一个或多个金属层,其中至少有一个金属层设有电感器件,并在所述电感器件的外部填充有一根或多根条形冗余金属。An integrated circuit chip is characterized by comprising one or more metal layers, wherein at least one metal layer is provided with an inductance device, and the outside of the inductance device is filled with one or more strip-shaped redundant metals.
- 如权利要求9所述的芯片,其特征在于,所述条形冗余金属与电感器件的线圈方向不平行。The chip of claim 9, wherein the strip-shaped redundant metal is not parallel to the coil direction of the inductor device.
- 如权利要求10所述的芯片,其特征在于,所述条形冗余金属与电感器件的线圈方向垂直。The chip of claim 10, wherein the strip-shaped redundant metal is perpendicular to the coil direction of the inductance device.
- 一种计算机可读存储介质,其特征在于,所述计算机可读存储介质有程序,所述程序能够被处理器执行以实现如权利要求1至3或5至7中任一项所述的方法。A computer-readable storage medium, characterized in that the computer-readable storage medium has a program, and the program can be executed by a processor to implement the method according to any one of claims 1 to 3 or 5 to 7 .
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202180003222.7A CN113853674B (en) | 2021-02-03 | 2021-02-03 | Chip, method of manufacturing the same, method of filling redundant metal, and computer-readable storage medium |
PCT/CN2021/075075 WO2022165670A1 (en) | 2021-02-03 | 2021-02-03 | Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2021/075075 WO2022165670A1 (en) | 2021-02-03 | 2021-02-03 | Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022165670A1 true WO2022165670A1 (en) | 2022-08-11 |
Family
ID=78982727
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2021/075075 WO2022165670A1 (en) | 2021-02-03 | 2021-02-03 | Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN113853674B (en) |
WO (1) | WO2022165670A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116404006B (en) * | 2023-06-09 | 2023-08-25 | 合肥晶合集成电路股份有限公司 | Chip layout |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020036335A1 (en) * | 2000-09-28 | 2002-03-28 | Kabushiki Kaisha Toshiba | Spiral inductor and method for fabricating semiconductor integrated circuit device having same |
CN1734767A (en) * | 2004-08-03 | 2006-02-15 | 三星电子株式会社 | Comprise integrated circuit (IC)-components of passive device shielding construction and forming method thereof |
US20070228515A1 (en) * | 2006-03-30 | 2007-10-04 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit with spiral inductors |
CN102543853A (en) * | 2011-12-31 | 2012-07-04 | 中国科学院微电子研究所 | redundant metal filling method and integrated circuit layout structure |
CN104011860A (en) * | 2011-12-29 | 2014-08-27 | 英特尔公司 | Inductor design with metal dummy features |
CN104051435A (en) * | 2013-03-11 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Structure and Method for an Inductor With Metal Dummy Features |
US20140284763A1 (en) * | 2013-03-25 | 2014-09-25 | Realtek Semiconductor Corp. | Integrated inductor and integrated inductor fabricating method |
CN104810244A (en) * | 2014-01-26 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor device and electronic device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005236033A (en) * | 2004-02-19 | 2005-09-02 | Mitsubishi Electric Corp | Semiconductor device |
US7652348B1 (en) * | 2006-07-27 | 2010-01-26 | National Semiconductor Corporation | Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits |
CN102082143B (en) * | 2009-12-01 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Figure filler structure inserted about inductor |
JP5494214B2 (en) * | 2010-05-14 | 2014-05-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP2018026475A (en) * | 2016-08-10 | 2018-02-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2021
- 2021-02-03 WO PCT/CN2021/075075 patent/WO2022165670A1/en active Application Filing
- 2021-02-03 CN CN202180003222.7A patent/CN113853674B/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020036335A1 (en) * | 2000-09-28 | 2002-03-28 | Kabushiki Kaisha Toshiba | Spiral inductor and method for fabricating semiconductor integrated circuit device having same |
CN1734767A (en) * | 2004-08-03 | 2006-02-15 | 三星电子株式会社 | Comprise integrated circuit (IC)-components of passive device shielding construction and forming method thereof |
US20070228515A1 (en) * | 2006-03-30 | 2007-10-04 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit with spiral inductors |
CN104011860A (en) * | 2011-12-29 | 2014-08-27 | 英特尔公司 | Inductor design with metal dummy features |
CN102543853A (en) * | 2011-12-31 | 2012-07-04 | 中国科学院微电子研究所 | redundant metal filling method and integrated circuit layout structure |
CN104051435A (en) * | 2013-03-11 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Structure and Method for an Inductor With Metal Dummy Features |
US20140284763A1 (en) * | 2013-03-25 | 2014-09-25 | Realtek Semiconductor Corp. | Integrated inductor and integrated inductor fabricating method |
CN104810244A (en) * | 2014-01-26 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor device and electronic device |
Also Published As
Publication number | Publication date |
---|---|
CN113853674A (en) | 2021-12-28 |
CN113853674B (en) | 2022-08-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI520392B (en) | Magnetoresistive random access memory (mram) device and method for fabricating the same | |
US9263442B2 (en) | Replacement gate structures and methods of manufacturing | |
US9230725B2 (en) | Methods of designing an inductor having opening enclosed within conductive line | |
CN102194875A (en) | Method and apparatus for reducing gate resistance | |
US8470682B2 (en) | Methods and structures for increased thermal dissipation of thin film resistors | |
US20180323158A1 (en) | Magnetic inductor stack including insulating material having multiple thicknesses | |
WO2022165670A1 (en) | Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium | |
US8518773B2 (en) | Method of fabricating semiconductor capacitor | |
US8691697B2 (en) | Self-aligned devices and methods of manufacture | |
US20140070334A1 (en) | Semiconductor device including graded gate stack, related method and design structure | |
US10438803B2 (en) | Semiconductor structures having low resistance paths throughout a wafer | |
CN107871706B (en) | Shallow trench isolation structure and manufacturing method thereof | |
CN105719947A (en) | Semiconductor device forming method | |
CN102437089B (en) | Copper subsequent interconnection technique | |
US8853076B2 (en) | Self-aligned contacts | |
US9236315B2 (en) | Electrical test structure for devices employing high-k dielectrics or metal gates | |
US8637403B2 (en) | Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics | |
US8927869B2 (en) | Semiconductor structures and methods of manufacture | |
CN109935631B (en) | Undoped L-shaped tunneling field effect transistor and preparation method thereof | |
US20130234138A1 (en) | Electrical test structure for determining loss of high-k dielectric material and/or metal gate material | |
US8916932B2 (en) | Semiconductor device including FINFET structures with varied epitaxial regions, related method and design structure | |
US8815733B2 (en) | Isolated wire structures with reduced stress, methods of manufacturing and design structures | |
US8564074B2 (en) | Self-limiting oxygen seal for high-K dielectric and design structure | |
US20220384615A1 (en) | Method for manufacturing metal gate | |
CN114256064A (en) | Method for improving back-etched photoresist process window |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21923698 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21923698 Country of ref document: EP Kind code of ref document: A1 |