CN113853674B - Chip, method of manufacturing the same, method of filling redundant metal, and computer-readable storage medium - Google Patents
Chip, method of manufacturing the same, method of filling redundant metal, and computer-readable storage medium Download PDFInfo
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- CN113853674B CN113853674B CN202180003222.7A CN202180003222A CN113853674B CN 113853674 B CN113853674 B CN 113853674B CN 202180003222 A CN202180003222 A CN 202180003222A CN 113853674 B CN113853674 B CN 113853674B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
Abstract
A chip manufacturing method, a redundant metal filling method, a chip and a computer-readable storage medium, one or more strip-shaped redundant metals (12) are provided outside an inductive device (11) of a metal layer, further, the strip-shaped redundant metals (12) are not parallel to a coil direction of the inductive device (11), and further, the strip-shaped redundant metals (12) are perpendicular to the coil direction of the inductive device (11). Compared with the traditional redundant metal filling technology aiming at the inductor device area, the invention can effectively improve the quality factor of the inductor.
Description
Technical Field
The invention relates to a chip manufacturing method, a redundant metal filling method and a chip.
Background
Redundant metal Fill (Dummy Fill) is a technique applied in Integrated Circuit (IC) manufacturing to improve surface planarization; specifically, in the manufacturing process of the integrated circuit, the uniformity of layout density is improved by means of redundant metal, the flatness of the surface of a chip of the integrated circuit after Chemical Mechanical Polishing (CMP) is improved, and further the reliability and yield of products are improved. Integrated circuit fabrication technology has been developed at a rate of doubling the integration density every 18 months in accordance with moore's law, but as the feature size of integrated circuits has decreased below, for example, 90 nm, integrated circuit fabrication technology has encountered unprecedented challenges, surface unevenness has severely impacted device performance and stability, and redundant metal filling has become an indispensable step.
Therefore, in layout design, redundant metal needs to be filled to meet the requirement of the production process on the metal density of each metal layer of the chip. However, the filling of redundant metals introduces other problems.
Disclosure of Invention
The invention provides a chip manufacturing method, a redundant metal filling method and a chip, which are used for solving one or more of the problems introduced by the redundant metal filling.
According to a first aspect, an embodiment provides a method of manufacturing a chip, comprising:
cleaning and drying the silicon wafer;
oxidizing the cleaned silicon wafer;
performing well region photoetching on the oxidized silicon wafer according to the circuit design on the mask;
after photoetching, carrying out wet etching on the silicon wafer to remove silicon dioxide and form a well region injection hole;
performing ion implantation on the silicon wafer to form a trap;
carrying out rapid thermal annealing on the silicon wafer subjected to ion implantation;
isolating by adopting a shallow slot isolation process;
oxidizing a silicon wafer, depositing polycrystalline silicon after the oxidation is finished, and carrying out active area photoetching according to the circuit design on a mask;
removing the polysilicon by dry etching after the photoetching is finished to form a gate and an active region injection hole;
performing ion implantation on the silicon wafer to form a source electrode and a drain electrode;
carrying out rapid thermal annealing on the silicon wafer subjected to ion implantation;
forming boron-phosphorus-silicon glass on the surface of a silicon wafer by using a chemical vapor deposition process, and carrying out through hole photoetching according to the circuit design on a mask;
removing the borophosphosilicate glass by dry etching after photoetching is finished, and depositing through hole metal by utilizing a physical vapor deposition process;
forming a metal layer on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, the preset rule comprising: one or more strip-shaped redundant metals are arranged outside the inductance device of the metal layer;
performing chemical mechanical polishing on the metal layer filled with the redundant metal to planarize the metal layer;
and testing and packaging the silicon chip.
In one embodiment, the strip-shaped redundant metal is not parallel to the coil direction of the inductance device.
In one embodiment, the strip-shaped redundant metal is perpendicular to the coil direction of the inductance device.
According to a second aspect, there is provided in an embodiment a chip manufactured according to the manufacturing method of any embodiment herein.
According to a third aspect, an embodiment provides a method for filling a redundant metal, including:
acquiring an integrated circuit layout to be filled, wherein the integrated circuit layout comprises one or more metal layers;
filling redundant metal at least for one metal layer according to a preset rule; wherein the preset rule comprises: and identifying the inductance device in which the metal layer to be filled exists, and filling one or more strip-shaped redundant metals outside the inductance device.
In one embodiment, the strip-shaped redundant metal is not parallel to the coil direction of the inductance device.
In one embodiment, the strip-shaped redundant metal is perpendicular to the coil direction of the inductance device.
According to a fourth aspect, there is provided in an embodiment a chip manufactured according to the filling method as described in any of the embodiments herein.
According to a fifth aspect, an embodiment provides a chip of an integrated circuit, comprising one or more metal layers, wherein at least one metal layer is provided with an inductive device, and one or more strip-like redundant metals are filled outside the inductive device.
In one embodiment, the strip-shaped redundant metal is not parallel to the coil direction of the inductance device.
In one embodiment, the strip-shaped redundant metal is perpendicular to the coil direction of the inductance device.
According to a sixth aspect, an embodiment provides a computer readable storage medium storing a program executable by a processor to implement the method of any of the embodiments herein.
Drawings
FIG. 1 is a schematic view of a metal bulk array;
FIG. 2 is a schematic diagram of filling redundant metal in a metal block array manner outside and inside an inductor;
FIG. 3 is a schematic view of the arrangement of metal strips;
FIG. 4 is a schematic view of the metal strips arranged around the outside of the inductor to meet the process requirements for metal density;
FIG. 5 is a schematic diagram showing the direction in which an alternating magnetic field generated by an inductor generates an induced current in an outer conductor parallel to the inductor coil;
FIG. 6 is a schematic diagram of the strip of redundant metal filled around the outside of the inductor, not lying along the direction of the inductor coil or induced current;
FIGS. 7(a) and 7(b) are two schematic views of a redundant metal strip;
FIG. 8 is a flow chart of a method of fabricating a chip according to one embodiment;
FIG. 9 is a flow chart of a method of filling a redundant metal according to an embodiment;
FIG. 10 is a partial schematic view of a metal layer of a chip of an embodiment of a circuit;
fig. 11(a) is a schematic diagram of the inductor a not filled with any redundant metal, fig. 11(b) is a schematic diagram of the inductor a filled with redundant metal or filled with bulk redundant metal in a block array manner, and fig. 11(c) is a schematic diagram of the inductor a filled with strip-shaped redundant metal in a radial manner; FIG. 12 shows the simulation results for these three cases;
fig. 13(a) is a diagram in which the inductor B is not filled with any redundant metal, fig. 13(B) is a diagram in which the inductor B is filled with redundant metal or filled with block redundant metal in a block array manner, and fig. 13(c) is a diagram in which the inductor B is filled with strip redundant metal in a radial manner; FIG. 14 shows the corresponding simulation results for these three cases;
fig. 15(a) is a diagram showing that the coupling inductors are not filled with any redundant metal, fig. 15(b) is a diagram showing that the coupling inductors are filled with redundant metal or filled with block redundant metal in a block array manner, and fig. 15(c) is a diagram showing that the coupling inductors are filled with strip redundant metal in a radial manner; fig. 16 is the corresponding simulation results for the primary coil quality factors for the three cases, and fig. 17 is the corresponding simulation results for the secondary coil quality factors for the three cases.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As described in the background art, in the actual production process of chips, the process requires that each metal layer is filled with redundant metal to ensure the flatness of the polished surface chemistry and machinery so as to obtain higher yield; however, the filling of the redundant metal also introduces some problems to the chip that are desired to be avoided when the circuit design is introduced, for example, the filling of the redundant metal also introduces parasitic capacitances to the chip that are desired to be avoided when the circuit design is introduced, and the parasitic capacitances increase signal delay, interference noise and energy loss; the effect of how to fill the redundant metal in a proper manner to reduce the interference of the parasitic effect on the circuit also becomes a part of the consideration in the layout design of the integrated circuit; for example, chinese patent publication No. CN102456080A proposes a redundant metal filling for reducing parasitic capacitance.
In the prior art, the parasitic capacitance caused by filling of the redundant metal is researched more, and then the redundant metal can also generate interference on an electromagnetic field, so that the quality factor of the inductor in the integrated circuit is reduced. In particular, in chips of integrated circuits, especially in radio frequency chips, there may be high frequency devices such as inductors, which are generally very low in pattern density, and therefore it is generally necessary to fill these areas with redundant metal.
Aiming at the problems caused by filling of redundant metal, a chip manufacturer also provides a method for avoiding filling of redundant metal by considering the actual requirements of circuit design, namely using an INDDMY layer in the layout design process; specifically, by using the INDDMY layer to frame the required region in the design software, the framed region is not checked for metal density, so that redundant metal is not required to be added; the inductor model provided in the manufacturing process is generally self-contained with the INDDMY layer, and in addition, the designer can manually add the INDDMY layer to the inductor designed by the designer to skip the metal density check. The advantage of this is that it can avoid placing redundant metal around the inductor, and prevent the quality factor of the inductor from decreasing due to the interference of the redundant metal to the magnetic field around the inductor; it is understood that the INDDMY layer is only a virtual structural layer in software, and does not exist in the physical process of actual production, and the function of the INDDMY layer is to artificially make the selected region skip the metal density check, so that naturally, the region is not further considered to be filled with redundant metal to meet the metal density check. Because the function of the INDDMY layer is only to make the selected region jump over the inspection of the metal density artificially, the occupied area of the INDDMY layer is smaller than a certain proportion relative to the whole area of the chip due to the limitation of the production process, so that the flatness of each metal layer of the chip in the actual production process can be ensured. In a typical digital chip design, the process-specific INDDMY layer is a sufficient proportion of the total chip area for the designer to use if little inductance is used. However, since inductors are widely used in analog and radio frequency circuits, if each inductor is protected from being filled with redundant metal by using an INDMY layer in such chip designs, the proportion of the INDMY layer to the total chip area tends to exceed the process limits. Therefore, how to fill the inductor with redundant metal in a proper way around the inductor in the layout, and minimizing the loss of the redundant metal to the quality factor of the inductor under the condition of satisfying the metal density is still a problem to be considered and worth studying.
Before describing the scheme of the present application, the inductance quality factor and the inductance loss are described.
The Quality factor (Quality factor) of an inductor can be generally represented by the symbol Q; the quality factor Q of the inductor plays a key role in various analog RF circuits, such as the phase noise and 1/Q of the oscillator 2 Proportional, and for example, the voltage gain of the tuning amplifier is proportional to Q, and the quality factor Q of the inductor often limits the performance of the circuit, for example, the top value of the FoM (quality factor) of the oscillator is limited by the top quality factor of the inductor in the process.
Therefore, the quality factor Q of the inductor is a very important concept; the skilled person quantifies the loss level of the inductor, the quality of the inductor, by the quality factor Q of the inductorThe factor Q is defined as the ratio of the maximum stored energy value of the system to the energy loss of the system over a period. Therefore, a key factor influencing the Q value is the amount of energy loss when current flows through the inductor, and the loss of the inductor is mainly derived from the equivalent resistance presented by the inductor metal structure itself and the surrounding space. According to the definition of the quality factor Q of the inductor, if the inductance is L, the equivalent series resistance is R s And when the working frequency is omega, the Q value is expressed as the following expression:
Q＝Lω/R s ；
under certain other conditions, the larger the total loss of the inductor is, the larger the equivalent series resistance R of the inductor is s The larger, the following will describe several mechanisms that cause inductive losses-specifically, metal ohmic losses and dielectric losses.
(1) Ohmic loss of metal
Because the metal used to make the inductor has a finite conductivity, a part of the energy is dissipated as heat when the current flows through the metal, and this part of the energy is called the ohmic loss of the metal wire. From the above expression of Q values we can see that for a given inductance, the quality factor can be improved by reducing the metal resistance of the inductance. Generally, the equivalent resistance can be reduced by increasing the width of the inductor; however, wider metal lines, while exhibiting lower resistance, may, on the other hand, exhibit greater parasitic capacitance with respect to the substrate, which may reduce the self-resonant frequency of the inductor. Designers often need to trade off between Q and parasitic capacitance in actual circuit designs.
At high frequencies, the current components in the inductor tend to repel each other and thus move away, and eventually the current tends to flow on the metal surface, a phenomenon known as the skin effect. The actual distribution of the current follows an exponential decay from the surface of the metal inwards:
J(s)＝J 0 exp(-x/δ)；
wherein J 0 For the current density at the surface, δ is the skin depth, and the value of δ is given by:
where f denotes frequency, μ is permeability, and σ is conductivity.
The reduced equivalent cross-sectional area through which current flows due to the smaller skin depth at high frequencies further increases its equivalent resistance and hence ohmic losses.
(2) Dielectric loss
Because capacitance exists between the inductor and the substrate, when the voltage of each part of the inductor changes along with time, a divergent electric field penetrates through a dielectric layer between the substrate and each layer of metal to form displacement current. Because of the non-ideal resistivity of the substrate, it is inevitable that a portion of the current flowing through the substrate is converted into losses during each voltage variation cycle. The losses that occur when an electric field passes through these media are called dielectric losses, which further degrade the quality factor of the inductor.
The research and understanding of the quality factor Q of the inductor, the metal ohmic loss and the dielectric loss are important for understanding the deficiencies of the prior art and the improvement scheme of the present application, and the following describes the prior redundant metal filling technology and the improvement scheme of the present application.
In the layout design process of an integrated circuit, at present, redundant metal is filled in a metal block array mode, and fig. 1 is an example of the metal block array; because the redundant metal has the limitation of metal-to-metal spacing under the limitation of the process, when the redundant metal is filled in the metal block array manner, the requirement of the process on metal density cannot be well met by only filling the redundant metal outside the inductor, and the redundant metal often needs to be filled inside the inductor, and fig. 2 is an example of filling the redundant metal in the metal block array manner outside and inside the inductor or the inductor device.
In view of the above, the applicant proposes to fill the periphery of the inductor with a strip of metal, the density of the metal arranged in the form of metal strips being greater than that of the metal block array, so that it is possible to reduce or avoid filling the inside of the inductor with redundant metal. Fig. 3 is an example of the arrangement of metal strips, and fig. 4 is an example of the arrangement of metal strips around the outside of the inductor and capable of meeting the process requirements for metal density.
This metal filling method is compared below.
It is not to be taken as an example that the side length of the redundant metal blocks in fig. 1 is 1um, and the distance between the redundant metal blocks is also 1um, if the arrangement is expanded infinitely, the space density occupied by the redundant metal is 25%. Taking fig. 3 as an example, when the strip-shaped redundant metals with the length of 9um and the width of 1um or the strip-shaped redundant metals are arranged at the same interval, i.e. 1um, if the arrangement mode is infinitely expanded downwards, the space density occupied by the redundant metals is 50%. Compared with the former, the filling mode of the latter can more easily meet the requirement of the process on the metal density under the condition of the same area.
As can be seen from the above analysis, since the metal block array itself only occupies 25% of the space density, it is difficult to meet the requirement of the process on the minimum metal density under the condition of occupying a smaller area, and therefore, the manner of filling the metal array with the redundant metal often needs more area to meet the requirement of the process metal density, for example, the redundant metal needs to be filled inside the inductor; because the magnetic flux density inside the inductor is higher, the redundant metal inside the inductor generates larger induced current under the alternating magnetic field compared with the metal around the outside of the inductor, and the quality factor of the inductor is reduced more remarkably.
In consideration of the situation, the filling mode of the redundant metal is improved, and the strip redundant metal is used for replacing the block redundant metal. Under the condition that the redundant metal occupies the same space, the space density of the strip-shaped redundant metal is far greater than that of the block-shaped redundant metal, so that the requirement of the process on the metal density can be met only by filling a small amount of redundant metal in the inductor or even when the redundant metal is not required to be filled in the inductor.
The redundant metal in the strip shape is used for replacing the massive redundant metal, so that the filling of the redundant metal in the area with larger magnetic flux density in the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved.
Further, although the magnetic flux density outside the inductor is less than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor still generates an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will reduce the quality factor of the inductor — the dashed line in fig. 5 shows the direction in which the alternating magnetic field generated by the inductor generates an induced current in the outer conductor parallel to the inductor coil. Considering this situation, the strip-shaped redundant metal filled outside the inductor is not arranged along the direction of the inductor coil or the induced current, which can further reduce the loss of the induced current in the filler metal, for example, fig. 6 is an example; furthermore, when the strip-shaped redundant metal is arranged along the direction of the coil or induced current of the vertical inductor, the gaps between the strips cut off the current flow path, which can further significantly reduce the loss of the induced current in the metal, as shown in fig. 4.
Therefore, in some embodiments, the present patent proposes to fill the strip-shaped redundant metal outside the inductor, so as to satisfy the metal density and reduce the influence of the filling of the redundant metal on the quality factor of the inductor, and further, the strip-shaped redundant metal is radially disposed around the outside of the inductor in a direction perpendicular to the induced current generated by the inductor to reduce the ohmic loss of the current as much as possible, thereby further reducing the influence of the filling of the redundant metal on the quality factor of the inductor.
It should be noted that in the strip-shaped redundant metal of the present invention, "strip" is used to define that the redundant metal is strip-shaped or strip-shaped as a whole, and such a shape may be a rectangle as in fig. 7(a), and an arc shape, for example, a semicircle, at both ends as in fig. 7 (b). When discussing the arrangement direction of the strip-shaped redundant metal, the invention is defined by the long axis direction of the strip-shaped redundant metal, for example, the direction of the long axis of the strip-shaped redundant metal is perpendicular to the direction of the inductance coil or the induced current, which means that the direction of the long axis of the strip-shaped redundant metal is perpendicular to the direction of the inductance coil or the induced current. The specific size and number of redundant metal strips when they are filled may be determined based on metal density requirements, etc.
In some embodiments of the invention, a method of manufacturing a chip is disclosed. The chip is a carrier of an integrated circuit, and the manufacturing method of the chip is a method for miniaturizing and manufacturing a circuit on the surface of a semiconductor wafer; specifically, a silicon wafer is generally used as a base layer, and then components such as MOSFET or BJT are fabricated by using processes such as photolithography, doping, and CMP, and then conductive lines are fabricated by using processes such as thin film and CMP, thereby completing the fabrication of a chip. The chip manufacturing complete process includes several links such as chip design, wafer manufacturing, package manufacturing and testing, wherein the wafer manufacturing process is particularly complex.
Referring to fig. 8, a method for manufacturing a chip according to some embodiments includes the following steps:
step 101: and cleaning and drying the silicon wafer.
During the manufacturing process, a silicon wafer or a silicon wafer is first cleaned to remove various impurities on the surface of the silicon wafer or the silicon wafer. Semiconductor devices are typically manufactured by a series of process steps including doping a silicon wafer with appropriate impurities (usually at a level of ppm), depositing a suitable thin film on the surface of the silicon wafer, and performing photolithography and etching to form a specific pattern, so that the actual producibility of the process steps can be achieved only by controlling the contamination level of the various extraneous impurities in advance without affecting the device characteristics and the chip yield. In practical applications, this requires that the concentration of extraneous impurities be controlled to below parts per million, or even parts per billion, while the effects of stray particles must be effectively removed.
It will be appreciated that at the end of each of the other steps shown in figure 8, further washing and drying may be performed.
It will be appreciated that some preliminary preparation is required before the fabrication is started, such as selecting the silicon wafer specification and the type of dopant ions according to the design circuit requirements.
Step 103: and oxidizing the cleaned silicon wafer.
In the chip manufacturing process, silicon dioxide is produced on the smooth surface of a silicon wafer through an oxidant and a gradual temperature rise condition, and the process can be called oxidation or thermal oxidation. In the whole chip manufacturing process, silicon dioxide formed by oxidizing a silicon wafer has a plurality of functions, such as surface passivation, a doping barrier layer, a surface insulator and a device insulator, wherein the surface passivation function means that the surface and the interior of a device can be protected by forming silicon dioxide with very high density on the surface of the silicon wafer; the function of the doped barrier layer is that the silicon dioxide can form a barrier protective layer to prevent the adulterant from invading the silicon surface; the surface insulator functions to prevent short circuit between adjacent upper and lower metal layers by the oxide layer of silicon dioxide, and the oxide layer with enough thickness can be used to prevent induction generated from the metal, namely field oxide; the function of the device insulator means that the oxide layer can function as a dielectric, and a gate electrode below the oxide layer can generate a sensing current.
Step 105: and carrying out well region photoetching on the oxidized silicon wafer according to the circuit design on the mask.
Photolithography is a cornerstone of modern IC manufacturing that enables the printing of sub-micron sized patterns on silicon wafer substrates. The principle of photolithography is to spin-coat a photosensitive photoresist on a silicon wafer to form a thin film on the surface, and then use a photomask, which contains the pattern information of the specific layer to be made, i.e. the mask in step 110, and a light source irradiates the photoresist through the photomask to selectively expose the photoresist; the photoresist is then developed and the pattern transfer from the plate to the silicon wafer is completed. The photoresist is then etched, and the underlying thin film layer may be etched, or may be used as a mask during ion implantation doping.
Step 107: and after the photoetching is finished, carrying out wet etching on the silicon wafer to remove silicon dioxide, and forming a well region injection hole.
The wet etching is a pure chemical etching, has excellent selectivity, and stops when the current film is etched without damaging the film of other materials below.
Step 109: and carrying out ion implantation on the silicon wafer to form a trap.
Ion implantation, which is a technique that combines ion sorting, acceleration, and dose measurement to introduce precise impurity atoms into a silicon substrate, provides a very precise method of incorporating a specific dose or amount of impurity atoms into silicon.
Step 111: and carrying out rapid thermal annealing on the silicon wafer subjected to ion implantation.
Rapid Thermal Annealing (RTA) is a process in the chip manufacturing process that is generally used to activate doping elements in semiconductor materials and restore the amorphous structure caused by ion implantation to a complete lattice structure. Specifically, the rapid thermal annealing process may be a process of rapidly heating the silicon wafer from ambient temperature to about 1000-.
Step 113: and isolation is carried out by adopting a shallow trench isolation process.
Shallow Trench Isolation (STI) is a process for Isolation from silicon by forming a Trench after depositing, patterning, and etching silicon using a silicon nitride mask, and filling the Trench with a deposited oxide.
Step 115: and oxidizing the silicon wafer, depositing polycrystalline silicon after the oxidation is finished, and carrying out active area photoetching according to the circuit design on the mask.
Step 117: and after the photoetching is finished, removing the polysilicon by adopting dry etching to form a gate and an active region injection hole.
Dry etching is a technique of performing thin film etching using plasma. When the gas is present in the form of a plasma, it has two characteristics: on one hand, the chemical activity of the gases in the plasma is much stronger than that of the gases in a normal state, and the gases can react with the materials more quickly by selecting proper gases according to the difference of the etched materials, so that the aim of etching removal is fulfilled; on the other hand, the electric field can be used for guiding and accelerating the plasma, so that the plasma has certain energy, and when the plasma bombards the surface of the etched object, atoms of the etched object material can be knocked out, thereby achieving the purpose of etching by utilizing physical energy transfer. Thus, dry etching is a result of a balance of both physical and chemical processes on the wafer surface. Dry etching can be classified into three types: physical etching, chemical etching, physical chemical etching.
Step 119: and carrying out ion implantation on the silicon wafer to form a source electrode and a drain electrode.
Step 121: and carrying out rapid thermal annealing on the silicon wafer subjected to ion implantation.
Step 123: forming boron-phosphorus-silicon glass on the surface of a silicon wafer by using a chemical vapor deposition process, and photoetching through holes (namely lead holes) according to the circuit design on a mask.
The thin film process refers to a processing process for forming a desired thin film on the surface of a silicon wafer. These particular thin films include insulators, semiconductors, or conductors. The main thin film techniques include Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and the like. Most of the thin films in integrated circuit fabrication are deposited by CVD techniques. The principle of CVD is to form a specific kind of thin film by chemical components containing the required atoms or molecules, which are mixed in a reaction chamber and reacted in a gaseous state so that the atoms or molecules thereof are deposited on the surface of a silicon wafer. The chemical reactions used are generally divided into pyrolysis, reduction, oxidation, nitridation. Pyrolysis refers to a chemical reaction that proceeds solely by heat. Reduction is a chemical reaction of molecules, hydrogen. Oxidation is a chemical reaction of atoms, molecules and oxygen. Nitridation mainly refers to a chemical reaction that forms a silicon nitride film on the surface of a silicon wafer.
Step 125: and removing the borophosphosilicate glass by dry etching after the photoetching is finished, and depositing the through hole metal by using a physical vapor deposition process.
Unlike chemical vapor deposition, which relies on chemical reactions to generate reactive particles to form a film, the physical vapor deposition method mainly uses a physical process to deposit the film, i.e., the physical process is used to transfer atoms or molecules from a gas source to the surface of a silicon wafer. PVD techniques are more versatile than CVD methods in that it allows the deposition of almost any material.
A typical integrated circuit chip is composed of multiple metal layers, which are connected by VIAs (VIA).
Step 127: forming a metal layer on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, the preset rule comprising: one or more strip-shaped redundant metals are arranged outside the inductance device of the metal layer.
In some embodiments, the strip-shaped redundant metal filled outside the inductor is not arranged along the direction of the induced current, which can further reduce the loss of the induced current in the filler metal. Furthermore, when the strip-shaped redundant metal is arranged along the direction perpendicular to the induced current, the gaps between the strips cut off the flow path of the current, which can further remarkably reduce the loss of the induced current in the metal.
Step 129: the metal layer filled with the redundant metal is subjected to chemical mechanical polishing to be planarized.
After the metal layer is grown, the difference between the uneven metal thickness and the etching concentration is formed on the surface of the silicon wafer, and the purpose of Chemical Mechanical Polishing (CMP) is to remove the excess metal so that the metal layers have the same height. In the CMP, two functions, i.e., chemical and mechanical, are combined when a metal layer is planarized, and a polishing solution containing chemical components acts on a layer to be polished simultaneously through mechanical and chemical effects.
Step 131: and testing and packaging the silicon chip.
The packaging is mainly used for realizing the connection and protection between the internal circuit and the external circuit of the chip. The silicon chip testing is to detect whether the silicon chip or the chip has design defects or physical defects caused by the manufacturing process by using various testing methods. In order to ensure that the chip can be used normally, the last two processes must be passed before the chip is delivered to the manufacturer of the whole machine: and packaging and testing.
The above are some descriptions of the methods of manufacturing the chips disclosed in the present invention. In other embodiments, the invention also discloses a chip manufactured by the method for manufacturing the chip disclosed by the invention. It is expected that the chip manufactured by the method for manufacturing a chip disclosed in the present invention may have a specific structure in the metal layer, for example, the exterior of the inductor device is filled with one or more strip-shaped redundant metals, further, the strip-shaped redundant metals are not parallel to the induced current direction of the inductor device, and further, the strip-shaped redundant metals are perpendicular to the induced current direction of the inductor device. Therefore, in one embodiment, the chip manufactured by the chip manufacturing method disclosed by the invention has the strip-shaped redundant metals radially arranged around the outer part of the inductor.
In other embodiments of the invention, a method for filling redundant metal is disclosed. Generally, filling of redundant metal is completed in a wafer manufacturing plant or a chip manufacturing room, the filling of redundant metal is located at the final stage of Layout physical Design, timing, Layout Logic Verification (LVS), Design Rule verification (DRC), and the like, have passed, and the Layout Design has been finalized.
Referring to fig. 9, another embodiment of the present invention discloses a method for filling a redundant metal, including the following steps:
step 191: an integrated circuit layout to be filled is obtained, wherein the integrated circuit layout comprises one or more metal layers.
Step 193: filling redundant metal at least for one metal layer according to a preset rule; wherein the preset rule comprises: and filling one or more strip-shaped redundant metals outside the inductance device of the metal layer.
In the layout design of the integrated circuit, the filling of the redundant metal is a process of the post-processing of the layout, and step 193 proposes a rule of filling the redundant metal in the metal layer, that is, filling one or more strip-shaped redundant metals outside the inductor device of the metal layer. By filling the strip-shaped redundant metal, the filling of the redundant metal in the area with higher magnetic flux density in the inductor is reduced or even avoided, and the quality factor of the inductor is effectively improved. Further, although the magnetic flux density outside the inductor is less than the magnetic flux density inside the inductor, the alternating magnetic field generated by the inductor still induces an induced current in the outer conductor parallel to the inductor coil, and the ohmic loss of this part of the current will reduce the quality factor of the inductor. Considering this case, the strip-shaped redundant metal filled outside the inductor in step 193 is not placed along the direction of the induced current, which can further reduce the loss of the induced current in the filler metal; further, the step 193 fills the strip-shaped redundant metal outside the inductor, the strip-shaped redundant metal is arranged along the direction perpendicular to the induced current, and the gaps among the strips cut off the flowing path of the current, so that the loss of the induced current in the metal can be further remarkably reduced.
In addition, there are a number of ways to identify and locate inductive devices in an integrated circuit layout. In some methods, according to the identification layer provided by a designer, a corresponding identification layer is usually provided for a special device such as an inductor, and if the chip factory needs the method, the designer can be required to reserve the identification layer when providing original design data and transmit the original design data to the chip factory through hierarchical conversion; in other methods, the designs have a fixed shape, such as an inductive device, with a metal layer pattern of parallel metal loops that exist as an inductive coil.
The above are some descriptions of the filling method of the redundant metal disclosed in the present invention. In other embodiments, the invention also discloses a chip manufactured by the filling method of the redundant metal disclosed by the invention. It is foreseen that the chip manufactured by the method for filling the redundancy metal disclosed in the present invention has a specific structure in the metal layer, for example, one or more strip-shaped redundancy metals are filled outside the inductor device, further, the strip-shaped redundancy metals are not parallel to the induced current direction of the inductor device, and further, the strip-shaped redundancy metals are perpendicular to the induced current direction of the inductor device. Therefore, in one embodiment, the chip manufactured by the filling method of the redundant metal disclosed by the invention has the strip-shaped redundant metal radially arranged around the outer part of the inductor.
Referring to fig. 10, in some embodiments of the present invention, a chip of an integrated circuit is further disclosed, where the chip includes one or more metal layers, at least one of the metal layers is provided with an inductance device 11, and one or more strip-shaped redundant metals 12 are filled outside the inductance device, where fig. 10 is a schematic partial area diagram of the metal layer provided with the inductance device 11, and 13 is a metal line or a signal line. In some embodiments, the strip-shaped redundant metals 12 are not parallel to the coil direction of the inductive device 11, or the strip-shaped redundant metals 12 are not parallel to the direction of an induced current generated in the strip-shaped redundant metals 12 by the inductive device 11 due to the generated alternating magnetic field. In some embodiments, the strip-shaped redundant metal 12 is perpendicular to the direction of the coil of the inductance device 11, or the strip-shaped redundant metal 12 is perpendicular to the direction of the induced current generated in the strip-shaped redundant metal 12 by the inductance device 11 due to the generated alternating magnetic field.
The application provides a technical scheme for radially filling strip-shaped redundant metal around an inductor. Compared with the method of filling the redundant metal in the form of the metal block array, the method can meet the requirement of the process on the metal density more easily, so that the redundant metal is prevented from being filled in the inductor. For example, the radial metal strips perpendicular to the induction current direction of the inductor are arranged around the outside of the inductor, so that the loss of the inductor quality factor caused by redundant metal is effectively inhibited on the premise of meeting the process production requirement, and compared with a general method for uniformly filling the redundant metal, the inductor with a higher quality factor can be obtained. Simulation results show that the method can be applied to the inductor working at 15GHz to 70GHz, the quality factor is improved by 7% -17%, and the following specific description is provided.
The invention uses simulation software (such as HFSS electromagnetic simulation software) to respectively carry out quality factor simulation on two different inductors A, B and a coupling inductor; in the quality factor simulation of each inductor, the condition that no redundant metal is added, the inductor is filled with redundant metal blocks in an array mode around the inductor, and the inductor is filled with strip-shaped redundant metal in a radiating mode around the inductor is simulated, and the condition is specifically described below.
(1) Simulation on inductance A
A two-turn inductor a with an inductance of 0.38nH and an inner diameter of 35um was simulated, the inductor design and the filling manner of the redundant metal are shown in fig. 11(a), 11(b), and 11(c), wherein fig. 11(a) is to fill the inductor a with no redundant metal, fig. 11(b) is to fill the inductor a with redundant metal or block redundant metal in a block array manner, fig. 11(c) is to fill the inductor a with strip redundant metal in a radial manner, electromagnetic field simulation was performed for these three cases, and the relationship of the inductance quality factor with frequency change was obtained according to the above calculation formula of the inductance quality factor Q, which is shown in fig. 12. As can be seen from fig. 12, the maximum value of the Q factor of the inductor is 16.04 when no redundant metal is filled; when the redundant metal is filled in a block array mode, the maximum value of the inductance quality factor Q is 14.93, and compared with an ideal condition (namely the condition that the redundant metal is not filled), the quality factor is reduced by (16.04-14.93)/16.04 which is 6.9%; according to the method for radially filling the strip-shaped redundant metal provided by one embodiment of the present invention, the maximum Q-factor of the inductor is 15.97, which is reduced by (15.97-16.04)/16.04-0.44% compared with the ideal case, while the Q-factor is improved by (15.97-14.93)/14.93-7.0% compared with the original block-shaped array filling method. In addition, it can be seen that the frequencies corresponding to the maximum values of the Q-factor of the inductance after the three filling modes are different, which is caused by the parasitic capacitance introduced by the redundant metal.
(2) Simulation on inductance B
Two loops of inductors B with the inductance value of 0.26nH and the inner diameter of 23um are simulated, the inductor design and the filling mode of redundant metal are shown in figures 13(a), 13(B) and 13(c), wherein figure 13(a) is to fill no redundant metal in the inductor B, figure 13(B) is to fill redundant metal or block redundant metal in the inductor B according to the block array mode, figure 13(c) is to fill strip redundant metal in the inductor B in a radial mode, electromagnetic field simulation is carried out on the three conditions, and the relation of the inductance quality factor changing along with the frequency is obtained according to the calculation formula of the inductance quality factor Q, and the relation is shown in figure 14. As can be seen from fig. 14, the maximum Q value of the Q factor is 17.45 when no redundant metal is filled, and the maximum Q value of the Q factor is 15.82 when the redundant metal is filled in a block array manner, which is 9.3% lower than the ideal case; according to the method for radially filling the strip-shaped redundant metal provided by the embodiment of the invention, the maximum value of the inductance quality factor Q is 16.92, the quality factor is reduced by only 3.0% compared with the ideal condition, and the quality factor is improved by 6.9% compared with the original block array filling method.
(3) Simulation on coupled inductors
The invention can be applied to single-port inductors and also can be applied to coupling inductors. As shown in fig. 15(a), 15(b), and 15(c), for one turn ratio of 2: 1, performing three-dimensional modeling and electromagnetic simulation on the coupling inductor under the three different filling conditions, specifically, fig. 15(a) is to fill the coupling inductor with no redundant metal, fig. 15(b) is to fill the coupling inductor with redundant metal or with massive redundant metal in a block array manner, and fig. 15(c) is to fill the coupling inductor with strip-shaped redundant metal in a radial manner; the periphery of the inductor after the massive array and the radiation strip-shaped redundant metal are filled meets the requirements of the process on metal density.
After the simulation, the Q factor of the primary coil is calculated according to the above calculation formula of the Q factor of the inductance to obtain the relationship between the Q factor of the inductance and the frequency variation under the condition that the port of the secondary coil is connected with the 50 Ω load, and the result is shown in fig. 16. As can be seen from fig. 16, the primary coil quality factor qmax is 19.86 without any redundant metal filling; when redundant metal is filled in a block array mode, the maximum value of the quality factor Q of the primary coil is 15.89, and compared with an ideal situation, the quality factor is reduced by 20%; according to the method for radially filling the strip-shaped redundant metal provided by the embodiment of the invention, the quality factor Qmax of the primary coil is 18.69, the quality factor is reduced by only 5.9% compared with the ideal condition, and the quality factor is improved by 17.6% compared with the original block array filling method. The secondary coil quality factor Q as a function of frequency is shown in fig. 17. As can be seen from fig. 17, the maximum value of the quality factor qm of the secondary coil when no redundant metal is filled is 11.07; when redundant metal is filled in a block array mode, the maximum value of the quality factor Q of the secondary coil is 10.08, and compared with an ideal situation, the quality factor is reduced by 8.9%; according to the method for radially filling the strip-shaped redundant metal provided by the embodiment of the invention, the quality factor Qmax of the secondary coil is 10.81, the quality factor is reduced by only 2.3% compared with the ideal condition, and the quality factor is improved by 7.2% compared with the original filling method of the uniform block array.
The following table summarizes the simulation results of the inductance quality factors of the inductor A, B and the coupling inductor, where method 1 refers to a method for filling a block array, and method 2 refers to a method for filling a strip-shaped redundant metal in a radial manner according to an embodiment of the present invention, and it can be known from the following table that the present invention can effectively prevent the reduction of the inductance quality factor caused by adding the redundant metal; under the condition of meeting the metal density of the process requirement, the quality factor of the inductor obtained by the redundant metal filling scheme provided by the invention is improved by about 7% compared with the common redundant metal filling mode, and the invention can also be applied to the coupling inductor.
In order to address the situation that redundant metal needs to be filled around the inductor due to the requirement of metal density in the chip production process, in some embodiments, a filling technology for placing radial strip-shaped metal perpendicular to the direction of an induced electric field is provided; the technology relieves the problem that the allowable use area of an INDDMY layer in the design of analog and radio frequency circuits is not enough to design and use due to process limitation. Simulation shows that the technology not only meets the metal density of the process requirement under the condition of neglecting the metal density check without using an INDDMY layer, but also cuts off an induced current path and avoids filling metal in the inductance coil. The electromagnetic full wave simulation shows that compared with the conventional mode of uniformly filling the massive array redundant metal, the technology can effectively reduce the loss of the redundant metal to the inductor, and is very favorable for designing the high-Q-value single-port inductor and the coupling inductor.
Reference is made herein to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope hereof. For example, the various operational steps, as well as the components used to perform the operational steps, may be implemented in differing ways depending upon the particular application or consideration of any number of cost functions associated with operation of the system (e.g., one or more steps may be deleted, modified or incorporated into other steps).
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. Additionally, as will be appreciated by one skilled in the art, the principles herein may be reflected in a computer program product on a computer readable storage medium, which is pre-loaded with computer readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CD-to-ROM, DVD, Blu-Ray discs, etc.), flash memory, and/or the like. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data processing apparatus create means for implementing the functions specified. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including means for implementing the function specified. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified.
While the principles herein have been illustrated in various embodiments, many modifications of structure, arrangement, proportions, elements, materials, and components particularly adapted to specific environments and operative requirements may be employed without departing from the principles and scope of the present disclosure. The above modifications and other changes or modifications are intended to be included within the scope of this document.
The foregoing detailed description has been described with reference to various embodiments. However, one skilled in the art will recognize that various modifications and changes may be made without departing from the scope of the present disclosure. Accordingly, the disclosure is to be considered in an illustrative and not a restrictive sense, and all such modifications are intended to be included within the scope thereof. Also, advantages, other advantages, and solutions to problems have been described above with regard to various embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any element(s) to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, system, article, or apparatus. Furthermore, the term "coupled," and any other variation thereof, as used herein, refers to a physical connection, an electrical connection, a magnetic connection, an optical connection, a communicative connection, a functional connection, and/or any other connection.
Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined only by the claims.
Claims (7)
1. A method of manufacturing a chip, comprising:
cleaning and drying the silicon wafer;
oxidizing the cleaned silicon wafer;
performing well region photoetching on the oxidized silicon wafer according to the circuit design on the mask;
after photoetching, carrying out wet etching on the silicon wafer to remove silicon dioxide and form a well region injection hole;
performing ion implantation on the silicon wafer to form a trap;
carrying out rapid thermal annealing on the silicon wafer subjected to ion implantation;
isolating by adopting a shallow slot isolation process;
oxidizing a silicon wafer, depositing polycrystalline silicon after the oxidation is finished, and carrying out active area photoetching according to the circuit design on a mask;
removing the polysilicon by dry etching after the photoetching is finished to form a gate and an active region injection hole;
performing ion implantation on the silicon wafer to form a source electrode and a drain electrode;
carrying out rapid thermal annealing on the silicon wafer subjected to ion implantation;
forming boron-phosphorus-silicon glass on the surface of a silicon wafer by using a chemical vapor deposition process, and carrying out through hole photoetching according to the circuit design on a mask;
removing the borophosphosilicate glass by dry etching after photoetching is finished, and depositing through hole metal by utilizing a physical vapor deposition process;
forming a metal layer on the surface of the silicon wafer by using a physical vapor deposition process; wherein the metal layer is filled with redundant metal according to a preset rule, the preset rule comprising: filling a plurality of strip-shaped redundant metals outside an inductance device of a metal layer, wherein the redundant metals are not filled inside the inductance device, an INDDMY layer is not arranged inside the inductance device, and the INDDMY layer is used for skipping metal density detection of a framed region; the working frequency of the inductance device is 15GHz to 70 GHz; the strip-shaped redundant metal is not parallel to the coil direction of the inductance device;
performing chemical mechanical polishing on the metal layer filled with the redundant metal to planarize the metal layer;
and testing and packaging the silicon chip.
2. The manufacturing method according to claim 1, wherein the strip-shaped redundant metal is perpendicular to a coil direction of the inductance device.
3. A chip manufactured according to the manufacturing method of claim 1 or 2.
4. A method for filling a redundant metal, comprising:
acquiring an integrated circuit layout to be filled, wherein the integrated circuit layout comprises one or more metal layers;
filling redundant metal at least for one metal layer according to a preset rule; wherein the preset rule comprises: identifying an inductance device in which the metal layer to be filled exists, and filling a plurality of strip-shaped redundant metals outside the inductance device, wherein the redundant metals are not filled inside the inductance device, an INDDMY layer is not arranged inside the inductance device, and the INDDMY layer is used for detecting the metal density of a framed area in a skipping mode; the working frequency of the inductance device is 15GHz to 70 GHz; the strip-shaped redundant metal is not parallel to the coil direction of the inductance device.
5. The filling method according to claim 4, wherein the strip-shaped redundant metal is perpendicular to a coil direction of the inductance device.
6. A chip manufactured according to the filling method of claim 4 or 5.
7. A computer-readable storage medium, characterized in that the computer-readable storage medium has a program which can be executed by a processor to implement the method according to any one of claims 1 to 2 or 4 to 5.
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| US7663205B2 (en) * | 2004-08-03 | 2010-02-16 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a dummy gate structure below a passive electronic element |
| JP4908035B2 (en) * | 2006-03-30 | 2012-04-04 | 株式会社東芝 | Semiconductor integrated circuit |
| US7652348B1 (en) * | 2006-07-27 | 2010-01-26 | National Semiconductor Corporation | Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits |
| CN102082143B (en) * | 2009-12-01 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Figure filler structure inserted about inductor |
| JP5494214B2 (en) * | 2010-05-14 | 2014-05-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2013101102A1 (en) * | 2011-12-29 | 2013-07-04 | Intel Corporation | Inductor design with metal dummy features |
| CN102543853B (en) * | 2011-12-31 | 2016-03-30 | 中国科学院微电子研究所 | Redundancy metal fill method and integrated circuit layout structure |
| US20140252542A1 (en) * | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and Method for an Inductor With Metal Dummy Features |
| TWI509771B (en) * | 2013-03-25 | 2015-11-21 | Realtek Semiconductor Corp | Integrated inductor and integrated inductor fabricating method |
| CN104810244B (en) * | 2014-01-26 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices, semiconductor devices and electronic device |
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