KR20080025191A - A semiconductor device including a vertical decoupling capacitor - Google Patents

Abstract

A vertical or three-dimensional non-planar configuration for a decoupling capacitor (240, 340, 440, 540) is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors (240, 340, 440, 540) also provides enhanced pattern uniformity during the highly critical gate patterning process. ® KIPO & WIPO 2008

Description

A SEMICONDUCTOR DEVICE INCLUDING A VERTICAL DECOUPLING CAPACITOR}

FIELD OF THE INVENTION The present invention relates generally to the field of integrated circuit fabrication, and more particularly to the formation of semiconductor devices comprising field effect transistors such as MOS transistors and decoupling capacitors for reducing switching noise.

In modern integrated circuits, a large number of individual circuit elements, for example field effect transistors, resistors, capacitors, etc. in the form of CMOS, NMOS, PMOS devices, are formed in a single chip region. Typically, the feature size of these circuit elements is steadily decreasing as new circuit generations are introduced each time, in order to provide improved performance to the currently available integrated circuits in speed and / or power consumption. Transistor size reduction is an important factor for continuous improvement of device performance in complex integrated circuits such as CPUs. In general, reducing the size increases the switching speed, which improves signal processing performance and increases the dynamic power consumption of individual transistors. That is, with the reduction of the switching time period, the transistor current is greatly reduced when switching the CMOS transistor element from logic low to logic high.

On the other hand, a number of problems arise in the deep sub-micron regime that can partially offset the benefits obtained by improved switching performance due to the reduction in feature size, such as the channel length of transistor devices. For example, in order to reduce the channel length of the field effect transistor, it is necessary to reduce the thickness of the gate insulator layer, since it is necessary to appropriately control the formation of the conductive channel established when the control voltage is applied to the gate electrode. This is to maintain a sufficiently high capacitive coupling of the gate electrode. For very sophisticated devices that currently feature channel lengths of 0.1 μm or even less, the thickness of the gate insulation layer typically including silicon dioxide for the good and well-known properties of the interface between the silicon oxide and the underlying channel region is about 1.5-3 nm or even less. For gate dielectrics of this magnitude, it turns out that, as a whole, the leakage current through the thin gate dielectric can be compared with the transient current because the leakage current rises exponentially as the gate dielectric thickness decreases linearly. to be.

In addition to many transistor elements, a plurality of passive capacitors are typically formed in integrated circuits used for various purposes such as decoupling. Decoupling in integrated circuits is important to reduce the switching noise of fast switching transistors, because decoupling capacitors can provide energy at certain points in the circuit, for example, the position of fast switching transistors, so if not This is because it can reduce the voltage change that can inadequately affect the logic state represented by. Since these capacitors are generally formed in the active semiconductor region and on the active semiconductor region, significant die area is consumed by the decoupling capacitors. Typically, such capacitors are formed in a flat configuration over the active semiconductor region, which acts as the first capacitor electrode. The capacitor dielectric is formed during the process of manufacturing the gate insulating layer of the field effect transistor, where the gate material is generally patterned with the gate electrode structure to serve as the second capacitor electrode. Thus, in addition to a significant consumption of die area, leakage current may increase in devices requiring high capacitive decoupling elements, whereby this may contribute significantly to the overall static leakage consumption and thus to the overall power consumption of the integrated circuit. Can contribute. For sophisticated applications, in terms of power consumption and / or thermal management, large amounts of static power consumption are unacceptable, so in general so-called dual gate oxide processing can be used to increase the thickness of the dielectric layer of capacitors and Thus, leakage currents of these devices can be reduced.

Referring now to FIGS. 1A-1C, a typical conventional process flow for forming a semiconductor device including a high capacitive decoupling capacitor with moderate leakage current is now described. 1A schematically illustrates a cross-sectional view of a semiconductor device 100 at a particular fabrication stage. The semiconductor device 100 includes a substrate 101, for example silicon, comprising a first semiconductor region 130 for receiving transistor elements and a second semiconductor region 120 for receiving a high capacitance decoupling capacitor. It includes a substrate. Thus, unlike the semiconductor region 13, the semiconductor region 120 may occupy a substantial portion of the functional block of the device 100. The first semiconductor region 130 and the second semiconductor region 120 are surrounded by respective isolation structures 102. The isolation structure 102, which partially corresponds to the first semiconductor region 130, is covered with a mask layer 103, which may be composed of photoresist. Second semiconductor region 120 includes surface portion 104 having severe lattice damage caused by ion implantation as indicated by 105.

Typical flows for forming a semiconductor device as shown in FIG. 1A include sophisticated photolithography and etching techniques to define the isolation structure 102 and subsequent photolithography steps for patterning the resist mask 103 thereafter. do. This process technique is well known in the art, and thus its detailed description is omitted. Subsequently, ion implantation 105 is performed with any suitable ions such as silicon, argon, xenon, and the like, where the dose and energy are selected to produce severe lattice damage to the portion 104, thereby Greatly changes the diffusion form of the part 104 during the oxidation process to be performed subsequently.

1B schematically shows a semiconductor structure 100 in an improved manufacturing step. A first dielectric layer 131 (substantially composed of silicon dioxide and having a first thickness 132) is formed on the first semiconductor region 130. A second dielectric layer 121 (having a second thickness 122 and made of the same material as the first dielectric layer 131) is formed on the second semiconductor region 120. The first dielectric layer 131 and the second dielectric layer 121 are formed by a conventional oxidation process in a high temperature furnace or by a high speed thermal oxidation process. Due to the severe lattice damage of the surface portion 104, the oxygen diffusion in this surface portion 104 is, for example, compared to the silicon portion having substantially undisturbed crystallinity, for example in the first semiconductor region ( As in the surface area of 130). In conclusion, oxide growth in the second semiconductor region 120 and oxide growth on the second semiconductor region 120 increase compared to the growth rate of the first semiconductor region 130, so that the first thickness 132 is increased. Is different from the second thickness 122 by about 0.2-1.0 nm relative to the thickness of the first dielectric layer 131, and the second thickness is about 1-5 nm.

1C schematically illustrates a semiconductor device 100 in a more advanced fabrication stage, in which a decoupling capacitor 140 is formed in and on the second semiconductor region 120 and the electric field. Effect transistor 150 is formed in and on first semiconductor region 130. Transistor element 150 includes, for example, gate electrode 133 comprising highly doped polysilicon and metal silicide portion 135. Furthermore, sidewall spacers 134 are formed adjacent to the sidewall of the gate electrode 133. Source and drain regions 136 (each including metal silicide portion 135) are formed in first semiconductor region 130. The capacitor 140 includes a conductive electrode 123 made of the same material as the gate electrode 133 and formed over the second dielectric layer 121. Electrode 123 represents the first electrode of capacitor 140. Capacitor electrode 123 includes metal silicide portion 125 and is surrounded by sidewall spacer element 124.

A typical process flow for forming transistor device 150 and capacitor 140 may include the following steps. The polysilicon layer may be deposited over the device as shown in FIG. 1B and patterned by known photolithography and etching techniques to create the capacitor electrode 123 and the gate electrode 133 in a common process. have. As a result, the drain and source region 136 is formed by ion implantation, where the sidewall spaces 134 and sidewall spacers 124 are formed intermittently, so that the sidewall spacers 134 operate as implant masks. As a result, the dopant concentrations of the drain and source regions 136 can be appropriately formed. The metal silicide portions 125 and 135 then deposit a refractory metal and between the metal and the underlying polysilicon of the capacitor electrode 123, the gate electrode 133, and the silicon in the drain and source region 136. It can be formed by initiating a chemical reaction of.

As is apparent from FIG. 1C, the capacitor 140 with the second dielectric layer 121 with the increased thickness 122 has a second thickness optimized for providing the required dynamic performance of the transistor 150. 132 shows a reduced leakage current ratio compared to the corresponding leakage current ratio generated by the relatively thin first dielectric layer 131. Although an excellently improved leak rate of the capacitor 140 can be obtained with the conventional method described above, one critical drawback is the capacitance per unit area of the capacitor 140 due to the increased thickness of the second dielectric layer 121. The turn is greatly reduced. Thus, for the given and required charge storage capability as required for the enhanced decoupling effect, a much larger area is needed for the capacitor 140. Another disadvantage of the prior art is that it requires a high temperature oxidation process to form the first dielectric layer 131 and the second dielectric layer 121, so this process approach is an improvement for forming extremely thin gate insulator layers. It is not compatible with alternative methods for forming very thin gate insulators, such as a deposited deposition method. Moreover, this process flow described above is such that an area with a very non-uniform pattern density, i.e., an increased dimension representing, for example, capacitor 140, is located around a very small area, such as transistor 150, which is a gate Patterning processes for forming very critical gate electrodes such as electrode 133 can be difficult.

In view of those described above, there is a need for an improved technique that can form capacitors while avoiding or at least reducing the impact of one or more of the problems identified above.

The following provides a simplified overview of the invention to provide a basic understanding of some embodiments of the invention. This summary is not an overview that is intended to describe all possible embodiments of the invention. It is not intended to identify key or critical elements of the invention or to limit the scope of the invention. Its purpose is merely to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

In general, the present invention is directed to semiconductor devices and corresponding manufacturing methods, where chip area can be saved, and thus can be used for other circuits, because high charge carrier storage capabilities (such as decoupling capacitors) This is because capacitors of high charge carrier storage capability are formed in three-dimensional or vertical configurations. By providing a three-dimensional configuration, the "two-dimensional consumption" of the previous chip region for a given target capacitance can be reduced, or the decoupling capacitance in a particular die region can be greatly increased without requiring additional die area. have. Moreover, providing a three-dimensional capacitor configuration in logic circuits such as a CPU enhances flexibility in capacitor design, where device-specific and process-specific requirements, for example, improved pattern density uniformity. ) May be considered.

According to one exemplary embodiment of the invention, a semiconductor device comprises a decoupling capacitor having a non-planar configuration with at least one transistor element, wherein the decoupling capacitor is connected to the at least one transistor element.

According to another exemplary embodiment of the present invention, a method is provided that includes forming a plurality of transistor elements in or on a semiconductor layer, wherein the plurality of transistor elements define a computing unit. Moreover, the method includes forming a recess in the semiconductor layer and forming a capacitor in the recess.

The present invention can be understood by referring to the following description in conjunction with the accompanying drawings, wherein like reference numerals designate like elements.

1A-1C schematically illustrate cross-sectional views of a conventional semiconductor device including circuitry and decoupling capacitors in a conventional planar configuration, thereby requiring a significant amount of die area.

2A and 2C schematically illustrate cross-sectional views of a semiconductor device including circuitry and decoupling capacitors in a non-planar configuration in accordance with an exemplary embodiment of the present invention.

FIG. 2B schematically depicts a top view of the device of FIG. 2A.

3A-3E schematically illustrate cross-sectional views of a semiconductor device including circuitry and decoupling capacitors during various fabrication steps in accordance with an exemplary embodiment of the present invention, wherein the three-dimensional configuration of the decoupling capacitors is a conventional gate patterning process. the process is substantially compatible with the gate patterning process.

4A-4B are cross-sectional and top views, respectively, of a decoupling capacitor and trench isolation structure formed in a common fabrication process in accordance with yet another exemplary embodiment of the present invention.

5 schematically illustrates a cross-sectional view of an SOI, in accordance with another exemplary embodiment of the present invention, wherein the decoupling capacitor extends through an embedded insulating layer.

While there are many variations and alternative forms of the invention, specific embodiments thereof are shown by way of example in the drawings and are described in detail herein. It will be understood, however, that the description of particular embodiments herein is not limited to this particular form in which the invention is disclosed, and on the contrary, the invention is within the spirit and scope of the invention as defined by the appended claims. It encompasses all variants, equivalents, and alternatives.

Exemplary embodiments of the invention are described below. For clarity, not all features of the actual embodiments are shown in this specification. It should be understood, of course, that in the development of any such practical embodiment, a number of implementation decisions must be made to achieve a developer-specific goal, such as compliance that is well-suited to system-related and business-related constraints. This is different from embodiment to embodiment. Moreover, as will be appreciated, this development effort is complex and time consuming, but nevertheless is a routine process that should be made by those skilled in the art having the benefit of this disclosure.

The invention is now described with reference to the accompanying drawings. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only, so as not to obscure the invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with those words and phrases understood by those skilled in the art. Any meaning of a term or phrase different from the ordinary and ordinary meanings understood by those skilled in the art, ie no definitions are implied in the consistent use of the term or phrase herein. not. Where terms or phrases having special meanings, that is, meanings different from those understood by skilled technicians, are used, such special definitions are clearly defined in the specification in a way that directly and clearly provides a particular definition of the term or phrase. Is provided.

In general, the present invention contemplates forming a three-dimensional or vertically aligned capacitor with high charge carrier storage capability, in particular these embodiments represent decoupling capacitors, which include CPU, ASIC, or many switching operations. Is required to reduce switching noise in high performance semiconductor devices such as any other circuitry including improved logic circuits. The three-dimensional or non-planar configuration of the decoupling capacitor can greatly reduce the horizontal area occupied by conventional decoupling capacitors in planar configuration, which can entail significant difficulties in patterning high scale gate electrodes. This is because a high non-uniform pattern density is created in the die region, thereby also affecting the uniformity of critical etch and photolithography processes due to the pattern-dependent behavior of this process.

Referring to the accompanying drawings, more detailed embodiments of the present invention are now described in detail. 2A is a schematic cross-sectional view of a semiconductor device 200 in an improved manufacturing stage. The semiconductor device 200 includes a substrate 201, which is suitable for forming a silicon bulk substrate, a silicon-on-insulator (SOI) substrate, or a substantially crystalline semiconductor layer 210. It may be provided in the form of any suitable substrate, such as any other semiconducting or insulating carrier material. Since the majority of complex logic circuits, such as CPUs, ASICs, and any other device including complex logic circuits, are currently fabricated on a silicon basis, semiconductor layer 210 may represent a silicon layer or silicon-based layer. This may include other materials such as germanium, carbon and the like. Typically, semiconductor layer 210 includes a suitable dopant concentration, which may vary locally in the vertical and lateral directions.

The semiconductor device 200 may also include a first die region including a plurality of transistor elements 250, which may form a computing unit such as a CPU or the like. The device 200 may also include a second die region 220, which includes a capacitor 240 with high charge carrier storage capability. In one particular embodiment, capacitor 240 represents a decoupling capacitor, as is typically required in advanced semiconductor devices that include fast switching logic circuits. In one exemplary embodiment, capacitor 240 may represent a plurality of capacitor elements 240a, 240b, 240c, 24od, which may be configured as individual capacitors, while in other embodiments, capacitor ( The 240 may include capacitors 240a, 240b, 240c, and 24od as capacitor elements commonly forming the capacitor 240. Capacitor 240, i.e., in the illustrated embodiment, individual elements 240a, 240b, 240c, 24Od comprises a first or inner electrode 241, which may be any such as doped polysilicon, metal silicide, metal, or the like. Can be formed of any suitable conductive material.

Moreover, each dielectric layer 242 is provided, which electrically and physically separates the inner electrode 241 from the outer electrode 243, where, in some embodiments, the outer electrode 243 is It may be represented by the material of the semiconductor layer 210 surrounding the dielectric layer 242. In other embodiments, the outer electrode 243 may be formed of a material of enhanced conductivity compared to the semiconductor material of the layer 210, where the enhanced conductivity may be due to increased dopant concentrations and / or suitable materials, or the like. Can be provided. For example, the outer electrode 243 may be made of highly doped polysilicon, metal silicide, metal, or the like. In addition to the total electrode surface area of the capacitor 240, the dielectric layer 242, which largely determines the resulting capacitance, can have a suitable relative dielectric constant and thickness so that the desired target capacitance can be obtained along with the total capacitor area. For example, a high-k material may be used with other standard materials, possibly silicon oxide, silicon oxynitride, silicon nitride, and the like, so that the inner electrode High capacitive coupling between 241 and outer electrode 243 can be achieved while still providing a moderately high thickness of layer 242, thereby providing static leakage of capacitor 240. Can reduce the current. For example, high-k materials such as zirconium oxide, zirconium silicate, hafnium oxide, hafim silicate and combinations thereof can be used, where some implementations In an example, one or more of these high-k materials may be bounded or surrounded by other well proven insulating materials such as silicon nitride, silicon dioxide, and the like.

FIG. 2B graphically shows a top view of the die 200 and illustrates a large increase in capacitance that can be obtained for a given area occupied by the capacitor 240 within the die region 220. As is apparent, the capacitor 240 occupies an area indicated by a dotted line. In conventional devices having decoupling capacitors in planar configuration occupying the same die area, capacitance is reduced, which also separates the upper and lower electrodes, as described and shown with reference to capacitor 140 in FIG. 1C. It may be largely determined by the material to be used. According to the present invention, for a given material and a given thickness thereof for the dielectric layer 242, it is assumed that this is the same as the material of the gate dielectric 121 in FIG. 1C for convenience, which greatly widens the capacitor due to the non-planar configuration. The area becomes available, and as a result the capacitance becomes very large. By varying the thickness of dielectric layer 242 and its material components, it is possible to obtain significantly increased capacitance and / or significantly reduced leakage current compared to conventional planar configurations. On the other hand, for a given target capacitance of capacitor 240, the area consumed in die region 220 can be greatly reduced, making more floor space available for other components of device 200.

An exemplary process for forming the device 200 shown in FIG. 2A or 2B may include the following process. According to an embodiment, by forming at least the gate electrode structure 251 of the plurality of transistor elements 250 first and subsequently forming the capacitor 240, high flexibility in forming the capacitor 240 may be obtained. . In this process, gate electrode 251 is formed according to a well-established process that includes an improved oxidation and / or deposition method for forming a gate insulating layer having a thickness and material composition required to meet device requirements. Can be. Thereafter, a layer of gate electrode material, such as doped polysilicon, may be deposited by well-established low pressure chemical vapor deposition (CVD) techniques. Thereafter, the layer of gate electrode material may be patterned by improved photolithography and etching techniques, where the die region 220 may be exposed to an etching atmosphere, whereby the gate electrode material over the die region 220 Can be removed substantially completely. As previously described, the improved patterning process for forming the gate electrode 251 may be sensitive to pattern density due to micro-loading effects, etc., so that the etching and patterning uniformity is It may vary depending on the size of the surface area occupied by the capacitor 240 to be formed. Thus, for any desired decoupling capacitance, the required floor space as compared to conventional planar configurations is greatly reduced, so that non-uniformity in pattern density is greatly reduced compared to conventional devices (see FIG. 1C), then This also improves the overall uniformity of the patterning process for forming the gate electrode 251.

After the formation of the gate electrode 251, according to one embodiment, the transistor forming process can continue by forming the drain and source regions, respectively, using ion implantation in accordance with a well established process scheme, where the sidewalls are intermittently Spacers are formed to appropriately adjust the side dopant profile for the individual transistor 250. In another embodiment, the process for forming transistor 250 may be stopped after the formation of gate electrode 251 and the process flow may continue by forming capacitor 240. Regardless of whether the transistor formation process continues after completion of the gate electrode 251 or not, the capacitor 240, i.e., the individual capacitor elements 240a, 240b, substantially covers the die region 230 completely. Appropriate resist masks may be formed that provide the desired patterns for each of 240c and 24od). Based on this resist mask, an anisotropic etching process is performed to form a corresponding recess, for example in the form of a trench, in the semiconductor layer 210. For this purpose, process methods similar to those known from the formation of trench isolation structures can be used. After each recess or trench formation, the resist mask can be removed and subsequently the outer electrode 243 conformally deposits a suitable material such as, for example, highly doped polysilicon or the like. Can be formed. In other embodiments, the semiconductor material of the enclosing layer 210 may operate as the outer electrode 243 without other manipulations and processes. Depending on the process strategy, in other embodiments, the outer electrode 243 can be formed to include a metal. For example, if the formation of transistor element 250 is substantially complete or proceeds to any stage (no further high temperature processes are necessary at this stage), metals such as tungsten, cobalt, nickel, titanium, etc. may be well established. It may be deposited by physical or chemical vapor deposition techniques, where the metal may then have a semiconductor material on its own or underneath the compound and serve as the outer electrode 243. For example, when layer 210 is substantially comprised of silicon, the corresponding metal silicide is a process as is well known from the formation of drain and source regions of conventional transistor elements and metal silicide regions at gate electrodes. Can be formed according to the strategy.

In one exemplary embodiment, corresponding metal silicide regions in outer electrode 243 and transistor 250 may be formed in a common process, thereby greatly reducing process complexity. Dielectric layer 242 may then be formed by deposition and / or oxidation, depending on the previous process flow. That is, if the outer electrode 243 can be formed of the semiconductor material of the layer 210 or any other oxidizable material, if the oxidation temperature is compatible with the fabrication steps of the transistor device 250, then the dielectric layer ( 242 may be formed by oxidation. In other cases, suitable dielectric materials may be deposited by well-established physical or chemical vapor deposition techniques. For example, silicon dioxide, silicon nitride, silicon oxynitride and the like can be deposited by plasma enhanced CVD techniques based on well known methods. During deposition, the thickness of the dielectric layer 242 can be controlled according to the device requirements to achieve the required high capacitance for the capacitor 240. As will be appreciated, the formation of the dielectric layer 242 is substantially separated from the process for forming each gate insulating layer of the gate electrode 251, so that any desired thickness and material component can be applied to the dielectric layer 242. Can be selected.

In one exemplary embodiment, the deposition of the dielectric layer 242 may include the deposition of an etch stop layer that exhibits high etch selectivity with respect to the material used for the inner electrode 241, and thus, the electrode 241. Any excess material that may form on die region 230 during filling of the electrode material to may be removed in a subsequent selective etching process.

In one exemplary embodiment, inner electrode 241 may be formed by depositing highly doped polysilicon, thereby substantially filling the corresponding trench substantially. Subsequently, excess material may be removed by selective silicon etching, where the corresponding etch stop layer may ensure reliable removal of excess material from die regions 230 and 220, while inner electrode 241 Any excess etching of may be acceptable and may even improve the reliability of electrical insulation between the inner electrode 241 and the outer electrode 243, because some recessing of the inner electrode 241 may be generated. Because. Subsequent processing can then be continued to complete transistor device 250 and finally corresponding contacts in die region 230 and die region 220 can be formed, where a well established process method It can be used with a correspondingly designed photolithography mask to establish the required electrical connection between the individual capacitor elements 240a, 240b, 240c, 24od and the circuit represented by the plurality of transistor elements 250.

2C schematically illustrates an example of a wiring method for connecting the decoupling capacitor 240 to the logic circuit represented by transistor 250. As a result, device 200 may include a plurality of transistor contacts 254, which are formed in dielectric layer 208 and are connected to corresponding drain and gate regions and gate electrodes of the plurality of transistors 250. . Moreover, a capacitor contact 244 is formed inside the dielectric layer 208, which can provide electrical contact to each of the inner electrode 241 and the outer electrode 243. In the illustrated embodiment, only one contact 244 is shown to be connected to the outer electrode 243, which can be assumed to be in contact with all of the individual capacitor elements 240a, 240b, 240c, 24od. . In other embodiments, respective capacitor contacts to the plurality of outer electrodes 243 may be provided. Capacitor contact 244 connected to outer electrode 243 may also be connected to metal line 219, which also provides electrical contact to the logic circuit represented by the plurality of transistor elements 250. Similarly, a plurality of inner electrodes 241 may be connected to one or more metal lines 209, through each contact 244, which may also be required for the decoupling function of the capacitor 240. Likewise, electrical contact is provided to certain portions of the circuit represented by transistor element 250. As will be appreciated, the wiring method shown in FIG. 2C is merely exemplary, and any other structure may be used that connects capacitor 240 with a suitable node of the circuit represented by transistor element 250. For example, two or more separate capacitor elements 240a, 240b, 240c, 24od may be connected with different furnaces in the circuit of transistor element 250.

As mentioned above, transistor contacts 254 and capacitor contacts 244 may be formed based on well-established methods and in certain embodiments may be formed in a common fabrication process. For this purpose, an etch stop layer (not shown) may be conformally deposited over the die regions 230 and 220 followed by the deposition of the dielectric layer 208, which is then required if a highly uniform surface is desired. May be polished or otherwise planarized. A corresponding opening can then be formed in layer 208, which can then be etched through the etch stop layer to provide contact to each semiconductor region. A suitable conductive material may then be filled in this opening to form transistor contact 254 and capacitor contact 244. Thereafter, metal lines 219 and 209 may be formed according to well-established techniques for forming the metallization layer of the semiconductor device.

During the formation of metal lines 209 and 219 embedded in suitable interlayer dielectric materials, anisotropic etching techniques are typically formed based on the plasma atmosphere, during which damage due to plasma can be observed. In particular, for greatly improved semiconductor devices having a minimum feature size of 100 nm and much smaller, metal lines 209 and 219 can be composed of copper or copper alloys, thereby providing special copper for deposition and etching. Due to their nature, special strategies are required. For example, for copper-based metallization layers, so-called damascene methods are often used, in which interlayer dielectric materials are deposited and patterned to accommodate vias and trenches, which are subsequently subsequently copper or copper alloys. Filled with During the patterning process, wafer damage due to plasma is often observed, especially during the critical via etch process. As will be appreciated, one reason for the very large wafer arcing and wafer charging effect is caused by the excessive conductive area of the underlying layer, which can induce an antenna effect during the plasma assisted etching process. Due to the large reduction in the horizontal surface area occupied by the decoupling capacitor 240 compared to conventional planar configurations (see FIG. 1C), the antenna effect is greatly reduced and thereby damage due to any plasma such as wafer arcing and wafer charging The risk for is reduced.

Referring again to FIG. 2A, it should be understood that a semiconductor device, as shown in FIG. 2A, may be formed by forming capacitor 240 before forming a plurality of transistor elements 250 in another embodiment. Can be. Thus, if capacitor 240 is compatible with any high temperature process that may be required for the formation of transistor element 250, the process for forming capacitor 240 from the process of forming transistor element 250. Substantial separation of the flow can be obtained. In one exemplary embodiment, capacitor 240 may be formed based on trench isolation techniques, thereby providing capacitor 240 in a form that is compatible with other conventional process flows forming transistor device 250. have. To this end, before or after the formation of any trench isolation structure, if the inherent conductivity of the semiconductor layer 210 is considered to be inadequate, the capacitor 240 may have an outer electrode, for example in the form of doped polysilicon. And formed by a process flow including an anisotropic trench etch process and a subsequent deposition process to form 243. Dielectric layer 242 may then be formed by oxidation and / or deposition to form silicon dioxide, silicon oxynitride, or silicon nitride. Inner electrode 243 may then be formed by depositing polysilicon and removing any excess material by corresponding etching and chemical mechanical polishing (CMP) techniques. The fabrication process can then be resumed using standard methods to form transistor device 250. Subsequent processing may then continue as described above to form device 200 as shown in FIG. 2C.

With reference to FIGS. 3A-3E, another exemplary embodiment of the present invention is now described in detail, and many of the process steps described and related herein may also be applied in the embodiments described above, or in addition to FIGS. 4A and 4B. It can be applied to the embodiments described below with reference to 5. In the embodiments described above, the fabrication process for forming the non-planar capacitor can be performed entirely before the formation of any transistor elements or after the formation of the electrode structure. 3A-3E, a process strategy is described that enables the formation of a non-planar decoupling capacitor by using at least some process steps (which are also used for the formation of the gate electrode structure).

In FIG. 3A, the semiconductor device 300 includes a substrate 301, on which a semiconductor layer 310 is formed. Further, trench isolation structure 302 may be formed in semiconductor layer 310. Trench isolation 302 may separate first die region 330 from second die region 320. Moreover, in one exemplary embodiment, the first portion 352a of the gate insulating layer 352 may be formed on the semiconductor layer 310. In this embodiment, the gate insulating layer to be formed in the first die region 330 has a target thickness that is greater than the thickness of the first portion 352a. In another embodiment, the first portion 352a may not be formed at this stage of manufacture and the process for patterning the second die region 320 for receiving vertical or three-dimensional non-planar decoupling capacitors. The step may be performed as described below without this portion 352a. This device 300 as shown in FIG. 3A can be formed according to well-established trench isolation techniques, including sophisticated photolithography, etching, deposition, and planarization techniques.

3B illustrates the semiconductor device 300 in a subsequent improved manufacturing step. Device 300 may include an etch mask 360, which may be provided in the form of a resist mask or any suitable hard mask. Etch mask 360 includes a plurality of openings 360a, 360b, 360c. Corresponding recesses or openings 345a, 345b, 345c are formed in the semiconductor layer 310. The recesses 345a, 345b, 345c may have the form of a trench such as shown in FIGS. 2A and 2B, or any other suitable shape, for example. The size of the recesses 345a, 345b, 345c as well as the number thereof are selected such that, in combination, the required layer thickness of the capacitor dielectric to be formed and the capacitance required for a given material component can be achieved. The trenches may be the same size or may vary in size.

Etch mask 360 may be formed by well-established photolithography techniques and later well-established anisotropic etching techniques to form recesses 345a, 345b, and 345c, where formation of trench isolation structures 302 is achieved. Process methods similar to those used for this may be used. That is, depending on whether or not the first portion 352a of the gate insulating layer is provided on the semiconductor layer 310, the gate insulating layer 352 of the second die region 320 is opened and subsequently The semiconductor material is etched in a high anisotropic procedure. The resist mask 360 may then be removed by known wet or dry resist strip techniques or any other optional etching process when the etching mask 360 is provided in the form of a hard mask.

3C illustrates the semiconductor device 300 during the formation of the dielectric layer 342 in the capacitor recesses 345a, 345b, 345c. During this process, indicated as 361, the thickness of the first portion 352a (see FIG. 3B) may be increased to obtain the final thickness of the gate insulation layer 352. For example, process 361 can be used to adjust the capacitive coupling between the outer region, indicated by 343, which acts as the outer electrode after completion of the decoupling capacitor, and the interior of the recesses 345a, 345b, and 345c. An oxidation process for growing oxide in thickness can be shown. For example, dielectric layer 342 may be provided as a moderately thin layer having a thickness of approximately 1 nm to several nm, depending on device requirements. As will be appreciated, the thickness of the first portion 352a may be selected in a suitable manner to obtain the target thickness of the gate insulating layer 352 after the formation of the dielectric layer 342. In other embodiments, when the first portion 352a is not formed prior to the formation of the recesses 345a, 345b, 345c, the gate insulating layer 352 and the dielectric layer 342 are formed in a single common process. Such layers may have substantially the same properties.

3D schematically illustrates a semiconductor device 300 having a layer 351 of gate electrode material formed over the first die region 330 and the second die region 320. This layer 351 may be composed of doped polysilicon as frequently used in greatly improved CMOS technology. Moreover, this layer 351 may exhibit a particular shape due to the presence of the recesses 345a, 345b, 345c, which is substantially completely filled with the material of the layer 351. As a result, the layer 351 may be deposited with an excess thickness greater than the target thickness 351T for the gate electrode structure to be formed in the first die region 330. This layer 351 may be formed by well established low pressure CVD techniques. Thereafter, the shape of this layer 351 may be planarized by CMP to substantially obtain the target thickness 351T. Next, the planarized layer 351 may be patterned by well-established photolithography and etching techniques to form a gate electrode structure in the first die region 330. In some example embodiments, the patterning process for the gate electrode structure can be modified to form respective electrode structures over the recesses 345a, 345b, 345c, thereby patterning the gate electrode structure. The uniformity of the final pattern density can be greatly increased during the process. Moreover, the patterning of the electrodes over the corresponding recesses 345a, 345b, 345c is performed in such a way that the required electrical connection between the individual recesses 345a, 345b, 345c is established in accordance with the required electrical configuration. Can be.

3E schematically illustrates a semiconductor device 300 after the process sequence described above and after any ion implantation process and spacer formation sequence. Thus, the device 300 includes a plurality of transistors 350, and only one device is shown for convenience. Transistor 350 may represent a complex logic circuit, such as a computing unit, a CPU, or the like. Furthermore, a capacitor 340 is formed in the second die region 320, which may include individual capacitor elements 340a, 340b, 340c. Capacitor elements 340a, 340b, and 340c may have electrodes 341, which may be commonly patterned with the gate electrode 351 of transistor 350 in some embodiments. As described above, the electrodes 341 may be electrically connected in any suitable manner as indicated by dashed lines 341a in the form of local interconnections to provide the required electrical configuration of the capacitor 340.

As a result, capacitor 340 can be formed by well-established process techniques, where high compatibility with conventional process flows is maintained, as described with reference to FIGS. 1A-1C, while nevertheless decoupling The non-planar configuration of capacitor 340 provides very good advantages. Moreover, the patterning of the electrodes 341 in the common patterning process with the gate electrode 351 greatly increases the uniformity of the pattern density, thereby greatly contributing to enhanced process control during critical photolithography and etching techniques. do. Moreover, local interconnect structures such as connections 341a can be formed during the gate patterning process, thereby electrically connecting the individual capacitor elements 340a, 340b, and 340c in a highly efficient manner. Moreover, if the conductivity of the outer electrode 343 is considered inadequate based on the initial doping concentration of the semiconductor layer 310, then the corresponding ion implantation process positions the dopant species along the vertical portion of the dielectric layer 342. May be performed with an appropriate implant amount and energy, while the first die region 330 may be covered with a corresponding resist mask.

4A and 4B, another exemplary embodiment is now described, wherein the formation of the trench isolation structure is suitably modified to form the corresponding decoupling capacitor.

4A schematically illustrates a cross-sectional view of a semiconductor device 400 that includes a substrate 401, on which a semiconductor layer 410 is formed. With respect to the substrate 401 and the semiconductor layer 410, the same criteria as described above with respect to the substrate 201 and the layer 210 apply. The device 400 includes a three-dimensional decoupling capacitor 440 and a trench isolation structure 402 in the semiconductor layer 410. In this embodiment, the decoupling capacitor 440 and trench isolation structure 402 including the first element 440A and the second element 440B may have basically and substantially the same configuration. As a result, trench isolation structure 402 may also be considered as a capacitor element. Each of these isolation structures 402 and capacitor elements 440A, 440B includes a isolation layer 463, which separates the interior of each device from the surrounding semiconductor layer 410. For example, isolation layer 463 may be formed of silicon dioxide and / or silicon nitride and / or silicon oxynitride, or the like. In this case, isolation layer 463 is formed from an insulating material so that isolation layer 463 of trench isolation structure 402 is required for trench isolation structures 302, 202, and 102 as described above, for example. Meet the required insulation properties as described. Moreover, elements 402, 440A, 440B also include an outer electrode 443, a dielectric layer 442, and an inner electrode 441. Inner electrode 441 and outer electrode 443 may be formed from the same material, such as doped polysilicon, or the like. Dielectric layer 442 may be comprised of any suitable material, for example silicon dioxide, silicon nitride, silicon oxynitride, or any high-k material as described above. As will be appreciated, dielectric layer 442 may be comprised of a plurality of materials and / or different layers to provide the desired properties with respect to capacitive coupling and leakage current. The device 400 may also include a gate insulating layer 452 and a gate electrode 451. In some demonstrative embodiments, one or more of the elements 402, 440A, 440B may include corresponding “electrode” structures 451C, 451A, 451B, while in other embodiments of such electrode structures Some or all may be omitted.

4B schematically illustrates a top view of device 400, where exemplary configurations of capacitor elements 440A, 440B are shown. As will be appreciated, the configuration comprising a plurality of substantially square shaped elements 440A, 440B is merely exemplary and other geometric configurations and shapes may be selected. For example, a substantially rectangular outline may be selected for capacitor elements 440A, 440B. Moreover, as is apparent from FIG. 4B, the trench isolation structure 402 surrounds the gate electrode 451 and thus defines a region where the transistor should be formed adjacent to the gate electrode 451.

An exemplary process flow for forming device 400 as shown in FIGS. 4A and 4B may include the following process. First, corresponding trenches may be formed similarly to conventional trench isolation processes, where, in some embodiments, however, the dimensions of the isolation trenches may be configured to conform to the desired configuration of the isolation structure 402. For example, the trench width can be correspondingly increased to accommodate the isolation layer 463 as well as the inner electrode 441 and the outer electrode 443 and the dielectric layer 442. In other embodiments, standard isolation trench dimensions may be suitable to accommodate corresponding capacitor elements. Moreover, respective trenches or recesses for elements 440A and 440B may be formed, where their dimensions do not necessarily correspond to the dimensions of the isolation trenches. For example, the trench width, i. Regardless of the dimensions of the individual elements 402, 440A, 440B, these components can be formed in a common etch process in a well-established manner to form trench isolation structures. Thereafter, isolation layer 463 may be formed, for example, by performing a controlled oxidation process and / or by depositing any suitable insulating material, such as silicon dioxide, silicon oxynitride, silicon nitride, and the like. . Next, the material for the outer electrode 443 is in the form of a highly doped polysilicon or any other conductive material suitable to withstand subsequent high temperature processes, such as may be required for forming the transistor structure, for example. And conformally deposited. Next, the dielectric layer 442 can be formed by oxidation and / or deposition, where a plurality of different materials or layers of materials can be formed, as described above, to obtain the desired properties. Next, material may be deposited on the inner electrode 441, such as highly doped polysilicon or the like, thereby reliably filling the remaining volume of each trench and opening. Subsequently, any excess material may be removed in a manner similar to that in conventional trench isolation processes by etching and / or CMP. Thereafter, the gate insulating layer 452 may be formed based on a well established manner that includes a very well controlled oxidation and / or deposition process. Next, gate electrode 451 may be formed by depositing a gate electrode material such as polysilicon, which is then patterned according to sophisticated lithography and etching techniques based on conventional methods. In contrast to the prior art, a lithographic mask for patterning the gate electrode 451 can also be provided for the additional “electrode” structure 451C, 451A, or 451B, which in turn is a very uniform pattern during the patterning process. Density can be provided.

As can be seen from FIG. 4B, each gate electrode structure 451A, 451B, if provided, can be formed to provide sufficient space to contact the inner electrode 441 adjacent to each structure 451A, 451B. This becomes available. Subsequent processing, ie, the process for forming the complete transistor structure based on the gate electrode 451 may continue in a manner similar to that described above. During the formation of transistor contacts, corresponding contacts may be formed for capacitor 440 and the required electrical configuration may be established in a manner similar to that described with reference to FIG. 2C.

It will be appreciated that the embodiments described above provide the possibility of substantially completely separating the forming process for forming the capacitor 440 from the fabrication process of any circuit element, while nevertheless with respect to the conventional process flow. High compatibility is maintained. Moreover, in some embodiments, trench isolation structure 402 can be used efficiently as a decoupling capacitor, where in some embodiments the correspondingly obtained capacitor area is sufficient for decoupling purposes, while in other embodiments. Further capacitor elements 440A, 440B are provided. In another embodiment, trench isolation structure 402 may not be in electrical contact such that it does not act as a capacitive element. As will be appreciated, the embodiments described above are also applicable to SOI substrates. The same holds true for the embodiments described with reference to FIGS. 2A-2C and 3A-3E. However, in an improved semiconductor device based on SOI technology, the corresponding semiconductor layer can only show a very small thickness, for example a few tens of nm, which is a usable capacitor obtained by a three-dimensional decoupling capacitor configuration. The area can be overly constrained. In this case, in some embodiments, the capacitor may be formed to extend beyond the embedded insulating layer of the SOI substrate.

5 schematically illustrates a cross-sectional view of a semiconductor device 500 including a substrate 501, on which a semiconductor layer 501 is formed, which is separated from the substrate 501 by a buried insulating layer 503. do. In a particular embodiment, the configuration of the substrate 501, the embedded insulating layer 503, and the semiconductor layer 510 may represent an SOI substrate. Device 500 also includes a decoupling capacitor 540 that includes capacitor elements 540A, 540B. Corresponding elements 540A, 540B represent recesses that, in this fabrication step, extend into the substrate 501 through the semiconductor layer 510 and the insulating layer 503 embedded therein. Depending on the configuration of the capacitor 540, the recesses 540A and 540B may form a separation layer 563 on its inner surface, with the capacitor 540 described above with reference to FIGS. 4A and 4B. It is formed in a similar configuration. In other embodiments, the capacitor elements 540A, 540B may be formed according to a configuration as described with reference to FIGS. 2A-2C and 3A-3E, so in particular if the elements 540A, 540B are properly separated If provided in a separate die area surrounded by the structure, separation layer 563 may be omitted. In this case, layer 563 may represent the outer electrode of capacitor elements 540A, 540B.

The device 500 may be formed in the following manner depending on the device and process requirements. A certified anisotropic etch process may be performed to etch through the semiconductor layer 510 where the etch chemistry may be altered for efficient etching through the embedded insulating layer 503. Thereafter, the trench etch process may be resumed based on appropriate etching chemistry to remove material from the substrate 501. For example, if the semiconductor layer 510 is substantially comprised of silicon and the substrate 501 represents a crystalline silicon substrate, then the same etching parameters may be used to etch the substrate 501 through the layer 510. Can be used for After the required depth is achieved, the etching process can be stopped and subsequent processing can be resumed by forming layer 563 in the form of an insulating layer or an outer electrode layer depending on the process and device requirements. In some embodiments, substantially the same process strategy may be performed as described with reference to FIGS. 4A and 4B, where one or more of the elements of capacitor 540 are trenches, such as substrate 402. It can be designed as a separate structure. As will be appreciated, extending the corresponding isolation structure to the substrate 501 has substantially no negative impact on the function of the corresponding trench isolation structure. In other embodiments, a process strategy as described with reference to FIGS. 2A-2C and 3A-3E may be performed, wherein the individually formed trench isolation structures may be obtained in a conventional manner, while Capacitor elements 540A and 540B can be formed to extend to substrate 501 to provide high capacitance while occupying a minimum amount of chip area. Subsequent processing to complete the decoupling capacitor 540 may be performed as described above.

As a result, the present invention provides a technique that enables the formation of decoupling capacitors that occupy significantly reduced die area compared to conventional planar configurations. Moreover, by forming three-dimensional decoupling capacitors in complex logic circuits, the flexibility in forming semiconductor devices is very high, because in many embodiments the formation of the capacitor dielectric is substantially independent of the formation of the corresponding gate insulation layer. Because. That is, the thickness and / or material component of the capacitor dielectric may, in some embodiments, be selected in terms of enhanced capacitor operation rather than in terms of the characteristics of the gate insulating layer. In other embodiments, the formation of non-planar decoupling capacitors can be incorporated into conventional process strategies for forming gate electrode structures or trench isolation structures, thereby greatly reducing overall process complexity while enhancing process Many advantages can be provided, such as uniformity, die area consumption, and the like. Due to the reduction in die area consumed by the capacitor, the non-uniformity of the pattern density during the critical gate patterning process can be greatly reduced, and in some embodiments a corresponding electrode structure is formed over the corresponding capacitor element. Can be reduced even further. In addition, the wafer arcing problem arising in typical back end processes such as during the formation of the metallization layer can be greatly mitigated due to the reduction in the antenna effect of the extremely small horizontal die area occupied by the decoupling capacitor.

The particular embodiments disclosed are merely exemplary, since the invention may be modified and practiced in different but equivalent ways, which will be apparent to those skilled in the art that would benefit from the description herein. Because. For example, the process steps described above may be performed in a different order. Moreover, no limitations other than those set forth in the claims below are intended for the details of construction or design presented herein. Therefore, it is apparent that the specific embodiments disclosed above may be changed or modified, and all such changes are considered to be within the scope and spirit of the present invention. Accordingly, the protection scope herein is as set forth in the claims below.

Claims (12)

In the semiconductor devices 200, 300, 400, 500, A plurality of transistor elements 250 and 350 forming a computing unit; And And a decoupling capacitor (240, 340, 440, 540) having a non-planar configuration, said decoupling capacitor (240, 340, 440, 540) connected to said associating unit. The method of claim 1, The decoupling capacitors 240, 340, 440, and 540 are formed of the first electrodes 241, 341, 441 and the second electrodes 243, 343, separated by the non-planar dielectric layers 242, 342, 442, and 563. 443, wherein the first electrode and the second electrode extend into semiconductor layers 201, 301, 401, 501, and 510 and include the at least one semiconductor device within and on the semiconductor layer. 250, 350 are formed. The method of claim 1, The decoupling capacitors 240, 340, 440, 540 include two or more capacitor elements 240A-D, 340A-C, 402, 440A-B, each of which comprises a non-planar dielectric layer portion. A semiconductor device comprising a. The method of claim 1, The at least one transistor element 250, 350 includes a gate insulating layer 352, 352A, which is coupled to the non-planar decoupling capacitors 240, 340, 440, 540 in at least one of a thickness and a material component. And a non-planar dielectric layer (242, 342, 442, 563) formed. The method of claim 1, And a trench isolation structure (402) including at least a portion of the decoupling capacitor (440). The method of claim 2, Further includes an embedded insulating layer 503 that separates the semiconductor layer 510 from the substrate 501, wherein the non-planar dielectric layer 563 of the decoupling capacitor 500 is the embedded insulating layer 503 And into the substrate (501). Forming a plurality of transistor elements 250, 350 in the semiconductor layer 201, 301, 401, 510 and on the semiconductor layer 201, 301, 401, 510, and the plurality of transistor elements ( 250, 350 define a computing unit; Forming a recess (345A-C) in said semiconductor layer (201, 301, 401, 510); And Forming a capacitor (240, 340, 440, 540) in the recess (345A-C). The method of claim 7, wherein Forming the capacitors 240, 340, 440, 540 includes forming dielectric layers 242, 342, 442, 563 in the recesses 345A-C and dielectric layers 242, 342, 442. , 563) depositing a conductive material (241, 341, 441). The method of claim 7, wherein Forming a trench isolation structure 402 by etching a trench and filling the trench with a material comprising at least one layer 463, 442 of insulating material, wherein the recesses 345A-C. ) And the trench are formed in a common etching process. The method of claim 7. Forming a first portion (352A) of a gate insulating layer (352) for the plurality of transistor elements (250, 350) prior to forming the recess (345A-C); And Forming a second portion 342 of the gate insulating layer 352 on the first portion 352A and on an exposed surface of the recess 345A-C. And said second portion (342) of said gate insulating layer (352) in 345A-C represents a dielectric layer (342) of said capacitor (240, 340, 440, 540). The method of claim 10, Depositing a gate electrode material (351) to fill the recesses (345A-C); Planarizing the surface shape to form a gate electrode material layer 351; Forming gate electrodes (351) of the plurality of transistor elements from the gate electrode material layer (351); And And forming electrode portions (341) from the gate electrode material layer (351) for the inner electrode (341) of the capacitor (340). The method of claim 7, wherein Forming the recesses 345A-C includes etching the semiconductor layer 510 and the buried insulating layer 503 that separates the semiconductor layer 510 from the substrate 501. How to.

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