CN116404006B - Chip layout - Google Patents
Chip layout Download PDFInfo
- Publication number
- CN116404006B CN116404006B CN202310677388.8A CN202310677388A CN116404006B CN 116404006 B CN116404006 B CN 116404006B CN 202310677388 A CN202310677388 A CN 202310677388A CN 116404006 B CN116404006 B CN 116404006B
- Authority
- CN
- China
- Prior art keywords
- pattern
- patterns
- virtual
- chip
- corner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000007789 sealing Methods 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims description 30
- 238000005520 cutting process Methods 0.000 abstract description 17
- 238000012858 packaging process Methods 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention provides a chip layout, which relates to the field of semiconductors, and comprises at least one first layout, wherein each first layout is provided with first chip patterns distributed in an array and first chip protection patterns wound on the outer side of the first chip patterns, each first chip protection pattern comprises a first sealing ring and a first corner virtual pattern, the first sealing ring is arranged on the outer side of the first chip patterns in a surrounding mode, the first corner virtual pattern is arranged on the outer side of the first sealing ring, the whole shape of the first corner virtual pattern is a triangle with a chamfer, and the first corner virtual pattern with the chamfer is used as a stress buffer pattern, so that the impact of cutting impact force on a corner area can be effectively reduced, the corner collapse risk is reduced, and the yield of chips in the packaging process is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a chip layout.
Background
When the layout of chip sets up, can design chip protection architecture at the chip periphery generally, chip protection architecture includes the sealing washer, the sealing washer just like the great wall of chip encircles from all around the surrounding the chip to the internal circuit of chip is hurt when preventing the chip scribing, can also prevent external dust entering inside the chip, and can prevent moisture from invading from the side fracture of chip. The chip scribing is performed on the outer side of the sealing ring, and stress possibly acts on the inside of the chip during the chip scribing, and the chip protecting structure can prevent cracks generated during the chip scribing from damaging the chip.
Currently, conventional sealing rings include inner sealing rings, outer sealing rings, and corner dummy areas. During dicing of the chip, the corner dummy area is subjected to two dicing shocks, which presents challenges for stress relief of the corner dummy area. In terms of layout, the layout of the seal ring is a graph formed by overlaying layers such as diff (active area), contact (via), via (through hole), metal (metal) and the like according to a certain rule. In order to reduce the effect of stress, a metal slot (metal slot) may be formed in an IMD (inter-metal dielectric) outside the metal layer to mitigate the stress impact between the metal layer and the IMD. Since the metal layer that is first stressed during the cutting process is the metal layer that is 4X/6X in size (i.e., the topmost one, two or three metal layers), the need for stress relief of the metal grooves of these metal layers in the corner dummy pattern areas and stress impact on the corner areas of the seal ring present challenges.
Disclosure of Invention
The invention aims to provide a chip layout which can prevent corner collapse caused by overlarge stress release of a corner virtual pattern area.
In order to solve the problems, the invention provides a chip layout, which comprises at least one first layout, wherein each first layout is provided with first chip patterns distributed in an array manner and first chip protection patterns wound on the outer side of the first chip patterns, each first chip protection pattern comprises a first sealing ring and a first corner virtual pattern, the first sealing ring is arranged on the outer side of the first chip patterns in a surrounding manner, the first corner virtual pattern is arranged on the outer side of the first sealing ring, and the whole shape of the first corner virtual pattern is a triangle with chamfer angles.
Optionally, each first layout further has a first scribe line region pattern disposed between adjacent first chip protection patterns, and the first corner virtual pattern is disposed between an intersection point of two intersecting first scribe line region patterns and the first seal ring.
Optionally, the overall shape of the first corner virtual pattern is an isosceles right triangle with a chamfer, and the chamfer is a linear chamfer.
Optionally, at least one hollowed-out pattern is arranged in the corner virtual pattern, all the hollowed-out patterns are parallel and are arranged at intervals, and the hollowed-out pattern is parallel to the edge, opposite to the vertex, of the first outer ring seal ring pattern, of the first corner virtual pattern.
Further, the hollow pattern is in a parallelogram shape.
Further, a distance between the hollowed-out pattern positioned on one side of the first corner virtual pattern far away from the side opposite to the vertex of the first outer ring seal ring pattern and the side opposite to the vertex of the first corner virtual pattern far away from the first outer ring seal ring pattern is 1.5-3 μm; and
the width of the hollowed-out pattern is 1.5-3 mu m.
Optionally, the first sealing ring sequentially comprises a first inner ring sealing ring pattern and a first outer ring sealing ring pattern from inside to outside, the first chip patterns are arranged in the first inner ring sealing ring pattern at intervals, and the first inner ring sealing ring pattern and the first outer ring sealing ring pattern are rectangular rings with chamfers, so that one first corner virtual pattern is arranged on the outer side of each chamfer of the first outer ring sealing ring pattern.
Further, the first inner ring seal ring graph comprises two parallel first virtual graphs which are opposite to each other, two parallel second virtual graphs which are opposite to each other, and chamfer edge virtual graphs which connect the adjacent first virtual graphs and the second virtual graphs, wherein the included angle between the chamfer edge virtual graphs and the first virtual graphs is the same as the included angle between the chamfer edge virtual graphs and the second virtual graphs.
Further, a support pattern is arranged on the inner side of the first inner ring sealing ring pattern, and the support patterns are arranged on the outer side of the first chip pattern at intervals.
Further, the bracket pattern includes a first bracket pattern, or the bracket pattern includes a first bracket pattern and a plurality of second bracket patterns;
the first support patterns are arranged on the inner side of the chamfer edge virtual pattern at intervals, and the second support patterns are connected with the first support patterns and the chamfer edge virtual pattern.
Further, the shape of the first support pattern is the same as that of the chamfer edge virtual pattern, the first support pattern is parallel to the chamfer edge virtual pattern, and two ends of the first support pattern are respectively connected with the first virtual pattern and the second virtual pattern.
Further, the width of the first bracket pattern is 2-4 μm, and the distance between the first bracket pattern and the chamfer edge virtual pattern is 10-20 μm.
Further, all the second bracket patterns are sequentially connected end to end, two adjacent connecting points are respectively connected with the first bracket pattern and the chamfer edge virtual pattern, and two adjacent second bracket patterns are vertically arranged.
Further, the width of the second bracket pattern is 1.2 μm to 3 μm.
Optionally, the first chip pattern includes a metal layer pattern having metal lines, where the width of the metal lines is 4X or 6X.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a chip layout, which comprises at least one first layout, wherein each first layout is provided with first chip patterns distributed in an array manner and first chip protection patterns wound on the outer side of the first chip patterns, each first chip protection pattern comprises a first sealing ring and a first corner virtual pattern, the first sealing ring is arranged on the outer side of the first chip patterns in a surrounding manner, the first corner virtual pattern is arranged on the outer side of the first sealing ring, the whole shape of the first corner virtual pattern is a triangle with a chamfer angle, and the first corner virtual pattern with the chamfer angle is used as a stress buffer pattern, so that the impact of cutting impact force on a corner area can be effectively reduced, the corner collapse risk is reduced, and the yield of chips in the packaging process is improved.
Furthermore, the impact of cutting impact force on corner areas can be further reduced through the hollowed-out patterns, the risk of corner collapse is reduced, and the yield of chips in the packaging process is improved.
Further, the bracket patterns comprise a first bracket pattern or the bracket patterns comprise a first bracket pattern and a plurality of second bracket patterns; the first support patterns are arranged on the inner side of the chamfer edge virtual patterns at intervals, the second support patterns are connected with the first support patterns and the chamfer edge virtual patterns, so that the impact of cutting impact force on corner areas can be effectively reduced, the impact of the cutting impact force on the corner areas is further reduced, the corner collapse risk is reduced, and the yield of chips in the packaging process is improved.
Drawings
FIG. 1 is a schematic diagram of a first layout according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a second layout according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a first layout according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first layout according to a third embodiment of the present invention.
Reference numerals illustrate:
100-a first chip pattern; a 100' -second chip pattern; 210-a first corner virtual graphic; 211-hollowed-out patterns; 220-a first outer ring seal ring pattern; 230-a first inner ring seal ring pattern; 231-a first virtual graphic; 232-a second virtual graphic; 233-chamfer virtual graphics; 234-a first stent pattern; 235-a second scaffold pattern; 210' -second corner virtual graphics; 220' -second outer ring seal ring pattern; 230' -a second inner ring seal ring pattern; 300-a first scribe line region pattern; 300' -second scribe line region pattern.
Detailed Description
A chip layout of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
Example 1
Fig. 1 is a schematic structural diagram of a first layout provided in this embodiment. As shown in fig. 1, the present embodiment provides a chip layout including at least one first layout.
Each first layout is provided with first chip patterns 100, first chip protection patterns and first scribe line region patterns 300 which are distributed in an array mode, each first chip protection pattern is enclosed on the outer side of one first chip pattern 100, each first scribe line region pattern 300 is further arranged between adjacent first chip protection patterns, the first chip patterns 100 and the first chip protection patterns are arranged at intervals, and the first chip protection patterns and the first scribe line region patterns 300 are arranged at intervals.
The first chip protection pattern includes a first sealing ring and a first corner virtual pattern 230, the first sealing ring is enclosed on the outer side of the first chip pattern, and the first corner virtual pattern 230 is arranged on the outer side of the first sealing ring.
The first seal ring sequentially comprises a first inner ring seal ring pattern 210 and a first outer ring seal ring pattern 220 from inside to outside. The first corner virtual pattern is disposed between the intersection point of the two intersecting first scribe line region patterns 300 and the first seal ring, and the first chip pattern 100 is disposed in the first inner ring seal ring pattern 230 at intervals. The first inner ring seal ring pattern 230 and the first outer ring seal ring pattern 220 are both in a closed ring structure, and preferably, the first inner ring seal ring pattern 230 and the first outer ring seal ring pattern 220 are both rectangular rings with chamfers, each first angular virtual pattern 210 is disposed on the outer side of one chamfer of the first outer ring seal ring pattern 220, that is, 4 first angular virtual patterns 210 are disposed on the outer side of each first outer ring seal ring pattern 220.
The overall shape of the first corner virtual pattern 210 is a triangle (e.g., a right triangle) with a chamfer, that is, a chamfer is formed at the included angle between any two sides of each triangle, and the chamfer is, for example, a linear chamfer. Further, the overall shape of the first corner virtual pattern 210 is, for example, an isosceles right triangle with a chamfer, that is, the angle between the right-angle side and the hypotenuse of the triangle is 45 °. Compared with the prior art in which the corner dummy pattern is a right triangle without a chamfer, the first corner dummy pattern 210 of the right triangle with a chamfer is used as a stress buffer pattern, so that the impact of the cutting impact force on the corner area can be effectively reduced, the corner collapse risk is reduced, and the yield of the chip in the packaging process is improved.
At least one hollowed-out pattern 211 is arranged in the corner virtual pattern, and all the hollowed-out patterns 211 are arranged in parallel to the edge, opposite to the vertex of the first outer ring seal ring pattern 210, of the first corner virtual pattern 210 at intervals. The shape of the hollowed-out pattern 211 is, for example, a parallelogram, and the long directions of all the hollowed-out patterns 211 are parallel to the side of the first corner virtual pattern 210 opposite to the vertex far away from the first outer ring seal pattern 210, preferably, the length of the hollowed-out pattern 211 located on the side of the first corner virtual pattern 210 opposite to the vertex far away from the first outer ring seal pattern 210 (i.e. the hypotenuse of a right triangle) is longest. The width of the hollowed-out pattern 211 is 1.5 μm to 3 μm, and the distance between the hollowed-out pattern 211 on the side of the first corner virtual pattern 210, which is far away from the side opposite to the vertex of the first outer ring seal pattern 210, and the side of the first corner virtual pattern 210, which is far away from the vertex of the first outer ring seal pattern, is 1.5 μm to 3 μm. According to the embodiment, the impact of the cutting impact force on the corner area can be further reduced through the hollowed-out pattern, the corner collapse risk is reduced, and the yield of the chip in the packaging process is improved.
The first chip pattern 100 includes a metal layer pattern having metal lines with a width of 4X or 6X. Wherein, the value of X is 0.06 μm to 0.08 μm, namely the first layout can form a top metal layer, a top metal layer and a secondary top metal layer or a three-layer metal layer of the top layer of the chip.
Fig. 2 is a schematic structural diagram of a second layout provided in this embodiment. As shown in fig. 2, the chip layout further includes at least one second layout.
The second layout is provided with second chip patterns 100', second chip protection patterns and second scribe line region patterns 300' which are distributed in an array mode, each second chip protection pattern is enclosed on the outer side of one second chip pattern 100', the second scribe line region patterns 300' are arranged between the adjacent second chip protection patterns, the second chip patterns 100 'and the second chip protection patterns are arranged at intervals, and the second chip protection patterns and the second scribe line region patterns 300' are arranged at intervals.
The second chip protection pattern sequentially includes, from inside to outside, a second inner ring seal pattern 230', a second outer ring seal pattern 220', and a second corner virtual pattern 210', where the second inner ring seal pattern 230' and the second outer ring seal pattern 220' are both closed ring structures, and preferably, the second inner ring seal pattern 230' and the outer ring seal pattern 220' are rectangular rings with chamfers, each second corner virtual pattern 210' is disposed outside one chamfer of the second outer ring seal pattern 220', that is, 4 second corner virtual patterns 210' are disposed outside each second outer ring seal pattern 220 '.
The second corner dummy pattern 210' is an isosceles right triangle with a grid shape, and because the metal layer which is stressed first in the cutting process is a metal layer with the metal size of 4X/6X, only the corner dummy pattern in the chip protection pattern of the metal layer with the metal size of 4X or 6X needs to be modified, so that the modified layout is less, the updating of a photomask is reduced, and the cost is saved.
The second chip pattern 100' includes a metal layer pattern having metal lines with a width of less than 4X.
Example two
Fig. 3 is a schematic structural diagram of a first layout provided in this embodiment. As shown in fig. 3, compared with the first embodiment, the difference of this embodiment is that the first corner virtual pattern 210 is an isosceles right triangle with a grid shape as a whole, a bracket pattern is further disposed on the inner side of the first inner ring seal ring pattern 230, and the bracket patterns are disposed on the outer side of the first chip pattern 100 at intervals.
The first inner ring seal ring graphic 230 includes two parallel and opposite first virtual graphics 231, two parallel and opposite second virtual graphics 232, and a chamfer virtual graphics 233 connecting adjacent first virtual graphics 231 and second virtual graphics 232, where the included angle between the chamfer virtual graphics 233 and the first virtual graphics 231 is the same as the included angle between the chamfer virtual graphics 233 and the second virtual graphics 232, for example, both are 135 °.
The bracket pattern includes a first bracket pattern 234 or the bracket pattern includes a first bracket pattern 234 and a plurality of second bracket patterns 235. The first bracket patterns 234 are arranged at intervals on the inner side of the chamfer edge virtual pattern 233, and the second bracket patterns 235 connect the first bracket patterns 234 and the chamfer edge virtual pattern 233.
The shape of the first bracket graphic 234 is the same as that of the chamfer virtual graphic 233, the first bracket graphic 234 is parallel to the chamfer virtual graphic 233, and two ends of the first bracket graphic 234 are respectively connected with the first virtual graphic 231 and the second virtual graphic 232. The width of the first frame pattern 234 is 2 μm to 4 μm, and the distance between the first frame pattern 234 and the chamfer virtual pattern 233 is 10 μm to 20 μm. The first bracket pattern 234 may effectively reduce the impact of the cutting impact force on the corner region.
All the second support patterns 235 are sequentially connected end to end, two adjacent connection points are respectively connected with the first support pattern 234 and the chamfer edge virtual pattern 233, two adjacent second support patterns 235 are vertically arranged, and the impact of cutting impact force on corner areas can be effectively reduced by the first support pattern 234 and the second support patterns 235. The width of the second support pattern 235 is 1.2 μm to 3 μm.
In this embodiment, the angle between each of the second bracket patterns 235 and the first bracket pattern 234 or the angle between the second bracket pattern 235 and the chamfer virtual pattern 233 is 45 °.
Example III
Fig. 4 is a schematic structural diagram of a first layout provided in this embodiment. As shown in fig. 4, compared with the first embodiment, the difference of this embodiment is that a bracket pattern is further disposed inside the first inner ring seal pattern 230, and the bracket patterns are disposed at intervals outside the first chip pattern 100.
The first inner ring seal ring pattern includes two parallel and opposite first virtual patterns 231, two parallel and opposite second virtual patterns 232, and a chamfer virtual pattern 233 connecting adjacent first and second virtual patterns 231, where the included angle between the chamfer virtual pattern 233 and the first virtual pattern 231 is the same as the included angle between the chamfer virtual pattern 233 and the second virtual pattern 232, for example, 135 °.
The bracket pattern includes a first bracket pattern 234 or the bracket pattern includes a first bracket pattern 234 and a plurality of second bracket patterns 235. The first bracket patterns 234 are arranged at intervals on the inner side of the chamfer edge virtual pattern 233, and the second bracket patterns 235 connect the first bracket patterns 234 and the chamfer edge virtual pattern 233.
The shape of the first bracket graphic 234 is the same as that of the chamfer virtual graphic 233, the first bracket graphic 234 is parallel to the chamfer virtual graphic 233, and two ends of the first bracket graphic 234 are respectively connected with the first virtual graphic 231 and the second virtual graphic 232. The width of the first frame pattern 234 is 2 μm to 4 μm, and the distance between the first frame pattern 234 and the chamfer virtual pattern 233 is 10 μm to 20 μm. The first bracket pattern 234 may effectively reduce the impact of the cutting impact force on the corner region.
All the second support patterns 235 are sequentially connected end to end, two adjacent connection points are respectively connected with the first support pattern 234 and the chamfer edge virtual pattern 233, two adjacent second support patterns 235 are vertically arranged, and the impact of cutting impact force on corner areas can be effectively reduced by the first support pattern 234 and the second support patterns 235. The width of the second support pattern 235 is 1.2 μm to 3 μm.
In this embodiment, the angle between each of the second bracket patterns 235 and the first bracket pattern 234 or the angle between the second bracket pattern 235 and the chamfer virtual pattern 233 is 45 °.
In summary, the present invention provides a chip layout, including at least one first layout, where each first layout has a first chip pattern distributed in an array, and a first chip protection pattern wound around the outer side of the first chip pattern, where the first chip protection pattern includes a first seal ring surrounding the outer side of the first chip pattern and a first corner virtual pattern disposed on the outer side of the first seal ring, and the overall shape of the first corner virtual pattern is a triangle with a chamfer, and the first corner virtual pattern with a chamfer is used as a stress buffer pattern, so that impact of cutting impact force on a corner area can be effectively reduced, the corner collapse risk is reduced, and the yield of chips in the packaging process is improved.
Furthermore, the impact of cutting impact force on corner areas can be further reduced through the hollowed-out patterns, the risk of corner collapse is reduced, and the yield of chips in the packaging process is improved.
Further, the bracket patterns comprise a first bracket pattern or the bracket patterns comprise a first bracket pattern and a plurality of second bracket patterns; the first support patterns are arranged on the inner side of the chamfer edge virtual patterns at intervals, the second support patterns are connected with the first support patterns and the chamfer edge virtual patterns, so that the impact of cutting impact force on corner areas can be effectively reduced, the impact of the cutting impact force on the corner areas is further reduced, the corner collapse risk is reduced, and the yield of chips in the packaging process is improved.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (14)
1. The chip layout is characterized by comprising at least one first layout, wherein each first layout is provided with first chip patterns distributed in an array manner and first chip protection patterns wound on the outer side of the first chip patterns, each first chip protection pattern comprises a first sealing ring and a first corner virtual pattern, the first sealing ring is arranged on the outer side of the first chip patterns in a surrounding manner, the first corner virtual pattern is arranged on the outer side of the first sealing ring, and the whole shape of each first corner virtual pattern is a triangle with chamfer angles;
the first sealing ring sequentially comprises a first inner ring sealing ring figure and a first outer ring sealing ring figure from inside to outside, at least one hollowed-out figure is arranged in the corner virtual figure, all the hollowed-out figures are parallel and are arranged at intervals, and the hollowed-out figure is parallel to the edge, opposite to the vertex, of the first corner virtual figure, away from the first outer ring sealing ring figure.
2. The chip layout according to claim 1, wherein each of the first layouts further has a first scribe line region pattern disposed between adjacent ones of the first chip protection patterns, the first corner dummy pattern being disposed between an intersection of the two intersecting first scribe line region patterns and the first seal ring.
3. The chip layout according to claim 1, wherein the overall shape of the first corner dummy pattern is an isosceles right triangle with a chamfer, and the chamfer is a straight chamfer.
4. The chip layout according to claim 1, wherein the hollowed-out pattern is in the shape of a parallelogram.
5. The chip layout according to claim 4, wherein,
the distance between the hollowed-out pattern positioned on one side of the first corner virtual pattern, which is far away from the side opposite to the vertex of the first outer ring seal ring pattern, and the side opposite to the vertex of the first corner virtual pattern, which is far away from the first outer ring seal ring pattern, is 1.5-3 mu m; and
the width of the hollowed-out pattern is 1.5-3 mu m.
6. The chip layout according to claim 1, wherein the first chip patterns are arranged in the first inner ring seal ring patterns at intervals, and the first inner ring seal ring patterns and the first outer ring seal ring patterns are rectangular rings with chamfers, so that one first corner virtual pattern is arranged outside each chamfer of the first outer ring seal ring patterns.
7. The chip layout according to claim 6, wherein the first inner ring seal ring pattern comprises two parallel and opposite arranged first virtual patterns, two parallel and opposite arranged second virtual patterns, and a chamfer edge virtual pattern connecting adjacent first and second virtual patterns, wherein an included angle between the chamfer edge virtual pattern and the first virtual pattern is the same as an included angle between the chamfer edge virtual pattern and the second virtual pattern.
8. The chip layout according to claim 7, wherein a bracket pattern is provided on the inner side of the first inner ring seal pattern, and the bracket patterns are arranged on the outer side of the first chip pattern at intervals.
9. The chip layout according to claim 8, wherein the bracket pattern comprises a first bracket pattern or the bracket pattern comprises a first bracket pattern and a plurality of second bracket patterns;
the first support patterns are arranged on the inner side of the chamfer edge virtual pattern at intervals, and the second support patterns are connected with the first support patterns and the chamfer edge virtual pattern.
10. The chip layout according to claim 9, wherein the shape of the first support pattern is the same as the shape of the chamfer virtual pattern, the first support pattern is parallel to the chamfer virtual pattern, and two ends of the first support pattern are respectively connected with the first virtual pattern and the second virtual pattern.
11. The chip layout according to claim 10, wherein the width of the first support pattern is 2 μm to 4 μm, and the space between the first support pattern and the chamfer dummy pattern is 10 μm to 20 μm.
12. The chip layout according to claim 9, wherein all the second bracket patterns are sequentially joined end to end, two adjacent joining points are respectively connected with the first bracket pattern and the chamfer virtual pattern, and two adjacent second bracket patterns are vertically arranged.
13. The chip layout according to claim 12, wherein the width of the second support pattern is 1.2 μm to 3 μm.
14. The chip layout according to claim 1, wherein the first chip pattern comprises a metal layer pattern having metal lines with a width of 4X or 6X, wherein X has a value of 0.06 μm to 0.08 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310677388.8A CN116404006B (en) | 2023-06-09 | 2023-06-09 | Chip layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310677388.8A CN116404006B (en) | 2023-06-09 | 2023-06-09 | Chip layout |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116404006A CN116404006A (en) | 2023-07-07 |
| CN116404006B true CN116404006B (en) | 2023-08-25 |
Family
ID=87020229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310677388.8A Active CN116404006B (en) | 2023-06-09 | 2023-06-09 | Chip layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116404006B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006351878A (en) * | 2005-06-16 | 2006-12-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| CN101599465A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | Be used to protect the semiconductor structure of chip |
| CN103137567A (en) * | 2011-11-30 | 2013-06-05 | 和舰科技(苏州)有限公司 | Wafer structure for reducing damage of wafer cutting stress and layout design method |
| CN110492206A (en) * | 2019-08-09 | 2019-11-22 | 天津大学 | A kind of duplexer |
| CN113363176A (en) * | 2020-02-20 | 2021-09-07 | 格芯(美国)集成电路科技有限公司 | Chip corner region with dummy fill pattern |
| CN113853674A (en) * | 2021-02-03 | 2021-12-28 | 香港中文大学（深圳） | Chip manufacturing method, redundant metal filling method and chip |
| CN216773223U (en) * | 2021-11-04 | 2022-06-17 | 沈阳中光电子有限公司 | COB device packaging structure |
| CN114864506A (en) * | 2021-03-25 | 2022-08-05 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9059191B2 (en) * | 2011-10-19 | 2015-06-16 | International Business Machines Corporation | Chamfered corner crackstop for an integrated circuit chip |
| US9171759B2 (en) * | 2012-12-18 | 2015-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for die to die stress improvement |
| JP2018046094A (en) * | 2016-09-13 | 2018-03-22 | エイブリック株式会社 | Semiconductor chip, semiconductor device, semiconductor wafer, and method of dicing semiconductor wafer |
-
2023
- 2023-06-09 CN CN202310677388.8A patent/CN116404006B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006351878A (en) * | 2005-06-16 | 2006-12-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| CN101599465A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | Be used to protect the semiconductor structure of chip |
| CN103137567A (en) * | 2011-11-30 | 2013-06-05 | 和舰科技(苏州)有限公司 | Wafer structure for reducing damage of wafer cutting stress and layout design method |
| CN110492206A (en) * | 2019-08-09 | 2019-11-22 | 天津大学 | A kind of duplexer |
| CN113363176A (en) * | 2020-02-20 | 2021-09-07 | 格芯(美国)集成电路科技有限公司 | Chip corner region with dummy fill pattern |
| CN113853674A (en) * | 2021-02-03 | 2021-12-28 | 香港中文大学（深圳） | Chip manufacturing method, redundant metal filling method and chip |
| CN114864506A (en) * | 2021-03-25 | 2022-08-05 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN216773223U (en) * | 2021-11-04 | 2022-06-17 | 沈阳中光电子有限公司 | COB device packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116404006A (en) | 2023-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2311087B1 (en) | Integrated circuit structure | |
| JP5340047B2 (en) | Semiconductor integrated circuit device | |
| US10998277B2 (en) | Guard ring method for semiconductor devices | |
| JP2009177139A (en) | Semiconductor integrated circuit | |
| CN116404006B (en) | Chip layout | |
| CN112234028A (en) | Method for reducing stress of passivation layer and stress buffer structure of passivation layer | |
| US20070257337A1 (en) | Shield substrate, semiconductor package, and semiconductor device | |
| TWI416384B (en) | Mother board of touch panel and touch panel | |
| CN109461384B (en) | Manufacturing method of display panel or array assembly for preventing static electricity and display panel | |
| CN101599465B (en) | Semiconductor structure for protecting chip | |
| US8030773B2 (en) | Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy | |
| WO2010125619A1 (en) | Semiconductor integrated circuit chip and layout method thereof | |
| JP6875642B2 (en) | Semiconductor chips and semiconductor devices equipped with them | |
| US20210375788A1 (en) | Corner structures for an optical fiber groove | |
| US10056339B2 (en) | Semiconductor devices | |
| EP4195262A1 (en) | Semiconductor structure | |
| JP6376524B2 (en) | Wafer level package and wafer level chip size package | |
| WO2020255573A1 (en) | Semiconductor wafer and manufacturing method for semiconductor chip | |
| CN210640219U (en) | Chip protection ring and integrated circuit device | |
| JPH06326193A (en) | Semiconductor integrated circuit | |
| CN109782474B (en) | Display panel | |
| KR100949878B1 (en) | Layout Structure of a Semiconductor Device | |
| JPH0562974A (en) | Semiconductor device | |
| JPH0653320A (en) | Semiconductor device | |
| JP3171412B2 (en) | Semiconductor device and method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |