CN210640219U

CN210640219U - Chip protection ring and integrated circuit device

Info

Publication number: CN210640219U
Application number: CN201922115749.1U
Authority: CN
Inventors: 刘志拯
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-05-29
Anticipated expiration: 2029-11-29

Abstract

The disclosure relates to a chip guard ring and an integrated circuit device, wherein the chip guard ring comprises a body part and a corner part; the body part comprises a plurality of metal rings and isolating rings, the isolating rings are arranged between two adjacent metal rings, the metal rings and the isolating rings are in octagonal structures, the metal rings are in a first laminated structure in the direction perpendicular to a chip substrate, and the metal rings are electrically connected with the substrate; the corner part comprises a metal block, the projection of the metal block on the substrate is in an arch shape, the metal block is in a second laminated structure in the direction vertical to the substrate, and the metal block is electrically connected with the substrate; the corner parts are arranged at four corners of the substrate, and the projection of the corner parts and the body part on the substrate is not overlapped. The chip protection ring provided by the disclosure can enhance the protection effect on a chip.

Description

Chip protection ring and integrated circuit device

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a chip guard ring and an integrated circuit device.

Background

In a semiconductor manufacturing process, a semiconductor chip including a semiconductor active device and an interconnect structure provided on the device may be formed on a semiconductor substrate by photolithography, etching, deposition, and the like. Generally, a plurality of chips may be formed on a wafer, and finally, the chips are cut from the wafer and subjected to a packaging process to form integrated circuits. In the process of cutting the chip, the stress generated by the cutting knife can damage the edge of the chip, and even can cause the chip to collapse.

In the prior art, in order to prevent the chip from being damaged during cutting, a guard ring is arranged on the periphery of an active device area of the chip, the guard ring can prevent unwanted stress cracking of the active device area caused by stress generated by a cutting knife, and the chip guard ring can prevent chemical damage caused by water vapor permeation, such as diffusion of acid-containing substances, alkali-containing substances or pollution sources, and can also prevent electronic interference and the like outside the chip to a certain extent.

However, when sealing is performed using the guard ring of the related art, there is still a problem that the chip edge portion is broken and damaged.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a chip protection ring and an integrated circuit device, which can enhance the protection effect on a chip.

According to an aspect of the present disclosure, there is provided a chip guard ring including a body portion and a corner portion;

the body part comprises a plurality of metal rings and isolating rings, the isolating rings are arranged between two adjacent metal rings, the metal rings and the isolating rings are in octagonal structures, the metal rings are in a first laminated structure in the direction perpendicular to a chip substrate, and the metal rings are electrically connected with the substrate;

the corner part comprises a metal block, the projection of the metal block on the substrate is in an arch shape, the metal block is in a second laminated structure in the direction vertical to the substrate, and the metal block is electrically connected with the substrate;

the corner parts are arranged at four corners of the substrate, and the projection of the corner parts and the body part on the substrate is not overlapped.

In an exemplary embodiment of the present disclosure, an area of the metal block is smaller than an area of the preset triangular region.

In an exemplary embodiment of the present disclosure, the metal block is located within the preset triangular region.

In an exemplary embodiment of the present disclosure, an area of the metal block is greater than or equal to an area of a preset triangular region.

In an exemplary embodiment of the present disclosure, a part of the metal block is located outside the preset triangular region.

In an exemplary embodiment of the present disclosure, the first stacked structure includes a plurality of first metal layers, a plurality of first via holes, a plurality of first dielectric layers, and a first contact hole, the first dielectric layers being between two of the first metal layers, the plurality of first metal layers being electrically connected through the first via holes.

In an exemplary embodiment of the present disclosure, the substrate includes a first heavily doped region, the first stacked structure is located above the first heavily doped region, and the first metal layer above the first heavily doped region is electrically connected to the first heavily doped region through the first contact hole.

In an exemplary embodiment of the present disclosure, the second stacked structures each include a plurality of second metal layers, a plurality of second via holes, a plurality of second dielectric layers, and a second contact hole, the second dielectric layers are located between two of the second metal layers, and the plurality of second metal layers are electrically connected through the second via holes.

In an exemplary embodiment of the present disclosure, the substrate includes a second heavily doped region, the second stacked structure is located over the second heavily doped region, and the second metal layer over the second heavily doped region is electrically connected to the second heavily doped region through the second contact hole.

In an exemplary embodiment of the disclosure, the plurality of second through holes are strip-shaped and are sequentially arranged in a direction away from the metal ring.

In an exemplary embodiment of the present disclosure, the plurality of second through holes are parallel to each other.

In an exemplary embodiment of the present disclosure, the metal ring is grounded.

According to another aspect of the present disclosure, there is also provided an integrated circuit device including the chip guard ring described above.

The chip protection ring provided by the disclosure comprises the body part and the corner part, the metal block at the corner part is equivalent to a protection obstacle, the corner protection is formed, the protection effect of the protection ring on a chip is improved, and the reliability of the chip is improved. In addition, the projection of the metal block on the substrate is in an arc shape, namely the edge of the metal block, far away from the body part, is in an outward convex arc shape, namely the edge of the formed corner part, far away from the body part, is in an outward convex arc shape, so that the corner part has lower corner stress, the reliability of the protection ring is further improved, the protection of the protection ring on the chip is improved, and the reliability and the stability of the protection ring are improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIG. 1 is a schematic diagram of a chip guard ring according to an embodiment of the disclosure;

FIG. 2 is a cross-sectional view taken along the line A-A in FIG. 1;

FIG. 3 is a schematic diagram of a chip guard ring according to an embodiment of the disclosure;

fig. 4 is a schematic diagram of a metal block having an area smaller than an area of a predetermined triangular region according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a metal block having an area equal to an area of a predetermined triangular region according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a metal block having an area larger than a predetermined triangular region according to an embodiment of the disclosure.

Description of reference numerals:

10. a body part 11, a metal ring 12, an isolation ring 110, a first metal layer 120, a first through hole 130, a first dielectric layer 140 and a first contact hole;

20. corner parts 210, a second metal layer 220, a second through hole 230, a second dielectric layer 240 and a second contact hole;

30. the substrate comprises a substrate 310, a shallow trench isolation region 320, a first heavily doped region 330 and a second heavily doped region.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. However, it will be appreciated by one skilled in the art that aspects of the disclosure may be practiced without one or more of the specific details. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and the like are used merely as labels, and are not limiting on the number of their objects.

In the present exemplary embodiment, a chip protection ring is first provided, as shown in fig. 1 to 3, the chip protection ring includes a body portion 10 and a corner portion 20, the body portion 10 includes a plurality of metal rings 11 and isolation rings 12, the isolation rings 12 are disposed between two adjacent metal rings 11, each of the metal rings 11 and the isolation rings 12 is an octagonal structure, the metal rings 11 are in a first stacked structure in a direction perpendicular to a substrate 30 of a chip, and the metal rings 11 are electrically connected to the substrate 30. The corner portion 12 includes a metal block, a projection of which on the substrate 30 is arcuate, the metal block being in a second stacked structure in a direction perpendicular to the substrate 30, the metal block being electrically connected to the substrate 30. The corner portions 20 are disposed at four corners of the substrate 30, and the corner portions 20 do not overlap with the projection of the body portion 10 on the substrate 30.

During the dicing process to separate the integrated circuit devices from the wafer, the mechanical stress is more likely to cause damage to the corners than other areas of the integrated circuit devices. For example, the slicing process may create cracks in the corners, or a portion of the corners may even break. Also, the damaged area may serve as a core for delamination, and damage may extend to the guard ring, thereby making the active area of the integrated circuit susceptible to delamination or environmental stress. The chip protection ring provided by the disclosure comprises a body part 10 and a corner part 20, wherein a metal block of the corner part 20 is equivalent to a protection barrier, so that the corner protection is formed, the protection effect of the protection ring on a chip is improved, and the reliability of the chip is improved.

In addition, the projection of the metal block on the substrate 30 is in an arc shape, that is, the edge of the metal block far away from the main body portion 10 is in an outward convex arc shape, that is, the edge of the formed corner portion 20 far away from the main body portion 10 is in an outward convex arc shape, so that the corner portion 20 has lower corner stress, the reliability of the protection ring is further improved, the protection of the protection ring on the chip is improved, and the reliability and the stability of the protection ring are increased.

As shown in fig. 2, the first stacked structure includes a plurality of first metal layers 110, a plurality of first via holes 120, a plurality of first dielectric layers 130, and first contact holes 140, the first dielectric layers 130 are located between the two first metal layers 110, and the plurality of first metal layers 110 are electrically connected through the first via holes 120.

Specifically, the number of the first metal layers 110 can be 2-8, so that the protective layer has sufficient structural strength and the difficulty in increasing the manufacturing process of the protective ring is avoided; the material of the first metal layer 110 may be at least one of copper, aluminum, tungsten, cobalt, nickel, neodymium, platinum, titanium, and chromium, and the material of each first metal layer 110 may be different or the same, and may be selected by those skilled in the art according to actual needs; the width of the first metal layer 110 may be 0.2 μm to 5 μm, for example, 0.2 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, which is not listed here. The widths of the first metal layers 110 are the same, of course, the widths of the first metal layers 110 may also be different, the width of the first metal layer 110 may also be less than 0.2 μm or greater than 5 μm, and the number of the first metal layers 110 may also be less than 2 or greater than 8, which is not limited in this disclosure. In addition, the material of the first dielectric layer 130 includes at least one of silicon oxide, silicon nitride, silicon carbide, and fluorosilicate glass. The first via 120 may be located in a middle portion of the first metal layer 110 in the width direction, and the material of the first via 120 includes at least one of copper, aluminum, tungsten, cobalt, nickel, neodymium, platinum, titanium, chromium, and polysilicon. The width of the first through hole 120 is 0.1 μm to 3 μm, which prevents the occupation of too large space while ensuring the sufficient barrier protection. Of course, the width of the first via 120 may also be less than 0.1 μm or greater than 3 μm. In addition, two first through holes 120 may be included between adjacent first metal layers 110, and the two first through holes 120 are disposed at intervals, so as to further improve the structural strength of the metal ring 110, increase the protection effect on the chip, and improve the reliability of the protection ring. Of course, three, four or more first vias 120 may be included between adjacent first metal layers 110, which is not limited by the present disclosure.

Further, as shown in fig. 2, the substrate 30 includes first heavily doped regions 320, the first heavily doped regions 320 are located between the shallow trench isolation regions 310, the first stacked structure is located above the first heavily doped regions 320, and the first metal layer 110 above the first heavily doped regions 320 is electrically connected to the first heavily doped regions 320 through the first contact holes 140. The material of the first contact hole 140 includes at least one of copper, aluminum, tungsten, and polysilicon, the width of the first contact hole 140 is 0.1 μm to 3 μm, and the width of the first contact hole 140 is the same as that of the first via hole 120. Of course, the width of the first contact hole 140 may be less than 0.1 μm or greater than 3 μm, and the widths of the first contact hole 140 and the first via hole 120 may be different.

As shown in fig. 2, the second stacked structure includes a plurality of second metal layers 210, a plurality of second via holes 220, a plurality of second dielectric layers 230, and second contact holes 240, the second dielectric layers 230 are located between the two second metal layers 210, and the plurality of second metal layers 210 are electrically connected through the second via holes 220.

Specifically, the number of the second metal layers 210 can be 2-8, so that the protective layer has sufficient structural strength and the difficulty in increasing the manufacturing process of the protective ring is avoided; the material of the second metal layer 210 may be at least one of copper, aluminum, tungsten, cobalt, nickel, neodymium, platinum, titanium, and chromium, and the material of each second metal layer 210 may be different or the same, and may be selected by those skilled in the art according to actual needs; the width of the second metal layer 110 is 0.2 μm to 5 μm, for example, 0.2 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, which is not listed here. The widths of the second metal layers 210 are the same, of course, the widths of the second metal layers 210 may also be different, the width of the second metal layer 110 may also be less than 0.2 μm or greater than 5 μm, and the number of the second metal layers 210 may also be less than 2 or greater than 8, which is not limited in this disclosure. The material of the second dielectric layer 230 includes at least one of silicon oxide, silicon nitride, silicon carbide, and fluorosilicate glass.

Further, as shown in fig. 2, the substrate 30 includes a second heavily doped region 330, the second heavily doped region 330 is located between the shallow trench isolation regions 310, the second stacked structure is located above the second heavily doped region 330, and the second metal layer 210 above the second heavily doped region 330 is electrically connected to the second heavily doped region 330 through the second contact hole 240. The material of the second contact hole 240 includes at least one of copper, aluminum, tungsten, and polysilicon, the width of the second contact hole 240 is 0.1 μm to 3 μm, and the width of the second contact hole 240 is the same as that of the second contact hole 220. Of course, the width of the second contact hole 240 may be less than 0.1 μm or greater than 3 μm, and the widths of the second contact hole 240 and the second via hole 220 may be different.

The first dielectric layer 130 and the second dielectric layer 230 may be the same dielectric layer, that is, the first metal layer 110, the first via 120, the second metal layer 210 and the second via 220 are disposed in the same dielectric layer, which can reduce the difficulty of the process for manufacturing the guard ring and reduce the manufacturing cost. The spacer ring 12 is formed by a dielectric layer between the two metal rings 11. Of course, the isolation ring 12 may also be a separate structure formed from the substrate 10, which is not limited by the present disclosure.

As shown in fig. 1 and 2, the corner portion 20 includes a plurality of second through holes 220, that is, a plurality of second through holes 220 are disposed between two adjacent second metal layers 210, and the second through holes 220 are spaced between two adjacent second metal layers 210. The material of the second through hole 220 includes at least one of copper, aluminum, tungsten, cobalt, nickel, neodymium, platinum, titanium, chromium, and polysilicon, and the width of the second through hole 220 is 0.1 μm to 3 μm, such as 0.2 μm, 0.5 μm, 1 μm, 2 μm, and 3 μm, to name but not limited thereto, while ensuring sufficient barrier protection, the second through hole does not occupy too large space. Of course, the width of the second via 220 may also be less than 0.1 μm or greater than 3 μm.

Further, as shown in fig. 1, each second through hole 220 is strip-shaped and sequentially arranged in a direction away from the metal ring 11, and two ends of each second through hole extend towards the side edges on two sides of the oblique edge at the corner of the metal ring 11, respectively, so as to guide the defect to make the defect away from the oblique edge at the corner of the metal ring 11, thereby forming a blocking effect on the defect and preventing the defect from directly extending from the corner 20 to the metal ring 11; in addition, the plurality of strip-shaped second through holes 220 are equivalent to a plurality of partition walls arranged at intervals relative to the columnar through holes, and the partition walls have a larger protection range, can guide defects generated in more directions, and improve the chip protection effect of the corner part 20; in addition, the plurality of strip-shaped second through holes 220 are arranged at intervals, each second through hole 220 can form a partition wall, and the plurality of partition walls can guide a plurality of defects, so that the chip protection effect of the corner part 20 is further improved; in addition, the strip-shaped second through hole 220 is adopted, so that the connection strength between the adjacent second metal layers 210 is increased, the structural strength of the corner part 20 is improved, and the chip protection effect of the corner part 20 is further improved; in addition, the strip-shaped second through hole 220 is adopted, so that the area of the through hole is increased relative to the columnar through hole, the interference of external electrons to the chip can be further prevented, and the protective effect of the corner part 20 on the chip is improved.

The second through holes 220 are parallel to each other, so that more strip-shaped second through holes 220 are formed on the second metal layer 210 with a certain area.

In addition, as shown in fig. 2, the number of the metal layers in the body portion 10 and the corner portion 20 may be the same, and each corresponding first metal layer 110 and second metal layer 210 are in an opposite layer, that is, when the guard ring is formed, each first metal layer 110 and the second metal layer 210 in the same layer thereof may be formed through one process, thereby reducing the process difficulty, reducing the manufacturing cost, and improving the manufacturing efficiency. Of course, the number of metal layers in the body portion 10 and the corner portion 20 may be different.

Further, the metal ring 11 is grounded, and the metal block is floating and is not grounded.

As shown in fig. 1 and 3, the body portion 10 includes two metal rings 11. By arranging the two metal rings 11, the protection effect of the protection ring can be enhanced, and after the outer metal ring 11 is damaged due to stress, the inner metal ring 11 can continue to protect the chip, so that the reliability of the protection ring is improved. Of course, three or an equal number of metal rings 11 may also be provided, as the present disclosure is not limited in this regard.

The number of the first metal layers 110 of each metal ring 11 may be the same, and when forming the first metal ring and the second metal ring, the first metal layers 110 located on the same layer may be formed at the same time, so as to reduce the process difficulty and the manufacturing cost. In addition, the number and width of the first vias 120 in each metal ring 11 are the same, so as to reduce the process difficulty of manufacturing the guard ring. Of course, the number and width of the first through holes 120 in each metal ring 11 may also be different.

As shown in fig. 1 and 3, the metal ring 11 and the isolation ring 12 are octagonal to form four corner regions, and each corner region forms a predetermined triangular region a, which may be a triangular region formed by enclosing a hypotenuse at a corner of the metal ring 11 and an extension line extending from edges at two sides of the metal ring.

As shown in fig. 4, the area of the metal block is smaller than the area of the predetermined triangular region a. When the metal block is formed at the corner, the metal block can be conveniently arranged at the corner area due to the small area of the metal block, and the requirement on the position accuracy of the metal block formation is lowered; in addition, when the slicing process is carried out, the area of the metal block is small, the occupied area is also relatively small, and the substrate can be conveniently sliced, so that the manufacturing process difficulty is reduced, and the process cost is reduced.

Furthermore, as shown in fig. 4, the metal block is located in the preset triangular area a, during a dicing process for separating the integrated circuit device from the wafer, since the metal block is located in the triangular area formed by the bevel edge at the corner of the metal ring 11 and the extension lines extending from the edges at the two sides, the dicing process does not damage the metal block, thereby avoiding directly damaging the metal block during the dicing process, ensuring the reliability of the metal block, and ensuring the protection effect of the metal block on the chip; in addition, because the metal block is located in the triangular region formed by the extending line which is formed by enclosing the bevel edge at the corner of the metal ring 11 and the extending lines extending from the edges of the two sides, the integrated circuit device can be conveniently separated from the wafer slice, the slicing process difficulty is reduced, and the reliability of the protection ring is improved. Of course, the local part of the metal block may also be located outside the preset triangular area a, which is not limited by the present disclosure.

As shown in fig. 5, the area of the metal block is equal to the area of the preset triangular area a, that is, the area of the metal block outside the triangular area a is the same as the area of the preset triangular area a where no metal block is disposed. The radian of the edge of the metal block away from the body part 10 can be further improved by adopting the metal block with the same area as the preset triangular area A, so that the corner part 20 has lower corner stress, the reliability of the protection ring is further improved, the protection of the protection ring on a chip is improved, and the reliability and the stability of the protection ring are improved.

As shown in fig. 6, the area of the metal block is larger than the area of the preset triangular region a, and the metal block with a larger area can further increase the radian of the edge of the metal block away from the body portion 10, so that the corner portion 20 has a lower corner stress, the area of the metal block covering the corner portion is increased, and more second through holes 220 can be arranged on the metal block, thereby enhancing the blocking effect and the bearing capacity of the corner portion 20 on defects, thereby improving the protection of the protection ring on the chip, and increasing the reliability and the stability of the protection ring.

Furthermore, the part of the metal block is located outside the preset triangular area a, namely the area of the metal block is larger than that of the preset triangular area a, the metal block with a larger area is adopted, the corner stress can be reduced, the reliability of the protection ring is further improved, the area protected by the metal block is increased along with the increase of the area of the metal block, the blocking effect and the bearing capacity of the corner part 20 on the defect can be increased, more defects can be blocked and borne, the defect is prevented from extending to the metal ring 11 towards the metal ring 11, and the reliability and the stability of the protection ring are further improved.

In addition, the areas of the metal blocks in the four preset triangular regions a may be different, for example, there may be a metal block whose area is greater than the area of the preset triangular region a, a metal block whose area is equal to the area of the preset triangular region a, and a metal block whose area is less than the area of the preset triangular region a at the same time, which is not limited by the present disclosure.

The disclosure also provides an integrated circuit device, which includes the above chip protection ring, and the technical effect of the integrated circuit device can refer to the discussion of the technical effect of the above chip protection ring, which is not described herein again.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A chip guard ring, comprising a body portion and a corner portion;

2. The chip guard ring of claim 1, wherein an area of the metal block is smaller than an area of a predetermined triangular region.

3. The chip guard ring of claim 2, wherein the metal block is located within the predetermined triangular region.

4. The chip guard ring of claim 1, wherein an area of the metal block is greater than or equal to an area of a predetermined triangular region.

5. The chip guard ring of claim 4, wherein a portion of the metal block is located outside the predetermined triangular region.

6. The chip guard ring of claim 1, wherein the first stack structure includes a plurality of first metal layers, a plurality of first vias, a plurality of first dielectric layers, and a first contact hole, the first dielectric layers being between two of the first metal layers, the plurality of first metal layers being electrically connected through the first vias.

7. The chip guard ring of claim 6, wherein the substrate comprises a first heavily doped region, the first stacked structure is over the first heavily doped region, and a first metal layer over the first heavily doped region is electrically connected to the first heavily doped region through the first contact hole.

8. The chip guard ring of claim 1 or 6, wherein the second stacked structures each include a plurality of second metal layers, a plurality of second vias, a plurality of second dielectric layers, and a second contact hole, the second dielectric layers being between two of the second metal layers, the plurality of second metal layers being electrically connected through the second via hole.

9. The chip guard ring of claim 8, wherein the substrate comprises a second heavily doped region, the second stacked structure is over the second heavily doped region, and the second metal layer over the second heavily doped region is electrically connected to the second heavily doped region through the second contact hole.

10. The chip guard ring of claim 8, wherein the second through holes are strip-shaped and are sequentially arranged in a direction away from the metal ring.

11. The guard ring of claim 10, wherein the plurality of second vias are parallel to each other.

12. The chip guard ring of claim 1, wherein the metal ring is grounded.

13. An integrated circuit device comprising the chip guard ring of any of claims 1-12.