CN216288375U - Wafer - Google Patents

Abstract

The utility model provides a wafer, this wafer includes a plurality of chips and scribing way, and adjacent chip in a plurality of chips is divided to the scribing way, and wherein, partial or all apex angles of at least part chip are provided with first protection architecture outward, and first protection architecture is located the scribing way, along the cross-section that is on a parallel with the wafer surface, and first protection architecture is crooked or the bar pattern of buckling, partly surrounds corresponding apex angle. The wafer can relieve the stress concentration problem at the top corner of the chip during scribing by arranging the protection structure adjacent to and semi-surrounding the top corner of the chip in the scribing channel. Meanwhile, because of the protection structure is arranged in the scribing channel and is adjacent to the top angle of the chip, the occupied scribing channel area is small, enough space is reserved for other structures in the scribing channel, and the utilization efficiency of the scribing channel is increased.

Description

Wafer

Technical Field

The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to wafers.

Background

After the wafer processing process is completed, the wafer is usually cut along a scribe line (or called a scribe line) to obtain a single chip (die), so as to facilitate subsequent chip packaging. This cutting step is commonly referred to as dicing. The existing chip is generally rectangular, and in the scribing process, the vertex angle of the chip often has a stress concentration phenomenon, so that the vertex angle of the chip is cracked or the edge of the chip has an invisible crack. Chips with broken top corners can be generally removed through testing, but the yield of products is reduced, and waste is caused. For the chip with the invisible crack, early parameter abnormality may not be caused and the chip is taken as a qualified chip to be shipped or continuously packaged, but the invisible crack is likely to continue to extend, so that the chip fails in the subsequent processing or use process, and a potential risk exists.

In order to solve the above problems, the prior art generally tends to increase the width of the scribe line, but this method inevitably increases the total area of the chip, and reduces the chip yield of the wafer; or a transition region is additionally arranged between the chip and the scribing channel, even a protection ring is required to be arranged in the transition region under certain conditions so as to achieve the purposes of protecting the functional region of the chip and preventing the chip from cracking or cracking in the scribing process.

Therefore, it is necessary to improve the existing wafer structure, and on the premise of not losing the effective utilization rate of the wafer, the problem of chip failure caused by cutting the wafer is reduced, thereby improving the yield of the product.

SUMMERY OF THE UTILITY MODEL

In view of this, the present disclosure provides an improved wafer, in which a first protection structure is disposed in a scribe lane, the first protection structure being adjacent to and semi-surrounding a chip vertex angle, so as to take account of both wafer utilization and chip quality.

The wafer provided by the embodiment of the disclosure comprises a plurality of chips and scribing channels, wherein the scribing channels separate adjacent chips in the plurality of chips, a first protection structure is arranged outside part or all top corners of at least part of the chips, the first protection structure is positioned in the scribing channels, and along a section parallel to the surface of the wafer, the first protection structure is a bent or bent strip-shaped pattern and semi-surrounds the corresponding top corners.

Optionally, the bar pattern is L-shaped or C-shaped.

Optionally, the first protection structure is spaced apart from a top corner of the corresponding chip.

Optionally, the chip further includes a substrate and an insulating layer on the substrate, where at least a portion of the chip includes a semiconductor device functional region in the substrate and a metal interconnection layer penetrating through the insulating layer, and the first protection structure corresponding to the portion of the chip includes a metal strip and a conductive plug corresponding to the metal interconnection layer.

Optionally, the device structure layer includes a substrate and a device structure layer located on the substrate, where at least a part of the chip includes a semiconductor device functional region located in the substrate and the device structure layer, an insulating layer located in the device structure layer, and a multilayer metal interconnection layer passing through the insulating layer, and the first protection structure corresponding to the part of the chip includes a metal strip and a conductive plug corresponding to the multilayer metal interconnection layer.

Optionally, the first protection structure further comprises a trench isolation structure located in the substrate.

Optionally, a plurality of groups of protection units are further disposed in the scribe lane, and are respectively located on one side of the first protection structure away from the corresponding chip, and are separated from the first protection structure.

Optionally, the protection unit includes one or more separated second protection structures, wherein the plurality of second protection structures in one protection unit are sequentially arranged along a direction toward an edge of the center of the corresponding chip.

Optionally, in a cross section parallel to the surface of the wafer, the second protection structures are in a curved or bent stripe pattern, semi-surrounding the respective first protection structures.

Optionally, the second protective structure is the same structure as the first protective structure.

The wafer of the embodiment of the disclosure can relieve the stress concentration problem at the top corner of the chip when scribing by setting the first protection structure adjacent to and semi-surrounding the top corner of the chip in the scribing channel, and does not occupy the area of the chip because the first protection structure is arranged in the scribing channel. Meanwhile, the first protection structure is only arranged aiming at the top corner of the chip, the occupied area of the scribing channel is small, and enough space is reserved for other structures in the scribing channel, so that the width of the scribing channel does not need to be increased, and the utilization efficiency of the scribing channel is increased.

Moreover, because the first protection structure in the embodiment of the disclosure replaces part of the function of the conventional protection ring, in the specific implementation process, the number of the protection rings can be properly reduced, so that the area of the transition region (i.e., the region for arranging the protection ring) can be reduced, the available area of the functional region of the semiconductor device can be increased, the utilization rate of the wafer can be increased, and the chip cost can be reduced.

Furthermore, a plurality of groups of protection units corresponding to the first structures are arranged in the scribing channel, each protection unit comprises one or more second protection structures which semi-surround the first protection structures, and stress is further prevented from being transmitted to the top angle of the chip during scribing.

Therefore, the wafer disclosed by the invention can reduce the chip failure caused by cutting the wafer on the premise of not losing the effective utilization rate of the wafer, and the yield of products is improved.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Fig. 1 shows a top view of a wafer of a first embodiment of the present disclosure.

Fig. 2 is a schematic perspective view illustrating a first structure of a portion of the chip and the scribe line region in fig. 1.

Fig. 3 is a schematic diagram illustrating a second three-dimensional structure of a portion of the chip and the scribe line region in fig. 1.

Fig. 4 shows a top view of a wafer of a second embodiment of the present disclosure.

Fig. 5 shows a first cross-sectional view along line AA in fig. 4.

Fig. 6 shows a second cross-sectional view taken along line AA in fig. 4.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

The present disclosure may be presented in various forms, some examples of which are described below.

Fig. 1 shows a top view of a wafer according to a first embodiment of the disclosure, fig. 2 shows a first three-dimensional structural diagram of a portion of a chip and a scribe lane region in fig. 1, and fig. 3 shows a second three-dimensional structural diagram of a portion of a chip and a scribe lane region in fig. 1. For clarity, the specific structures of the insulating layer and the chip 100 are not shown in fig. 2 and 3.

As shown in fig. 1, the wafer 10 includes a plurality of chips 100 and scribe lanes 11, the chips 100 are arranged in rows and columns in an array, and the scribe lanes 11 are formed in an area between adjacent chips 100. Wherein each chip 100 is substantially rectangular with 4 corners and a plurality of spaced first guard structures 110 in the scribe line 11.

In this embodiment, the first protection structures 110 are disposed outside the 4 corners of each chip 100, each first protection structure 110 is located in the scribe line 10, and each first protection structure 110 is separated from the corresponding corner of the chip 100. In some embodiments, the distance between the first protection structure 110 and the chip 100 is 1-2 μm. Of course, the embodiments of the present disclosure are not limited thereto, and a person skilled in the art may perform other arrangements on the distance between the first protection structure 110 and the chip 100 as needed, and may also provide the first protection structure 110 only for a part of the chip 100, or provide the first protection structure 110 only for certain top corners of some chips 100 as needed.

In a cross section parallel to the surface of the wafer 10, the first protective structures 110 are in a curved or bent stripe pattern, half surrounding the top corners of the respective chips 100. In this embodiment, the first protection structure 110 is L-shaped, but the bending angle of the first protection structure 110 is not limited to 90 °, and those skilled in the art can perform other settings on the bending angle of the first protection structure 110 as required. In some other embodiments, the bending angle of the first protection structure 110 is chamfered, such as in a C-shape. Other arrangements of the shape of the first protection structure 110 may be made as required by those skilled in the art.

The specific structure of the first protection structure 110 may be determined according to the actual structure of the chip 100. In the case where the structure of the chip 100 is simple, as shown in fig. 2, the wafer 10 includes a substrate 101, an insulating layer (not shown) on the substrate 101, and a metal interconnection layer (not shown) in the insulating layer, along the thickness direction of the wafer 10. The chip 100 includes, for example, a semiconductor device functional region in the substrate 101 for forming a semiconductor device, such as a diode, a transistor, or a simple discrete device, and a metal interconnection layer penetrating through the insulating layer and connected to the semiconductor device functional region. Such a chip 100 with a simple structure generally has only one metal interconnection layer, that is, the metal interconnection layer includes a conductive plug located in an insulating layer and a metal layer located on the surface of the insulating layer to implement electrode lead-out; correspondingly, the first protection structure 110 may also have only one layer of metal strip 112 and one layer of conductive plug 111, in other words, the first protection structure 110 may include the conductive plug 111 penetrating the insulating layer 102 and the metal strip 112 on the surface of the insulating layer 102, and the metal strip 112 is connected to the conductive plug 111.

In some other embodiments, the wafer 10 includes a substrate 101 and a device structure layer located on the substrate 101, in the case that the structure of the chip 100 is complex, such as the chip 100 is a CMOS device or a more complex semiconductor device or even an integrated circuit, the chip 100 includes, for example, a semiconductor device functional region located in the substrate 101 and the device structure layer, wherein the device structure layer includes, for example, a gate dielectric layer, a gate conductor, an insulating layer covering the gate dielectric layer and the gate conductor, and a metal interconnection layer passing through the insulating layer on the substrate 101; in addition, a plurality of doped regions (as well regions, source/drain regions, etc.) are formed in the substrate 101, and the doped regions, the gate dielectric layer, the gate conductor, the insulating layer, and the metal interconnection layer are all formed in the functional region of the semiconductor device. The metal interconnection layers of the chip 100 with a more complex structure are typically multi-layered, and correspondingly, the first protection structure 110 may also have a plurality of metal strips and a plurality of conductive plugs, and the metal strips and the conductive plugs are typically arranged alternately. As shown in fig. 3, the first protection structure 110 includes a conductive plug 111, a metal strip 112, a conductive plug 113, a metal strip 114, a conductive plug 115, a metal strip 116, a conductive plug 117, and a metal strip 118 in sequence. In some other embodiments, the first protection structure 110 further comprises a trench isolation structure 119 located in the substrate 101.

Fig. 4 shows a top view of a wafer according to a second embodiment of the present disclosure, fig. 5 shows a first cross-sectional view taken along line AA in fig. 4, and fig. 6 shows a second cross-sectional view taken along line AA in fig. 4.

As shown in fig. 4, the wafer 10 has a plurality of chips 100 and scribe lanes 11, the chips 100 are arranged in rows and columns in an array, and the scribe lanes 11 are formed in the area between adjacent chips 100. Wherein each chip 100 is substantially rectangular with 4 corners and a plurality of spaced first guard structures 110 in the scribe line 11.

The first protection structure 110 in this embodiment is substantially the same as the first embodiment, and the description of the same parts is omitted. The difference from the first embodiment is that the scribe lane 11 of the present embodiment further has a plurality of groups of protection units 12, which are in one-to-one correspondence with the first protection structures 110, located on a side of the first protection structures 110 away from the corresponding chip 100, and separated from the first protection structures 110. I.e. the guard units 12 are relatively closer to the middle area of the scribe street 11 than the corresponding first guard structure 110. Each group of protection units 12 includes two separated second protection structures 120a and 120b, and the second protection structures 120a and 120b are sequentially arranged along a direction toward an edge of the center of the corresponding chip 100. In some embodiments, the distance between the first protective structure 110 and the second protective structure 120a and the distance between the adjacent second protective structures 120a and 120b are 1-3 μm. Of course, the embodiment of the present disclosure is not limited thereto, and a person skilled in the art may provide the protection unit 12 only for a part of the first protection structure 110 as needed; the distance between the adjacent protection structures can be set in other ways according to requirements; other arrangements of the number of second protection structures in each group of protection units 12 may also be made as desired, for example there may be only the second protection structure 120a, etc.

In a cross section parallel to the surface of the wafer 10, the second protection structures 120a, 120b are in a curved or bent stripe pattern, and semi-surround the corresponding first protection structures 110. In this embodiment, the second protection structures 120a, 120b are L-shaped; the included angle of the L-shape is not limited to 90 degrees, of course. In some other embodiments, the second protective structures 120a, 120b may also be C-shaped, i.e., the second protective structures 120a, 120b have smooth corners. In the present embodiment, the second protection structures 120a and 120b have the same composition structure as the first protection structure 110, for example, when the first protection structure 110 includes the conductive plugs 111 and the metal strips 112, the second protection structures 120a and 120b also include the same number of conductive plugs and metal strips, as shown in fig. 5. When the first protection structure 110 includes the conductive plugs 111, the metal strips 112, 113, 114, 115, 116, 117, and 118, the second protection structures 120a and 120b also include the same number of conductive plugs and metal strips, as shown in fig. 6. In addition, if the first protection structure 110 further includes a trench isolation structure 119 located in the substrate 101, the second protection structures 120a and 120b may also include the trench isolation structure 119 located in the substrate 101.

In the above embodiments of the disclosure, the first protection structure 110 and the second protection structures 120a and 120b may be formed simultaneously with the chip 100 process, or may be formed only along with the metal interconnection layer of the chip 100. For example, for a chip 100 having only one metal interconnection layer, a metal plug and an L-shaped metal strip may be simultaneously formed on the substrate 101 located in the scribe lane 11 as a stress protection structure when forming the metal interconnection layer. For a chip 100 with a more complex structure such as a CMOS, the stress protection structure may be formed simultaneously with the chip 100 process (including a device structure layer on the substrate 101, L-shaped metal strips in the device structure layer, an insulating layer, and L-shaped metal strips), or may be formed only with the fabrication of multiple metal interconnection layers of the chip 100, and the stress protection structure and the chip 100 are formed on the same substrate 101, and include a plurality of L-shaped metal strips stacked on the substrate 101 in sequence and conductive plugs disposed between adjacent L-shaped metal strips (the number of layers of interconnection metal strips of the chip 100 determines the number of layers stacked in the L-shaped metal strips).

In the above embodiments of the present disclosure, the scribe line 11 should further have a photolithography alignment mark, a photolithography width measurement structure, a thickness measurement structure, an electrical performance detection structure, and the like. The above structure is common knowledge in semiconductor manufacturing and will not be described herein. It should be noted that, due to the above structure, for the sake of avoidance, the protection structure is not necessarily disposed outside the top corner of the partial chip 100, or only the first protection structure 110 is disposed; or one, two or three corners of part of the chip 100 are provided with the protection structures, instead of all four corners. Meanwhile, the stress protection structure in the embodiment of the disclosure may share a reticle with the chip 100, and does not increase the manufacturing cost.

According to the wafer of the embodiment, the first protection structure which is adjacent to the top corner of the chip and semi-surrounds the top corner is arranged in the scribing channel, so that the problem of stress concentration at the top corner of the chip can be relieved during scribing, and the chip is prevented from being damaged; and because the first protection structure is arranged in the scribing channel, the area of the chip can not be occupied. Meanwhile, the first protection structure is only arranged aiming at the top corner of the chip, the width of the scribing channel is not required to be increased, and compared with the protection ring, the area of the scribing channel occupied by the divided first protection structure is small, so that enough space is reserved for other structures in the scribing channel, and the utilization efficiency of the scribing channel is increased.

Moreover, because the protection structure in the embodiment of the disclosure replaces part of the function of the conventional protection ring, in the specific implementation process, the number of the protection rings can be properly reduced, so that the area of the transition region (i.e., the region for arranging the protection ring) can be reduced, the available area of the functional region of the semiconductor device is increased, the utilization rate of the wafer is increased, and the chip cost is reduced.

Furthermore, a plurality of groups of protection units corresponding to the first structures are arranged in the scribing channel, each protection unit comprises one or more second protection structures which semi-surround the first protection structures, stress can be further prevented from being transmitted to the top angle of the chip when scribing is carried out, and the protection capability and the protection effect on the chip are further improved.

Therefore, the wafer disclosed by the invention can reduce the chip failure caused by cutting the wafer and improve the yield of products on the premise of at least not losing the effective utilization rate of the wafer.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A wafer comprising a plurality of chips and scribe lanes separating adjacent ones of the plurality of chips,

wherein, a first protection structure is arranged outside part or all top corners of at least part of the chip, the first protection structure is positioned in the scribing channel,

and along the section parallel to the surface of the wafer, the first protection structure is in a bent or bent strip-shaped pattern and semi-surrounds the corresponding top corner.

2. The wafer of claim 1, wherein the bar pattern is L-shaped or C-shaped.

3. The wafer of claim 1, wherein the first protection structures are spaced apart from corresponding top corners of the chips.

4. The wafer of claim 1, comprising a substrate and an insulating layer on the substrate,

wherein at least part of the chip comprises a semiconductor device functional region in the substrate and a metal interconnection layer penetrating through the insulating layer,

the first protection structure corresponding to the part of the chip comprises a metal strip and a conductive plug corresponding to the metal interconnection layer.

5. The wafer of claim 1, comprising a substrate and a device structure layer on the substrate,

wherein at least part of the chip comprises a semiconductor device functional region positioned in the substrate and the device structure layer, an insulating layer positioned in the device structure layer and a plurality of metal interconnection layers penetrating through the insulating layer,

the first protection structure corresponding to the part of the chip comprises a metal strip and a conductive plug corresponding to the multilayer metal interconnection layer.

6. The wafer of claim 5, wherein the first protective structure further comprises a trench isolation structure in the substrate.

7. The wafer according to any one of claims 1 to 6, wherein a plurality of groups of protection units are further disposed in the scribe lane, and are respectively located on a side of the first protection structure away from the corresponding chip and separated from the first protection structure.

8. The wafer of claim 7, wherein the protection unit comprises one or more separate second protection structures,

the plurality of second protection structures in one protection unit are sequentially arranged along the direction corresponding to the center of the chip towards the edge.

9. The wafer of claim 8, wherein the second protective structures are in a curved or bent stripe pattern, semi-surrounding the respective first protective structures, in a cross section parallel to the surface of the wafer.

10. The wafer of claim 8, wherein the second protective structure is the same structure as the first protective structure.

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