WO2022163346A1 - 固体撮像装置及び電子機器 - Google Patents

固体撮像装置及び電子機器 Download PDF

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Publication number
WO2022163346A1
WO2022163346A1 PCT/JP2022/000668 JP2022000668W WO2022163346A1 WO 2022163346 A1 WO2022163346 A1 WO 2022163346A1 JP 2022000668 W JP2022000668 W JP 2022000668W WO 2022163346 A1 WO2022163346 A1 WO 2022163346A1
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Prior art keywords
wiring
state imaging
solid
substrate
imaging device
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PCT/JP2022/000668
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English (en)
French (fr)
Japanese (ja)
Inventor
大伸 福井
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2022578212A priority Critical patent/JPWO2022163346A1/ja
Priority to US18/261,615 priority patent/US20240395835A1/en
Priority to CN202280010842.8A priority patent/CN116711078A/zh
Publication of WO2022163346A1 publication Critical patent/WO2022163346A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • the present disclosure relates to solid-state imaging devices and electronic devices.
  • a photoelectric conversion portion and at least part of a pixel circuit for reading out the charge stored in the photoelectric conversion portion have been provided on separate substrates.
  • a so-called 3D sequential technology has been proposed, in which the substrates are arranged in the same direction and bonded together to form a single chip.
  • the wiring density (ratio of wiring area to cell size) of the 3D sequential structure is lower than that of the structure in which the pixel circuit, the photoelectric conversion unit, and the transfer transistor are arranged on a single substrate (hereinafter, also referred to as a flat structure). Not much different from that. Therefore, in the conventional 3D sequential structure, there is a possibility that the reduction in parasitic capacitance due to the reduction in wiring density is small, and the device characteristics are degraded.
  • the present disclosure proposes a solid-state imaging device and an electronic device capable of suppressing deterioration of device characteristics.
  • a solid-state imaging device includes a first substrate including a photoelectric conversion unit that photoelectrically converts incident light to generate an electric charge, and is bonded to the first substrate, a second substrate including at least part of a pixel circuit that generates a voltage signal based on the charge generated in the photoelectric conversion portion; and a first metal disposed on the opposite side of the first substrate with the second substrate therebetween and a wiring, wherein the pixel circuit includes a charge accumulation unit that accumulates charges generated in the photoelectric conversion unit, and converts the charges accumulated in the charge accumulation unit to a voltage value corresponding to the charge amount of the charges.
  • an amplifying transistor for conversion a reset transistor for releasing the charge accumulated in the charge storage section, and a first through electrode connected to the charge storage section through the first metal wiring through the second substrate. and a first wiring that connects the gate electrode of the amplification transistor and the first through electrode.
  • a solid-state imaging device includes a photoelectric conversion unit that photoelectrically converts incident light to generate charges, and a pixel circuit that generates a voltage signal based on the charges generated in the photoelectric conversion unit.
  • the photoelectric conversion unit is arranged on a first substrate, at least part of the pixel circuit is arranged on a second substrate bonded to the first substrate, and the pixel circuit is arranged on the photoelectric conversion unit a charge accumulating portion for accumulating the generated charge; an amplifying transistor for converting the charge accumulated in the charge accumulating portion into a voltage having a voltage value corresponding to the charge amount of the charge; a reset transistor that releases electric charge, the amplifying transistor is arranged on the second substrate, and the second substrate comprises a second metal arranged on the opposite side of the first substrate with the second substrate interposed therebetween. and a shield electrode arranged at least partly between the second metal wiring and the gate electrode of the amplification transistor.
  • FIG. 1 is a block diagram showing a schematic configuration example of an electronic device equipped with a solid-state imaging device according to a first embodiment
  • FIG. 1 is a block diagram showing a schematic configuration example of a solid-state imaging device according to a first embodiment
  • FIG. 3 is a circuit diagram showing a schematic configuration example of a unit pixel according to the first embodiment
  • FIG. 1 is a cross-sectional view showing an example of a cross-sectional structure of a solid-state imaging device according to a first embodiment
  • FIG. 3 is a circuit diagram showing a circuit configuration example of FD sharing according to the first example of the first embodiment
  • FIG. 4 is a plan view showing a layout example of a light-receiving chip according to a first example of the first embodiment
  • 3 is a plan view showing a layout example of a circuit chip according to the first example of the first embodiment
  • FIG. FIG. 3 is a cross-sectional view showing a structural example taken along line A-A′ according to the first example of the first embodiment
  • FIG. 4 is a cross-sectional view showing a structural example of a B-B′ cross section according to the first example of the first embodiment
  • FIG. 7 is a plan view showing a layout example of a circuit chip according to a second example of the first embodiment
  • FIG. 10 is a cross-sectional view showing a structural example of a cross section taken along line A-A′ according to a second example of the first embodiment
  • FIG. 11 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to a second example of the first embodiment
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to a third example of the first embodiment
  • FIG. 11 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to a third example of the first embodiment
  • FIG. 11 is a plan view showing a layout example of a light receiving chip according to a fourth example of the first embodiment
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to a fourth example of the first embodiment;
  • FIG. 11 is a cross-sectional view showing a structural example of a cross section taken along line A-A′ according to a fourth example of the first embodiment;
  • FIG. 11 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to a fourth example of the first embodiment;
  • FIG. 14 is a cross-sectional view showing a structural example of a cross section taken along line C-C′ according to a fourth example of the first embodiment;
  • FIG. 11 is a circuit diagram showing a circuit configuration example of FD sharing according to a fifth example of the first embodiment;
  • FIG. 11 is a plan view showing a layout example of a light-receiving chip according to a fifth example of the first embodiment
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to a fifth example of the first embodiment
  • FIG. 14 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to a fifth example of the first embodiment
  • FIG. 11 is a plan view showing a layout example of a light receiving chip according to a sixth example of the first embodiment
  • FIG. 14 is a plan view showing a layout example of a circuit chip according to a sixth example of the first embodiment
  • FIG. 11 is a cross-sectional view showing a structural example of a cross section taken along line A-A′ according to a sixth example of the first embodiment;
  • FIG. 11 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to a sixth example of the first embodiment;
  • FIG. 21 is a plan view showing a layout example of a circuit chip according to a seventh example of the first embodiment;
  • FIG. 21 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to a seventh example of the first embodiment;
  • FIG. 21 is a cross-sectional view showing a structural example of a cross section taken along line D-D′ according to the seventh example of the first embodiment;
  • FIG. 21 is a plan view showing a layout example of a circuit chip according to an eighth example of the first embodiment
  • FIG. 21 is a cross-sectional view showing a structural example of a B-B′ cross section according to an eighth example of the first embodiment
  • FIG. 20 is a cross-sectional view showing a structural example of a cross section taken along line D-D′ according to an eighth example of the first embodiment
  • FIG. 21 is a plan view showing a layout example of a light-receiving chip according to a ninth example of the first embodiment
  • FIG. 21 is a plan view showing a layout example of a circuit chip according to a ninth example of the first embodiment
  • FIG. 21 is a cross-sectional view showing a structural example of the A-A′ cross section according to the ninth example of the first embodiment
  • FIG. 20 is a cross-sectional view showing a structural example of a cross section taken along line C-C′ according to the ninth example of the first embodiment
  • FIG. 20 is a cross-sectional view showing a structural example of a DD′ cross section according to the ninth example of the first embodiment
  • FIG. 21 is a plan view showing a layout example of a light-receiving chip according to a tenth example of the first embodiment
  • FIG. 21 is a plan view showing a layout example of a circuit chip according to a tenth example of the first embodiment
  • FIG. 20 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to the tenth example of the first embodiment;
  • FIG. 20 is a cross-sectional view showing a structural example of a cross section taken along line C-C′ according to the tenth example of the first embodiment;
  • FIG. 20 is a cross-sectional view showing a structural example of a cross section taken along line D-D′ according to the tenth example of the first embodiment;
  • FIG. 21 is a plan view showing a layout example of a light-receiving chip according to an eleventh example of the first embodiment;
  • FIG. 21 is a plan view showing a layout example of a circuit chip according to an eleventh example of the first embodiment;
  • FIG. 20 is a cross-sectional view showing a structural example of a cross section taken along line C-C′ according to the eleventh example of the first embodiment
  • FIG. 21 is a cross-sectional view showing an example of the cross-sectional structure of a unit pixel according to the twelfth example of the first embodiment
  • FIG. 21 is a plan view showing a layout example of a light-receiving chip according to a twelfth example of the first embodiment
  • FIG. 21 is a plan view showing a layout example of a circuit chip according to a twelfth example of the first embodiment
  • FIG. 21 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to the twelfth example of the first embodiment;
  • FIG. 20 is a cross-sectional view showing an example of the cross-sectional structure of a unit pixel according to the thirteenth example of the first embodiment;
  • FIG. 21 is a plan view showing a layout example of a light-receiving chip according to the thirteenth example of the first embodiment;
  • FIG. 20 is a plan view showing a layout example of a circuit chip according to the thirteenth example of the first embodiment;
  • FIG. 21 is a cross-sectional view showing an example of the cross-sectional structure of a unit pixel according to the fourteenth example of the first embodiment;
  • FIG. 21 is a plan view showing a layout example of a light-receiving chip according to a fourteenth example of the first embodiment
  • FIG. 20 is a plan view showing a layout example of a circuit chip according to the fourteenth example of the first embodiment
  • FIG. 20 is a cross-sectional view showing a structural example of the EE′ cross section according to the fourteenth example of the first embodiment
  • FIG. 20 is a cross-sectional view showing a structural example of a cross section taken along line F-F′ according to the fourteenth example of the first embodiment
  • FIG. 21 is a cross-sectional view showing a structural example of a G-G′ cross section according to the fourteenth example of the first embodiment
  • FIG. 21 is a cross-sectional view showing a structural example of the H-H′ cross section according to the fourteenth example of the first embodiment
  • FIG. 20 is a cross-sectional view showing a structural example of the LL′ cross section according to the fourteenth example of the first embodiment
  • FIG. 11 is a plan view showing a layout example of a light-receiving chip according to a first example of the second embodiment
  • FIG. 5 is a plan view showing a layout example of a circuit chip according to a comparative example
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to the first example of the second embodiment
  • FIG. 10 is a partial cross-sectional view showing a partial structural example of the X-X′ cross section according to the first example of the second embodiment;
  • FIG. 10 is a partial cross-sectional view showing a partial structural example of a Y-Y′ cross section according to the first example of the second embodiment;
  • FIG. 10 is a cross-sectional view showing a structural example of a ZZ′ cross section according to the first example of the second embodiment;
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to a modification of the first example of the second embodiment;
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to a second example of the second embodiment;
  • FIG. 10 is a cross-sectional view showing a structural example of a cross section taken along line W-W′ according to a second example of the second embodiment
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to a third example of the second embodiment
  • FIG. 11 is a cross-sectional view showing a structural example of a cross section taken along line A-A′ according to a third example of the second embodiment
  • FIG. 14 is a cross-sectional view showing a structural example of a cross section taken along line B-B′ according to a third example of the second embodiment
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system
  • FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit; 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system; FIG. 3 is a block diagram showing an example of functional configurations of a camera head and a CCU; FIG.
  • a photoelectric conversion portion and a transfer transistor output a signal based on the charge extracted from the photoelectric conversion portion (hereinafter referred to as a pixel signal).
  • a 3D sequential technology has been proposed in which at least one of an amplification transistor, a selection transistor, and a reset transistor that constitute a pixel circuit is arranged on separate substrates, and these substrates are bonded together to form a single chip.
  • the decrease in wiring density is small compared to the flat structure in which the photoelectric conversion unit, transfer transistor, reset transistor, amplification transistor, and selection transistor are arranged on a single substrate.
  • the wiring capacitance of the wiring formed on the substrate depends on the wiring density. Therefore, the lower the wiring density, the lower the parasitic capacitance caused by the wiring. Therefore, it is important to reduce parasitic capacitance in order to improve device characteristics, such as speeding up circuit operation and increasing conversion efficiency. is small, there is a possibility that the device characteristics will deteriorate.
  • the lower the wiring density the easier the difficulty of designing the wiring layout. Therefore, in the conventional 3D sequential structure, there is also a problem that the design difficulty of the wiring layout may increase due to the increase in the wiring density.
  • CMOS Complementary Metal-Oxide-Semiconductor
  • image sensor Electronic Image Sensor
  • the technology according to the present embodiment is applied to various sensors including photoelectric conversion elements, such as CCD (Charge Coupled Device) type solid-state imaging devices, ToF (Time of Flight) sensors, and EVS (Event-based Vision Sensors). It is possible to
  • FIG. 1 is a block diagram showing a schematic configuration example of an electronic device equipped with a solid-state imaging device according to the first embodiment.
  • the electronic device 1 includes, for example, an imaging lens 11, a solid-state imaging device 10, a storage section 14, and a processor 13.
  • the imaging lens 11 is an example of an optical system that collects incident light and forms the image on the light receiving surface of the solid-state imaging device 10 .
  • the light-receiving surface may be a surface on which the photoelectric conversion elements in the solid-state imaging device 10 are arranged.
  • the solid-state imaging device 10 photoelectrically converts incident light to generate image data.
  • the solid-state imaging device 10 also performs predetermined signal processing such as noise removal and white balance adjustment on the generated image data.
  • the storage unit 14 is composed of, for example, flash memory, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), etc., and records image data and the like input from the solid-state imaging device 10 .
  • the processor 13 is configured using, for example, a CPU (Central Processing Unit), and may include an application processor that executes an operating system and various application software, a GPU (Graphics Processing Unit), a baseband processor, and the like.
  • the processor 13 executes various processes as necessary on the image data input from the solid-state imaging device 10 and the image data read from the storage unit 14, executes display for the user, and processes the image data through a predetermined network. or send it to the outside via
  • FIG. 2 is a block diagram showing a schematic configuration example of a CMOS-type solid-state imaging device according to the first embodiment.
  • the CMOS-type solid-state imaging device is an image sensor manufactured by applying or partially using a CMOS process.
  • the solid-state imaging device 10 according to the present embodiment is configured with a back-illuminated image sensor.
  • a first semiconductor chip 410 (substrate) on which the pixel array section 21 is arranged and a second semiconductor chip 420 (substrate) on which the peripheral circuit is arranged are laminated. It has a stack structure (see, for example, FIG. 4).
  • Peripheral circuits may include, for example, a vertical drive circuit 22 , a column processing circuit 23 , a horizontal drive circuit 24 and a system controller 25 .
  • the solid-state imaging device 10 further includes a signal processing section 26 and a data storage section 27 .
  • the signal processing unit 26 and the data storage unit 27 may be provided on the same semiconductor chip as the peripheral circuit, or may be provided on a separate semiconductor chip.
  • unit pixels (hereinafter sometimes simply referred to as “pixels”) 30 having photoelectric conversion elements that generate and accumulate electric charges according to the amount of received light are arranged in the row direction and the column direction, that is, , are arranged in a two-dimensional lattice in a matrix.
  • the row direction refers to the arrangement direction of pixels in a pixel row (horizontal direction in the drawing)
  • the column direction refers to the arrangement direction of pixels in a pixel column (vertical direction in the drawing). Details of the specific circuit configuration and pixel structure of the unit pixel will be described later.
  • pixel drive lines LD are wired along the row direction for each pixel row and vertical signal lines VSL are wired along the column direction for each pixel column with respect to the matrix-like pixel array.
  • the pixel drive line LD transmits a drive signal for driving when reading a signal from a pixel.
  • the pixel drive lines LD are shown as wirings one by one, but are not limited to one each.
  • One end of the pixel drive line LD is connected to an output terminal corresponding to each row of the vertical drive circuit 22 .
  • the vertical drive circuit 22 is composed of shift registers, address decoders, etc., and drives each pixel of the pixel array section 21 simultaneously or in units of rows. That is, the vertical drive circuit 22 constitutes a drive section that controls the operation of each pixel in the pixel array section 21 together with a system control section 25 that controls the vertical drive circuit 22 .
  • the vertical drive circuit 22 generally has two scanning systems, a readout scanning system and a discharge scanning system, although the specific configuration thereof is not shown.
  • the readout scanning system sequentially selectively scans the unit pixels of the pixel array section 21 row by row in order to read out signals from the unit pixels.
  • a signal read from a unit pixel is an analog signal.
  • the sweep-scanning system performs sweep-scanning ahead of the read-out scanning by the exposure time for the read-out rows to be read-scanned by the read-out scanning system.
  • a so-called electronic shutter operation is performed by sweeping out (resetting) the unnecessary charges in this sweeping scanning system.
  • the electronic shutter operation means an operation of discarding the charge of the photoelectric conversion element and newly starting exposure (starting charge accumulation).
  • the signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or the electronic shutter operation.
  • the period from the readout timing of the previous readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the charge accumulation period (also referred to as the exposure period) in the unit pixel.
  • a signal output from each unit pixel of a pixel row selectively scanned by the vertical drive circuit 22 is input to the column processing circuit 23 through each vertical signal line VSL for each pixel column.
  • the column processing circuit 23 performs predetermined signal processing on a signal output from each pixel of the selected row through the vertical signal line VSL for each pixel column of the pixel array section 21, and temporarily stores the pixel signal after the signal processing. to be retained.
  • the column processing circuit 23 performs at least noise removal processing, such as CDS (Correlated Double Sampling) processing and DDS (Double Data Sampling) processing, as signal processing.
  • CDS Correlated Double Sampling
  • DDS Double Data Sampling
  • the CDS processing removes pixel-specific fixed pattern noise such as reset noise and variations in threshold values of amplification transistors in pixels.
  • the column processing circuit 23 also has an AD (analog-digital) conversion function, for example, and converts analog pixel signals read from the photoelectric conversion elements into digital signals and outputs the digital signals.
  • AD analog-digital
  • the horizontal drive circuit 24 is composed of shift registers, address decoders, etc., and sequentially selects readout circuits (hereinafter referred to as pixel circuits) corresponding to the pixel columns of the column processing circuit 23 .
  • pixel circuits readout circuits
  • the system control unit 25 is composed of a timing generator that generates various timing signals. and other drive control.
  • the signal processing unit 26 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on pixel signals output from the column processing circuit 23 .
  • the data storage unit 27 temporarily stores data required for signal processing in the signal processing unit 26 .
  • the image data output from the signal processing unit 26 is, for example, subjected to predetermined processing in the processor 13 or the like in the electronic device 1 in which the solid-state imaging device 10 is mounted, or is transmitted to the outside via a predetermined network. You may
  • FIG. 3 is a circuit diagram showing a schematic configuration example of a unit pixel according to the present embodiment.
  • the unit pixel 30 includes a photoelectric conversion portion PD, a transfer transistor 31, a reset transistor 32, an amplification transistor 33, a selection transistor 34, and a floating diffusion region FD.
  • a select transistor drive line LD34 included in the pixel drive line LD is connected to the gate of the select transistor 34, a reset transistor drive line LD32 included in the pixel drive line LD is connected to the gate of the reset transistor 32, and a transfer transistor is connected. 31 is connected to a transfer transistor drive line LD31 included in the pixel drive line LD.
  • a vertical signal line VSL one end of which is connected to the column processing circuit 23 , is connected to the source of the amplification transistor 33 via the selection transistor 34 .
  • the reset transistor 32, amplification transistor 33, and selection transistor 34 are also collectively referred to as a pixel circuit.
  • This pixel circuit may include a floating diffusion region FD and/or a transfer transistor 31 .
  • the photoelectric conversion unit PD photoelectrically converts incident light.
  • the transfer transistor 31 transfers charges generated in the photoelectric conversion unit PD.
  • the floating diffusion region FD functions as a charge accumulation portion that accumulates charges transferred by the transfer transistor 31 .
  • the amplification transistor 33 causes a pixel signal having a voltage value corresponding to the charge accumulated in the floating diffusion region FD to appear on the vertical signal line VSL.
  • the reset transistor 32 releases charges accumulated in the floating diffusion region FD.
  • the selection transistor 34 selects the unit pixel 30 to be read.
  • the photoelectric conversion unit PD has an anode grounded and a cathode connected to the source of the transfer transistor 31 .
  • the drain of the transfer transistor 31 is connected to the source of the reset transistor 32 and the gate of the amplification transistor 33, and the node that is the connection point of these constitutes the floating diffusion region FD.
  • a drain of the reset transistor 32 is connected to a vertical reset input line (not shown).
  • the drain of the amplification transistor 33 is connected to a vertical voltage supply line (not shown).
  • the source of the amplification transistor 33 is connected to the drain of the selection transistor 34, and the source of the selection transistor 34 is connected to the vertical signal line VSL.
  • the potential of the floating diffusion region FD is determined by the charge accumulated there and the capacitance of the floating diffusion region FD.
  • the capacitance of the floating diffusion region FD is determined by the drain diffusion layer capacitance of the transfer transistor 31, the source diffusion layer capacitance of the reset transistor 32, the gate capacitance of the amplification transistor 33, and the like, in addition to the capacitance to ground.
  • the reset transistor 32 controls discharge (reset) of charges accumulated in the floating diffusion region FD according to a reset signal RST supplied from the vertical drive circuit 22 via a reset transistor drive line LD32.
  • RST supplied from the vertical drive circuit 22 via a reset transistor drive line LD32.
  • the photoelectric conversion unit PD photoelectrically converts incident light and generates charges according to the amount of light. The generated charge is accumulated on the cathode side of the photoelectric conversion part PD.
  • the transfer transistor 31 controls charge transfer from the photoelectric conversion unit PD to the floating diffusion region FD according to a transfer control signal TRG supplied from the vertical drive circuit 22 via the transfer transistor drive line LD31.
  • the potential of the floating diffusion region FD when the reset transistor 32 is off is determined by the amount of charge transferred from the photoelectric conversion unit PD via the transfer transistor 31 and the capacitance of the floating diffusion region FD, as described above.
  • the amplification transistor 33 functions as an amplifier whose input signal is the potential fluctuation of the floating diffusion region FD connected to its gate, and its output voltage signal appears as a pixel signal on the vertical signal line VSL via the selection transistor 34 .
  • the selection transistor 34 controls the appearance of the pixel signal by the amplification transistor 33 on the vertical signal line VSL according to the selection control signal SEL supplied from the vertical drive circuit 22 via the selection transistor drive line LD34. For example, when a High-level selection control signal SEL is input to the gate of the selection transistor 34, a pixel signal from the amplification transistor 33 appears on the vertical signal line VSL. On the other hand, when the Low level selection control signal SEL is input to the gate of the selection transistor 34, the appearance of the pixel signal to the vertical signal line VSL is stopped. This makes it possible to take out only the output of the selected unit pixel 30 on the vertical signal line VSL to which the plurality of unit pixels 30 are connected.
  • FIG. 4 is a diagram showing a layered structure example of the image sensor according to the present embodiment.
  • the solid-state imaging device 10 has a structure in which a first semiconductor chip 410 and a second semiconductor chip 420 are vertically stacked.
  • the first semiconductor chip 410 has a structure in which the light receiving chip 41 and the circuit chip 42 are stacked.
  • the light-receiving chip 41 is, for example, a semiconductor chip including the pixel array section 21 in which the photoelectric conversion sections PD are arranged
  • the circuit chip 42 is, for example, a semiconductor chip in which pixel circuits are arranged.
  • so-called direct bonding can be used in which the respective bonding surfaces are flattened and the two are bonded together by inter-electron force.
  • so-called Cu—Cu bonding in which electrode pads made of copper (Cu) formed on each other's bonding surfaces are bonded together, or bump bonding.
  • the first semiconductor chip 410 and the second semiconductor chip 420 are electrically connected via a connecting portion such as a TSV (Through-Silicon Via), which is a through contact penetrating the semiconductor substrate.
  • a connecting portion such as a TSV (Through-Silicon Via), which is a through contact penetrating the semiconductor substrate.
  • TSVs for connection using TSVs, for example, two TSVs, a TSV provided on the first semiconductor chip 410 and a TSV provided from the first semiconductor chip 410 to the second semiconductor chip 420, are connected on the outside of the chip.
  • a twin TSV system or a so-called shared TSV system in which a TSV penetrating from the first semiconductor chip 410 to the second semiconductor chip 420 connects the two can be adopted.
  • FIG. 5 is a cross-sectional view showing an example of the cross-sectional structure of a unit pixel according to the first embodiment. Note that FIG. 5 shows an example of the cross-sectional structure of the light receiving chip 41 in which the photoelectric conversion part PD in the unit pixel 30 is arranged.
  • the photoelectric conversion unit PD receives incident light L1 incident from the back surface (upper surface in the figure) side of the semiconductor substrate 58. As shown in FIG. A planarizing film 53, a color filter 52, and an on-chip lens 51 are provided above the photoelectric conversion unit PD. photoelectric conversion is performed.
  • the N-type semiconductor region 59 is formed as a charge accumulation region that accumulates charges (electrons).
  • the N-type semiconductor region 59 is provided within a region surrounded by the P-type semiconductor regions 56 and 64 of the semiconductor substrate 58 .
  • a P-type semiconductor region 64 having a higher impurity concentration than the back surface (upper surface) side is provided on the N-type semiconductor region 59 on the front surface (lower surface) side of the semiconductor substrate 58 .
  • the photoelectric conversion unit PD has a HAD (Hole-Accumulation Diode) structure, and in order to suppress the generation of dark current at each interface between the upper surface side and the lower surface side of the N-type semiconductor region 59, P-type semiconductor regions 56 and 64 are provided.
  • HAD Hole-Accumulation Diode
  • a pixel separation section 60 is provided for electrically separating the plurality of unit pixels 30, and a photoelectric conversion section PD is provided in a region partitioned by the pixel separation section 60. ing.
  • the pixel separation section 60 is provided in a lattice shape so as to be interposed between the plurality of unit pixels 30, for example, and the photoelectric conversion section PD is It is arranged within the area partitioned by the pixel separation section 60 .
  • each photoelectric conversion unit PD the anode is grounded, and in the solid-state imaging device 10, signal charges (for example, electrons) accumulated in the photoelectric conversion unit PD are transferred through a transfer transistor 31 (see FIG. 3) (not shown) or the like. and output as an electrical signal to a vertical signal line VSL (see FIG. 3), not shown.
  • a transfer transistor 31 see FIG. 3 (not shown) or the like.
  • the wiring layer 65 is provided on the surface (lower surface) of the semiconductor substrate 58 opposite to the back surface (upper surface) on which the light shielding film 54, the planarizing film 53, the color filter 52, the on-chip lens 51, and the like are provided. be done.
  • the wiring layer 65 is composed of a wiring 66, an insulating layer 67, and a through electrode (not shown). An electric signal from the light receiving chip 41 is transmitted to the circuit chip 42 via the wiring 66 and through electrodes (not shown). Similarly, the substrate potential of the light receiving chip 41 is also applied from the second semiconductor chip 420 via the wiring 66 and through electrodes (not shown).
  • the circuit chip 42 illustrated in FIG. 4 is bonded to the surface of the wiring layer 65 opposite to the side on which the photoelectric conversion part PD is provided.
  • the light shielding film 54 is provided on the back surface (upper surface in the drawing) of the semiconductor substrate 58 and blocks part of the incident light L1 directed from above the semiconductor substrate 58 toward the back surface of the semiconductor substrate 58 .
  • the light shielding film 54 is provided above the pixel separation section 60 provided inside the semiconductor substrate 58 .
  • the light shielding film 54 is provided on the rear surface (upper surface) of the semiconductor substrate 58 so as to protrude in a convex shape through an insulating film 55 such as a silicon oxide film.
  • the photoelectric conversion unit PD provided inside the semiconductor substrate 58, the light shielding film 54 is not provided and is open so that the incident light L1 is incident on the photoelectric conversion unit PD. ing.
  • the planar shape of the light shielding film 54 is a lattice shape, and openings are formed through which the incident light L1 passes to the light receiving surface 57.
  • the light shielding film 54 is made of a light shielding material that shields light.
  • the light shielding film 54 is formed by sequentially laminating a titanium (Ti) film and a tungsten (W) film.
  • the light shielding film 54 can be formed by sequentially laminating a titanium nitride (TiN) film and a tungsten (W) film, for example.
  • the light shielding film 54 is covered with the planarizing film 53 .
  • the planarizing film 53 is formed using an insulating material that transmits light. Silicon oxide (SiO 2 ), for example, can be used for this insulating material.
  • the pixel separation section 60 has, for example, a groove section 61, a fixed charge film 62, and an insulating film 63, and is a groove section that partitions the plurality of unit pixels 30 on the back surface (upper surface) side of the semiconductor substrate 58. It is provided so as to cover 61 .
  • the fixed charge film 62 is provided so as to cover the inner surface of the groove 61 formed on the back surface (upper surface) side of the semiconductor substrate 58 with a constant thickness.
  • An insulating film 63 is provided (filled) so as to bury the inside of the trench 61 covered with the fixed charge film 62 .
  • the fixed charge film 62 a high dielectric material having negative fixed charges is used so that a positive charge (hole) accumulation region is formed at the interface with the semiconductor substrate 58 and generation of dark current is suppressed. formed by Since the fixed charge film 62 has negative fixed charges, the negative fixed charges apply an electric field to the interface with the semiconductor substrate 58 to form a positive charge (hole) accumulation region.
  • the fixed charge film 62 can be formed of, for example, a hafnium oxide film (HfO 2 film).
  • the fixed charge film 62 can be formed so as to contain at least one oxide of hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, lanthanide elements, or the like.
  • the pixel separating section 60 is not limited to the configuration described above, and can be variously modified.
  • a reflective film that reflects light such as a tungsten (W) film
  • the pixel separation section 60 can have a light reflective structure.
  • the incident light L1 entering the photoelectric conversion unit PD can be reflected by the pixel separation unit 60, so that the optical path length of the incident light L1 within the photoelectric conversion unit PD can be increased.
  • the pixel separating section 60 have a light reflecting structure, it is possible to reduce the leakage of light into adjacent pixels, so that it is possible to further improve the image quality, distance measurement accuracy, and the like.
  • a metal material such as tungsten (W)
  • the configuration in which the pixel separating section 60 has a light reflecting structure is not limited to the configuration using a reflective film. can do.
  • FIG. 5 illustrates a pixel isolation portion 60 having a so-called RDTI (Reverse Deep Trench Isolation) structure, in which the pixel isolation portion 60 is provided in a groove portion 61 formed from the back surface (upper surface) side of the semiconductor substrate 58.
  • RDTI Reverse Deep Trench Isolation
  • FTI Frull Trench Isolation
  • FIG. 6 is a circuit diagram showing a circuit configuration example of FD sharing according to the first example.
  • FIG. 7 is a plan view showing a layout example of a light receiving chip according to the first example.
  • FIG. 8 is a plan view showing a layout example of a circuit chip according to the first example.
  • FIG. 9 is a cross-sectional view showing a structural example taken along the line A-A' according to the first example.
  • FIG. 10 is a cross-sectional view showing a structural example of the B-B' cross section according to the first example.
  • FD shared configuration As shown in FIG. 6, in the FD sharing configuration in which four unit pixels 30a to 30d share one floating diffusion region FD, four photoelectric conversion units PDa to PDd share common floating diffusion regions via transfer transistors 31a to 31d, respectively. It is connected to diffusion region FD. The configuration beyond the floating diffusion region FD is shared by the four unit pixels 30a to 30d. Therefore, in this example, the reset transistor 32, amplification transistor 33 and selection transistor 34 are shared by the four unit pixels 30a to 30d.
  • the light receiving chip 41 includes photoelectric conversion units PDa to PDd and transfer transistors 31a to 31d.
  • the transfer gate electrodes 111a to 111d of the transfer transistors 31a to 31d are arranged in two rows and two columns on the element formation surface (hereinafter also referred to as the surface) of the semiconductor substrate 101 of the light receiving chip 41.
  • FIG. The photoelectric conversion units PDa to PDd are arranged on the light receiving surface (hereinafter also referred to as the rear surface) side of the semiconductor substrate 101 so as to overlap the respective transfer gate electrodes 111a to 111d in the substrate thickness direction.
  • the semiconductor substrate 101 may correspond to the semiconductor substrate 58 in the cross-sectional structure illustrated in FIG. 5, for example.
  • Penetrating electrodes 112a to 112d penetrating through the circuit chip 42 and reaching the first metal wiring M1 on the circuit chip 42 are connected to the respective transfer gate electrodes 111a to 111d.
  • the through electrodes 112a to 112d are part of the transfer transistor drive line LD31.
  • a floating diffusion region FD is arranged in the center of the transfer gate electrodes 111a to 111d arranged in two rows and two columns.
  • a penetrating electrode 103 penetrating through the circuit chip 42 and reaching the first metal wiring M1 on the circuit chip 42 is connected to the floating diffusion region FD.
  • the floating diffusion region FD is connected to the source of the reset transistor 32 and the gate of the amplification transistor 33 via the through electrode 103 and the first metal wiring M1.
  • the through electrodes 112a to 112d and 103 are, for example, an interlayer insulating film between the light receiving chip 41 and the circuit chip 42 and an insulating film region 265 penetrating the circuit chip 42 (hereinafter, the interlayer insulating film and the insulating film region 265 are collectively referred to as It is connected to the first metal wiring M1 on the upper layer of the circuit chip 42 by penetrating through the insulating layer 301 .
  • through electrodes 105 are connected to contact portions 104 formed on the element forming surface of the semiconductor substrate 101.
  • the contact portion 104 may be, for example, a P+ type diffusion region.
  • the reset transistor 32 is composed of a reset gate electrode 221, a gate insulating film and a channel forming region (not shown), and the amplifying transistor 33 is composed of an amplifying gate electrode 231, a gate insulating film 231a and a channel forming region.
  • the select transistor 34 is composed of a select gate electrode 241, a gate insulating film and a channel forming region (not shown).
  • the reset gate electrode 221 is connected to the first metal wiring M1 through a contact plug 222 which is part of the reset transistor drive line LD32.
  • the select gate electrode 241 is connected to the first metal wiring M1 through a contact plug 242 which is part of the select transistor drive line LD34.
  • Diffusion regions 210 arranged to sandwich each gate electrode are, for example, N+ type diffusion regions, and function as sources and drains of the reset transistor 32, the amplification transistor 33, and the selection transistor 34, respectively.
  • the diffusion region 210 which functions as the drain of the reset transistor 32 and the drain of the amplification transistor, is connected to the reset voltage line of the first metal wiring M1 via the contact plug 224.
  • This reset voltage line is a voltage line that supplies a reset potential for resetting the floating diffusion region FD, and may be, for example, a power line that supplies a power supply voltage VDD.
  • the diffusion region 210 functioning as the source of the reset transistor 32 is connected via a contact plug 223 to the first metal wiring M1 connected to the through electrode 103 connected to the floating diffusion region FD.
  • the amplification gate electrode 231 has an extending portion 233 extending in the direction of the floating diffusion region FD along the element formation surface of the semiconductor substrate 201, and is short-circuited with the through electrode 103 connected to the floating diffusion region FD via the extending portion 233. do. Thereby, the gate of the amplification transistor 33, the source of the reset transistor 32, and the floating diffusion region FD are electrically connected.
  • the source of the amplification transistor 33 and the drain of the selection transistor 34 share the same diffusion region 210 .
  • the diffusion region 210 functioning as the source of the selection transistor 34 is connected to the first metal wiring M1 through the contact plug 243 which is part of the vertical signal line VSL.
  • a contact plug 205 is connected to the contact portion 204 formed on the element formation surface of the semiconductor substrate 201 . That is, the well potential of the semiconductor substrate 201 is controlled through the contact plug 205 reaching the first metal wiring M1.
  • the contact portion 204 may be, for example, a P+ type diffusion region, like the contact portion 104 .
  • the conventional 3D sequential structure provides an amplification It is possible to reduce the required number of electrodes compared to the total of two electrodes (one each for the gate electrode and the floating diffusion region).
  • the number of electrodes may be, for example, the number of through electrodes and/or the number of contact plugs. As a result, the wiring density of the circuit chip 42 can be reduced, and the parasitic capacitance caused by the wiring can be reduced. As a result, device characteristics can be improved.
  • the dense wiring density of the circuit chip 42 is reduced.
  • FIG. 11 is a plan view showing a layout example of a circuit chip according to the second example.
  • FIG. 12 is a cross-sectional view showing a structural example of the A-A' cross section according to the second example.
  • FIG. 13 is a cross-sectional view showing a structural example of the B-B' cross section according to the second example.
  • the extended portion 233 of the amplification gate electrode 231 is omitted in the configuration similar to those according to the first example.
  • the through electrode 103 of the floating diffusion region FD and the contact plug 232 of the amplification gate electrode 231 are connected by a first metal wiring M1 in the upper layer.
  • the through electrode 105 passes through a contact portion 204 formed to penetrate the semiconductor substrate 201 and is connected to the contact portion 104 formed on the element forming surface of the semiconductor substrate 101 .
  • the contact portion 104 is electrically short-circuited with the contact portion 204 via the through electrode 105 . Therefore, the well potentials of the semiconductor substrates 101 and 201 can be controlled via the through electrodes 105 reaching the first metal wirings M1.
  • the contact portions 104 and 204 may be, for example, P+ type diffusion regions as in the first example.
  • FIG. 14 is a plan view showing a layout example of a circuit chip according to the third example.
  • FIG. 15 is a cross-sectional view showing a structural example of the B-B' cross section according to the third example.
  • the diffusion region 210 is routed along the device formation surface of the semiconductor substrate 201 to the through electrode 103 and short-circuited to the diffusion region 210a.
  • a diffusion region 210 a formed to penetrate the semiconductor substrate 201 is short-circuited to the through electrode 103 .
  • a recessed groove 302 exposing a part of the side surface of the through electrode 103 is provided in a part of the insulating film region 265.
  • a diffusion region 210 a is formed in the semiconductor substrate 201 within the trench 302 .
  • the horizontal cross section of the through electrode 103 may have a shape elongated vertically or horizontally (longitudinally in FIG. 14).
  • FIG. 16 is a plan view showing a layout example of a light receiving chip according to the fourth example.
  • FIG. 17 is a plan view showing a layout example of a circuit chip according to the fourth example.
  • FIG. 18 is a cross-sectional view showing a structural example of the A-A' cross section according to the fourth example.
  • FIG. 19 is a cross-sectional view showing a structural example of the B-B' cross section according to the fourth example.
  • FIG. 20 is a cross-sectional view showing a structural example of the C-C' cross section according to the fourth example.
  • the light-receiving chip 41 includes an amplification transistor 33 in addition to photoelectric conversion units PDa to PDd and transfer transistors 31a to 31d.
  • transfer gate electrodes 111a to 111d arranged in two rows and two columns in the same configuration as those in the first example.
  • a pair of diffusion regions 110 functioning as the source and drain of the amplification transistor 33 are arranged under the amplification gate electrode 131 and sandwiching the channel forming region 131b.
  • the through electrode 132 connected to the amplification gate electrode 131 is connected to the first metal wiring M1 through the circuit chip 42 in the upper layer.
  • the wiring 133 provided in the wiring layer between the semiconductor substrate 101 and the semiconductor substrate 201 allows the through electrode 132 connected to the amplification gate electrode 131 and the through electrode 132 connected to the floating diffusion region FD.
  • electrode 103 is connected. Thereby, the gate of the amplification transistor 33 and the floating diffusion region FD are short-circuited.
  • the wiring 133 may be made of a conductive material such as polysilicon doped with impurities (polycrystalline silicon).
  • a reset transistor 32 and a select transistor 34 are arranged on the circuit chip 42 .
  • the diffusion region 210 functioning as the source of the reset transistor 32 is part of the diffusion region 210.
  • 210 a is formed so as to penetrate the semiconductor substrate 201 .
  • the through electrode 132 is arranged so as to penetrate the diffusion region 210a. That is, in the fourth example, the through electrode 132 connecting the gate (amplification gate electrode 131) of the amplification transistor 33 to the first metal wiring M1 connects the source (diffusion region 210a) of the reset transistor 32 to the first metal wiring M1.
  • the gate and floating diffusion region FD of the amplification transistor 33 and the source of the reset transistor 32 are short-circuited.
  • the positional relationship between the reset transistor 32 and the select transistor 34 is changed from that in the first example. It is not limited.
  • the drain (diffusion region 210 a ) of the reset transistor 32 is short-circuited to the drain (diffusion region 110 ) of the amplification transistor 33 via the through electrode 135 .
  • the through electrode 135 is connected to a power supply line that supplies a power supply voltage VDD via a first metal wiring M1 in the upper layer.
  • the drain (diffusion region 210 a ) of the selection transistor 34 is short-circuited to the source (diffusion region 110 ) of the amplification transistor 33 via the through electrode 134 .
  • the contact portions 204 formed on the element formation surface of the semiconductor substrate 201 are short-circuited to the contact portions 104 formed on the element formation surface of the semiconductor substrate 101 via the through electrodes 105 .
  • the amplification transistor 33 is shorted to the drain of the reset transistor 32 via the through electrode 135, and the source of the amplification transistor 33 is shorted to the drain of the selection transistor via the through electrode 134. Since the number of electrodes is further reduced, the wiring density of the circuit chip 42 can be reduced to further improve the device characteristics, and the difficulty of designing the wiring layout of the circuit chip 42 can be further simplified. Become.
  • FIG. 21 is a circuit diagram showing a circuit configuration example of FD sharing according to the fifth example.
  • FIG. 22 is a plan view showing a layout example of a light receiving chip according to the fifth example.
  • FIG. 23 is a plan view showing a layout example of a circuit chip according to the fifth example.
  • FIG. 24 is a cross-sectional view showing a structural example of a cross section taken along line B-B' according to the fifth example. Note that the A-A' cross-sectional structure may be the same as the structure described with reference to FIG. 9 in the first example, so detailed description is omitted here.
  • FD shared configuration As shown in FIG. 21, in the FD sharing configuration in which eight unit pixels 30a to 30h share one floating diffusion region FD, similarly to the circuit configuration described with reference to FIG. Portions PDa to PDh are connected to a common floating diffusion region FD via transfer transistors 31a to 31h, respectively.
  • the configuration beyond the floating diffusion region FD is shared by eight unit pixels 30a to 30h. Therefore, in this example, the reset transistor 32, the amplification transistor 33, the selection transistor 34, the switching transistor 35, and the capacitor C are shared by the eight unit pixels 30a to 30h.
  • the switching transistor 35 is connected between the floating diffusion region FD and the source of the reset transistor 32 .
  • a capacitor C is connected to a connection node between the source of the reset transistor 32 and the drain of the switching transistor 35 .
  • This capacitor C may be, for example, a capacitance intentionally added using metal wiring or the like, or may be a parasitic capacitance formed between the connection node and the substrate.
  • the capacity for accumulating the charges transferred from the photoelectric conversion units PDa to PDh is divided into the capacity of the floating diffusion region FD alone and the capacity of the floating diffusion region FD. and the capacitance of the capacitor C added to the capacitance of the capacitor C.
  • the voltage applied to the gate of the amplification transistor 33 can be controlled, so that the dynamic range of each unit pixel 30 can be switched.
  • parasitic capacitance such as wiring connected to the floating diffusion region FD is also included in the capacitance for accumulating charges transferred from the photoelectric conversion units PDa to PDh.
  • a parasitic capacitance such as wiring connected to the floating diffusion region FD is not taken into consideration.
  • the light-receiving chip 41 includes photoelectric conversion units PDa to PDh and transfer transistors 31a to 31h.
  • the transfer gate electrodes 111a to 111d of the transfer transistors 31a to 31d are arranged in two rows and two columns, and the floating diffusion region FD1 is arranged in the center of this arrangement. be done.
  • Transfer gate electrodes 111e to 111h of transfer transistors 31e to 31h are arranged in two rows and two columns, and a floating diffusion region FD2 is arranged in the center of this arrangement. Therefore, the entire FD shared pixel has a configuration in which eight unit pixels 30 are arranged in four rows and two columns.
  • the transfer gate electrodes 111a to 111h are connected to the first metal wiring M1 via the through electrodes 112a to 112h, respectively.
  • the floating diffusion region FD1 is connected to the first metal wiring M1 via the through electrode 103, and the floating diffusion region FD2 is connected to the first metal wiring M1 via the through electrode 107.
  • FIG. In other words, the floating diffusion region FD1 and the floating diffusion region FD2 are short-circuited through the first metal wiring M1. As a result, sharing of the floating diffusion region FD of the eight unit pixels 30 is realized.
  • two pairs of contact portions and through electrodes for controlling the well potential of the semiconductor substrate 101 are provided: the contact portion 104 and the through electrode 105 and the contact portion 108 and the through electrode 109.
  • the contact portion 104 and the through electrode 105 and the contact portion 108 and the through electrode 109 are provided: the contact portion 104 and the through electrode 105 and the contact portion 108 and the through electrode 109.
  • one set or three or more sets may be provided.
  • the reset transistor 32 the amplification transistor 33 , the selection transistor 34 and the switching transistor 35 are arranged in the circuit chip 42 .
  • the amplification transistor 33, the selection transistor 34, and the reset transistor 32 are arranged in the same configuration as the layout example and cross-sectional structure example of the circuit chip 42 according to the first example. and the switching transistor 35 are arranged in this order, and the diffusion region 210 arranged between the amplification gate electrode 231 and the selection gate electrode 241 functions as the source of the amplification transistor 33 and the drain of the selection transistor 34, and the switching gate electrode A diffusion region 210 arranged between 251 and the reset gate electrode 221 functions as the drain of the switching transistor 35 and the source of the reset transistor 32 .
  • Diffusion region 210 functioning as the drain of amplification transistor 33 is connected to first metal wiring M1 via contact plug 234, and diffusion region 210 functioning as the source of switching transistor 35 is connected to first metal wiring M1 via contact plug 253. connected to
  • the amplification gate electrode 231 includes an extension portion 233 extending toward the floating diffusion region FD1, as in the first example, and the extension portion 233 is connected to the through-electrode 103 so that the amplification transistor 33 and the floating diffusion region FD1 are short-circuited.
  • the contact plug 253 connected to the diffusion region 210 functioning as the source of the switching transistor 35 is connected to the through electrode 107 of the floating diffusion region FD2 and the through electrode 103 of the floating diffusion region FD1 via the first metal wiring M1. be done. Thereby, the gate of the amplification transistor 33, the floating diffusion regions FD1 and FD2, and the source of the switching transistor 35 are short-circuited.
  • two pairs of contact portions and through electrodes for controlling the well potential of the semiconductor substrate 201 are provided: the contact portion 204 and the through electrode 105 and the contact portion 208 and the through electrode 109.
  • the contact portion 204 and the through electrode 105 and the contact portion 208 and the through electrode 109 are provided: the contact portion 204 and the through electrode 105 and the contact portion 208 and the through electrode 109.
  • Sixth Example as in the fifth example, eight unit pixels 30 arranged in four rows and two columns share one floating diffusion region FD.
  • a circuit configuration example of FD sharing may be the same as the configuration described with reference to FIG. 21 for the fifth example, so detailed description is omitted here.
  • FIG. 25 is a plan view showing a layout example of a light receiving chip according to the sixth example.
  • FIG. 26 is a plan view showing a layout example of a circuit chip according to the sixth example.
  • FIG. 27 is a cross-sectional view showing a structural example of the A-A' cross section according to the sixth example.
  • FIG. 28 is a cross-sectional view showing a structural example of the B-B' cross section according to the sixth example.
  • the through electrode 103 and the through electrode 107 are arranged in the same configuration as those according to the fifth example. are connected by the wiring 160, the floating diffusion region FD1 and the floating diffusion region FD2 are electrically connected.
  • the wiring 160 may be composed of a conductive material such as, for example, polysilicon doped with impurities.
  • the necessary number of electrodes is reduced by extending the amplification gate electrode 231 in the direction of the floating diffusion region FD and short-circuiting it to the through electrode 103 .
  • the area of the first metal wiring M1 in the upper layer of the circuit chip 42 is reduced compared to the fifth example. be done.
  • the wiring density of the circuit chip 42 can be reduced to improve the device characteristics, and the design difficulty of the wiring layout of the circuit chip 42 can be simplified.
  • a seventh example as in the fifth example, eight unit pixels 30 arranged in four rows and two columns share one floating diffusion region FD.
  • An example of the circuit configuration for sharing the FD and an example of the layout of the light-receiving chip 41 may be the same as the configurations described with reference to FIGS. 21 and 22 in the fifth example. Since the AA' cross-sectional structure may be the same as the structure described with reference to FIG. 9 in the first example, detailed description thereof is omitted here. However, in the seventh example, the switching transistor 35 in the pixel circuit is omitted.
  • FIG. 29 is a plan view showing a layout example of a circuit chip according to the seventh example.
  • FIG. 30 is a cross-sectional view showing a structural example of the B-B' cross section according to the seventh example.
  • FIG. 31 is a cross-sectional view showing a structural example taken along line D-D' according to the seventh example.
  • the diffusion region 210 functioning as the source of the reset transistor 32 extends toward the floating diffusion region FD2. It is shorted to diffusion region 210a. Further, the diffusion region 210a is in contact with the through electrode 107. As shown in FIG. As a result, the source of the reset transistor 32, the gate of the amplification transistor, and the floating diffusion regions FD1 and FD2 pass through the through electrodes 103 and 107, the first metal wiring M1 connecting them, and the extending portion 233. shorted.
  • a diffusion region 210a that is part of the diffusion region 210 functioning as the source of the reset transistor 32 is formed so as to penetrate the semiconductor substrate 201.
  • FIG. Furthermore, in order to bring the diffusion region 210a into contact with the through electrode 107, the insulating film region 265 for penetrating the through electrodes 112e to 112h is divided into two along the extending direction of the diffusion region 210a.
  • the necessary number of electrodes is reduced by extending the amplification gate electrode 231 in the direction of the floating diffusion region FD1 and short-circuiting it to the through electrode 103 . Furthermore, by short-circuiting the diffusion region 210a that functions as the source of the reset transistor 32 to the floating diffusion region FD2 via the through electrode 107, the area of the first metal wiring M1 in the upper layer of the circuit chip 42 is reduced compared to the fifth example. be done. As described above, the wiring density of the circuit chip 42 can be reduced to improve the device characteristics, and the design difficulty of the wiring layout of the circuit chip 42 can be simplified.
  • Eighth Example as in the fifth example, eight unit pixels 30 arranged in four rows and two columns share one floating diffusion region FD.
  • the circuit configuration example for sharing the FD may be the same as the configuration described using FIG. 21 in the fifth example
  • the layout example of the light receiving chip 41 is the layout example described using FIG. 25 in the sixth example.
  • the AA' cross-sectional structure of the circuit chip 42 shown in FIG. 32 may be the same as the structure described with reference to FIG. 27 in the sixth example. Description is omitted.
  • the switching transistor 35 in the pixel circuit is omitted.
  • FIG. 32 is a plan view showing a layout example of a circuit chip according to the eighth example.
  • FIG. 33 is a cross-sectional view showing a structural example of a B-B' cross section according to the eighth example.
  • FIG. 34 is a cross-sectional view showing a structural example taken along the line D-D' according to the eighth example.
  • the through electrodes 103 are the first through-electrodes 103 in the seventh example. While short-circuited to the through electrode 107 via the metal wiring M1, it is short-circuited via the wiring 160 in the eighth example.
  • FIG. 35 is a plan view showing a layout example of a light receiving chip according to the ninth example.
  • FIG. 36 is a plan view showing a layout example of a circuit chip according to the ninth example.
  • FIG. 37 is a cross-sectional view showing a structural example of the A-A' cross section according to the ninth example.
  • FIG. 38 is a cross-sectional view showing a structural example of a C-C' cross section according to the ninth example.
  • FIG. 39 is a cross-sectional view showing a structural example taken along line D-D' according to the ninth example.
  • the light-receiving chip 41 includes a reset transistor 32 in addition to photoelectric conversion units PDa to PDh and transfer transistors 31a to 31h.
  • the reset gate electrode 121 constituting the reset transistor 32, the gate insulation A film 121 a , a channel formation region 121 b and a pair of diffusion regions 110 are provided on the device formation surface of the semiconductor substrate 101 .
  • the reset gate electrode 121 is connected to the first metal wiring M1 through the through electrode 122 .
  • the diffusion region 110 that functions as the drain of the reset transistor 32 is short-circuited to the diffusion region 210a that is part of the drain of the amplification transistor 33 via the through electrode 124 .
  • the diffusion region 110 functioning as the source of the reset transistor 32 is arranged so as to overlap the wiring 160 in the substrate thickness direction.
  • the through electrode 123 penetrates the wiring 160 and is connected to the diffusion region 110 .
  • the through electrode 103 is connected to the floating diffusion region FD1
  • the through electrode 107 is connected to the floating diffusion region FD2 through the wiring 160.
  • the wiring 160 may be made of a conductive material such as polysilicon doped with an impurity, for example.
  • the amplifier transistor 33 and the selection transistor 34 are arranged in the circuit chip 42 .
  • the amplification gate electrode 231 of the amplification transistor 33 has an extension 233 similar to that of the first example, and is connected to the floating diffusion region FD1 via the extension 233. It is connected to the through electrode 103 .
  • the source of the reset transistor 32, the gate of the amplification transistor 33, and the floating diffusion regions FD1 and FD2 are short-circuited via the through electrodes 103, 107 and 123, the extension 233, and the wiring 160.
  • the necessary number of electrodes is reduced by extending the amplification gate electrode 231 in the direction of the floating diffusion region FD1 and short-circuiting it to the through electrode 103 .
  • the wiring density of the circuit chip 42 can be reduced to improve the device characteristics, and the design difficulty of the wiring layout of the circuit chip 42 can be simplified.
  • the reset transistor 32 in the light receiving chip 41, the area in which the amplification transistor can be arranged in the circuit chip is increased. In other words, it is possible to increase the gate area of the amplification transistor, and as a result, characteristics such as random noise can be improved over the fifth example.
  • a tenth example as in the fifth example, eight unit pixels 30 arranged in four rows and two columns share one floating diffusion region FD.
  • a circuit configuration example of FD sharing may be the same as the configuration described using FIG. 21 in the fifth example, so detailed description is omitted here. However, in the tenth example, the switching transistor 35 in the pixel circuit is omitted.
  • FIG. 40 is a plan view showing a layout example of a light receiving chip according to the tenth example.
  • FIG. 41 is a plan view showing a layout example of a circuit chip according to the tenth example.
  • FIG. 42 is a cross-sectional view showing a structural example of a cross section taken along line B-B' according to the tenth example.
  • FIG. 43 is a cross-sectional view showing a structural example of a C-C' cross section according to the tenth example.
  • FIG. 44 is a cross-sectional view showing a structural example taken along line D-D' according to the tenth example.
  • the light-receiving chip 41 includes an amplification transistor 33 in addition to photoelectric conversion units PDa to PDh and transfer transistors 31a to 31h.
  • FIGS. 40 and 42 to 44 in the layout example and cross-sectional structure example of the light-receiving chip 41, in the same configuration as those in the fifth example, 4 rows and 2 columns as illustrated in the fourth example.
  • An amplification gate electrode 131 is arranged at a position adjacent to the transfer gate electrodes 111a to 111h arranged in a row, and a pair of amplification gate electrodes 131 functioning as a source and a drain of the amplification transistor 33 are provided in a region sandwiching a channel forming region 131b under the amplification gate electrode 131.
  • a diffusion region 110 is located.
  • the through electrode 103 connected to the floating diffusion region FD1 and the through electrode 107 connected to the floating diffusion region FD2 are connected by the wiring 160 as in the sixth example.
  • the wiring 160 has an extending portion 161 extending in parallel with the element forming surface toward the amplification gate electrode 131 .
  • This extending portion 161 is connected to the through electrode 132 connected to the amplification gate electrode 131 .
  • the extending portion 161 may be made of the same material as the wiring 160, for example, a conductive material such as impurity-doped polysilicon.
  • the reset transistor 32 and the select transistor 34 are arranged on the circuit chip 42 .
  • the through electrode 132 connected to the amplification gate electrode 131 of the amplification transistor 33 penetrates the diffusion region 210a functioning as the source of the reset transistor 32.
  • FIG. As a result, the source of the reset transistor 32, the gate of the amplification transistor 33, and the floating diffusion regions FD1 and FD2 are short-circuited via the through electrodes 103, 107 and 132 and the wiring 160 including the extended portion 161.
  • the drain (diffusion region 210a) of the reset transistor 32 is short-circuited to the drain (diffusion region 110) of the amplification transistor 33 via the through electrode 135.
  • FIG. The through electrode 135 is connected to a power supply line that supplies a power supply voltage VDD via a first metal wiring M1 in the upper layer.
  • the drain (diffusion region 210 a ) of the selection transistor 34 is short-circuited to the source (diffusion region 110 ) of the amplification transistor 33 via the through electrode 134 .
  • the through electrode 132 connected to the gate of the amplification transistor 33 (amplification gate electrode 131) is connected to the source of the reset transistor 32 (diffusion region 210a).
  • the drain of the amplification transistor 33 is short-circuited to the drain of the reset transistor 32 through the through electrode 135, and the source of the amplification transistor 33 is short-circuited to the drain of the selection transistor through the through electrode 134.
  • the required number of electrodes can be further reduced, so that the wiring density of the circuit chip 42 can be reduced and the device characteristics can be further improved. It is also possible to make it easier.
  • the eleventh example as in the fifth example, eight unit pixels 30 arranged in four rows and two columns share one floating diffusion region FD.
  • the example of circuit configuration for sharing the FD may be the same as the configuration described with reference to FIG. It may be the same, and the DD' cross-sectional structure may be the same as the structure described with reference to FIG. 44 in the tenth example, so detailed description is omitted here.
  • the pixel circuit includes the switching transistor 35 .
  • FIG. 45 is a plan view showing a layout example of a light receiving chip according to the eleventh example.
  • FIG. 46 is a plan view showing a layout example of a circuit chip according to the eleventh example.
  • FIG. 47 is a cross-sectional view showing a structural example taken along line C-C' according to the eleventh example.
  • the light-receiving chip 41 is provided with the amplification transistor 33 in addition to the photoelectric conversion units PDa to PDh and the transfer transistors 31a to 31h, as in the tenth example.
  • the position where the extending portion 161 protrudes from the wiring 160 is the diffusion region 210a functioning as the source of the switching transistor 35 in the circuit chip 42. adjusted according to the position of
  • the reset transistor 32 , the selection transistor 34 and the switching transistor 35 are arranged in the circuit chip 42 .
  • the through electrode 132 connected to the amplification gate electrode 131 of the amplification transistor 33 penetrates the diffusion region 210 a functioning as the source of the switching transistor 35 .
  • the source of the switching transistor 35, the gate of the amplifying transistor 33, and the floating diffusion regions FD1 and FD2 are short-circuited via the through electrodes 103, 107 and 132 and the wiring 160 including the extended portion 161.
  • the drain (diffusion region 210a) of the reset transistor 32 is short-circuited to the drain (diffusion region 110) of the amplification transistor 33 via the through electrode 123.
  • the through electrode 123 is connected to a power supply line that supplies a power supply voltage VDD via a first metal wiring M1 in the upper layer.
  • the drain (diffusion region 210a) of the selection transistor 34 is short-circuited to the source (diffusion region 110) of the amplification transistor 33 via the through electrode 124.
  • the through electrode 132 connected to the gate of the amplification transistor 33 (amplification gate electrode 131) is connected to the source of the switching transistor 35 (diffusion region 210a).
  • the drain of the amplification transistor 33 is short-circuited to the drain of the reset transistor 32 via the through electrode 123, and the source of the amplification transistor 33 is short-circuited to the drain of the selection transistor via the through electrode 124.
  • the required number of electrodes can be further reduced, so that the wiring density of the circuit chip 42 can be reduced and the device characteristics can be further improved. It is also possible to make it easier.
  • circuit configuration for sharing the FD may be the same as the configuration described with reference to FIG. It may be the same, and the DD' cross-sectional structure may be the same as the structure described with reference to FIG. 44 in the tenth example, so detailed description is omitted here. However, in the twelfth example, the switching transistor 35 in the pixel circuit is omitted.
  • FIG. 48 is a cross-sectional view showing a cross-sectional structure example of a unit pixel according to the twelfth example.
  • FIG. 49 is a plan view showing a layout example of a light receiving chip according to the twelfth example.
  • FIG. 50 is a plan view showing a layout example of a circuit chip according to the twelfth example.
  • FIG. 51 is a cross-sectional view showing a structural example taken along the line B-B' according to the twelfth example.
  • FIG. 48 shows a cross-sectional structure example of the light-receiving chip 41 in which the photoelectric conversion part PD in the unit pixel 30 is arranged, similarly to FIG.
  • one on-chip lens 51 and one color filter 52 are arranged across two or more unit pixels 30 arranged in the row direction or the column direction. Thereby, one on-chip lens 51 and one color filter 52 are shared by two or more unit pixels 30 arranged in the row direction or the column direction.
  • the light-receiving chip 41 has an amplification transistor 33 in addition to the photoelectric conversion units PDa to PDh and the transfer transistors 31a to 31h, as in the tenth example.
  • the reset transistor 32 and the select transistor 34 are arranged in the circuit chip 42, as in the tenth example.
  • the through electrode 132 connected to the gate of the amplification transistor 33 (amplification gate electrode 131) is connected to the source of the reset transistor 32 (diffusion region 210a). Since the required number of electrodes can be further reduced by combining them, the wiring density of the circuit chip 42 can be reduced and the device characteristics can be further improved. It is also possible to convert
  • one on-chip lens 51 and one color filter 52 are shared by two or more unit pixels 30 described in the twelfth example is, for example, a quad-bayer (also called quadra) array of color filters 52. or when the solid-state imaging device 10 has a mechanism for automatically adjusting the focus based on the phase difference between adjacent pixels.
  • a quad-bayer also called quadra
  • the solid-state imaging device 10 has a mechanism for automatically adjusting the focus based on the phase difference between adjacent pixels.
  • a circuit configuration example for FD sharing may be the same as the configuration described using FIG. 6 in the first example, so detailed description is omitted here.
  • FIG. 52 is a cross-sectional view showing a cross-sectional structure example of a unit pixel according to the thirteenth example.
  • FIG. 53 is a plan view showing a layout example of a light receiving chip according to the thirteenth example.
  • FIG. 54 is a plan view showing a layout example of a circuit chip according to the thirteenth example.
  • photoelectric conversion units PDa to PDd and transfer transistors 31a to 31d are arranged in the light receiving chip 41, as in the first example.
  • the photoelectric conversion units PDa to PDd and the transfer transistors 31a to 31d are arranged in respective regions (hereinafter referred to as pixel regions) partitioned by the pixel separation unit 170 on the semiconductor substrate 101 .
  • diffusion regions 110a to 110d functioning as drains of the transfer transistors 31a to 31d are provided in the pixel regions partitioned by the pixel separation section 170, respectively. Diffusion regions 110a-110d also function as floating diffusion regions FDa-FDd.
  • the floating diffusion regions FDa to FDd are short-circuited via the wiring 162 and the through electrodes 113a to 113d passing therethrough.
  • the parasitic capacitance formed between the wiring 162 and the floating diffusion regions FDa to FDd and the semiconductor substrate 101 and/or the semiconductor substrate 201 functions as the capacitance of the floating diffusion regions FDa to FDd.
  • the wiring 162 may be composed of a conductive material such as polysilicon doped with impurities, for example.
  • each pixel region in which the photoelectric conversion units PDa to PDd are arranged is partitioned by the pixel separation unit 170 having the FTI structure, each pixel region is provided with contact portions 104a to 104d.
  • the well potential of each pixel region is controlled by being connected to the first metal wiring M1 via the through electrodes 105a to 105d.
  • the circuit chip 42 has a reset transistor 32, an amplification transistor 33, and a selection transistor 34 arranged therein.
  • the amplification gate electrode 231 has an extending portion 233 through which one of the through electrodes 113a to 113d (the through electrode 113b in FIG. 54) penetrates.
  • a through-electrode (through-electrode 113b in FIG. 54) penetrating the extending portion 233 is connected to one of the floating diffusion regions FDa to FDd (floating diffusion region FDb in FIG. 53). Further, one of the through electrodes 113a to 113d (the through electrode 113d in FIG.
  • the amplification gate electrode 231 of the amplification transistor 33 and the diffusion region 210a functioning as the source of the reset transistor 32 are short-circuited to the floating diffusion regions FDa to FDd via the through electrodes 113b and 113d, respectively.
  • the number of required electrodes is reduced, and the number of wirings to be formed in the wiring layer of the circuit chip 42 is reduced.
  • the wiring density of the circuit chip 42 can be reduced to improve the device characteristics, and the design difficulty of the wiring layout of the circuit chip 42 can be simplified.
  • a circuit configuration example for FD sharing may be the same as the configuration described using FIG. 21 in the fifth example, so detailed description is omitted here. However, in the fourteenth example, the switching transistor 35 in the pixel circuit is omitted.
  • FIG. 55 is a cross-sectional view showing a cross-sectional structure example of a unit pixel according to the fourteenth example.
  • FIG. 56 is a plan view showing a layout example of a light-receiving chip according to the fourteenth example.
  • FIG. 57 is a plan view showing a layout example of a circuit chip according to the fourteenth example.
  • FIG. 58 is a cross-sectional view showing a structural example of the EE' cross section according to the fourteenth example.
  • FIG. 59 is a cross-sectional view showing a structural example of the FF' cross section according to the fourteenth example.
  • FIG. 60 is a cross-sectional view showing a structural example of a G-G' cross section according to the fourteenth example.
  • FIG. 61 is a cross-sectional view showing a structural example of the H-H' cross section according to the fourteenth example.
  • FIG. 62 is a cross-sectional view showing a structural example of the LL' cross section according
  • Example of cross-sectional structure of unit pixel As shown in FIG. 55, in the fourteenth example, one on-chip lens 51 and one color filter 52 are shared in a structure similar to the cross-sectional structure of the unit pixel 30 described with reference to FIG. 48 in the twelfth example. A pixel separation section that separates two unit pixels 30 is replaced with an RDTI-type pixel separation section 60 . Therefore, in the fourteenth example, the FTI-type pixel separation unit 170 replaces the region in which eight unit pixels 30 arranged in two rows and four columns are arranged with two unit pixels 30 arranged in the row direction. It is divided into regions for each phase difference detection pixel (hereinafter also referred to as phase difference pixel regions), and the RDTI type pixel separation unit 60 divides the phase difference pixel region into pixel regions for each unit pixel 30 .
  • phase difference pixel regions regions for each phase difference detection pixel
  • the light-receiving chip 41 includes photoelectric conversion units PDa to PDh, transfer transistors 31a to 31h, and an amplification transistor 33, as in the tenth example. placed.
  • the amplification gate electrode constituting the amplification transistor 33 is separated into an amplification gate electrode 131A and an amplification gate electrode 131B. are placed.
  • the transfer gate electrodes 111a1, 111a2, 111b1, 111b2, 111c1, 111c2, 111d1 and 111d2 arranged in each pixel region are connected to the first electrodes through the through electrodes 112a1, 112a2, 112b1, 112b2, 112c1, 112c2, 112d1 and 112d2, respectively. It is connected to the metal wiring M1.
  • diffusion regions 110a and 110b functioning as drains of the transfer transistors 31a to 31h, 110c and 110d are arranged.
  • Each diffusion region 110a, 110b, 110c, 110d is shared between transfer transistors 31a and 31b, 31c and 31d, 31e and 31f, 31g and 31h formed in the same phase difference pixel region.
  • Diffusion regions 110a, 110b, 110c, and 110d also function as floating diffusion regions FDa to FDd.
  • the diffusion regions 110a, 110b, 110c and 110d are connected to the first metal wiring M1 via the through electrodes 113a, 113b, 113c and 113d.
  • the amplification gate electrodes 131A and 131B are connected to the first metal wiring M1 via through electrodes 132a and 132b.
  • the through electrodes 113 a , 113 b , 113 c , 113 d , 132 a and 132 b are short-circuited through wirings 160 and 163 . From the above, it becomes possible to short-circuit the FDa, FDb, FDc, FDd and the amplification gate electrodes 131A and 131B.
  • Contact portions 104a to 104d are provided in each phase difference pixel region, and these contact portions 104a to 104d are connected to the first metal wirings M1 through the through electrodes 105a to 105d, so that the well of each pixel region is A potential is controlled.
  • the reset transistor 32 and the select transistor 34 are arranged in the circuit chip 42.
  • the reset gate electrode constituting the reset transistor 32 is separated into the reset gate electrode 221A and the reset gate electrode 221B, and the reset gate electrodes 221A and 221B are respectively provided with diffusion regions 210 functioning as sources and drains. and 210a are arranged.
  • the selection gate electrode constituting the selection transistor 34 is separated into a selection gate electrode 241A and a selection gate electrode 241B, and diffusion regions 210 and 210a functioning as sources and drains are arranged in the selection gate electrodes 241A and 241B, respectively. ing.
  • the diffusion region 210a divided into two, which functions as the source of the reset transistor 32, is connected to the first metal wiring M1 via through electrodes 132a and 132b connected to the amplification gate electrodes 131A and 131B. That is, the through electrodes 132a and 132b connected to the amplification gate electrodes 131A and 131B also serve as through electrodes connecting the source of the reset transistor 32 to the first metal wiring M1. As a result, the source of the reset transistor 32, the gate of the amplification transistor 33, and the floating diffusion regions FDa to FDd are short-circuited.
  • the two divided diffusion regions 210 and 210a functioning as the drain of the reset transistor 32 are connected to the diffusion region 110 functioning as the drain of the amplifying transistor 33 through the through electrodes 134a to 134d connected to the first metal wiring. connected to M1. That is, the through electrodes 134a to 134d connected to the drain of the amplification transistor 33 also serve as through electrodes that connect the drain of the reset transistor 32 to the first metal wiring M1.
  • the diffusion region 210a divided into two, which functions as the drain of the selection transistor 34, is connected to the first metal wiring M1 through the through electrodes 135a to 135d connected to the diffusion region 110, which functions as the source of the amplification transistor 33.
  • the through electrodes 135a to 135d connected to the source of the amplification transistor 33 also serve as through electrodes connecting the drain of the selection transistor 34 to the first metal wiring M1.
  • the through electrodes 132a and 132b connected to the gates (amplification gate electrodes 131A and 131B) of the amplification transistor 33 are connected to the source (diffusion region 210a) of the reset transistor 32.
  • the through electrodes 134a to 134d connected to the drain of the amplification transistor 33 also serve as through electrodes connected to the drain of the reset transistor 32; and the through electrodes connected to the source of the amplification transistor 33. Since the through electrodes 135a to 135d also serve as through electrodes connected to the drain of the select transistor 34, the number of necessary electrodes is further reduced, so that the wiring density of the circuit chip 42 can be reduced and the device characteristics can be further improved. In addition, the degree of difficulty in designing the wiring layout of the circuit chip 42 can be further simplified.
  • the amplification gate electrodes 231/131 are connected to the extension portions 233 extending from the amplification gate electrodes 231 or the wirings 133/160 (and 161 or 163)/162 or electrically connected to the through electrodes 103/107 connected to the floating diffusion region FD via the first metal wiring M1 in the upper layer.
  • the wiring density can be reduced.
  • the parasitic capacitance caused by the wiring can be reduced, so that the device characteristics can be improved.
  • by reducing the wiring density it is possible to simplify the wiring layout design difficulty.
  • wiring (hereinafter referred to as wiring) connected to the amplification gate electrode and the floating diffusion region FD is used.
  • FD wiring) and other wiring for example, a power supply line (hereinafter also referred to as VDD wiring), a wiring connected to a reset gate electrode (hereinafter also referred to as RST control line), etc.).
  • VDD wiring a power supply line
  • RST control line a wiring connected to a reset gate electrode
  • the ratio of the area occupied by the amplification gate electrode in the pixel region tends to be larger than in the conventional structure. Therefore, there is a problem that the coupling capacitance between the amplification gate electrode and other wiring is more likely to increase than in the conventional structure.
  • VSS wiring a ground line or VSS wiring
  • this embodiment proposes a structure in which at least part of the amplification gate electrode and the FD wiring is covered with a conductive shield electrode.
  • an insulating film is arranged between the amplification gate electrode or the FD wiring and the shield electrode in order to avoid an electrical short circuit between them.
  • the shield electrode is connected to the VSS wiring.
  • the configuration of the electronic device according to the present embodiment (see FIG. 1), the configuration of the solid-state imaging device (see FIG. 2) and layered structure (see FIG. 4), the configuration and basic functions of the unit pixel (FIGS. 3, 6, 21, etc.) and the cross-sectional structure (see FIGS. 5, 48, 52, 55, etc.) may be the same as those of the above-described first embodiment.
  • FIG. 63 is a plan view showing a layout example of the light receiving chip according to the first example.
  • FIG. 64 is a plan view showing a layout example of a circuit chip according to a comparative example.
  • FIG. 65 is a plan view showing a layout example of the circuit chip according to the first example.
  • FIG. 66 is a partial cross-sectional view showing a partial structural example of the X-X' cross section according to the first example.
  • FIG. 67 is a partial cross-sectional view showing a partial structural example of the Y-Y' cross section according to the first example.
  • FIG. 68 is a cross-sectional view showing a structural example of a ZZ' cross section according to the first example.
  • the light-receiving chip 41 includes photoelectric conversion units PDa to PDh and transfer transistors 31a to 31h.
  • a layout example of the light-receiving chip 41 according to the first example may be the same as that described using FIG. 22 in the fifth example of the first embodiment. However, in FIG. 63, the layout example illustrated in FIG. 22 is rotated by 90 degrees (90 degrees to the left in FIG. 63) for convenience of explanation.
  • a reset transistor 32 In the comparative example, a reset transistor 32 , an amplification transistor 33 , a selection transistor 34 and a switching transistor 35 are arranged in the circuit chip 42 .
  • a planar layout example of the circuit chip 42 according to the comparative example may be the same as that described with reference to FIG. 23 in the fifth example of the first embodiment.
  • the extension portion 233 extending from the amplification gate electrode 231 is omitted, and instead, the gate of the amplification transistor 33 (amplification gate electrode 231), the floating diffusion regions FD1 and FD2, and the source (diffusion) of the switching transistor 35 are used.
  • FIG. 64 the gate widths of the reset transistor 32, the amplification transistor 33, the selection transistor 34, and the switching transistor 35 are expanded. Furthermore, in FIG. 64, the layout example illustrated in FIG. 23 is rotated by 90 degrees (90 degrees leftward in FIG. 64) for convenience of explanation.
  • the second metal wiring M2 above the first metal wiring M1 overlaps the amplification gate electrode 231 in the thickness direction of the substrate.
  • the second metal wiring M2 is connected to the diffusion region 210 functioning as the drain of the amplifying transistor 33 via the contact plug 234, the first metal wiring M1 and the via hole 235, and the diffusion region functioning as the drain of the reset transistor 32. 210 through contact plugs 223 , first metal wirings M 1 and via holes 225 . Therefore, the second metal wiring M2 is a VDD wiring.
  • the coupling capacitance between the amplification gate electrode 231 and the second metal wiring M2 increases as described above. As a result, deterioration of image quality is caused.
  • designing while suppressing the coupling capacitance between the second metal wiring M2 and the amplification gate electrode 231 leads to an increase in the wiring density of other portions, which increases design difficulty.
  • a shield electrode 260 that covers at least part of the region where the second metal wiring M2 and the amplification gate electrode 231 overlap in the substrate thickness direction is combined with the second metal wiring M2. It is interposed between the amplification gate electrode 231 and the amplification gate electrode 231 .
  • the shield electrode 260 may be composed of a conductive material such as, for example, impurity-doped polysilicon.
  • the shield electrode 260 is maintained at a potential lower than the power supply potential (eg, ground potential or VSS potential) by being connected to the through electrode 105 (or through electrode 109) connected to the VSS wiring, for example.
  • the power supply potential eg, ground potential or VSS potential
  • the through electrode 105 or through electrode 109 connected to the VSS wiring, for example.
  • the layout example of the circuit chip 42 according to the first example may be the same as the comparative example shown in FIG. 64 except for the shield electrode 260 .
  • the amplifying transistor 33 formed on the semiconductor substrate 201 includes, for example, a gate insulating film 231a covering part of the surface of the semiconductor substrate 201 and an amplifying transistor arranged on the gate insulating film 231a.
  • a gate electrode 231 and a pair of diffusion regions 210 (source/drain) sandwiching a channel forming region 231b under the amplification gate electrode 231 are provided.
  • a side wall 231 c may be provided on the side surface of the amplification gate electrode 231 to secure a distance between the diffusion region 210 functioning as a source/drain and the amplification gate electrode 231 .
  • the sidewall 231c may be an insulating film such as a silicon oxide film. Note that such a transistor structure may also be applied to the reset transistor 32 , the selection transistor 34 and the switching transistor 35 .
  • At least the region where the shield electrode 260 is formed on the upper surface of the semiconductor substrate 201 on which the amplification transistor 33 is formed is covered with an insulating film 261 . This prevents the shield electrode 260 from being short-circuited to the semiconductor substrate 201 or the amplification transistor 33 .
  • FIG. 69 is a plan view showing a layout example of a circuit chip according to a modification of the first example.
  • the objects to suppress capacitive coupling are not limited to the VDD wiring and the amplification gate electrode 231 .
  • a shield electrode 260 may be arranged so as to suppress capacitive coupling between the amplification gate electrode 231 and the second metal wiring M2 connected to the reset gate electrode 221 .
  • a shield electrode 260 is provided between the second metal wiring M2 and the amplification gate electrode 231 to cover at least part of the region where the second metal wiring M2 and the amplification gate electrode 231 overlap in the substrate thickness direction.
  • the shield electrode 260 arranged with respect to the amplification gate electrode 231 shared by eight unit pixels 30 sharing the floating diffusion region FD (hereinafter referred to as a shared pixel group) is connected to the shared pixel group.
  • the shield electrode 260 is connected to the through electrodes 105/109 for controlling the well potential of the shield electrode 260 is not limited to this.
  • they may be connected to through electrodes 105/109 for controlling well potentials of adjacent shared pixel groups.
  • FIG. 70 is a plan view showing a layout example of a circuit chip according to the second example.
  • FIG. 71 is a cross-sectional view showing a structural example of a W-W' cross section according to the second example.
  • a layout example of the light receiving chip 41 according to the second example may be the same as the layout example described with reference to FIG. 53 in the thirteenth example of the first embodiment.
  • FIG. 70 the layout example of the circuit chip 42 according to the second example is similar to the layout example described with reference to FIG. 54 in the thirteenth example of the first embodiment.
  • a second metal wiring M2 (VDD) as a VDD wiring and a second metal wiring M2 (RST) connected to the reset gate electrode 221 are wired.
  • the shield electrode 260 is formed so as to cover at least part of the overlapping region of the amplification gate electrode 231 and the second metal wiring M2 (VDD) and/or M2 (RST) in the substrate thickness direction. is placed.
  • the second metal wiring M2 (VDD) is connected through a via hole 225 to the first metal wiring M1 short-circuited to the diffusion region 210 functioning as the drain of the reset transistor 32 .
  • the second metal wiring M2 (RST) is connected through a via hole 226 to the first metal wiring M1 short-circuited to the reset gate electrode 221 .
  • the shield electrode 260 is connected to one or more of the through electrodes 105a to 105d (the through electrode 105a in FIG. 70) to maintain a potential lower than the power supply potential (eg, ground potential or VSS potential). be.
  • the power supply potential eg, ground potential or VSS potential.
  • the shield electrode 260 is arranged on the amplification gate electrode 231 via the insulating film 261 so as to cover at least part of the amplification gate electrode 231 .
  • the region where the shield electrode 260 is arranged may correspond to at least part of the region where the amplification gate electrode 231 and the second metal wiring M2 (VDD) and/or M2 (RST) overlap.
  • FIG. 72 is a plan view showing a layout example of a circuit chip according to the third example.
  • FIG. 73 is a cross-sectional view showing a structural example taken along line A-A' according to the third example.
  • FIG. 74 is a cross-sectional view showing a structural example of the B-B' cross section according to the third example.
  • a layout example of the light-receiving chip 41 according to the third example may be the same as the layout example described with reference to FIG. 7 in the first example of the first embodiment.
  • FIG. 72 to 74 the layout example of the circuit chip 42 according to the third example is similar to the layout example described with reference to FIG. 14 in the third example of the first embodiment.
  • a second metal wiring M2 (RST) connected to the reset gate electrode 221 is wired so as to straddle the diffusion region 210 (corresponding to the FD wiring) functioning as the source of 32 and the amplification gate electrode 231 .
  • the shield electrode 260 is formed so as to cover at least part of the region where the diffusion region 210 and/or the amplification gate electrode 231 and the second metal wiring M2 (RST) overlap in the substrate thickness direction. placed.
  • the shield electrode 260 is maintained at a potential lower than the power supply potential (eg, ground potential or VSS potential) by being connected to the through electrode 105 for controlling the well potential of the adjacent shared pixel group.
  • the power supply potential eg, ground potential or VSS potential
  • At least part of the region where the diffusion region 210 and/or the amplification gate electrode 231 and the second metal wiring M2 (RST) overlap in the thickness direction of the substrate is a shield electrode maintained at the ground potential or the VSS potential.
  • a shield electrode maintained at the ground potential or the VSS potential.
  • the shield electrode 260 maintained at the ground potential or VSS potential. This suppresses the wiring from being capacitively coupled with other wiring such as the second metal wiring M2. As a result, the parasitic capacitance caused by the capacitive coupling of the wiring is reduced, so that it is possible to suppress the deterioration of the device characteristics and the difficulty of designing the wiring layout.
  • the technology according to the present disclosure (this technology) can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 75 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) functions including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) functions including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display section 12062 and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 76 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 76 shows an example of the imaging range of the imaging units 12101 to 12104.
  • FIG. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above.
  • By applying the technology according to the present disclosure to the imaging unit 12031 it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.
  • FIG. 77 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (this technology) can be applied.
  • FIG. 77 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000 .
  • an endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, and a support arm device 11120 for supporting the endoscope 11100. , and a cart 11200 loaded with various devices for endoscopic surgery.
  • An endoscope 11100 is composed of a lens barrel 11101 whose distal end is inserted into the body cavity of a patient 11132 and a camera head 11102 connected to the proximal end of the lens barrel 11101 .
  • an endoscope 11100 configured as a so-called rigid scope having a rigid lens barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel. good.
  • the tip of the lens barrel 11101 is provided with an opening into which the objective lens is fitted.
  • a light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel 11101 by a light guide extending inside the lens barrel 11101, where it reaches the objective. Through the lens, the light is irradiated toward the observation object inside the body cavity of the patient 11132 .
  • the endoscope 11100 may be a straight scope, a perspective scope, or a side scope.
  • An optical system and an imaging element are provided inside the camera head 11102, and the reflected light (observation light) from the observation target is focused on the imaging element by the optical system.
  • the imaging device photoelectrically converts the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image.
  • the image signal is transmitted to a camera control unit (CCU: Camera Control Unit) 11201 as RAW data.
  • CCU Camera Control Unit
  • the CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the operations of the endoscope 11100 and the display device 11202 in an integrated manner. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing such as development processing (demosaicing) for displaying an image based on the image signal.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 under the control of the CCU 11201 .
  • the light source device 11203 is composed of a light source such as an LED (light emitting diode), for example, and supplies the endoscope 11100 with irradiation light for imaging a surgical site or the like.
  • a light source such as an LED (light emitting diode)
  • LED light emitting diode
  • the input device 11204 is an input interface for the endoscopic surgery system 11000.
  • the user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204 .
  • the user inputs an instruction or the like to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100 .
  • the treatment instrument control device 11205 controls driving of the energy treatment instrument 11112 for tissue cauterization, incision, blood vessel sealing, or the like.
  • the pneumoperitoneum device 11206 inflates the body cavity of the patient 11132 for the purpose of securing the visual field of the endoscope 11100 and securing the operator's working space, and injects gas into the body cavity through the pneumoperitoneum tube 11111. send in.
  • the recorder 11207 is a device capable of recording various types of information regarding surgery.
  • the printer 11208 is a device capable of printing various types of information regarding surgery in various formats such as text, images, and graphs.
  • the light source device 11203 that supplies the endoscope 11100 with irradiation light for photographing the surgical site can be composed of, for example, a white light source composed of an LED, a laser light source, or a combination thereof.
  • a white light source is configured by a combination of RGB laser light sources
  • the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy. It can be carried out.
  • the observation target is irradiated with laser light from each of the RGB laser light sources in a time-division manner, and by controlling the drive of the imaging element of the camera head 11102 in synchronization with the irradiation timing, each of RGB can be handled. It is also possible to pick up images by time division. According to this method, a color image can be obtained without providing a color filter in the imaging element.
  • the driving of the light source device 11203 may be controlled so as to change the intensity of the output light every predetermined time.
  • the drive of the imaging device of the camera head 11102 in synchronism with the timing of the change in the intensity of the light to obtain an image in a time-division manner and synthesizing the images, a high dynamic A range of images can be generated.
  • the light source device 11203 may be configured to be able to supply light in a predetermined wavelength band corresponding to special light observation.
  • special light observation for example, the wavelength dependence of light absorption in body tissues is used to irradiate a narrower band of light than the irradiation light (i.e., white light) used during normal observation, thereby observing the mucosal surface layer.
  • irradiation light i.e., white light
  • Narrow Band Imaging in which a predetermined tissue such as a blood vessel is imaged with high contrast, is performed.
  • fluorescence observation may be performed in which an image is obtained from fluorescence generated by irradiation with excitation light.
  • the body tissue is irradiated with excitation light and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and the body tissue is examined.
  • a fluorescence image can be obtained by irradiating excitation light corresponding to the fluorescence wavelength of the reagent.
  • the light source device 11203 can be configured to supply narrowband light and/or excitation light corresponding to such special light observation.
  • FIG. 78 is a block diagram showing an example of functional configurations of the camera head 11102 and CCU 11201 shown in FIG.
  • the camera head 11102 has a lens unit 11401, an imaging section 11402, a drive section 11403, a communication section 11404, and a camera head control section 11405.
  • the CCU 11201 has a communication section 11411 , an image processing section 11412 and a control section 11413 .
  • the camera head 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400 .
  • a lens unit 11401 is an optical system provided at a connection with the lens barrel 11101 . Observation light captured from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401 .
  • a lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.
  • the number of imaging elements constituting the imaging unit 11402 may be one (so-called single-plate type) or plural (so-called multi-plate type).
  • image signals corresponding to RGB may be generated by each image pickup element, and a color image may be obtained by synthesizing the image signals.
  • the imaging unit 11402 may be configured to have a pair of imaging elements for respectively acquiring right-eye and left-eye image signals corresponding to 3D (dimensional) display.
  • the 3D display enables the operator 11131 to more accurately grasp the depth of the living tissue in the surgical site.
  • a plurality of systems of lens units 11401 may be provided corresponding to each imaging element.
  • the imaging unit 11402 does not necessarily have to be provided in the camera head 11102 .
  • the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.
  • the drive unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under control from the camera head control unit 11405 . Thereby, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.
  • the communication unit 11404 is composed of a communication device for transmitting and receiving various information to and from the CCU 11201.
  • the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400 .
  • the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies it to the camera head control unit 11405 .
  • the control signal includes, for example, information to specify the frame rate of the captured image, information to specify the exposure value at the time of capturing, and/or information to specify the magnification and focus of the captured image. Contains information about conditions.
  • the imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately designated by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. good.
  • the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function and AWB (Auto White Balance) function.
  • the camera head control unit 11405 controls driving of the camera head 11102 based on the control signal from the CCU 11201 received via the communication unit 11404.
  • the communication unit 11411 is composed of a communication device for transmitting and receiving various information to and from the camera head 11102 .
  • the communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400 .
  • the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102 .
  • Image signals and control signals can be transmitted by electrical communication, optical communication, or the like.
  • the image processing unit 11412 performs various types of image processing on the image signal, which is RAW data transmitted from the camera head 11102 .
  • the control unit 11413 performs various controls related to imaging of the surgical site and the like by the endoscope 11100 and display of the captured image obtained by imaging the surgical site and the like. For example, the control unit 11413 generates control signals for controlling driving of the camera head 11102 .
  • control unit 11413 causes the display device 11202 to display a captured image of the surgical site and the like based on the image signal that has undergone image processing by the image processing unit 11412 .
  • the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 detects the shape, color, and the like of the edges of objects included in the captured image, thereby detecting surgical tools such as forceps, specific body parts, bleeding, mist during use of the energy treatment tool 11112, and the like. can recognize.
  • the control unit 11413 may use the recognition result to display various types of surgical assistance information superimposed on the image of the surgical site. By superimposing and presenting the surgery support information to the operator 11131, the burden on the operator 11131 can be reduced and the operator 11131 can proceed with the surgery reliably.
  • a transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable of these.
  • wired communication is performed using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.
  • the technology according to the present disclosure can be applied to, for example, the imaging unit 11402 of the camera head 11102 among the configurations described above.
  • the technology according to the present disclosure can be applied to the camera head 11102, a clearer image of the surgical site can be obtained, so that the operator can reliably confirm the surgical site.
  • the technology according to the present disclosure may also be applied to, for example, a microsurgery system.
  • a first substrate including a photoelectric conversion portion that photoelectrically converts incident light to generate electric charge; a second substrate that is attached to the first substrate and includes at least part of a pixel circuit that generates a voltage signal based on the charge generated in the photoelectric conversion unit; a first metal wiring disposed on the side opposite to the first substrate with the second substrate interposed therebetween; with
  • the pixel circuit is a charge storage unit that stores charges generated in the photoelectric conversion unit; an amplification transistor that converts the charge accumulated in the charge accumulation unit into a voltage having a voltage value corresponding to the charge amount of the charge; a reset transistor that releases the charge accumulated in the charge accumulation unit; a first through electrode connected to the charge storage section through the second substrate from the first metal wiring; a first wiring that connects the gate electrode of the amplification transistor and the first through electrode;
  • Solid-state imaging device including (2) The solid-state imaging device according to (1), wherein the first wiring is an extension extending from the gate electrode of the a
  • the pixel circuit further comprises a second through electrode connected to the gate electrode of the amplification transistor, The solid-state imaging device according to (1), wherein the first wiring is wiring that connects the first through electrode and the second through electrode.
  • the reset transistor is disposed on the second substrate;
  • the amplification transistor is arranged on the first substrate,
  • the pixel circuit further comprises a second through electrode connected to the gate electrode of the amplification transistor,
  • the first substrate includes a plurality of photoelectric conversion units,
  • the pixel circuit is a plurality of the charge storage units; a third wiring that connects the plurality of charge storage units;
  • a photoelectric conversion unit that photoelectrically converts incident light to generate electric charges
  • a pixel circuit that generates a voltage signal based on the charge generated in the photoelectric conversion unit; with The photoelectric conversion unit is arranged on the first substrate, at least part of the pixel circuit is disposed on a second substrate bonded to the first substrate;
  • the pixel circuit is a charge storage unit that stores charges generated in the photoelectric conversion unit; an amplification transistor that converts the charge accumulated in the charge accumulation unit into a voltage having a voltage value corresponding to the charge amount of the charge; a reset transistor that releases the charge accumulated in the charge accumulation unit; including
  • the amplification transistor is arranged on the second substrate,
  • the second substrate is a second metal wiring disposed on the side opposite to the first substrate with the second substrate interposed therebetween; a shield electrode arranged at least partly between the second metal wiring and the gate electrode of the amplification transistor;
  • a solid-state imaging device further comprising: (16) The solid-state imaging device according to (15), wherein

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