WO2022157822A1 - 画素回路、表示装置、および、その駆動方法 - Google Patents

画素回路、表示装置、および、その駆動方法 Download PDF

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Publication number
WO2022157822A1
WO2022157822A1 PCT/JP2021/001628 JP2021001628W WO2022157822A1 WO 2022157822 A1 WO2022157822 A1 WO 2022157822A1 JP 2021001628 W JP2021001628 W JP 2021001628W WO 2022157822 A1 WO2022157822 A1 WO 2022157822A1
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Prior art keywords
bias
switching element
voltage
data
holding capacitor
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English (en)
French (fr)
Japanese (ja)
Inventor
真仁 佐野
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Sharp Corp
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Sharp Corp
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Priority to US18/271,930 priority Critical patent/US12159582B2/en
Priority to JP2022576248A priority patent/JP7512444B2/ja
Priority to PCT/JP2021/001628 priority patent/WO2022157822A1/ja
Publication of WO2022157822A1 publication Critical patent/WO2022157822A1/ja
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to a current-driven display device having a display element driven by current, such as an organic EL (Electro Luminescence) element, and particularly to a pixel circuit used in the display device.
  • a display element driven by current such as an organic EL (Electro Luminescence) element
  • a pixel circuit of an organic EL display device includes a drive transistor, a write control transistor, a holding capacitor, etc. in addition to the organic EL element.
  • a thin film transistor is used for the drive transistor and the write control transistor, and a holding capacitor is connected to the gate terminal as the control terminal of the drive transistor.
  • a voltage corresponding to a video signal representing an image to be displayed (more specifically, a voltage representing a gradation value of a pixel to be formed by the pixel circuit) is applied as a data voltage.
  • An organic EL element is a self-luminous display element that emits light with a luminance corresponding to the current flowing through it.
  • the drive transistor is provided in series with the organic EL element and controls the current flowing through the organic EL element according to the voltage held in the holding capacitor.
  • a display device that performs pause driving is known as a display device with low power consumption.
  • pause driving when the same image is displayed continuously, a drive period (refresh period) and a rest period (non-refresh period) are provided, the drive circuit is operated during the drive period, and the operation of the drive circuit is stopped during the rest period.
  • It is a driving method, and is also called “intermittent driving” or "low frequency driving”.
  • Pause driving can be applied when the off-leakage current of a transistor as a switching element included in a pixel circuit is small.
  • a thin film transistor hereinafter referred to as an "oxide TFT" having a channel layer formed of an oxide semiconductor is known.
  • indium gallium zinc oxide (InGaZnO) is used as the oxide semiconductor.
  • the adopted oxide TFT (hereinafter referred to as “IGZO-TFT”) is used.
  • IGZO-TFT thin film transistor
  • LTPS-TFT thin film transistor having a channel layer formed of low-temperature polysilicon with high mobility
  • IGZO-TFT having a small off-leak current is used as a switching element.
  • An organic EL display device has been proposed in which a display unit configured by such a pixel circuit is used as a pixel circuit and performs pause driving (see, for example, US Patent Application Publication No. 2020/0118487).
  • the organic EL element of each pixel circuit When rest driving is performed in an organic EL display device, the organic EL element of each pixel circuit is turned off by the light emission control transistor during a non-light emitting period provided for each frame period in the driving period. The operation of the circuit stops, and the organic EL element of each pixel circuit continues to emit light with a luminance corresponding to the data voltage written in the previous driving period.
  • the pause period is much longer than the drive period (for example, the drive period consists of one or several frame periods, and the pause period consists of several tens of frame periods). , such drive periods and rest periods alternate. Therefore, when such a pause drive is performed, the off-lighting of the organic EL element during the drive period is visually recognized as flicker.
  • the thin film transistor as the driving transistor in the pixel circuit has hysteresis. Due to its characteristic, flicker is still visible in low frequency drive (pause drive). That is, in this periodic light-off configuration, the voltage stress applied to the thin film transistor as the drive transistor differs between the drive period and the rest period. Unlike, this makes the flicker visible.
  • bias stress voltage hereinafter referred to as "on-bias voltage” or simply “bias voltage”
  • bias voltage is applied intentionally to the drive transistor during the idle period.
  • a current-driven display device such as an organic EL display device be able to perform good display without visible flicker in the entire area of the display image even if the pause drive is performed.
  • a pixel circuit is a display device having a display section including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of emission control lines, and first and second power supply lines. in any one of the plurality of data signal lines, corresponding to any one of the plurality of first scanning signal lines, and any one of the plurality of emission control lines
  • a correspondingly arranged pixel circuit comprising: a display element driven by a current; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal and provided in series with the display element; a data retention capacitor; a data write control switching element having a control terminal connected to a corresponding first scanning signal line and controlling writing of the voltage of the corresponding data signal line to the data holding capacitor; a first emission control switching element having a control terminal connected to a corresponding emission control line; a bias supply circuit;
  • the display unit further includes a plurality of bias control lines, the pixel circuit corresponds to one of the plurality of
  • a display device comprises: a display unit including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of emission control lines, a plurality of bias control lines, a first power supply line, a second power supply line, and a plurality of pixel circuits; a data side driver circuit that generates a plurality of data signals and applies them to the plurality of data signal lines; a scanning side drive circuit that selectively drives the plurality of first scanning signal lines, selectively drives the plurality of emission control lines, and selectively drives the plurality of bias control lines; A driving period consisting of a refresh frame period for writing the voltages of the plurality of data signals to the plurality of pixel circuits as data voltages, and a rest period consisting of a non-refresh frame period for stopping writing of the data voltages to the plurality of pixel circuits.
  • each of the plurality of pixel circuits corresponds to any one of the plurality of data signal lines, corresponds to any one of the plurality of first scanning signal lines, and corresponds to any one of the plurality of emission control lines; , and corresponding to any one of the plurality of bias control lines, a display element driven by current; a drive transistor having a control terminal, a first conduction terminal and a second conduction terminal and provided in series with the display element; a data holding capacitor; and a corresponding first scanning signal line.
  • a data write control switching element for controlling writing of the voltage of the corresponding data signal line to the data holding capacitor and having a control terminal connected to the corresponding light emission control line; including a light emission control switching element and a bias supply circuit,
  • the bias supply circuit has a bias holding capacitor for holding a voltage corresponding to the voltage of the corresponding data signal line, and a control terminal connected to the corresponding bias control line, and is connected in series with the bias holding capacitor.
  • the display control circuit is In the drive period, the voltage of the corresponding data signal line is written and held as the data voltage in the data holding capacitor when the first light emission control switching element is in an off state, and a voltage corresponding to the data voltage is produced.
  • the data-side driving circuit and the controlling the scanning side drive circuit In the idle period, when the first light emission control switching element is in an off state, the voltage held by the bias holding capacitor is applied to the first conduction terminal of the driving transistor through the bias control switching element.
  • the scanning side drive circuit is controlled such that a current corresponding to the voltage held by the data holding capacitor flows through the display element when the light emission control switching element is in an ON state.
  • a driving method provides a display including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of emission control lines, first and second power supply lines, and a plurality of pixel circuits.
  • a method of driving a display device comprising: The display unit further includes a plurality of bias control lines, each of the plurality of pixel circuits, corresponds to any one of the plurality of data signal lines, corresponds to any one of the plurality of first scanning signal lines, and corresponds to any one of the plurality of emission control lines; , and corresponding to any one of the plurality of bias control lines, a display element driven by current; a drive transistor having a control terminal, a first conduction terminal and a second conduction terminal and provided in series with the display element; a data holding capacitor; and a corresponding first scanning signal line.
  • a data write control switching element for controlling writing of the voltage of the corresponding data signal line to the data holding capacitor and having a control terminal connected to the corresponding light emission control line; including a light emission control switching element and a bias supply circuit,
  • the bias supply circuit has a bias holding capacitor for holding a voltage corresponding to the voltage of the corresponding data signal line, and a control terminal connected to the corresponding bias control line, and is connected in series with the bias holding capacitor.
  • the driving method includes a drive period consisting of a refresh frame period in which voltages of a plurality of data signals are written as data voltages in the plurality of pixel circuits, and a non-refresh frame period in which writing of data voltages to the plurality of pixel circuits is stopped.
  • the rest drive step includes: In the drive period, when the first light emission control switching element is in an off state, the voltage of the corresponding data signal line is written and held in the data holding capacitor as a data voltage, and a voltage corresponding to the data voltage is produced. The plurality of data signals are written and held in the bias holding capacitor so that a current corresponding to the voltage held in the data holding capacitor flows through the display element when the first emission control switching element is in an ON state.
  • the idle period when the first light emission control switching element is in an off state, the voltage held by the bias holding capacitor is applied to the first conduction terminal of the driving transistor through the bias control switching element, Driving of the plurality of first scanning signal lines is stopped so that a current corresponding to the voltage held by the data holding capacitor flows through the display element when the light emission control switching element is in an ON state, and the plurality of bias control lines are driven. and selectively inactivating the plurality of emission control lines.
  • the bias holding capacitor In a display device using a pixel circuit including a bias supply circuit having a bias control switching element and a bias control switching element, when pause driving is performed in which a drive period consisting of a refresh frame period and a rest period consisting of a non-refresh frame period alternately appear, The emission control line and the bias control line are driven during both the drive period and the rest period.
  • the bias holding capacitor By driving the light emission control line and the bias control line in this manner, in each pixel circuit, when the voltage of the data signal line is written into the data holding capacitor, the bias holding capacitor also responds to the voltage of the data signal line during the drive period. The voltage is written and held, and in the idle period, the holding voltage of the bias holding capacitor is applied to the first conduction terminal of the drive transistor during the non-light emitting period. That is, a bias stress voltage corresponding to the display gradation of the pixel circuit is applied to the first conduction terminal of the driving transistor during the non-light emitting period of the idle period.
  • FIG. 1 is a block diagram showing the overall configuration of a display device according to a first embodiment
  • FIG. 4 is a timing chart for explaining the schematic operation in the normal drive mode of the display device according to the first embodiment
  • FIG. 4 is a circuit diagram showing a configuration of a pixel circuit in a comparative example with respect to the first embodiment
  • 4 is a timing chart for explaining the operation of the pixel circuit in the comparative example
  • 7A and 7B are circuit diagrams for explaining the initialization operation, the data write operation, and the lighting operation of the pixel circuit in the comparative example
  • FIG. 10 is a circuit diagram for explaining a light-off operation (without on-bias application) and an on-bias application operation of the pixel circuit in the comparative example;
  • 2 is a circuit diagram showing the configuration of a pixel circuit in the first embodiment;
  • FIG. 4 is a timing chart for explaining the operation of the pixel circuit in the first embodiment;
  • FIG. 4A and 4B are circuit diagrams for explaining an initialization operation, a data write operation, and a lighting operation of the pixel circuit in the first embodiment;
  • FIG. 4A and 4B are circuit diagrams for explaining a light-off operation (without on-bias application) and an on-bias application operation of the pixel circuit in the first embodiment;
  • FIG. 5 is a timing chart for explaining a method of driving the display device according to the comparative example; 4 is a timing chart for explaining a driving method of the display device according to the first embodiment;
  • FIG. 5 is a waveform diagram for explaining the extinguishing operation in the first embodiment and the comparative example;
  • FIG. 4 is a waveform diagram for explaining a difference in turn-off waveforms between the first embodiment and the comparative example;
  • FIG. 7 is a circuit diagram showing the configuration of a pixel circuit in a display device according to a second embodiment; 8 is a timing chart for explaining the operation of the pixel circuit in the second embodiment;
  • FIG. 8A and 8B are circuit diagrams for explaining an initialization operation, a data write operation, and a lighting operation of the pixel circuit in the second embodiment
  • FIG. FIG. 10 is a circuit diagram for explaining the extinguishing operation (without on-bias application) and the on-bias application operation of the pixel circuit in the second embodiment
  • FIG. 4 is a circuit diagram showing the configuration of a pixel circuit in a display device according to a modification of the first embodiment; 20 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 19;
  • FIG. 4 is a circuit diagram showing a configuration example when a bias supply circuit is provided in a pixel circuit that does not perform threshold compensation by diode connection; 22 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 21;
  • the gate terminal corresponds to the control terminal
  • one of the drain terminal and the source terminal corresponds to the first conduction terminal
  • the other corresponds to the second conduction terminal.
  • connection in this specification means “electrical connection” unless otherwise specified. Indirect connection via an element is also included.
  • FIG. 1 is a block diagram showing the overall configuration of a display device 10 according to the first embodiment.
  • This display device 10 is an organic EL display device that performs internal compensation. That is, in the display device 10, each pixel circuit 15 has a function of compensating for variations and fluctuations in the threshold voltage of the driving transistor therein.
  • the display device 10 also has two operation modes, a normal drive mode and a pause drive mode. That is, in the normal drive mode, the display device 10 operates so that the refresh frame periods Trf for rewriting the image data (data voltage in each pixel circuit) of the display section are continuous.
  • a driving period TD and a rest period TP consisting of a plurality of non-refresh frame periods Tnrf for stopping rewriting of image data on the display section alternately appear (see FIG. 12 described later).
  • the display device 10 includes a display section 11, a display control circuit 20, a data side drive circuit 30, a scanning side drive circuit 40, and a power supply circuit .
  • the data side driver circuit 30 functions as a data signal line driver circuit (also called “data driver”).
  • the scanning-side driving circuit 40 functions as a scanning signal line driving circuit (also called “gate driver”), a light emission control circuit (also called “emission driver”), and a bias control circuit.
  • these three scanning-side circuits are implemented as one scanning-side drive circuit 40, but these three circuits may be separated as appropriate, and these three circuits may be separated. may be arranged separately on one side and the other side of the display section 11 .
  • the power supply circuit 50 supplies the display unit 11 with a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, an initialization voltage Vini, a display control circuit 20 , a data-side drive circuit 30 , and a scanning-side drive circuit 40 . and a power supply voltage (not shown) to be supplied to .
  • the display unit 11 has m data signal lines D1, D2, .
  • This (n is an integer equal to or greater than 2) second scanning signal lines NS-1, NS0, NS1, . . . , NSn are arranged.
  • n light emission control lines (emission lines) EM1 to EMn are arranged along the n first scanning signal lines PS1 to PSn, respectively, and the n first scanning signal lines PS1 to PSn are provided with n light emission control lines (emission lines) EM1 to EMn, respectively.
  • n bias control lines BS1 to BSn are arranged along it.
  • the display unit 11 is provided with m ⁇ n pixel circuits 15 arranged in a matrix along m data signal lines D1 to Dm and n first scanning signal lines PS1 to PSn. .
  • Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and corresponds to one of the n first scanning signal lines PS1 to PSn (hereinafter each pixel circuit 15 , the pixel circuit corresponding to the i-th first scanning signal line PSi and the j-th data signal line Dj is also referred to as the "i-th row j-th column pixel circuit", and the code "Pix (i, j )”).
  • Each pixel circuit 15 corresponds to any one of the n second scanning signal lines NS1 to NSn and to any one of the n emission control lines EM1 to EMn. Each pixel circuit 15 also corresponds to any one of the n bias control lines BS1 to BSn.
  • a power supply line (not shown) common to each pixel circuit 15 is arranged. That is, a first power supply line (hereinafter referred to as a “high level power supply line” and a symbol “ ELVDD”), and a second power supply line as a fixed voltage line for supplying the low level power supply voltage ELVSS for driving the organic EL element (hereinafter referred to as "low level power supply line", low level power supply voltage (indicated by the symbol "ELVSS”) is arranged.
  • the display unit 11 is provided with an initialization voltage Vini as a fixed voltage line (not shown) for supplying an initialization voltage Vini used for a reset operation (also referred to as an “initialization operation”) for initializing each pixel circuit 15 .
  • a line (labeled "Vini" like the initialization voltage) is also provided.
  • a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, and an initialization voltage Vini are supplied from the power supply circuit 50 .
  • the display control circuit 20 receives an input signal Sin including image information representing an image to be displayed and timing control information for image display from the outside of the display device 10, and based on this input signal Sin, a data side control signal Scd and a scanning signal. A side control signal Scs is generated, and a data side control signal Scd and a scanning side control signal Scs are output to the data side driving circuit 30 and the scanning side driving circuit 40, respectively.
  • the data side drive circuit 30 drives the data signal lines D1 to Dm based on the data side control signal Scd from the display control circuit 20. That is, the data-side drive circuit 30 generates m data signals D(1) to D(m) representing images to be displayed based on the data-side control signal Scd, and applies them to the data signal lines D1 to Dm, respectively. .
  • the scanning drive circuit 40 drives the n first scanning signal lines PS1 to PSn and the n+2 second scanning signal lines NS-1 to NSn based on the scanning control signal Scs from the display control circuit 20. It functions as a signal line drive circuit, an emission control circuit that drives the emission control lines EM1 to EMn, and a bias control circuit that drives the bias control lines BS1 to BSn.
  • the scanning-side driving circuit 40 drives the n first scanning signal lines PS1 to PSn for one horizontal period based on the scanning-side control signal Scs.
  • n+2 second scanning signal lines NS-1 to NSn are sequentially selected for a predetermined period corresponding to one horizontal period, and the selected first scanning signal line PSk is activated for a predetermined period.
  • a signal is applied (k is an integer satisfying 1 ⁇ k ⁇ n), an active signal is applied to the selected second scanning signal line NSs (s is an integer satisfying ⁇ 1 ⁇ s ⁇ n), and An inactive signal is applied to the selected first scanning signal line, and an inactive signal is applied to the non-selected second scanning signal line.
  • m pixel circuits Pix(k, 1) to Pix(k, m) corresponding to the selected first scanning signal line PSk are collectively selected.
  • m data signals D (1 ) to D(m) (hereinbelow, these voltages may be simply referred to as “data voltages” without distinction) are used as pixel data for the pixel circuits Pix(k, 1) to Pix(k, m ), respectively.
  • a light-emission control signal high level
  • a light emission control signal low level voltage
  • the organic EL elements in the pixel circuits Pix (i, 1) to Pix (i, m) corresponding to the i-th first scanning signal line PSi are connected to the light emission control line. While the voltage of EMi is at the low level (activated state), the i-th pixel circuits Pix(i, 1) to Pix(i, m) emit light with luminance corresponding to the data voltages written respectively.
  • the scanning-side drive circuit 40 also drives the emission control lines EM1 to EMn during the non-refresh frame period Tnrf in the same manner as during the refresh frame period Tnrf (see FIG. 12, which will be described later).
  • the scanning-side drive circuit 40 drives the bias control lines BS1 to BSn so that they are sequentially selected in both the refresh frame period Trf and the non-refresh frame period Tnrf in the rest drive mode. (see FIG. 12 described later). Details of this operation will be described later.
  • driving of the bias control lines BS1-BSn is stopped, and the bias control lines BS1-BSn are all maintained in a non-selected state.
  • the display device 10 has two operation modes, the normal drive mode and the pause drive mode. First, the general operation of the display device 10 in the normal drive mode will be described.
  • FIG. 2 is a timing chart for explaining the schematic operation of the display device 10 in normal drive mode.
  • the scanning-side control signal Scs supplied from the display control circuit 20 to the scanning-side driving circuit 40 includes a two-phase clock signal composed of the first and second gate clock signals CK1 and CK2.
  • the scan-side drive circuit 40 In the normal drive mode, the scan-side drive circuit 40 generates first scan signals PS(1) to PS(n) and second scan signals NS(-1), NS as shown in FIG. 2 based on the two-phase clock signals. (0), NS(1), . NS(-1) to NS(n) are applied to the second scanning signal lines NS-1 to NSn, respectively. Further, the scanning-side drive circuit 40 generates emission control signals EM(1) to EM(n) as shown in FIG.
  • the data-side drive circuit 30 Based on the data-side control signal Scd from the display control circuit 20, the data-side drive circuit 30 outputs a data signal that changes in conjunction with the first scanning signals PS(1) to PS(n) as shown in FIG. D(1) to D(m) are generated and applied to the data signal lines D1 to Dm, respectively.
  • each pixel circuit Pix(i, j) is initialized and data voltage is written. to emit light.
  • the above various signals shown in FIG. By being driven as described above, the first scanning signal lines PS1 to PSn and the second scanning signal lines NS-1 to NSn are sequentially selected in one frame period, and the pixel circuits Pix (1, 1 of the display section 11) are selected. ) to Pix(n,m)) are repeated.
  • the bias control lines BS1 to BSn are stopped from being driven and are maintained in a non-selected state (low level voltage).
  • a drive period TD consisting of such a refresh frame period (hereinafter also referred to as "RF frame period”) Trf and a plurality of non-refresh frame periods (
  • a pause period TP consisting of Tnrf (hereinafter also referred to as an "NRF frame” period) is alternately repeated.
  • the scanning side driving circuit 40 drives the first scanning signal lines PS1 to PSn and the second scanning signal lines NS-1 to NSn, and the data side driving circuit 30 drives the data signal lines D1 to
  • the driving of Dm is stopped, and the display based on the image data written in the previous driving period TD (RF frame period Trf) continues. Therefore, the rest drive mode is effective in reducing the power consumption of the display device when displaying a still image.
  • bias control lines BS1-BSn are driven so as to be sequentially selected in both RF frame period Trf and NRF frame period Tnrf in the rest drive mode.
  • the driving period TD is composed of only one RF frame period Trf, but may be composed of two or more RF frame periods Trf.
  • the input signal Sin from the outside includes an operation mode signal Sm that indicates in which operation mode the display unit 11 is to be driven, the normal drive mode or the rest drive mode.
  • This operation mode signal Sm is applied to the scanning side driving circuit 40 as part of the scanning side control signal Scs, and is also applied to the data side driving circuit 30 as part of the data side control signal Scd.
  • the scanning-side drive circuit 40 drives the first scanning signal lines PS1 to PSn and the second scanning signal lines NS-1 to NSn according to the operation mode indicated by the operation mode signal Sm, and drives the emission control lines EM1 to EMn. They are driven in the same manner (same cycle and same duty ratio) regardless of whether they are in the normal drive mode or the rest drive mode.
  • the scanning-side drive circuit 40 drives the bias control lines BS1 to BSn in the pause drive mode, and stops driving them in the normal drive mode.
  • the data side drive circuit 30 drives the data signal lines D1 to Dn according to the operation mode indicated by this operation mode signal Sm. Since the subject of the present application is not related to the normal drive mode, the operation of the display device 10 or its pixel circuit will be mainly described below in the rest drive mode (the same applies to other embodiments described later). ).
  • each pixel circuit Pix(i, j) data is written when the corresponding first and second scanning signal lines PSi, NSi are in the selected state.
  • An initializing operation is performed when the second scanning signal line NSi-2 two lines before the second scanning signal line NSi is in a selected state.
  • P-channel transistors are used as the first and second emission control transistors T5 and T6.
  • L level voltage of level
  • H level voltage of high level
  • pixel circuit in the comparative example a pixel circuit in a display device as a comparative example of the present embodiment
  • the configuration and operation of the pixel circuit 15 in the present embodiment The operation will be described in comparison with the configuration and operation of the pixel circuit in the comparative example.
  • the bias control lines BS1 to BSn are not provided in the display section of the display device as the comparative example, and therefore the scanning side drive circuit 40 does not have a function as a bias control circuit.
  • the configuration of the display device as the comparative example is the same as that of the display device according to the present embodiment except for the components related to the bias control lines BS1 to BSn. , and the description is omitted.
  • a pixel circuit corresponding to such a configuration will be described as a pixel circuit in a comparative example.
  • the inventor of the present application has confirmed that even if such a configuration is adopted, flicker cannot necessarily be suppressed in the entire area of the display image, and flicker can still be visually recognized. Therefore, hereinafter, the configuration and operation of the pixel circuit in the comparative example will be described while referring to the mechanism that causes this problem.
  • the transistors T1, T2, and T7 are N-type transistors (more specifically, N-type IGZO-TFTs).
  • the transistors T3 to T6 are P-type transistors (more specifically, P-type LTPS-TFTs).
  • the data holding capacitor Cst is a capacitive element having two electrodes consisting of a first electrode and a second electrode. In the pixel circuit 15, the transistors T1 to T3 and T5 to T7 other than the driving transistor T4 function as switching elements.
  • a corresponding first scanning signal line hereinafter also referred to as a "corresponding first scanning signal line” in the description focused on the pixel circuit) PSi, and a corresponding second scanning signal line.
  • corresponding second scanning signal line in the description focused on the pixel circuit
  • the second scanning signal line two lines before the corresponding second scanning signal line NSi second scanning signal lines NS-1 to the scanning signal line two lines before NSn in the scanning order
  • the i-2-th second scanning signal line hereinafter also referred to simply as the "preceding second scanning signal line” in the description focused on the pixel circuit) NSi-2
  • Corresponding light emission control line hereinafter also referred to as “corresponding light emission control line” in the description focusing on the pixel circuit) EMi
  • corresponding data signal line hereinafter also referred to as "corresponding data signal line” in the description focusing on the pixel circuit
  • the gate terminal as the control terminal of the driving transistor T4 is connected to the high-level power supply line ELVDD via the data holding capacitor Cst. It is connected to the initialization voltage line Vini through the first initialization transistor T1.
  • a source terminal as a first conductive terminal of the drive transistor T4 is connected to the high-level power supply line ELVDD through the first light emission control transistor T5, and is connected to the corresponding data signal line Dj through the data write control transistor T3.
  • a drain terminal as a second conductive terminal of the driving transistor T4 is connected to an anode electrode as a first terminal of the organic EL element OL via the second emission control transistor T6, and is connected to the driving transistor T4 via the threshold compensating transistor T2. It is connected to the gate terminal of transistor T4.
  • the anode electrode of the organic EL element OL is connected to the initialization voltage line Vini through the second initialization transistor T7, and the cathode electrode as the second terminal of the organic EL element OL is connected to the low level power supply line ELVSS.
  • the gate terminal of the data write control transistor T3 is connected to the first scanning signal line PSi
  • the gate terminal of the threshold compensating transistor T2 is connected to the second scanning signal line NSi
  • the gate terminal of the first initialization transistor T1 is connected to the preceding second scanning signal line. NSi-2, respectively.
  • Gate terminals of the first emission control transistor T5, the second emission control transistor T5, and the second initialization transistor T7 are all connected to the corresponding emission control line EMi.
  • FIG. 4 is a timing chart for explaining the operation of the pixel circuit Pix(i,j) during the non-light emitting period included in each frame period.
  • times t1 to t8 are included in the RF frame period Trf that constitutes the drive period TD
  • the drive period TD is switched to the pause period TP at time t9
  • times t10 to t12 are the first frames in the pause period TP. It is included in the NRF frame period Tnrf.
  • a light emission control signal (hereinafter referred to as a “corresponding light emission control signal”) EM(i) supplied to the pixel circuit Pix(i,j) of FIG. 3 via a corresponding light emission control line EMi changes from L level to H level at time t1.
  • the P-type first and second emission control transistors T5 and T6 change from the ON state to the OFF state, and maintain the OFF state while the emission control signal EM(i) is at H level. Therefore, during the period t1 to t8 when the light emission control signal EM(i) is at H level, no current flows through the organic EL element OL and the pixel circuit Pix(i,j) is in the off state.
  • the N-type second initialization transistor T7 is turned on, thereby initializing the voltage Va of the anode electrode of the organic EL element OL (hereinafter referred to as "anode voltage").
  • anode voltage Such initialization of the anode voltage Va cuts off the influence of the past display history and suppresses deterioration of the display quality.
  • the light emission control signal EM(i) supplied to the gate terminal of the second initialization transistor T7 is driven in the idle period TP in the same manner as in the drive period TD (see FIG. 4). Therefore, the initialization of the anode voltage Va by the second initialization transistor T7 works in the direction of further suppressing flicker in the pause drive by making the extinguishing period the same length in the drive period TD and the pause period TP.
  • the second scanning signal supplied to the pixel circuit Pix(i, j) through the preceding second scanning signal line NSi-2 during the period in which the pixel circuit Pix(i, j) is in the off state that is, the non-light emitting period t1 to t8.
  • NS(i-2) (hereinafter also referred to as "preceding second scanning signal”) changes from L level to H level at time t2.
  • the N-type first initialization transistor T1 changes from the off state to the on state, and maintains the on state while the second scanning signal NS(i-2) is at H level.
  • the data holding capacitor Cst is initialized, and the gate terminal of the driving transistor T4 and the first electrode of the data holding capacitor Cst are initialized. and the voltage of the node N2 becomes the initialization voltage Vini. That is, the voltage Vg of the gate terminal of the drive transistor T4 (hereinafter referred to as "gate voltage”) becomes the initialization voltage Vini.
  • the pixel circuit 15a schematically shows the state of the pixel circuit Pix(i, j) at this time, that is, the circuit state during the initialization operation.
  • dotted line circles indicate that the transistors as switching elements therein are in the OFF state
  • dotted line rectangles indicate that the transistors as switching elements therein are in the ON state. It shows that Such a representation method is also employed in the pixel circuits 15a (WR) and 15a (EM) in FIG. 5, and further employed in FIGS. It is
  • a second scanning signal (hereinafter also referred to as a "corresponding second scanning signal”) NS(i) given by the second scanning signal NS(i) changes from L level to H level at time t4.
  • the N-type threshold compensating transistor T2 changes from an off state to an on state, and maintains the on state while the corresponding second scanning signal NS(i) is at H level. and its drain terminal are short-circuited, that is, in a diode-connected state.
  • the first scanning signal (hereinafter also referred to as the “corresponding first scanning signal”) is applied to the pixel circuit Pix(i,j) through the corresponding first scanning signal line PSi. ) PS(i) changes from H level to L level at time t5. As a result, the P-type data write control transistor T3 changes from the off state to the on state, and maintains the on state while the corresponding first scanning signal PS(i) is at L level.
  • a data signal D ( The voltage j) is applied as the data voltage Vdata to the data holding capacitor Cst via the diode-connected drive transistor T4.
  • the threshold-compensated data voltage is written to and held in the data holding capacitor Cst, and the gate voltage Vg of the driving transistor T4 becomes the voltage of the first electrode of the data holding capacitor Cst (hereinafter referred to as the voltage of the data holding capacitor Cst). (also called “holding voltage”).
  • the pixel circuit 15a (WR) schematically shows the state of the pixel circuit Pix(i, j) at this time, that is, the circuit state during the data write operation.
  • the corresponding second scanning signal NS(i) changes from H level to L level, and the threshold compensation transistor T2 is turned off.
  • the corresponding light emission control signal EM(i) changes from H level to L level, thereby turning on the first and second light emission control transistors T5 and T6, and the light emission period starts.
  • It flows through the control transistor T5, the drive transistor T4, the second emission control transistor T6, and the organic EL element OL to the low-level power supply line ELVSS.
  • the organic EL element OL emits light with luminance corresponding to the current I1.
  • the pixel circuit 15a schematically shows the state of the pixel circuit Pix(i, j) at this time, that is, the circuit state during the lighting operation.
  • the above light emission period continues until time t9 when the corresponding light emission control signal EM(i) changes from L level to H level.
  • the corresponding emission control signal EM(i) changes to H level at time t9
  • the first and second emission control transistors T5 and T6 change from ON to OFF
  • the emission control signal EM(i) changes to H level. remains off during Therefore, during the period t9 to t12 in which the light emission control signal EM(i) is at H level, no current flows through the organic EL element OL, and the pixel circuit Pix(i,j) is in the off state.
  • the drive period TD is switched to the pause period TP.
  • the driving of the second scanning signal lines NS-1 to NSn is stopped and the second scanning signals NS(-1) to NS(n) are maintained at L level.
  • the driving of the single scanning signal lines PS1 to PSn and the emission control lines EM1 to EMn continues (see FIG. 4 and FIG. 11 described later).
  • the corresponding first scanning signal PS(i) changes from the H level to the L level at time t10 during the non-light emitting period t9 to t12 within the pause period TP (NRF frame period Tnrf).
  • the data write control transistor T3 changes from the off state to the on state, and maintains the on state while the corresponding first scanning signal PS(i) is at L level.
  • the data-side drive circuit 30 is connected to the corresponding data signal line Dj.
  • the pixel circuit 15a (OB) schematically shows the state of the pixel circuit Pix(i, j) at this time, that is, the circuit state during the on-bias application operation.
  • the pixel circuit 15a (NEM) schematically shows the state of the pixel circuit Pix(i, j) during the period other than the on-bias application period t10 to t11 in the non-light emitting period t9 to t12 within the idle period TP. clearly shown.
  • the voltage stress applied to the drive transistor T4 during the non-light emission period within the drive period TD and the voltage stress applied to the driving transistor T4 during the non-light emitting period within the pause period TP can be reduced. This suppresses the difference in the threshold value Vth of the drive transistor T4 between the start time t8 of the lighting operation in the drive period TD and the start time t12 of the lighting operation in the pause period TP.
  • the difference in the waveform portion indicating the extinguishing operation (more specifically, the rising waveform that changes from the extinguished state to the lit state) in the luminance waveform becomes small, and flickering occurs during the pause driving. becomes difficult to see.
  • the gate-source voltage Vgs of the drive transistor T4 during the on-bias application period t10 to t11 within the pause period TP is the display gradation indicated by the holding voltage of the data holding capacitor Cst.
  • Dependent For example, in the circuit configuration shown in FIG. 3, the lower the display gradation, the higher the data voltage Vdata to be written. The absolute value of the inter-voltage Vgs becomes smaller.
  • the driving transistor T4 is in a diode-connected state due to the ON-state threshold compensating transistor T2.
  • the on-bias voltage Vob is a fixed value
  • flicker cannot be simultaneously suppressed in all pixel circuits 15, that is, in the entire display image area, and flicker is visible due to other factors affecting flicker. also more likely. Therefore, in the display device according to the present embodiment, an appropriate on-bias voltage is applied to each pixel circuit in accordance with the display gradation in order to reliably perform good display without visible flicker in the entire area of the display image while performing pause driving. is applied.
  • the pixel circuit according to this embodiment will be described below.
  • FIG. 7 is a circuit diagram showing the configuration of the pixel circuit 15 in this embodiment.
  • FIG. 4 is a circuit diagram showing a configuration of a j-th pixel circuit Pix(i,j) (1 ⁇ i ⁇ n, 1 ⁇ j ⁇ m);
  • This pixel circuit like the pixel circuit 15a in the comparative example shown in FIG. 1 initialization transistor T1", “threshold compensation transistor T2", “data write control transistor T3", “driving transistor T4", "first emission control transistor T5", “second emission control transistor T6", “second initialization transistor T7”) and one data holding capacitor Cst.
  • Transistors T1, T2 and T7 are N-type transistors.
  • Transistors T3-T6 are P-type transistors.
  • the N-type transistors T1, T2, and T7 are IGZO-TFTs
  • the P-type transistors T3 to T6 are LTPS-TFTs, but they are not limited to this.
  • the data holding capacitor Cst is a capacitive element having two electrodes consisting of a first electrode and a second electrode.
  • the pixel circuit 15 in this embodiment includes a bias supply circuit 151 including a bias control transistor T8 and a bias holding capacitor Cbs. is provided.
  • the transistors T1 to T3 and T5 to T8 other than the driving transistor T4 function as switching elements.
  • the second scanning signal line two lines before the corresponding second scanning signal line NSi, that is, the i-2-th second scanning signal line (preceding second scanning signal line) NSi-2, the corresponding first scanning signal line line (corresponding first scanning signal line) PSi, corresponding emission control line (corresponding emission control line) EMi, corresponding data signal line (corresponding data signal line) Dj, initialization voltage line Vini, high level power supply line ELVDD , and a low-level power supply line ELVSS are connected.
  • the bias control line BSi corresponding thereto is also connected.
  • the pixel circuit Pix(i,j) may be connected to a second scanning signal line immediately preceding the corresponding second scanning signal line NSi instead of the preceding second scanning signal line NSi-2.
  • the bias control transistor T8 and the bias holding capacitor Cbs are connected in series with each other.
  • the bias control transistor T8 has a gate terminal connected to the corresponding bias control line BSi, and a node (hereinafter referred to as "first node ) has a drain terminal connected to N1.
  • a source terminal of the drive transistor T4 is connected to the high level power supply line ELVDD via the bias control transistor T8 and the bias holding capacitor Cbs.
  • the capacitance value of the bias holding capacitor Cbs is set to a value sufficiently larger than the capacitance value of the parasitic capacitance formed between the first node N1 and other nodes.
  • FIG. 7 is a timing chart for explaining the operation of the pixel circuit Pix(i,j) during the non-light emitting period included in each frame period.
  • the first scanning signal PS(i) and the second scanning signal NS for driving the pixel circuit 15 in this embodiment are the first scanning signal PS(i) for driving the pixel circuit 15a in the comparative example
  • the 2 Scanning signals NS(i), NS(i-2), emission control signal EM(i), and data signal D(j) change in the same manner.
  • the transistors T1 to T3 and T5 to T7 as switching elements included in the pixel circuit 15 in this embodiment are similar to the transistors T1 to T3 and T5 to T7 as switching elements included in the pixel circuit 15a in the comparative example. , and similar initialization and data write operations are performed.
  • the first scanning signal PS(i) supplied to the pixel circuit 15a in the comparative example is the same as in the drive period TD (RF frame period Trf) as shown in FIG.
  • the first scanning signal PS(i) applied to the pixel circuit 15 according to the present embodiment is maintained at H level as shown in FIG.
  • the pixel circuit 15 of the present embodiment has a configuration in which the bias supply circuit 151 including the bias control transistor T8 and the bias holding capacitor Cbs is added to the pixel circuit of the comparative example (see FIG. 7). ), and a bias control signal BS(i) (hereinafter referred to as "corresponding bias control signal BS(i)”) is applied to the gate terminal of the bias control transistor T8 through a corresponding bias control line BSi.
  • corresponding bias control signal BS(i) (hereinafter referred to as "corresponding bias control signal BS(i)”
  • the bias control signal BS(i) changes from the L level to the H level at time t5, and changes from the H level to the L level at time t8. and change.
  • the bias control signal BS(i) changes during the idle period TP (NRF frame period Tnrf) as well as during the drive period TD (RF frame period Trf). That is, the bias control signal BS(i) changes from the L level to the H level at time t12 and changes from the H level to the L level at time t13 during the non-light emitting period t11 to t14 within the NRF frame period Tnrf. do.
  • FIG. 9 is a diagram showing the circuit state of the pixel circuit Pix(i, j) in this embodiment during each operation during the drive period TD.
  • the pixel circuit 15 schematically shows the state of the pixel circuit Pix(i,j) during the initialization period t2 to t3, that is, the circuit state during the initialization operation.
  • the state of the pixel circuit Pix(i, j) during the data write period t6 to t7 that is, the circuit state during the data write operation.
  • j that is, the circuit state during the lighting operation.
  • the bias control signal BS(i) is at H level during the period t5-t8 including the data write periods t6-t7, so the bias control transistor T8 is turned on during the data write periods t6-t7. is. Therefore, as can be seen from the pixel circuit 15 (WR) during the data write operation shown in FIG. 9, the voltage of the corresponding data signal line Dj (the voltage of the data signal D(j)) is is written in the data storage capacitor Cst as a data voltage via the data write control transistor T3 in the ON state and the drive transistor T4 in the diode connection state, and the data write control transistor T3 in the ON state and the bias control transistor in the ON state. It is also applied to bias holding capacitor Cbs through T8. Therefore, in the data write period t6 to t7, the voltage of the corresponding data signal line Dj at that time, that is, the data voltage Vdata is also written and held in the bias holding capacitor Cbs.
  • FIG. 10 is a diagram showing the circuit state during each operation during the pause period TP for the pixel circuit Pix(i, j) in this embodiment.
  • the pixel circuit 15 (OB) is the pixel circuit Pix(i,j ), that is, the circuit state during the on-bias application operation
  • the pixel circuit 15 (NEM) is in the state of the pixel circuit Pix ( The state of i, j) is shown schematically.
  • the data voltage is written to the data holding capacitor Cst while performing internal compensation as described above, thereby causing the voltage of the gate terminal of the driving transistor T4 (
  • the gate voltage Vg) is the value given by the above equation (1).
  • This gate voltage Vg corresponds to the holding voltage of the bias holding capacitor Cbs, and is maintained during the rest period TP immediately thereafter. Therefore, during the on-bias application period t12 to t13, a voltage corresponding to the threshold voltage Vth is applied between the gate and source of the driving transistor T4 regardless of the display grayscale indicated by the voltage held by the data holding capacitor Cst. Become. In the present embodiment, as shown in FIG.
  • the emission control signal EM(i) and the bias control signal BS(i) change in the same way regardless of whether it is the drive period TD or the pause period TP.
  • the on-bias voltage Vob as described above is applied between the gate and source of the driving transistor T4.
  • the capacitance value of the bias holding capacitor Cbs is sufficiently larger than the capacitance value of the parasitic capacitance formed between the first node N1 and other nodes, the bias holding capacitor Cbs Even if the on-bias application is repeated a plurality of times during the pause period TP for one data voltage write, the voltage held by the bias holding capacitor Cbs does not substantially change.
  • the pixel circuits Pix(1, 1) to Pix(n, m) of the display unit 11 receive the first scanning signals PS(1) to PS(1) to Pix(n, m) as shown in FIG. It is driven by PS(n), second scanning signals NS(-1) to NS(n), emission control signals EM(1) to EM(n), and data signals D(1) to D(m).
  • the pixel circuits Pix(1,1) to Pix(n,m) of the display unit 11 receive the first scanning signal PS as shown in FIG. (1) to PS(n), second scanning signals NS(-1) to NS(n), bias control signals BS(1) to BS(n), emission control signals EM(1) to EM(n), It is driven by data signals D(1)-D(m).
  • FIG. 13 shows a luminance waveform (hereinafter referred to as “comparative luminance waveform”) La(i,j) of the pixel circuit Pix(i,j) in a comparative example based on the driving method shown in FIG. 11, and
  • FIG. 3 shows a luminance waveform (hereinafter referred to as “luminance waveform of the present embodiment”) L(i, j) of the pixel circuit Pix(i, j) in the present embodiment based on the driving method.
  • FIG. 14 shows the luminance waveform La(i, j) of the comparative example and the luminance waveform L(i, j) of the present embodiment so as to make it easier to see the difference between both luminance waveforms.
  • a luminance waveform L(i, j) is indicated by a solid line
  • a luminance waveform La(i, j) of the comparative example is indicated by a dotted line.
  • the waveform (light-off waveform) indicating the light-off operation in the drive period TD (RF frame period Trf) and the idle period TP (NRF) There is a difference from the waveform (light-off waveform) indicating the light-off operation in the frame period Tnrf). More specifically, there is a difference in the rise of the luminance waveform when the pixel circuit Pix(i, j) changes from the off state to the on state due to the emission control signal EM(i) changing from the H level to the L level. .
  • the emission control signal EM(i) changing from the H level to the L level.
  • the rise of the luminance waveform in the NRF frame period Tnrf is steeper than the rise of the luminance waveform in the RF frame period Trf. It is considered that this is due to the hysteresis characteristic of the drive transistor T4.
  • Such a difference in rise of the luminance waveform between the RF frame period Trf and the NRF frame period Tnrf is due to the corresponding data signal line Dj and the data signal line Dj from the data side drive circuit 30 during the on-bias application period t10 to t11 (see FIG. 4). It can be reduced by changing the on-bias voltage Vob applied to the source terminal of the drive transistor T4 via the write control transistor T3 (the pixel circuit 15a (OB )reference).
  • the gate voltage Vg of the driving transistor T4 during the on-bias application period t10 to t11 depends on the display gradation indicated by the holding voltage of the data holding capacitor Cst. Therefore, in order to sufficiently reduce such a difference in rising waveform of the luminance waveform, the value of the on-bias voltage Vob to be applied to the pixel circuit Pix(i, j) is set to It is necessary to adjust according to the display gradation. However, such adjustment of the on-bias voltage Vob is difficult to achieve in the display device as the comparative example. Therefore, in the display device as the comparative example, the on-bias voltage Vob is usually set as a fixed value.
  • the data voltage Vdata held in the bias holding capacitor Cbs is applied through the ON-state bias control transistor T8 during the ON bias application period t12 to t13. , is applied as an on-bias voltage Vob to the source terminal of the drive transistor T4 (see the pixel circuit 15 (OB) during the on-bias application operation shown in FIG. 10).
  • the data voltage Vdata indicating the display gradation in each pixel circuit Pix(i, j) is applied to the source terminal of the drive transistor T4, thereby causing the drive transistor T4 to be energized during the on-bias application period t12 to t13.
  • the gate-source voltage Vgs does not depend on the display gradation, and has a value substantially equal to the gate-source voltage Vgs of the driving transistor T4 during the data writing period t6 to t7 in the immediately preceding driving period TD.
  • the difference in rising waveform of the luminance waveform between the RF frame period Trf and the NRF frame period Tnrf is sufficiently reduced in all pixel circuits 15 at the same time.
  • flicker is simultaneously suppressed in the entire area of the displayed image, and even if the optimum value of the on-bias voltage Vob deviates due to other factors affecting flicker, the flicker becomes less visible.
  • FIG. 1 This organic EL display device has first bias control lines BS11 to BS1n as bias write control lines and bias control lines as bias application control lines instead of the bias control lines BS1 to BSn in the display device according to the first embodiment.
  • Second bias control lines BS21 to BS2n are provided, and each pixel circuit in the present embodiment corresponds to any one of the n first bias control lines BS11 to BS1n, and n second bias control lines BS11 to BS1n. It corresponds to any one of the control lines BS21 to BS2n.
  • the scanning-side drive circuit applies first bias control signals BS1(1) to BS1(n) to first bias control lines BS11 to BS1n, respectively, and applies second bias control signals BS2(n) to second bias control lines BS21 to BS2n. 1) to BS2(n) are applied.
  • the pixel circuit in this embodiment is provided with a bias supply circuit as in the pixel circuit in the first embodiment. is different from the configuration of the bias supply circuit in .
  • Other configurations of the display device according to the present embodiment are basically the same as those of the display device according to the first embodiment. Description is omitted (see FIGS. 1 and 2).
  • FIG. 15 is a circuit diagram showing the configuration of the pixel circuit 16 in this embodiment.
  • FIG. 4 is a circuit diagram showing a configuration of a j-th pixel circuit Pix(i,j) (1 ⁇ i ⁇ n, 1 ⁇ j ⁇ m);
  • This pixel circuit 16 has the same configuration as the pixel circuit 15 (FIG. 7) in the first embodiment except for the configuration of the bias supply circuit 152 .
  • the components other than the bias supply circuit 152 are denoted by the same reference numerals as the components included in the pixel circuit 15 in the first embodiment. A detailed explanation is omitted.
  • the pixel circuit Pix(i, j) of the i-th row and the j-th column which is the pixel circuit 16 in this embodiment, includes the corresponding first scanning signal line PSi, the corresponding second scanning signal line NSi, the preceding
  • the corresponding emission control line EMi the corresponding data signal line Dj
  • the initialization voltage line Vini the high level power supply line ELVDD
  • the low level power supply line ELVSS the pixel circuit Pix(i , j) are connected to the first and second bias control lines BS1i and BS2i.
  • a bias supply circuit 152 provided in the pixel circuit 16 includes a bias application control transistor T8, a bias write control transistor T9, a bias holding capacitor Cbs1, and a voltage dividing capacitor Cbs2.
  • the bias write control transistor T9 has a gate terminal connected to a first bias control line (hereinafter referred to as "corresponding first bias control line”) BS1i corresponding to the pixel circuit Pix(i, j), and a switching element. function as
  • the bias application control transistor T8 has a gate terminal connected to a second bias control line (hereinafter referred to as a "corresponding second bias control line”) BS2i corresponding to the pixel circuit Pix(i,j). It functions as a switching element corresponding to the bias control transistor T8 in the first embodiment.
  • the source terminal of the driving transistor T4 is connected to the high-level power supply line ELVDD through the bias application control transistor T8 and the bias holding capacitor Cbs1 in this order, and is connected to the bias holding voltage through the bias write control transistor T9 and the voltage dividing capacitor Cbs2. It is connected to the connection point between the capacitor Cbs1 and the bias application control transistor T8. Also in this embodiment, the source terminal of the drive transistor T4 is connected to the corresponding data signal line Dj through the data write control transistor T3, so the corresponding data signal line Dj is connected to the bias write control transistor T9 and the voltage dividing transistor T9. Through the capacitor Cbs2, it is connected to the connection point between the bias application control transistor T8 and the bias holding capacitor Cbs1. The bias holding capacitor Cbs1 and the voltage dividing capacitor Cbs2 are connected in series to form a voltage dividing circuit.
  • FIG. 16 is a timing chart for explaining the operation of the pixel circuit Pix(i,j) during the non-light emitting period included in each frame period.
  • the first scanning signal PS(i) for driving the pixel circuit Pix(i, j) in this embodiment corresponds to the pixel circuit Pix(i, j) in the first embodiment.
  • the first scanning signal PS(i) for driving, the second scanning signals NS(i) and NS(i-2), the light emission control signal EM(i), and the data signal D(j) change in the same manner. .
  • the transistors T1 to T3 and T5 to T7 serving as switching elements included in the pixel circuit 15 of the present embodiment are replaced with the transistors T1 to T3 and T5 serving as switching elements included in the pixel circuit 15 of the first embodiment.
  • the same initialization operation and data write operation are performed.
  • the gate terminal of the bias write control transistor T9 is connected to the first bias control line BS1i through the corresponding first bias control line BS1i.
  • a signal BS1(i) (hereinafter referred to as a “corresponding first bias control signal BS1(i)”) is applied as a bias write control signal, and a corresponding second bias control line BS2i is connected to the gate terminal of the bias application control transistor T8.
  • a second bias control signal BS2(i) (hereinafter referred to as a “corresponding second bias control signal BS2(i)”) is applied as a bias application control signal via the second bias control signal BS2(i). As shown in FIG.
  • the corresponding first bias control signal BS1(i) changes from L level to H level at time t5, and changes from H level to L level at time t8. change to level.
  • the first bias control signal BS1(i) is maintained at low level during the pause period TP (NRF frame period Tnrf).
  • the corresponding second bias control signal BS2(i) is maintained at a low level during the driving period TD (RF frame period Trf), and during the non-light emitting period t11 to t14 during the pause period TP (NRF frame period Tnrf). , and changes from H level to L level at time t13.
  • FIG. 17 is a diagram showing the circuit state during each operation during the drive period TD for the pixel circuit Pix(i, j) in this embodiment.
  • the pixel circuit 16 (INI) schematically shows the state of the pixel circuit Pix(i, j) during the initialization period t2 to t3, that is, the circuit state during the initialization operation, and the pixel circuit 16 (WR) , the state of the pixel circuit Pix(i, j) during the data write period t6 to t7, that is, the circuit state during the data write operation. , j), that is, the circuit state during the lighting operation.
  • FIG. 18 is a diagram showing circuit states during each operation during the pause period TP for the pixel circuit Pix(i, j) in this embodiment.
  • the pixel circuit 16 (NEM) is the pixel circuit Pix ( i, j)
  • the pixel circuit 16 (OB) is in the on-bias application period t12-t13 in which the corresponding second bias control signal BS2(i) is at H level during the non-light-emitting period t11-t14.
  • 2 schematically shows the state of the pixel circuit Pix(i, j) of , that is, the circuit state during the on-bias application operation.
  • the data write control transistor T3, the first emission control transistor T5, and the bias The write control transistor T9 is in an off state and the bias application control transistor T8 is in an on state (see the pixel circuit 16 (OB) during the on-bias application operation shown in FIG. 18).
  • the voltage difference between the data voltage Vdata held in the voltage dividing circuit and the high-level power supply voltage ELVDD during the data writing period t6 to t7 in the immediately preceding driving period TD is transferred to the bias holding capacitor Cbs1 and the voltage dividing capacitor Cbs2.
  • a voltage obtained by dividing the voltage by V that is, a voltage Vob expressed by the following equation is applied to the source terminal of the driving transistor T4 as an on-bias voltage.
  • symbols "Cbs1" and “Cbs2” denote the capacitance values of the bias holding capacitor Cbs1 and the voltage dividing capacitor Cbs2, respectively.
  • Vob ELVDD+(Vdata ⁇ ELVDD) ⁇ Cbs2/(Cbs1+Cbs2) ⁇ ...(2)
  • the on-bias voltage Vob applied to the source terminal of the driving transistor T4 in each pixel circuit 16 can be adjusted by the capacitance ratio Cbs1/Cbs2 as shown in the above equation (2). Therefore, according to the present embodiment, by setting the capacitance ratio Cbs1/Cbs2, the same effects as those of the first embodiment can be obtained more reliably.
  • FIG. 19 is a circuit diagram showing a configuration example when the present invention is applied to a pixel circuit (see JP-A-2019-211775) using an N-type LTPS-TFT as the drive transistor T4.
  • the pixel circuit 17 shown in FIG. 19 includes one organic EL element OL as a display element, an initialization transistor T1, a threshold compensation transistor T2, a data write control transistor T3, a drive transistor T4, and a first light emission. It includes a control transistor T5, a second emission control transistor T6, and one data holding capacitor Cst, and these components T1 to T6, Cst, and OL are connected as shown in FIG.
  • the pixel circuit 17 is also provided with a bias supply circuit 151 including a bias control transistor T8 and a bias holding capacitor Cbs connected in series.
  • the source terminal of the drive transistor T4 is connected to the low level power supply line ELVSS via the bias control transistor T8 and the bias holding capacitor Cbs.
  • the first scanning signal lines PS1 to PSn and the second scanning signal lines NS-1 to NSn (FIG. 1 ), the first scanning signal lines NS11 to NS1n for transmitting the first scanning signals NS1(1) to NS1(n), respectively, and the second scanning signals NS2(1) to NS2(n), respectively.
  • Second scanning signal lines NS21 to NS2n for transmission and third scanning signal lines NS31 to NS3n for transmitting the third scanning signals NS3(1) to NS3(n), respectively, are arranged in the display section 11. It is Further, in the display device according to this modification, first emission control signals EM1(1) to EM1(n) are respectively transmitted instead of the emission control lines EM1 to EMn (see FIG. 1) in the first embodiment.
  • the display unit 11 is provided with first emission control lines EM11 to EM1n for transmitting second emission control signals EM2(1) to EM2(n), and second emission control lines EM21 to EM2n for transmitting the second emission control signals EM2(1) to EM2(n), respectively.
  • Other configurations in this modification are basically the same as those in the first embodiment.
  • a first emission control signal EM1(i), a second emission control signal EM2(i), and a bias control signal BS(i) are provided.
  • the initialization operation is performed during the periods t2 to t3 of the non-light emitting periods t1 to t8 in the drive period TD (refresh frame period), and the data is held during the periods t5 to t6.
  • Data voltage Vdata is written with internal compensation to capacitor Cst. Since the bias control transistor T8 is on during the period t4-t7, the data voltage Vdata is also written to the bias holding capacitor Cbs through the bias control transistor T8 during the period t5-t6.
  • the data write control transistor T3 is P-type, and the threshold compensation transistor T2 and the first initialization transistor T1 are N-type. It may be a conductive type. For example, these transistors T1 to T3 may all be P-type.
  • n+2 scanning signal lines serving as the first scanning signal lines PS1 to PSn and the second scanning signal lines NS-1 to NSn may be arranged in the display section 11. FIG. In this way, the number of scanning signal lines can be reduced to about half compared with the above-described embodiments, and the configurations of the display section 11 and the scanning-side driving circuit 40 are simplified.
  • the bias control transistor T8 controls the writing of the data voltage to the bias holding capacitor Cbs and also controls the voltage held in the bias holding capacitor Cbs (on-bias voltage Vob). is applied to the drive transistor T4.
  • the function of the bias control transistor T8 may be realized by two transistors. That is, instead of the bias control transistor T8, a bias write control transistor for controlling writing of the data voltage to the bias holding capacitor Cbs and application of the holding voltage (on-bias voltage Vob) in the bias holding capacitor Cbs to the drive transistor T4. may be configured to use a bias application control transistor for controlling .
  • the pixel circuit has, for example, the connection point between the bias control transistor T8 and the bias holding capacitor Cbs in the configuration shown in FIG. is configured to function as a bias application control transistor.
  • first and second bias control signals BS1(i) and BS2(i) as shown in FIG. 16 are applied to the gate terminal of the bias write control transistor and the gate terminal of the bias application control transistor, respectively. be done.
  • the pixel circuit 15 configured as shown in FIG. 7 or the pixel circuit 16 configured as shown in FIG. 15 is used. is not limited to the configurations shown in FIGS. 7 and 15, either.
  • the pixel circuits (FIGS. 7 and 15) in the above-described embodiments are configured to perform threshold compensation by diode connection of the drive transistor T4. It is also applicable to a pixel circuit without a threshold compensation function).
  • FIG. 21 shows a configuration example in which the present invention is applied to a pixel circuit that does not perform threshold compensation by diode connection of the driving transistor T4, that is, a configuration example in which a bias supply circuit is provided in a pixel circuit without a threshold compensation function.
  • the pixel circuit 18 shown in FIG. 21 includes one organic EL element OL as a display element, a data write control transistor T3, a drive transistor T4, a first emission control transistor T5, and a second emission control transistor T6. , an initialization transistor T7 and one data holding capacitor Cst, and these components T3-T7, Cst, OL are connected as shown in FIG.
  • the pixel circuit 18 is also provided with a bias supply circuit 152 including a bias application control transistor T8 and a bias holding capacitor Cbs connected in series, and a bias write control transistor T9.
  • the source terminal of the drive transistor T4 is connected to the high level power supply line ELVDD through the bias application control transistor T8 and the bias holding capacitor Cbs.
  • the data signal line Dj corresponding to the pixel circuit 18 is connected via the bias write control transistor T9 to the connection point between the bias application control transistor T8 and the bias holding capacitor Cbs.
  • the first bias control signal BS1 (see FIG. 1) is used.
  • FIG. 22 shows the pixel circuit 18 of FIG. 21 configured as described above, that is, the pixel circuit 18 corresponding to the i-th scanning signal line PSi and the j-th data signal line Dj, i-th row and j-th column pixel circuit.
  • 4 is a timing chart for explaining the operation of Pix(i, j), more specifically timing for explaining the operation of the pixel circuit Pix(i, j) during a non-light emitting period included in each frame period; Chart.
  • a first scanning signal PS(i), an emission control signal EM(i), a first bias control signal BS1(i), and a first bias control signal BS1(i) which change as shown in FIG.
  • a second bias control signal BS2(i) is provided.
  • the voltage of the data signal line Dj corresponding to the data holding capacitor Cst in the period t4 to t5 among the non-light emitting periods t1 to t8 in the drive period TD (refresh frame period) is the data.
  • the voltage of the corresponding data signal line Dj is written to the bias holding capacitor Cbs via the bias write control transistor T9.
  • the voltage of the corresponding data signal line Dj written to the bias holding capacitor Cbs is a voltage corresponding to the data voltage Vdata written to the data holding capacitor Cst, but not the same level as the data voltage Vdata.
  • This voltage is set so as to eliminate or reduce the difference between the voltage stress applied during the non-light-emitting period within the drive period TD and the voltage stress applied during the non-light-emitting period within the pause period TP for T4.
  • such a voltage is applied from the corresponding data signal line Dj to the bias holding capacitor Cbs in the pixel circuit Pix(i,j) during the period t6 to t7.
  • the data side drive circuit 30 drives the data signal lines D1 to Dm.
  • the voltage (voltage corresponding to the data voltage Vdata) held in the bias holding capacitor Cbs is biased.
  • An on-bias voltage Vob is applied to the source terminal of the drive transistor T4 via the application control transistor T8.
  • the period t5 to t8 during which the corresponding bias control signal BS(i) or the corresponding first bias control signal BS1(i) is at the H level in the drive period TD is the corresponding second Although shorter than the period t4-t9 in which the scanning signal NS(i) is at H level and longer than the data write period t6-t7 (see FIGS.
  • the corresponding bias control signal BS(i) or the corresponding th The period t5 to t8 in which the 1 bias control signal BS1(i) is at H level is set to the same length as the period t4 to t9 in which the corresponding second scanning signal NS(i) is at H level or the data write period t6 to t7. good too.
  • the on-bias application period t12 to t13 in the pause period TP is longer than the data write period t6 to t7 (FIGS. 8 and 16), but the on-bias application period t12 ⁇ t13 may have the same length as the data write period t6 to t7 or a length shorter than the data write period t6 to t7.
  • each embodiment has been described by taking the organic EL display device as an example, but the present invention is not limited to the organic EL display device, and the pause driving is performed using the display element driven by current.
  • Any display device that performs Display elements that can be used here include, for example, organic EL elements, namely organic light emitting diodes (OLED), inorganic light emitting diodes and quantum dot light emitting diodes (Quantum dot Light Emitting Diode (QLED)). be.
  • Cst Data holding capacitor
  • Cbs Bias holding capacitor
  • Cbs2 Voltage dividing capacitor
  • T1 First initialization transistor (first initialization switching element) T2 ...
  • threshold compensation transistor threshold compensation switching element T3 ... data write control transistor (data write control switching element) T4: drive transistor T5: first emission control transistor (first emission control switching element) T6 ... second emission control transistor (second emission control switching element) T7 ... second initialization transistor (second initialization switching element) T8 ... bias control transistor (bias control switching element), Bias application control transistor (bias application control switching element) T9 ... bias write control transistor (bias write control switching element) TD ... drive period TP ... pause period Trf ... refresh frame period (RF frame period) Tnrf: non-refresh frame period (NRF frame period) Vob ... On-bias voltage

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  • Computer Hardware Design (AREA)
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  • Electroluminescent Light Sources (AREA)
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