WO2022153665A1 - 表示装置 - Google Patents

表示装置 Download PDF

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Publication number
WO2022153665A1
WO2022153665A1 PCT/JP2021/042295 JP2021042295W WO2022153665A1 WO 2022153665 A1 WO2022153665 A1 WO 2022153665A1 JP 2021042295 W JP2021042295 W JP 2021042295W WO 2022153665 A1 WO2022153665 A1 WO 2022153665A1
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WO
WIPO (PCT)
Prior art keywords
substrate
insulating film
display device
opening
switching element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/042295
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
龍法 村本
謙太朗 河合
善英 大植
明紘 花田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Display Inc
Original Assignee
Japan Display Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Display Inc filed Critical Japan Display Inc
Priority to CN202180090171.6A priority Critical patent/CN116745691A/zh
Priority to DE112021006307.3T priority patent/DE112021006307T5/de
Priority to JP2022575098A priority patent/JP7472323B2/ja
Publication of WO2022153665A1 publication Critical patent/WO2022153665A1/ja
Priority to US18/349,217 priority patent/US12025899B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1334—Constructional arrangements; Manufacturing methods based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/37—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being movable elements
    • G09F9/372—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being movable elements the positions of the elements being controlled by the application of an electric field
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element

Definitions

  • An embodiment of the present invention relates to a display device.
  • a liquid crystal layer having a first translucent substrate, a second translucent substrate, a polymer-dispersed liquid crystal display enclosed between the first translucent substrate and the second translucent substrate, and a liquid crystal layer.
  • a display device including a first translucent substrate and at least one light emitting unit arranged to face at least one side surface of the second translucent substrate is described.
  • An object of the embodiment is to provide a display device capable of suppressing a decrease in reliability.
  • the display device includes a first transparent substrate, a switching element provided with an oxide semiconductor, an organic insulating film covering the switching element, a transparent electrode having a first opening penetrating to the upper surface of the organic insulating film, and the first.
  • a first substrate including an inorganic insulating film having a second opening penetrating to the upper surface in one opening and a pixel electrode electrically connected to the switching element, and a second transparent substrate are provided.
  • a second substrate facing the substrate is provided.
  • FIG. 1 is a plan view showing an example of the display device DSP of the embodiment.
  • FIG. 2 is a plan view showing a region in the vicinity of the light emitting module 100.
  • FIG. 3 is a plan view showing an example of the pixel PX.
  • FIG. 4 is a plan view showing an example of the pixel electrode PE arranged in the pixel PX shown in FIG.
  • FIG. 5 is a plan view showing an example of the first substrate SUB1 including the switching element SW shown in FIG.
  • FIG. 6 is a cross-sectional view showing an example of the first substrate SUB1 along the line AB shown in FIG.
  • FIG. 7 is a cross-sectional view showing an example of the first substrate SUB1 along the CD line shown in FIG.
  • FIG. 1 is a plan view showing an example of the display device DSP of the embodiment.
  • FIG. 2 is a plan view showing a region in the vicinity of the light emitting module 100.
  • FIG. 3 is a plan view showing an example of the pixel
  • FIG. 8 is a cross-sectional view showing an example of a display panel PNL including the first substrate SUB1 along the line EF shown in FIG.
  • FIG. 9 is a plan view showing another example of the first substrate SUB1 including the switching element SW shown in FIG.
  • FIG. 10 is a cross-sectional view showing an example of a display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • FIG. 11 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • FIG. 12 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • FIG. 12 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line GH shown in FIG. FIG.
  • FIG. 13 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • FIG. 14 is a cross-sectional view of the display device DSP.
  • FIG. 15 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line EF shown in FIG.
  • a liquid crystal display device will be described as an example of the display device.
  • the main configuration disclosed in the present embodiment is not limited to an electroluminescence display device and a display device provided with a self-luminous light emitting element such as an organic electroluminescence (EL) element, a micro LED, or a mini LED. It can also be applied to various electronic devices such as capacitive sensors and optical sensors.
  • EL organic electroluminescence
  • FIG. 1 is a plan view showing an example of the display device DSP of the present embodiment.
  • the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees.
  • the first direction X and the second direction Y correspond to the directions parallel to the main surface of the substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP.
  • viewing the XY plane defined by the first direction X and the second direction Y is referred to as a plan view.
  • the display device DSP includes a display panel PNL, a wiring board 1, an IC chip 2, and a light emitting module 100.
  • the display panel PNL includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LC including a polymer-dispersed liquid crystal, and a seal SE.
  • the first substrate SUB1 and the second substrate SUB2 are formed in a flat plate shape along an XY plane.
  • the first substrate SUB1 and the second substrate SUB2 are superimposed in a plan view.
  • the region on which the first substrate SUB1 and the second substrate SUB2 overlap includes a display region DA for displaying an image.
  • the first substrate SUB1 includes a first transparent substrate 10
  • the second substrate SUB2 includes a second transparent substrate 20.
  • the first transparent substrate 10 has side surfaces 101 and 102 along the first direction X and side surfaces 103 and 104 along the second direction Y.
  • the second transparent substrate 20 has side surfaces 201 and 202 along the first direction X and side surfaces 203 and 204 along the second direction Y.
  • the side surfaces 102 and 202, the side surfaces 103 and 203, and the side surfaces 104 and 204 are superposed, respectively, but they are not necessarily superposed.
  • the side surface 201 does not overlap the side surface 101 and is located between the side surface 101 and the display area DA.
  • the first substrate SUB1 has an extension portion Ex between the side surface 101 and the side surface 201. That is, the extension portion Ex corresponds to a portion of the first substrate SUB1 that extends in the second direction Y from the portion that overlaps with the second substrate SUB2, and does not overlap with the second substrate SUB2.
  • the display panel PNL is formed in a rectangular shape extending in the first direction X. That is, the side surfaces 101 and 102 and the side surfaces 201 and 202 are side surfaces along the long side of the display panel PNL, and the side surfaces 103 and 104 and the side surfaces 203 and 204 are along the short side of the display panel PNL.
  • the display panel PNL may be formed in a rectangular shape extending in the second direction Y, in a square shape, in another polygonal shape, or in another shape such as a circular shape or an elliptical shape. It may be formed into a shape.
  • the wiring board 1 and the IC chip 2 are mounted on the extension portion Ex.
  • the wiring board 1 is, for example, a bendable flexible printed circuit board.
  • the IC chip 2 has a built-in display driver or the like that outputs a signal necessary for displaying an image, for example.
  • the IC chip 2 may be mounted on the wiring board 1.
  • a plurality of wiring boards 1 arranged in the first direction X are mounted on the display panel PNL, but a single wiring board 1 extending in the first direction X is mounted. May be good.
  • a plurality of IC chips 2 arranged in the first direction X are mounted on the display panel PNL, a single IC chip 2 extending in the first direction X may be mounted.
  • the light emitting module 100 is superposed on the extending portion Ex and arranged along the side surface 201 of the second transparent substrate 20 in a plan view.
  • the seal SE adheres the first substrate SUB1 and the second substrate SUB2. Further, the seal SE is formed in a rectangular frame shape, and surrounds the liquid crystal layer LC between the first substrate SUB1 and the second substrate SUB2.
  • the liquid crystal layer LC is held between the first substrate SUB1 and the second substrate SUB2. Such a liquid crystal layer LC is arranged over a region (including a display region DA) surrounded by the seal SE in a plan view.
  • the liquid crystal layer LC contains a polymer 31 and a liquid crystal molecule 32.
  • the polymer 31 is a liquid crystal polymer.
  • the polymer 31 is formed in a streak extending along the first direction X and is aligned in the second direction Y.
  • the liquid crystal molecules 32 are dispersed in the gaps of the polymer 31, and the long axis thereof is oriented along the first direction X.
  • Each of the polymer 31 and the liquid crystal molecule 32 has optical anisotropy or refractive index anisotropy.
  • the responsiveness of the polymer 31 to the electric field is lower than the responsiveness of the liquid crystal molecule 32 to the electric field.
  • the orientation direction of the polymer 31 hardly changes regardless of the presence or absence of an electric field.
  • the orientation direction of the liquid crystal molecules 32 changes according to the electric field when a voltage higher than the threshold value is applied to the liquid crystal layer LC.
  • the optical axes of the polymer 31 and the liquid crystal molecules 32 are substantially parallel to each other, and the light incident on the liquid crystal layer LC almost all of the liquid crystal layer LC.
  • Transparent transparent state.
  • the orientation direction of the liquid crystal molecules 32 changes, and the optical axes of the polymer 31 and the liquid crystal molecules 32 intersect with each other. Therefore, the light incident on the liquid crystal layer LC is scattered in the liquid crystal layer LC (scattered state).
  • FIG. 2 is a plan view showing a region in the vicinity of the light emitting module 100.
  • the light emitting module 100 includes a plurality of light emitting elements 110 and a light guide body 120.
  • the plurality of light emitting elements 110 are arranged along the first direction X.
  • the light guide body 120 is formed in the shape of an extended rod in the first direction X.
  • the light guide body 120 is located between the seal SE and the light emitting element 110.
  • the display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. These pixels PX are shown by dotted lines in the figure. Further, each of the pixel PX includes a pixel electrode PE shown by a solid square in the figure.
  • each pixel PX includes a switching element SW.
  • the switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line G and the signal line S.
  • the scanning line G is electrically connected to the switching element SW in each of the pixels PX arranged in the first direction X.
  • the signal line S is electrically connected to the switching element SW in each of the pixels PX arranged in the second direction Y.
  • the pixel electrode PE is electrically connected to the switching element SW.
  • the common electrode CE and the feeder line CL are arranged over the display area DA and its peripheral area.
  • a predetermined voltage Vcom is applied to the common electrode CE.
  • a voltage having the same potential as the common electrode CE is applied to the feeder line CL.
  • Each of the pixel electrode PEs faces the common electrode CE in the third direction Z.
  • the liquid crystal layer LC (particularly, the liquid crystal molecules 32) is driven by an electric field generated between the pixel electrode PE and the common electrode CE.
  • the capacitance CS is formed, for example, between the feeder line CL and the pixel electrode PE.
  • the scanning line G, the signal line S, the feeder line CL, the switching element SW, and the pixel electrode PE are provided on the first substrate SUB1, and the common electrode CE is provided on the second substrate SUB2. ..
  • FIG. 3 is a plan view showing an example of the pixel PX. Here, only a part of the configurations included in the first substrate SUB1 are shown.
  • the first substrate SUB1 includes a plurality of scanning lines G, a plurality of signal lines S, a switching element SW, a feeder line CL, a metal wire ML, an insulating film IL, and a connection electrode CN1.
  • the plurality of scanning lines G each extend in the first direction X.
  • Each of the plurality of signal lines S extends in the second direction Y and intersects the plurality of scanning lines G.
  • the pixel PX corresponds to a region defined by two adjacent scanning lines G and two adjacent signal lines S.
  • the switching element SW is arranged at the intersection of the scanning line G and the signal line S.
  • the insulating film IL is formed in a grid pattern that defines the opening OP in each pixel PX.
  • the insulating film IL is, for example, an organic insulating film.
  • the insulating film IL is superimposed on the scanning line G, the signal line S, and the switching element SW, respectively.
  • the drain electrode DE of the switching element SW extends to the opening OP.
  • the connection electrode CN1 is formed in an island shape, is located at the opening OP, and is electrically connected to one end of the drain electrode DE.
  • the feeder line CL is arranged on the insulating film IL and is formed in a grid pattern surrounding the pixel PX.
  • the planar shape of the feeder CL is substantially the same as the planar shape of the insulating film IL.
  • the feeder line CL is separated from the connection electrode CN1.
  • the opening OPC of the feeder line CL is superimposed on the opening OP of the insulating film IL.
  • the metal wire ML is arranged on the feeder line CL and is formed in a grid pattern surrounding the pixel PX.
  • the metal wire ML is formed so as to have a width smaller than that of the feeder line CL, and does not protrude from the feeder line CL in a plan view.
  • These feeder lines CL and metal wire ML are superimposed on the scanning line G, the signal line S, and the switching element SW, respectively.
  • FIG. 4 is a plan view showing an example of the pixel electrode PE arranged in the pixel PX shown in FIG.
  • the pixel electrode PE indicated by the alternate long and short dash line is superimposed on the opening OPC of the feeder line CL. Further, the peripheral portion of the pixel electrode PE is superimposed on the feeder line CL.
  • An insulating film is interposed between the pixel electrode PE and the feeder line CL, and the capacitance CS shown in FIG. 2 is formed between the peripheral edge of the pixel electrode PE and the feeder line CL.
  • connection electrode CN1 is located at the opening OPC.
  • the pixel electrode PE is superimposed on the connection electrode CN1 in the opening OPC.
  • a contact hole CH1 is formed in the insulating film interposed between the pixel electrode PE and the connection electrode CN1.
  • the pixel electrode PE is in contact with the connection electrode CN1 in the contact hole CH1. As a result, the pixel electrode PE is electrically connected to the switching element SW.
  • FIG. 4 shows a light-shielding layer BM provided on the second substrate SUB2 with a dotted line.
  • the light-shielding layer BM is formed in a grid pattern and is superimposed on the feeder line CL, the switching element SW, a part of the connection electrode CN1 and the like in a plan view.
  • the light-shielding layer BM is also superimposed on the scanning line G, the signal line S, and the metal line ML shown in FIG.
  • the light-shielding layer BM has an opening AP that is superimposed on the pixel electrode PE in a plan view.
  • FIG. 5 is a plan view showing an example of the first substrate SUB1 including the switching element SW shown in FIG.
  • the switching element SW includes a semiconductor SC, a gate electrode (or a first gate electrode) GE integrated with a scanning line G, a source electrode SO integrated with a signal line S, a drain electrode DE, and an auxiliary gate electrode (or a second gate electrode).
  • the gate electrode) AG is provided.
  • the semiconductor SC is an oxide semiconductor.
  • the semiconductor SC may be a silicon-based semiconductor such as polycrystalline silicon or amorphous silicon.
  • the three semiconductor SCs are superimposed on the gate electrode GE and are arranged along the second direction Y at intervals.
  • the auxiliary gate electrode AG is superimposed on the gate electrode GE and the semiconductor SC.
  • the semiconductor SC is located between the gate electrode GE and the auxiliary gate electrode AG.
  • the auxiliary gate electrode AG is further superimposed on the scanning line G.
  • a connection electrode CN2 is interposed between the scanning line G and the auxiliary gate electrode AG.
  • a contact hole CH21 is formed in the insulating film interposed between the scanning line G and the connection electrode CN2.
  • the connection electrode CN2 is in contact with the scanning line G in the contact hole CH21.
  • a contact hole CH22 is formed in the insulating film interposed between the connection electrode CN2 and the auxiliary gate electrode AG.
  • the auxiliary gate electrode AG is in contact with the connection electrode CN2 in the contact hole CH22.
  • the auxiliary gate electrode AG is electrically connected to the scanning line G in the same manner as the gate electrode GE. That is, the gate electrode GE and the auxiliary gate electrode AG have the same potential as the scanning line G.
  • the source electrode SO and the drain electrode DE extend along the second direction Y, respectively, and are lined up along the first direction X at intervals.
  • the source electrode SO is in contact with one end side of each of the semiconductor SCs.
  • the drain electrode DE is in contact with the other end side of each of the semiconductor SCs.
  • connection electrode CN3 One end of the drain electrode DE is superimposed on the connection electrode CN3.
  • a contact hole CH3 is formed in the insulating film interposed between the drain electrode DE and the connection electrode CN3.
  • the drain electrode DE is in contact with the connection electrode CN3 in the contact hole CH3.
  • the connecting electrode CN1 indicated by the alternate long and short dash line is in contact with the connecting electrode CN3.
  • the connection electrode CN1 is electrically connected to the switching element SW, and is electrically connected to the pixel electrode PE shown in FIG. 4 in the contact hole CH1.
  • the feeder line CL indicated by the alternate long and short dash line is superimposed on the gate electrode GE and the auxiliary gate electrode AG of the switching element SW.
  • the feeder line CL has a first opening (through hole) AP11.
  • the insulating film arranged on the feeder line CL has a second opening (through hole) AP12.
  • the edge E11 defining the first opening AP11 and the edge E12 defining the second opening AP12 are both formed in a quadrangular shape.
  • the edge E12 is located inside the edge E11 without intersecting the edge E11.
  • the edges E11 and E12 are not limited to the illustrated examples, and may be formed into other polygonal shapes, circular shapes, elliptical shapes, or the like. Further, the edge E11 and the edge E12 may intersect each other, or the edge E11 may be located inside the edge E12.
  • the metal wire ML indicated by the alternate long and short dash line is superimposed on the feeder line CL and also superimposed on a part of the switching element SW.
  • the spacer SP is superimposed on the switching element SW, the feeder line CL, and the metal wire ML.
  • the metal wire ML and the spacer SP are not superimposed on the first opening AP11 and the second opening AP12.
  • FIG. 6 is a cross-sectional view showing an example of the first substrate SUB1 along the line AB shown in FIG.
  • the first substrate SUB1 includes the first transparent substrate 10, the insulating films 11 to 13, the insulating film IL, the switching element SW, the feeder line CL, the metal wire ML, the pixel electrode PE, the alignment film AL1, and the like. It has.
  • the gate electrode GE integrated with the scanning line G is arranged on the first transparent substrate 10.
  • the insulating film 11 covers the first transparent substrate 10 and the gate electrode GE.
  • the semiconductor SC is arranged on the insulating film 11 and is located directly above the gate electrode GE.
  • the source electrode SO and the drain electrode DE integrated with the signal line S are arranged on the insulating film 11 and are in contact with the semiconductor SC, respectively. These source electrode SO and drain electrode DE are made of the same metal material.
  • the insulating film 12 covers the insulating film 11, the source electrode SO, and the drain electrode DE. Further, the insulating film 12 is in contact with the semiconductor SC between the source electrode SO and the drain electrode DE.
  • the auxiliary gate electrode AG is arranged on the insulating film 12, and is located directly above the gate electrode GE and the semiconductor SC.
  • the connection electrode CN3 is arranged on the insulating film 12 and is in contact with the drain electrode DE in the contact hole CH3 formed in the insulating film 12.
  • the auxiliary gate electrode AG and the connection electrode CN3 are made of the same metal material.
  • the insulating film IL covers the auxiliary gate electrode AG.
  • the connection electrode CN3 is located at the opening OP and is exposed from the insulating film IL.
  • the feeder line CL is arranged on the insulating film IL.
  • the connection electrode CN1 is separated from the feeding line CL and is arranged on the insulating film 12 in the opening OP of the insulating film IL or the opening OPC of the feeding line CL. That is, these feeder lines CL and the connection electrode CN1 are substantially located in the same layer, and are collectively formed by using the same material.
  • the connection electrode CN1 is arranged on the connection electrode CN3 and is in contact with the connection electrode CN3.
  • the metal wire ML is arranged on the feeder line CL and is in contact with the feeder line CL.
  • the insulating film 13 covers the feeder line CL, the metal wire ML, and the connection electrode CN1. Further, the insulating film 13 is in contact with the insulating film 12 between the feeder line CL and the connection electrode CN1.
  • the pixel electrode PE is arranged on the insulating film 13 and is in contact with the connection electrode CN1 in the contact hole CH1 formed in the insulating film 13.
  • the peripheral edge of the pixel electrode PE faces the feeder line CL and the metal wire ML via the insulating film 13.
  • the alignment film AL1 covers the pixel electrode PE and the insulating film 13.
  • the insulating films 11 to 13 are transparent inorganic insulating films such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the insulating film IL is a transparent organic insulating film such as an acrylic resin.
  • the feeder line CL, the connection electrode CN1, and the pixel electrode PE are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • FIG. 7 is a cross-sectional view showing an example of the first substrate SUB1 along the CD line shown in FIG.
  • the connection electrode CN2 is arranged on the insulating film 11 and is in contact with the scanning line G in the contact hole CH21 formed in the insulating film 11.
  • the connection electrode CN2 is made of the same metal material as the source electrode SO and the drain electrode DE.
  • the insulating film 12 covers the insulating film 11, the connection electrode CN2, the source electrode SO, and the drain electrode DE.
  • the auxiliary gate electrode AG is arranged on the insulating film 12 and is in contact with the connection electrode CN2 in the contact hole CH 22 formed in the insulating film 12.
  • FIG. 8 is a cross-sectional view showing an example of a display panel PNL including the first substrate SUB1 along the line EF shown in FIG.
  • the switching element SW is covered with the insulating film IL which is an organic insulating film.
  • the feeder line CL which is a transparent electrode, is in contact with the upper surface ILT of the insulating film IL.
  • the first opening AP11 of the feeder line CL penetrates to the upper surface ILT.
  • the insulating film 13 which is an inorganic insulating film is in contact with the feeder line CL, and is in contact with the upper surface ILT at the first opening AP11.
  • the second opening AP12 of the insulating film 13 penetrates to the upper surface ILT in the first opening AP11.
  • the upper surface ILT is exposed from the feeder line CL (transparent electrode) and the insulating film 13 (inorganic insulating film).
  • the alignment film AL1 is in contact with the upper surface ILT at the second opening AP12.
  • the second substrate SUB2 includes a second transparent substrate 20, a light-shielding layer BM, a common electrode CE, and an alignment film AL2.
  • the spacer SP is arranged between the first transparent substrate 10 and the second transparent substrate 20. In the example shown in FIG. 8, the spacer SP is provided on the second substrate SUB2.
  • the light-shielding layer BM faces the first opening AP11, the second opening AP12, the switching element SW, and the like via the liquid crystal layer LC.
  • the light-shielding layer BM also faces the spacer SP.
  • the common electrode CE faces the pixel electrode PE via the liquid crystal layer LC.
  • the alignment film AL2 covers the common electrode CE and the spacer SP.
  • the spacer SP corresponds to a main spacer for forming a cell gap in contact with the first substrate SUB1 (or the alignment film AL1).
  • the spacer SP may be a sub-spacer separated from the first substrate SUB1 (or the alignment film AL1).
  • the alignment film AL2 may be interposed between the spacer SP and the alignment film AL1.
  • a transparent organic insulating film may be interposed between the light-shielding layer BM and the common electrode CE, or between the common electrode CE and the alignment film AL2.
  • the upper surface ILT of a part of the insulating film IL which is an organic insulating film is a region where the first opening AP11 of the feeder line CL and the second opening AP12 of the insulating film 13 overlap. It is exposed in.
  • Such a region can serve as an outlet for moisture contained in the insulating film IL. That is, in the process of manufacturing the first substrate SUB1, the water contained in the insulating film IL is discharged to the outside from the discharge port at a stage before the alignment film AL1 is formed. As a result, the water content of the insulating film IL is reduced, and the performance deterioration due to the water content of the switching element SW covered with the insulating film IL is suppressed. Therefore, it is possible to suppress a decrease in reliability due to a deterioration in the performance of the switching element.
  • FIG. 9 is a plan view showing another example of the first substrate SUB1 including the switching element SW shown in FIG.
  • the first opening AP11 and the second opening AP12 are superimposed on the switching element SW, and the spacer SP is superimposed on the first opening AP11 and the second opening AP12, as compared with the example shown in FIG. It is different in that it is.
  • the edge E12 defining the second opening AP12 is located inside the edge E11 without intersecting the edge E11 defining the first opening AP11.
  • the spacer SP is located inside the edge E12 and is superimposed on the switching element SW or the gate electrode GE and the auxiliary gate electrode AG.
  • FIG. 10 is a cross-sectional view showing an example of a display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • the first opening AP11 of the feeder line CL and the second opening AP12 of the insulating film 13 are formed directly above the switching element SW or directly above the gate electrode GE and the auxiliary gate electrode AG.
  • the first opening AP11 penetrates to the upper surface ILT.
  • the second opening AP12 penetrates to the upper surface ILT in the first opening AP11. That is, in the second opening AP12, the upper surface ILT is exposed from the feeder line CL (transparent electrode) and the insulating film 13 (inorganic insulating film).
  • the alignment film AL1 is in contact with the upper surface ILT at the second opening AP12.
  • the spacer SP is located directly above the switching element SW or the gate electrode GE and the auxiliary gate electrode AG.
  • the spacer SP is a main spacer in contact with the first substrate SUB1 (or alignment film AL1), but may be a subspacer separated from the first substrate SUB1 (or alignment film AL1).
  • the light-shielding layer BM faces the first opening AP11, the second opening AP12, and the spacer SP.
  • the spacer SP is arranged so as to overlap most of the gate electrode GE and the auxiliary gate electrode AG to which a relatively high voltage is applied. Therefore, an undesired leakage electric field from the gate electrode GE is less likely to be applied to the liquid crystal layer LC. Therefore, it is possible to suppress the misalignment of the liquid crystal molecules 32 caused by the electric field leaking from the gate electrode GE.
  • impurities when ionic impurities are generated in the liquid crystal layer LC, impurities can be collected around the spacer SP that does not contribute to the display by utilizing the electric field leaking from the gate electrode GE.
  • FIG. 11 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • the example shown in FIG. 11 is different from the example shown in FIG. 10 in that the island-shaped pedestal 15 superimposed on the spacer SP is arranged in the second opening AP12.
  • the pedestal 15 is in contact with the upper surface ILT and is separated from the feeder line CL and the insulating film 13.
  • the alignment film AL1 is in contact with the upper surface ILT between the pedestal 15 and the insulating film 13.
  • Such a pedestal 15 is the same as the thin film formed of the transparent conductive material which is the same material as the feeding line CL, the thin film formed of the transparent insulating material which is the same material as the insulating film 13, and the pixel electrode PE. It has at least one thin film formed of a transparent conductive material that is a material. That is, the pedestal 15 may be a single-layered body of thin films or a laminated body of a plurality of thin films.
  • the upper surface ILT is exposed between the pedestal 15 and the insulating film 13 before the alignment film AL1 is formed, and can serve as a moisture discharge port. Therefore, the same effect as described above can be obtained.
  • the region of the alignment film AL1 that can be damaged is limited to the region directly above the pedestal 15, and this region is the light-shielding layer BM. Is shaded by. Therefore, deterioration of display quality can be suppressed.
  • FIG. 12 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • the example shown in FIG. 12 is different from the above example in that the insulating film IL has a recess CC in the second opening AP12.
  • Such a recess CC is formed, for example, by etching when the second opening AP12 is formed in the insulating film 13 under the condition that not only the insulating film 13 is removed but also the surface of the insulating film IL is removed. ..
  • the alignment film AL1 is in contact with the upper surface ILT of the recess CC at the second opening AP12.
  • the spacer SP is a sub-spacer SS separated from the first substrate SUB1 (or alignment film AL1), but may be a main spacer in contact with the first substrate SUB1 (or alignment film AL1).
  • the upper surface ILT is exposed before the alignment film AL1 is formed, and it can serve as a water discharge port.
  • the surface area of the upper surface ILT that can serve as a discharge port is increased as compared with the case where the insulating film IL does not have the recess CC, and the water release is promoted.
  • FIG. 13 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line GH shown in FIG.
  • the example shown in FIG. 13 is different from the example shown in FIG. 12 in that the island-shaped pedestal 15 superimposed on the spacer SP is arranged in the second opening AP12.
  • the pedestal 15 is in contact with the upper surface ILT in the recess CC and is separated from the feeder line CL and the insulating film 13.
  • the alignment film AL1 is in contact with the upper surface ILT between the pedestal 15 and the insulating film 13.
  • the pedestal 15 has at least one of a thin film formed of a transparent conductive material and a thin film formed of a transparent insulating material, as described with reference to FIG.
  • the spacer SP is a main spacer MS in contact with the first substrate SUB1 (or alignment film AL1), but may be a subspacer separated from the first substrate SUB1 (or alignment film AL1).
  • the spacer SP can also be used in the main spacer MS depending on the presence or absence of the pedestal 15. It can be a subspacer SS.
  • FIG. 14 is a cross-sectional view of the display device DSP. As for the display panel PNL, only the main part is shown in a simplified manner.
  • the display panel PNL includes a third transparent substrate 30 in addition to the first substrate SUB1 and the second substrate SUB2.
  • the inner surface 30A of the third transparent substrate 30 faces the outer surface 20B of the second transparent substrate 20 in the third direction Z.
  • the adhesive layer AD adheres the second transparent substrate 20 and the third transparent substrate 30.
  • the third transparent substrate 30 is, for example, a glass substrate, but may be an insulating substrate such as a plastic substrate.
  • the third transparent substrate 30 has a refractive index equivalent to that of the first transparent substrate 10 and the second transparent substrate 20.
  • the adhesive layer AD has a refractive index equivalent to that of each of the second transparent substrate 20 and the third transparent substrate 30.
  • the side surface 301 of the third transparent substrate 30 is located directly above the side surface 201 of the second transparent substrate 20.
  • the light emitting element 110 of the light emitting module 100 is electrically connected to the wiring board F and is provided between the first board SUB1 and the wiring board F in the third direction Z.
  • the light guide body 120 is provided between the light emitting element 110 and the side surface 201 and between the light emitting element 110 and the side surface 301 in the second direction Y.
  • the light guide body 120 is adhered to the wiring board F by the adhesive layer AD1 and is adhered to the first substrate SUB1 by the adhesive layer AD2.
  • the light emitting element 110 emits light L1 toward the light guide body 120.
  • the light L1 emitted from the light emitting element 110 propagates along the direction of the arrow indicating the second direction Y, passes through the light guide body 120, is incident on the second transparent substrate 20 from the side surface 201, and is incident on the second transparent substrate 20 from the side surface 301. 3 It is incident on the transparent substrate 30.
  • the light L1 incident on the second transparent substrate 20 and the third transparent substrate 30 propagates inside the display panel PNL while being repeatedly reflected.
  • the light L1 incident on the liquid crystal layer LC to which no voltage is applied passes through the liquid crystal layer LC with almost no scattering. Further, the light L1 incident on the liquid crystal layer LC to which the voltage is applied is scattered by the liquid crystal layer LC.
  • Such a display device DSP can be observed from the outer surface 10A side of the first transparent substrate 10 and also from the outer surface 30B side of the third transparent substrate 30. Further, the background of the display device DSP can be observed via the display device DSP regardless of whether the display device DSP is observed from the outer surface 10A side or the outer surface 30B side.
  • FIG. 15 is a cross-sectional view showing another example of the display panel PNL including the first substrate SUB1 along the line EF shown in FIG.
  • the example shown in FIG. 15 is different from the example shown in FIG. 8 in that the alignment film AL1 is omitted.
  • the region where the first opening AP11 and the second opening AP12 overlap can serve as a discharge port for the moisture contained in the insulating film IL. Therefore, the amount of water in the insulating film IL covering the switching element SW is reduced, and deterioration of the performance of the switching element SW and deterioration of reliability can be suppressed.
  • DSP ... Display device PNL ... Display panel DA ... Display area PX ... Pixel SUB1 ... First substrate 10 ... First transparent substrate PE ... Pixel electrode SW ... Switching element SC ... Semiconductor (oxide semiconductor) GE ... Gate electrode G ... Scanning line S ... Signal line IL ... Insulating film (organic insulating film) ILT ... Top surface CC ... Recessed OP ... Opening CL ... Feeding line (transparent electrode) AP11 ... First opening 13 ... Insulating film (inorganic insulating film) AP12 ... Second opening 15 ... Pedestal AL1 ... Alignment film SP ... Spacer SUB2 ... Second substrate 20 ... Second transparent substrate LC ... Liquid crystal layer 30 ... Third transparent substrate 100 ... Light emitting module 110 ... Light emitting element

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Dispersion Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
PCT/JP2021/042295 2021-01-12 2021-11-17 表示装置 Ceased WO2022153665A1 (ja)

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DE112021006307.3T DE112021006307T5 (de) 2021-01-12 2021-11-17 Anzeigevorrichtung
JP2022575098A JP7472323B2 (ja) 2021-01-12 2021-11-17 表示装置
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US12481191B2 (en) 2023-08-24 2025-11-25 Japan Display Inc. Display device

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CN116745691A (zh) 2023-09-12
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JP7472323B2 (ja) 2024-04-22
DE112021006307T5 (de) 2023-09-21

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