WO2022152312A1 - 用于电子束曝光的芯片内嵌复合物及其制备方法与应用 - Google Patents

用于电子束曝光的芯片内嵌复合物及其制备方法与应用 Download PDF

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WO2022152312A1
WO2022152312A1 PCT/CN2022/072513 CN2022072513W WO2022152312A1 WO 2022152312 A1 WO2022152312 A1 WO 2022152312A1 CN 2022072513 W CN2022072513 W CN 2022072513W WO 2022152312 A1 WO2022152312 A1 WO 2022152312A1
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chip
composite
substrate
electron beam
beam exposure
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PCT/CN2022/072513
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English (en)
French (fr)
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张昭宇
黄要然
刘歌行
李浩川
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香港中文大学（深圳）
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Priority to US18/002,573 priority Critical patent/US20230343605A1/en
Publication of WO2022152312A1 publication Critical patent/WO2022152312A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Definitions

  • the present application belongs to the technical field of the field of semiconductor chip manufacturing, and in particular relates to a chip embedded compound for electron beam exposure and a preparation method and application thereof.
  • EBL electron beam exposure
  • the use of electron beam exposure to make the pattern of optoelectronic semiconductor chips needs to make full use of the corners of the entire small chip as much as possible, and lithography various design patterns on the chip to improve the utilization rate of the wafer; however, electron beam exposure equipment There are strict requirements on whether the surface of the photoresist is a plane.
  • the purpose of this application is to provide a chip embedded composite for electron beam exposure and its preparation method and application, which aims to solve the problem that small chips in the prior art cannot be directly spun and used in the fixing process of electron beam exposure.
  • the lithography area creates the problem of waste.
  • the present application provides a method for preparing an in-chip composite for electron beam exposure, comprising the following steps:
  • a composite structure is provided, wherein the composite structure includes a first substrate, a conductive layer disposed on a surface of the first substrate, and an array of chips disposed on a surface of the conductive layer facing away from the first substrate;
  • a protective layer is laid on the outer surface of the chip array, and the protective layer covers the chip array;
  • the composite structure and the protective layer are encapsulated and cured by using a polymer solution
  • the protective layer is removed to obtain an in-chip composite.
  • the present application provides an in-chip composite for electron beam exposure, the in-chip composite includes a first substrate, a conductive layer disposed on the surface of the first substrate, and a conductive layer disposed on the conductive layer.
  • a chip inlay layer of the layer faces away from the first substrate, and the chip inlay layer includes a chip array in contact with the conductive layer and an inlay layer distributed between the chip arrays.
  • the present application provides the application of the in-chip composite for electron beam exposure in designing integrated circuits by electron beam exposure.
  • the first aspect of the present application provides a method for preparing a chip-embedded composite for electron beam exposure.
  • the preparation method uses a composite structure including chips as a raw material, and lays a protective layer on the outer surface of the chip array of the composite structure.
  • the chip array protects the chip array, and on the other hand, it provides a flat surface; further, a polymer solution is provided and packaged and cured, and polymer filling is formed in the interval of the chip array; and then the protective layer is removed to obtain a chip embedded compound , so that the surface of the chip can be directly spin glued evenly, and electron beam exposure can be carried out, which can make full use of the lithography area of the chip, realize that the small chip will not be wasted in the process of curing the lithography area, and can make full use of the small size of the lithography area.
  • the chip can improve the utilization rate of the chip, and at the same time, the composite structure includes a conductive layer, which can realize electrical conduction, which is beneficial to the application and electron beam exposure treatment; the preparation method saves valuable consumables, has low material cost, simple manufacturing process, convenient operation, and operation.
  • the time is short, the obtained chip embedded compound has high product yield, stable performance, and high operation fault tolerance, which is favorable for wide use.
  • the chip embedded composite for electron beam exposure since the chip array and the embedded layer disposed between the chip arrays are at the same level, the obtained embedded composite can be directly and evenly spin glued , and carry out electron beam exposure.
  • the chip embedded composite can maximize the use of the lithography area of the chip without causing waste, and the conductive layer can achieve the effect of conducting electricity, maintaining the overall conductivity of the composite, so that in the During the high-voltage operation of the electron beam exposure machine, the emitted electrons pass through the surface of the chip and will not accumulate inside the chip.
  • the product has high yield, stable performance and excellent use effect.
  • the chip embedded compound for electron beam exposure provided in the third aspect of the application is applied to the design of integrated circuits by electron beam exposure. Based on the fact that the chip embedded compound has a flat surface, it can directly spin glue evenly, and can be widely used Based on electron beam exposure, the integrated circuit is designed, which improves the utilization rate of the chip.
  • FIG. 1 is a schematic diagram of a composite structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of lamination of the composite structure and the protective layer provided in the embodiment of the present application.
  • FIG. 3 is a structural diagram of an in-chip composite provided in an embodiment of the present application.
  • FIG. 4 is a perspective view of an in-chip composite provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of lamination of the composite structure and the protective layer provided in the embodiment of the present application.
  • FIG. 6 is an actual diagram of the finished chip embedded compound provided in the embodiment of the present application after spinning.
  • At least one means one or more
  • plural items means two or more.
  • At least one item(s) below” or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • at least one (one) of a, b, or c or, “at least one (one) of a, b, and c” can mean: a,b,c,a-b( That is, a and b), a-c, b-c, or a-b-c, where a, b, and c can be single or multiple respectively.
  • the weight of the relevant components mentioned in the description of the examples of this application can not only refer to the specific content of each component, but also can represent the proportional relationship between the weights of the components. It is within the scope disclosed in the description of the embodiments of the present application that the content of the ingredients is scaled up or down.
  • the mass described in the description of the embodiment of the present application may be a mass unit known in the chemical field, such as ⁇ g, mg, g, kg, etc.
  • first and second are only used for descriptive purposes to distinguish objects such as substances from each other, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features.
  • first XX may also be referred to as the second XX
  • second XX may also be referred to as the first XX.
  • a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • a first aspect of the embodiments of the present application provides a method for preparing an in-chip composite for electron beam exposure, comprising the following steps:
  • the composite structure includes a first substrate, a conductive layer disposed on a surface of the first substrate, and a chip array disposed on a surface of the conductive layer facing away from the first substrate;
  • S02. Lay a protective layer on the outer surface of the chip array, and the protective layer covers the chip array;
  • the first aspect of the present application provides a method for preparing an in-chip composite for electron beam exposure.
  • the preparation method uses a composite structure including a chip as a raw material, places the composite structure in a container, and controls the chips in the composite structure. Contact with the soft bottom surface of the provided container, further add a polymer solution for curing treatment, and form an embedded layer at the interval of the array chips to obtain a chip embedded composite; The embedded layer between them and on the same level as the chip surface enables the chip surface to be directly spun and electron beam exposed. It causes waste of lithography area, and can make full use of small-sized chips to improve the utilization rate of chips.
  • the composite structure includes a conductive layer, which can realize ground conduction, which is beneficial to application and electron beam exposure processing; the preparation method saves precious
  • the cost of consumables and materials is low, the manufacturing process is simple, the operation is convenient, and the operation time is short.
  • step S01 a composite structure is provided, as shown in FIG. 1, wherein the composite structure includes a first substrate 1, a conductive layer 2 disposed on the surface of the first substrate, and a conductive layer 2 disposed on the surface of the conductive layer 2 away from the first substrate Chip array 3 on the surface.
  • the first substrate may be selected from materials with a smooth surface, high electrical conductivity, and high temperature resistance, and conventional materials that meet the above conditions can be used.
  • the first substrate is selected from a silicon wafer with a certain doping degree, and providing a silicon wafer with a certain doping degree is favorable for right-angle cutting processing and convenient for use.
  • the thickness of the first substrate is not required, and a substrate with a conventional thickness can be selected for use as required.
  • the material of the conductive layer may be selected from conductive adhesive materials with high conductivity, high temperature resistance and curable properties.
  • the material of the conductive layer is selected from ECA-1003 conductive adhesive, and ECA-1003 conductive adhesive is selected as the material of the conductive layer, which can be cured quickly and at the same time ensures good conductive performance, which is beneficial to the development of the chip embedded compound. Electron beam exposure.
  • the size of the chip is (2 ⁇ 3) mm ⁇ (4 ⁇ 5) mm. Since chips with larger specifications can be used directly, this application mainly focuses on a method for recycling small chips. The curing process will not cause waste of lithography area, and can make full use of small-sized chips, improve the utilization rate of chips, save valuable consumables, low cost of materials, and simple manufacturing process.
  • the size of the chip is 2mm x 4mm.
  • the small chips need to meet the characteristics of small surface area.
  • two small chips with approximately the same size are provided for setting, which is conducive to manufacturing the horizontal plane and realizes the effect of uniform spinning.
  • the preparation of the in-chip composite requires experimental operations in a clean room with a cleanliness level of ⁇ 1000, including all steps such as the preparation of the provided composite structure.
  • the preparation method includes the following steps:
  • a conductive layer is arranged on the surface of the first substrate, a number of chips are arranged on the surface of the conductive layer away from the first substrate, and a heating and curing process is performed to obtain a composite structure;
  • the composite structure includes a first substrate, a conductive layer disposed on the surface of the first substrate, and a chip array disposed on a surface of the conductive layer facing away from the first substrate.
  • step S02 as shown in FIG. 2, a protective layer 4 is laid on the outer surface of the chip array 3, and the protective layer 4 covers the chip array; on the one hand, the protective layer is laid to protect the surface of the chip, and on the other hand On the one hand, it is to provide a flat surface, which is conducive to the preparation of subsequent materials.
  • the protective layer is selected from a soft film layer with a smooth surface or a hard substrate composite.
  • a soft film layer with a flat surface is conducive to better contact with the chip, and at the same time, it is conducive to better detachment after the chip embedded structure is formed, and will not affect the use of the chip.
  • a protective layer is laid on the outer surface of the chip array, and the protective layer is a soft film layer, and the preparation method includes the following steps:
  • the soft film layer solution is configured and stirred evenly, the soft film layer solution is introduced into the container, and the liquid surface is evacuated to no bubbles, and then heated and cured to obtain a soft film layer;
  • the soft film layer is attached to the outer surface of the chip array to obtain a protective layer laid on the outer surface of the chip array.
  • the container is a container with a flat surface, and the material is not required.
  • the container may be selected from conventional glass petri dishes.
  • the steps of removing impurities include: soaking in acetone for about 2 minutes and pouring it into a waste liquid tank, then washing the residual acetone on the surface of the container with isobutanol, and finally drying the surface of the container with an air gun to obtain a clean container surface.
  • the thickness of the soft film layer is 2-4 microns, and the thickness of the soft film layer is controlled to be moderate, which is conducive to the separation processing with the finished product.
  • the material of the soft film layer is selected to be consistent with the material of the polymer solution, which is beneficial to curing treatment.
  • the material of the soft film layer is selected from polydimethylsiloxane, benzocyclobutene, epoxy resin, dimethylsiloxane, cyclomethicone, aminosiloxane, At least one of polymethylphenylsiloxane and polyether polysiloxane copolymer.
  • the hard substrate composite includes a second substrate and a connecting layer, and along the extending direction from the conductive layer to the chip array, the connecting layer and the second substrate are stacked in sequence, and the connecting layer covers the chip array.
  • the material of the connection layer is selected from materials with high adhesion and easy cutting.
  • the material of the tie layer is selected from PMMA materials.
  • the thickness of the connection layer is 1-1.2 microns, and the connection layer is provided, which is mainly used for bonding the second substrate and the chip, in order to ensure that the chip has a horizontal plane and is conducive to cutting and falling off.
  • a protective layer is laid on the outer surface of the chip array, and the protective layer is a hard substrate composite, and the preparation method includes the following steps:
  • a conductive layer is arranged on the surface of the first substrate, and a number of chips are arranged on the surface of the conductive layer away from the first substrate, and heat curing treatment is performed;
  • connection layer and the chip array are bonded to obtain a protective layer laid on the outer surface of the chip array.
  • acetone and isopropanol are used for cleaning and removing impurities, so as to ensure that the first substrate, the second substrate and the chip are clean and tidy and free of impurities.
  • step S03 a polymer solution is used to encapsulate and cure the composite structure and the protective layer.
  • the composite structure and the protective layer are encapsulated and cured by using a polymer solution, and the polymer solution is selected from materials that can be cured below 300° C. to ensure that the embedded layer is preferably formed.
  • the material of the polymer solution is selected from at least one of polydimethylsiloxane, benzocyclobutene, epoxy resin, and cyclomethicone.
  • the contact angle of the provided polymer solution material and the chip surface to the electronic glue is not much different, so as to ensure that the obtained chip embedded composite can be smoothly spin glued, and at the same time, the electron beam exposure can be smoothly carried out.
  • the material of the polymer solution is selected from polydimethylsiloxane.
  • the polydimethylsiloxane has stable properties, high temperature resistance, and is easy to cure. Embedded layers between chip arrays.
  • the step of using the polymer solution to encapsulate and cure the composite structure and the protective layer includes: applying pressure to the composite structure and the protective layer, adding a polymer solution to fill, and then performing encapsulation and curing.
  • the pressure is 10-40N.
  • the constant pressure is provided to prevent the polymer solution from immersing in the gap between the chip and the substrate, so that the chip and the substrate will not be doped with the polymer solution during the whole preparation process, which will affect the performance of the chip. If the pressure is too small, the applied pressure of the composite structure will be insufficient, and it cannot be ensured that the gap between the chip and the substrate will not be immersed in the polymer solution.
  • the method of applying pressure is optional but not limited to placing a fixable weight (eg, a weight), clamping the bottom of the container and the top of the substrate with clips.
  • a fixable weight eg, a weight
  • the composite structure is subjected to vacuum treatment.
  • the purpose of the vacuum treatment is to extract the air between the chip and the substrate, and at the same time, to extract the air in the polymer solution, so that no impurity molecules remain in the polymer solution.
  • the vacuuming process is optional but not limited to using a vacuuming machine for vacuuming, a nitrogen box equipped with a vacuuming function for vacuuming, and an ICP plasma etching machine equipped with a vacuuming function. Carry out vacuum treatment.
  • a container is provided, a protective layer is provided on the surface of the container, the chip array of the composite structure is adhered to the protective layer, the polymer solution is added into the container and the curing process is performed, wherein the polymer solution is controlled
  • the added amount is consistent with the height of the upper surface of the first substrate of the composite structure. Controlling the amount of polymer solution added can ensure that the obtained chip embedded compound forms a flat surface for use.
  • the temperature and time of the curing treatment can be determined according to the material of the polymer solution. If there is a very high flatness requirement, natural curing is recommended to prevent the surface flatness error caused by thermal expansion and contraction of the polymer.
  • a container is provided, a protective layer is arranged on the surface of the container, the chip array of the composite structure is attached to the protective layer, the material of the polymer solution is selected from polydimethylsiloxane, and the configuration mass ratio is 10:1 PDMS solution, vacuumize the prepared PDMS solution, and then slowly pour it to the side of the composite structure.
  • the material of the polymer solution is selected from polydimethylsiloxane, and the configuration mass ratio is 10:1 PDMS solution
  • vacuumize the prepared PDMS solution vacuumize the prepared PDMS solution, and then slowly pour it to the side of the composite structure.
  • the upper surface of the entire device was placed on a hot plate and heated at 100 °C for 35 min until the upper layer of PDMS was cured.
  • step S04 the protective layer is removed to obtain a chip embedded compound.
  • the step of removing the protective layer includes: cutting and removing the protective layer, and cleaning with an organic solvent.
  • the cured composite is cut and separated with a clean knife, the chip embedded composite is taken out, and the chip embedded composite is soaked in acetone for 1-2 minutes until the impurity material falls off.
  • the chip embedded compound needs to be cleaned several times with acetone and isopropanol to meet the cleanliness requirements. If there are other effective cleaning solvents, the remaining effective cleaning solvents can be used to replace acetone and isopropanol, but it is necessary to ensure that other effective cleaning solvents will not react with the polymer material and damage the surface flatness of the finished product.
  • the preparation method of the in-chip complex comprises the following steps:
  • the composite structure includes a first substrate, a conductive layer disposed on a surface of the first substrate, and a chip array disposed on a surface of the conductive layer facing away from the first substrate;
  • the protective layer is removed to obtain a chip-embedded composite.
  • PDMS polydimethylsiloxane
  • PDMS solution Configure the PDMS solution, provide the PDMS solution of A solution (about 5ml) and B solution with a mass ratio of 10:1, stir the mixed solution with a glass rod until it is uniform, pour the mixed solution into a glass dish, and put it into a vacuum machine. Vacuum until there are no bubbles on the liquid surface, and finally place the petri dish on a hot plate and heat at 120°C for 30 minutes to form a flat protective layer;
  • the prepared PDMS solution is vacuumized, and then slowly poured to the side of the sandwich structure. During the operation, ensure that the upper silicon wafer is continuously subjected to constant pressure. Pressure was applied until the PDMS solution slightly diffused over the upper surface of the upper silicon wafer. Place the entire device on a hot plate and heat at 100°C for 35 minutes until the upper layer of PDMS is cured;
  • the sandwich structure was cut out with a clean knife, and the sandwich structure was soaked in acetone until the PMMA electronic glue was dissolved, and the second silicon wafer fell off the sandwich structure to obtain a chip embedded compound.
  • a second aspect of the embodiments of the present application provides an in-chip composite for electron beam exposure.
  • the in-chip composite includes a first substrate 1 , and a conductive layer disposed on the surface of the first substrate 1 2.
  • a perspective view of the obtained chip-embedded complex is shown in FIG. 5 .
  • the chip embedded composite for electron beam exposure provided in the second aspect of the embodiment of the present application, since the chip array and the embedded layer disposed between the chip arrays are at the same level, the obtained embedded composite can be directly uniformized Spin glue, and carry out electron beam exposure, at the same time, the chip embedded composite can maximize the use of the lithography area of the chip, without causing waste, and the conductive layer can achieve the effect of conduction, maintaining the overall conductivity of the composite, In the high-voltage working process of the electron beam exposure machine, the emitted electrons pass through the surface of the chip and will not accumulate inside the chip. The product has high yield, stable performance and excellent use effect.
  • the thickness of the embedded layer is less than or equal to 15 microns compared to the chip array, and the height difference between the embedded layer and the chip is controlled to be small, so as to ensure uniform spin glue processing.
  • the entire structure is observed and inspected with a SEM electron microscope. If the chip surface can be observed by SEM, the conductivity is good, which meets the requirements of electron beam exposure conductivity.
  • a layer of adhesion promoter can be spin-coated on the surface of the chip embedded layer (ie, the chip and the polymer material layer) to create a better plane.
  • the adhesion promoter is selected from hexamethyldisilazane, and hexamethyldisilazane can improve the adhesion of the material, and at the same time interact with the silicon dioxide on the surface of the substrate to produce a strong waterproof layer, which can improve the adhesion of the material. Effectively prevent the developer from penetrating the photoresist. Its thickness is not required and can be adjusted according to the height difference of the embedded layer of the chip.
  • the third aspect of the embodiments of the present application provides the application of the in-chip composite for electron beam exposure in designing integrated circuits by electron beam exposure.
  • the chip embedded compound for electron beam exposure provided in the third aspect of the present application is applied to the design of integrated circuits by electron beam exposure. Because the chip embedded compound has a flat surface, it can be directly and evenly spun, and can be widely used in Electron beam exposure is used to design integrated circuits, which improves the utilization rate of chips. The following description will be given in conjunction with specific embodiments.
  • the preparation method comprises the following steps:
  • a composite structure is provided, wherein the composite structure includes a first substrate, a conductive layer disposed on the surface of the first substrate, and a chip array disposed on a surface of the conductive layer facing away from the first substrate;
  • a protective layer is laid on the outer surface, and the protective layer covers the chip array:
  • PDMS solution Configure the PDMS solution, provide the PDMS solution of A solution (about 5ml) and B solution with a mass ratio of 10:1, stir the mixed solution with a glass rod until it is uniform, pour the mixed solution into a glass dish, and put it into a vacuum machine. Vacuum until there are no bubbles on the liquid surface, and finally place the petri dish on a hot plate and heat it at 100°C for 30 minutes to form a flat protective layer;
  • the prepared PDMS solution is vacuumized, and then slowly poured to the side of the sandwich structure. During the operation, ensure that the upper silicon wafer is continuously subjected to constant pressure. Pressure was applied until the PDMS solution slightly diffused over the upper surface of the upper silicon wafer. Place the whole device on a hot plate and heat at 100°C for 30 minutes until the upper layer of PDMS is cured;
  • the sandwich structure was cut out with a clean knife, and the sandwich structure was soaked in acetone until the PMMA electronic glue was dissolved, and the second silicon wafer fell off the sandwich structure to obtain a chip embedded compound.
  • the chip embedded compound includes a first substrate, a conductive layer disposed on the surface of the first substrate, a chip embedded layer disposed on the conductive layer away from the first substrate, and the chip embedded layer includes a chip array and a chip array disposed between the chip arrays. Inlay layer.
  • the preparation method comprises the following steps:
  • a composite structure is provided, wherein the composite structure includes a first substrate, a conductive layer disposed on the surface of the first substrate, and a chip array disposed on a surface of the conductive layer away from the first substrate; a protective layer is laid on the outer surface of the chip array, A protective layer covers the chip array:
  • PDMS solution Configure the PDMS solution, provide the PDMS solution of A solution (about 5ml) and B solution with a mass ratio of 10:1.2, stir the mixed solution with a glass rod until it is uniform, pour the mixed solution into a glass dish, and put it into a vacuum machine. Vacuum until there are no bubbles on the liquid surface, and finally place the petri dish on a hot plate and heat it at 100°C for 30 minutes to form a flat protective layer;
  • the PDMS solution with a mass ratio of 10:1.2 is prepared, and the amount of solution A is about 5ml.
  • the prepared PDMS solution is vacuumized, and then slowly poured to the side of the sandwich structure. During the operation, it is necessary to ensure that the upper silicon wafer is continuously subjected to constant pressure. Pressure was applied until the PDMS solution slightly diffused over the upper surface of the upper silicon wafer. Place the whole device on a hot plate and heat at 120°C for 35 minutes until the upper layer of PDMS is cured;
  • the chip embedded complex was taken out with a clean knife, and the chip embedded complex was soaked and cleaned in acetone to obtain the chip embedded complex.
  • the chip embedded compound includes a first substrate, a conductive layer disposed on the surface of the first substrate, a chip embedded layer disposed on the conductive layer away from the first substrate, and the chip embedded layer includes a chip array and a chip array disposed between the chip arrays. Inlay layer.
  • the preparation method comprises the following steps:
  • a composite structure is provided, wherein the composite structure includes a first substrate, a conductive layer disposed on the surface of the first substrate, and a chip array disposed on a surface of the conductive layer away from the first substrate; a protective layer is laid on the outer surface of the chip array, A protective layer covers the chip array:
  • the second silicon wafer put the second silicon wafer after the spinning glue on the surface of the petri dish after curing the BCB, and press the cured small chip-conductive glue-silicon wafer as a whole on the spinning silicon wafer. Apply pressure on the upper surface of the silicon wafer and put it into a vacuum machine to vacuum, so as to achieve the effect of no air between the silicon wafer and the small chip;
  • Configure the BCB solution provide the BCB solution of A solution (about 5ml) and B solution with a mass ratio of 10:1, stir the mixed solution with a glass rod until it is uniform, pour the mixed solution into a glass dish, and put it into a vacuum machine. Vacuum until there are no bubbles on the liquid surface, and finally place the petri dish on a hot plate and heat it at 100°C for 30 minutes to form a flat protective layer;
  • the sandwich structure was cut out with a clean knife, and the sandwich structure was soaked in acetone until the PMMA electronic glue was dissolved, and the second silicon wafer fell off the sandwich structure to obtain a chip embedded compound.
  • the chip embedded compound includes a first substrate, a conductive layer disposed on the surface of the first substrate, a chip embedded layer disposed on the conductive layer away from the first substrate, and the chip embedded layer includes a chip array and a chip array disposed between the chip arrays. Embedded layer.
  • the chip-embedded composites obtained in Examples 1 to 3 were subjected to spinning treatment, and a step meter was provided to measure the height difference between the polymer and the chip surface before spinning, and the polymer and chip surface after spinning. The height difference and the roughness of the chip surface after spin glue, and statistics and analysis are carried out.
  • the chip embedded composites obtained in Examples 1 to 3 respectively measure the height difference between the polymer and the chip surface before spinning, the height difference between the polymer and the chip surface after spinning, and the data of the roughness of the chip surface after spinning as shown in the following table 1, as shown in Table 1 below, in Example 1, the surface of the polymer and the chip before spinning is 9837.06 nm, the surface of the polymer and the chip after spinning is 3398.62 nm, and the roughness of the chip after spinning is 3 nm; In Example 2, the surface of the polymer and chip before spinning was 9830.06 nm, the surface of the polymer and chip after spinning was 3390.62 nm, and the roughness of the chip after spinning was 4 nm; in Example 3, the surface of the polymer and chip before spinning was 9835.06nm, the surface of the polymer and the chip after spinning is 3392.62nm, and the roughness of the chip after spinning is 5nm.
  • the present application provides a method for preparing a chip-embedded composite for electron beam exposure.
  • the preparation method uses a composite structure including a chip as a raw material, places the composite structure in a container, and controls the chips in the composite structure. Contact with the soft bottom surface of the provided container, further add a polymer solution for curing treatment, and form an embedded layer at the interval of the array chips to obtain a chip embedded composite; The embedded layer between them and at the same level as the chip surface allows the chip surface to be directly glued and exposed to electron beams, which can make full use of the photolithography area of the chip, and realize that the small chip will not be cured during the curing process.
  • the composite structure includes a conductive layer, which can realize ground conduction, which is beneficial to application and electron beam exposure processing; the preparation method saves precious
  • the cost of consumables and materials is low, the manufacturing process is simple, the operation is convenient, and the operation time is short.

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Abstract

一种用于电子束曝光的芯片内嵌复合物的制备方法，该制备方法包括：提供一复合结构，其中，所述复合结构包括第一基底(1)、设置在所述第一基底(1)表面的导电层(2)和设置在所述导电层(2)的背离所述第一基底(1)的表面上的芯片阵列(3)；在所述芯片阵列(3)的外表面铺设保护层(4)，所述保护层(4)覆盖所述芯片阵列(3)；采用聚合物溶液对所述复合结构和所述保护层(4)进行封装固化处理；除去所述保护层(4)，得到芯片内嵌复合物。该方法涉及半导体芯片制造领域，可充分利用芯片光刻面积、利用小芯片进行旋胶，具有用料成本低、操作便捷、操作时间短、底面导电等特点，适合广泛应用。

Description

用于电子束曝光的芯片内嵌复合物及其制备方法与应用
本申请要求于2021年01月18日在中国专利局提交的、申请号为202110064658.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体芯片制造领域技术领域，尤其涉及一种用于电子束曝光的芯片内嵌复合物及其制备方法与应用。
背景技术
二十一世纪光学图形曝光(光刻)技术被广泛使用的原因在于其拥有低成本、高产率、较高的分辨率和容易操作等特点。然而，为了满足100nm以下的集成电路工艺的需求，电子束曝光(EBL)被广泛用于半导体工业中下一代超大规模集成电路。其优点在于拥有非常好的聚焦深度、能够校正晶圆的大规模高度变化、允许在一个晶圆上一起制造多种设计图案、高自动化及高精度控制等。但是EBL设备产率低，在分辨率小于100nm时约为每小时两片晶圆，这样的产率适合掩膜板的生产和需求小的制定电路。因此作为科研目的利用电子束曝光制作光电子半导体芯片的图案需要尽可能充分利用整片小芯片的边角，在芯片上光刻多种设计图案，提高晶圆的利用率；但是，电子束曝光设备对光刻物表面是否是一个平面有苛刻的要求。
目前，对于科研项目的进展、资金和时间的节约利用，很难将整片晶圆放置在电子束设备上进行曝光。目前大多数的做法为将切割出表面积较小的芯片进行电子束曝光，而棘手的问题在于两个点：(1)小芯片由于表面积(2mm×4mm)过小，难以抽真空固定在旋胶机上进行旋胶；(2)需将小芯片固定在电子束设备的机械平台上，目的在于防止电子束轰击时小芯片脱位，影响整个电子束曝光工艺。若用耐高温胶带固定其边角或任何固定方式，不可避免会浪费一部分小芯片的光刻面积。
因此为了在不浪费可用晶圆的情况下，对小芯片进行旋胶和电子束曝光，需要将其表面积“扩大”。然而电子束曝光工艺的精度要求非常高，如果仅是将小芯片固定于平底面，由于芯片表面与底面的高度差问题，会引起旋胶边缘不均匀和曝光精度的严重误差。
技术问题
本申请的目的在于提供一种用于电子束曝光的芯片内嵌复合物及其制备方法与应用，旨在解决现有技术中小芯片无法直接进行旋胶，以及用于电子束曝光的固定过程中光刻面积造成浪费的问题。
技术解决方案
为实现上述申请目的，本申请采用的技术方案如下：
第一方面，本申请提供一种用于电子束曝光的芯片内嵌复合物的制备方法，包括如下步骤：
提供一复合结构，其中，所述复合结构包括第一基底、设置在所述第一基底表面的导电层和设置在所述导电层的背离所述第一基底的表面上的芯片阵列；
在所述芯片阵列的外表面铺设保护层，所述保护层覆盖所述芯片阵列；
采用聚合物溶液对所述复合结构和所述保护层进行封装固化处理；
除去所述保护层，得到芯片内嵌复合物。
第二方面，本申请提供一种用于电子束曝光的芯片内嵌复合物，所述芯片内嵌复合物包括第一基底，设置在所述第一基底表面的导电层，设置在所述导电层的背离所述第一基底的芯片内嵌层，且所述芯片内嵌层包括与所述导电层接触的芯片阵列以及分布在芯片阵列之间的内嵌层。
第三方面，本申请提供了用于电子束曝光的芯片内嵌复合物在电子束曝光设计集成电路中的应用。
本申请第一方面提供的用于电子束曝光的芯片内嵌复合物的制备方法，该制备方法以包括芯片的复合结构为原材料，并在该复合结构的芯片阵列的外表面铺设保护层，一方面是对芯片阵列进行保护，另一方面是提供一平整的表面；进一步的提供聚合物溶液并封装固化处理，在芯片阵列的间隔形成聚合物填充；再去除保护层，得到芯片内嵌复合物，使得芯片表面可直接进行均匀旋胶，并进行电子束曝光，可充分利用芯片的光刻面积，实现将小芯片进行固化过程中不会造成光刻面积的浪费，且能够充分利用小规格的芯片，提高芯片的利用率，同时复合结构中包括一导电层，能够实现导电，有利于应用与电子束曝光处理；该制备方法节约贵重耗材、用料成本低、制作工艺简单、操作便捷、操作时间短，得到的芯片内嵌复合物成品良率高、性能稳定、操作容错率高，有利于广泛使用。
本申请第二方面提供的用于电子束曝光的芯片内嵌复合物，由于芯片阵列以及设置在芯片阵列之间的内嵌层处于同一水平面，使得到的内嵌复合物可直接进行均匀旋胶，并进行电子束曝光，同时该芯片内嵌复合物能够最大程度利用芯片的光刻面积，不会造成浪费，且设置导电层能够实现导电的作用，保持了复合物整体的导电性，使得在电子束曝光机高压工作过程中，射出的电子穿过芯片表面不会在芯片内部聚集，该产品成品良率高、性能稳定、使用效果优异。
本申请第三方面提供的用于电子束曝光的芯片内嵌复合物应用于电子束曝光设计集成电路，基于该芯片内嵌复合物具有平整的表面，能够直接进行均匀旋胶，并可广泛应用于电子束曝光，进行设计集成电路，提高了芯片的利用率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的复合结构的示意图。
图2是本申请实施例提供的复合结构和保护层贴合的示意图。
图3是本申请实施例提供的芯片内嵌复合物的结构图。
图4是本申请实施例提供的芯片内嵌复合物的立体图。
图5是本申请实施例提供的复合结构和保护层贴合的示意图。
图6是本申请实施例提供的成品芯片内嵌复合物旋胶后实际图。
本发明的实施方式
为了使本申请要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本 申请，并不用于限定本申请。
本申请中，术语“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况。其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，“a,b,或c中的至少一项(个)”，或，“a,b,和c中的至少一项(个)”，均可以表示：a,b,c,a-b(即a和b),a-c,b-c,或a-b-c，其中a,b,c分别可以是单个，也可以是多个。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，部分或全部步骤可以并行执行或先后执行，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本申请实施例说明书中所提到的相关成分的重量不仅仅可以指代各组分的具体含量，也可以表示各组分间重量的比例关系，因此，只要是按照本申请实施例说明书相关组分的含量按比例放大或缩小均在本申请实施例说明书公开的范围之内。具体地，本申请实施例说明书中所述的质量可以是μg、mg、g、kg等化工领域公知的质量单位。
术语“第一”、“第二”仅用于描述目的，用来将目的如物质彼此区分开，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。例如，在不脱离本申请实施例范围的情况下，第一XX也可以被称为第二XX，类似地，第二XX也可以被称为第一XX。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
本申请实施例第一方面提供一种用于电子束曝光的芯片内嵌复合物的制备方法，包括如下步骤：
S01.提供一复合结构，其中，复合结构包括第一基底、设置在第一基底表面的导电层和设置在导电层的背离第一基底的表面上的芯片阵列；
S02.在芯片阵列的外表面铺设保护层，保护层覆盖芯片阵列；
S03.采用聚合物溶液对复合结构和保护层进行封装固化处理；
S04.除去保护层，得到芯片内嵌复合物。
本申请第一方面提供的用于电子束曝光的芯片内嵌复合物的制备方法，该制备方法以包括芯片的复合结构为原材料，将该复合结构放置于容器中，且控制复合结构中的芯片与提供的容器的软底面接触，进一步加入聚合物溶液进行固化处理，在阵列芯片的间隔形成内嵌层，得到芯片内嵌复合物；该制备方法得到的芯片内嵌复合物包括设置在芯片阵列之间、且与芯片表面在同一水平线的内嵌层，使得芯片表面可直接进行均匀旋胶，并进行电子束曝光，可充分利用芯片的光刻面积，实现将小芯片进行固化过程中不会造成光刻面积的浪费，且能够充分利用小规格的芯片，提高芯片的利用率，同时复合结构中包括一导电层，能够实现地面导电，有利于应用与电子束曝光处理；该制备方法节约贵重耗材、用料成本低、制作工艺简单、操作便捷、操作时间短，得到的芯片内嵌复合物成品良率高、性 能稳定、操作容错率高，有利于广泛使用。
在步骤S01中，提供一复合结构，如图1所示，其中，复合结构包括第一基底1、设置在第一基底表面的导电层2和设置在导电层2的背离所述第一基底的表面上的芯片阵列3。
可选的，第一基底选自表面平整、电导率高、耐高温的材料即可，常规满足上述条件的材料均可使用。在一些实施例中，第一基底选自具有一定掺杂度的硅片，提供具有一定掺杂度的硅片，有利于进行直角切割处理，方便使用。
可选的，第一基底的厚度没有要求，可根据需要进行选择常规厚度的基底进行使用。
可选的，导电层的材料选自导电率较高、耐高温、能固化的导电胶材料即可。在一些实施例中，导电层的材料选自ECA-1003导电胶，选择ECA-1003导电胶作为导电层的材料，能够快速固化，同时保证具有良好的导电性能，有利于芯片内嵌复合物进行电子束曝光作用。
可选的，芯片的大小为(2～3)mm×(4～5)mm。由于规格较大的芯片可以直接进行使用，本申请主要是对小规格的芯片进行回收利用的方法，该方法可以针对小规格的芯片进行作用，可充分利用芯片的光刻面积，实现将小芯片进行固化过程中不会造成光刻面积的浪费，且能够充分利用小规格的芯片，提高芯片的利用率，节约贵重耗材、用料成本低、制作工艺简单。在一些实施例中，芯片的大小为2mm×4mm。
可选的，小芯片需满足表面积较小的特征，制备过程中提供两片大小接近一致的小芯片进行设置，有利于制造水平面，实现均匀旋胶的作用效果。
在一些实施例中，芯片内嵌复合物的制备均需要在洁净度≤1000级的洁净室进行实验操作，包括提供的复合结构的制备等所有步骤。
在一些实施例中，当复合结构为“芯片-导电胶-基底”结构，制备方法包括如下步骤：
提供第一基底和芯片，将第一基底和芯片进行除杂处理；
在第一基底的表面设置导电层，在导电层背离第一基底表面设置若干个芯片，进行加热固化处理，得到复合结构；
其中，所述复合结构包括第一基底、设置在所述第一基底表面的导电层和设置在所述导电层的背离所述第一基底的表面上的芯片阵列。
在步骤S02中，如图2所示，在所述芯片阵列3的外表面铺设保护层4，所述保护层4覆盖所述芯片阵列；铺设保护层一方面是为了对芯片表面进行保护，另一方面是为了提供一个平整的表面，有利于后续材料的制备。
在一些实施例中，保护层选自表面平整的软膜层或硬基底复合物。
进一步的，提供表面平整的软膜层，有利于与芯片较好的接触，同时在形成芯片内嵌结构之后有利于更好地脱落，不会影响芯片的使用。
在一些实施例中，在芯片阵列的外表面铺设保护层，保护层为软膜层，制备方法包括如下步骤：
提供容器，进行除杂处理；
配置软膜层溶液并搅拌均匀，将软膜层溶液导入容器中，抽真空至液面无气泡，再进 行加热固化处理，得到软膜层；
将软膜层贴合在芯片阵列的外表面，得到铺设在芯片阵列的外表面的保护层。
可选的，容器为具有平整的表面的容器，材料没有要求。在一些实施例中，容器选自常规的玻璃培养皿即可。
进一步，进行除杂处理的步骤包括：用丙酮浸泡2分钟左右并倒至废液箱，再用异丁醇清洗容器表面残留的丙酮，最后用气枪干燥容器表面，得到洁净的容器表面。
可选的，软膜层的厚度为2～4微米，控制软膜层的厚度适中，有利于与成品进行分割处理。
可选的，软膜层的材料选自与聚合物溶液的材料一致，有利于固化处理。在一些实施例中，软膜层的材料选自聚二甲基硅氧烷、苯并环丁烯、环氧树脂、二甲基硅氧烷，环甲基硅氧烷，氨基硅氧烷，聚甲基苯基硅氧烷，聚醚聚硅氧烷共聚物中的至少一种。
进一步的，提供平整的硬基底复合物，提供硬基底材料，能够保证形成水平的平面。其中，硬基底复合物包括第二基底和连接层，且沿导电层至芯片阵列的延伸方向，连接层和第二基底依次层叠，且连接层覆盖芯片阵列。
可选的，连接层的材料选自粘结性高，且易于切割的材料。在一些实施例中，连接层的材料选自PMMA材料。
可选的，连接层的厚度为1～1.2微米，提供连接层，主要是用于粘合第二基底和芯片，为保证芯片有水平平面，同时有利于切割脱落。
在一些实施例中，在芯片阵列的外表面铺设保护层，保护层为硬基底复合物，制备方法包括如下步骤：
提供第一基底、第二基底和芯片，将第一基底、第二基底和芯片进行除杂处理；
在第一基底的表面设置导电层，在导电层背离第一基底表面设置若干个芯片，进行加热固化处理；
在第二基底的表面进行烘干后，用旋胶机旋涂绝缘胶再进行烘干，得到设置在第二基底的表面的连接层；
将连接层层和芯片阵列粘合处理，得到铺设在芯片阵列的外表面的保护层。
可选的，除杂处理的步骤中，采用丙酮和异丙醇进行清洗除杂，保证第一基底、第二基底和芯片均干净整洁，无杂质物质。
在步骤S03中，采用聚合物溶液对复合结构和保护层进行封装固化处理。
其中，采用聚合物溶液对复合结构和保护层进行封装固化处理，聚合物溶液选自在300℃以下能够固化的材料，保证较好形成内嵌层。
在一些实施例中，聚合物溶液的材料选自聚二甲基硅氧烷、苯并环丁烯、环氧树脂、环甲基硅氧烷中的至少一种。提供的聚合物溶液材料与芯片表面对电子胶的接触角均相差不大，保证得到的芯片内嵌复合物能够顺利进行旋胶，同时顺利进行电子束曝光。在本申请具体实施例中，聚合物溶液的材料选自聚二甲基硅氧烷，聚二甲基硅氧烷性质稳定，耐高温，易于固化，作为聚合物溶液的材料能够较好形成设置在芯片阵列之间的内嵌层。
进一步的，采用聚合物溶液对复合结构和保护层进行封装固化处理的步骤中，包括： 对复合结构和保护层施加压力，加入聚合物溶液填充后，进行封装固化处理。可选的，压力为10～40N。提供恒定的压力，是防止聚合物溶液浸入芯片与基底的缝隙间，使整个制备过程中，芯片和基底不会掺杂聚合物溶液，导致影响芯片的性能。若压力过小，会导致复合结构的施加压力不足，无法保证芯片与基底的缝隙间不会浸入聚合物溶液。
在一些实施例中，施加压力的方法可选但不限于放置可固定重物(如砝码)、用夹子夹住容器底和基底顶部。
进一步的，对复合结构进行抽真空处理，抽真空处理的目的是抽离芯片与基底之间的空气，同时抽离聚合物溶液中的空气，使聚合物溶液无杂质分子残留。
在一些实施例中，进行抽真空处理可选但不限于采用抽真空机进行抽真空处理，采用配有抽真空功能的氮气箱进行抽真空处理，采用配有抽真空功能的ICP等离子刻蚀机进行抽真空处理。
在一些实施例中，提供一容器，在容器表面设置保护层，将复合结构的芯片阵列与保护层贴合，在容器中加入聚合物溶液并进行固化处理的步骤中，其中，控制聚合物溶液的加入量与复合结构的第一基底的上表面的高度一致。控制聚合物溶液的加入量较多，能够保证得到的芯片内嵌复合物形成平整的表面进行使用。
进一步的，固化处理的温度和时间根据聚合物溶液的材料进行确定即可，若有非常高的平整度要求建议自然固化，防止聚合物热胀冷缩带来的表面平整度误差。
在本申请具体实施例中，提供一容器，在容器表面设置保护层，将复合结构的芯片阵列与保护层贴合，聚合物溶液的材料选自聚二甲基硅氧烷，配置质量比例为10:1的PDMS溶液，将配好的PDMS溶液进行抽真空操作，再缓慢倒灌至复合结构侧边，在操作时要保证第一基底持续受到恒定压力作用，直至PDMS溶液稍微漫过第一基底的上表面，将整个装置放置在热板上100℃加热35分钟至上层PDMS固化。
在步骤S04中，除去保护层，得到芯片内嵌复合物。
进一步的，除去保护层的步骤中，包括：对保护层进行切割去除，并采用有机溶剂进行清洗。
在一些实施例中，用洁净小刀将固化复合物进行切割分离，取出芯片内嵌复合物，将芯片内嵌复合物放在丙酮中浸泡1～2分钟，至杂质材料脱落即可。
进一步的，当成品制备完成之后，需要用丙酮和异丙醇多次清洗芯片内嵌复合物，达到洁净度要求。若有其他有效清洗溶剂，则可利用其余有效清洗溶剂代替丙酮和异丙醇，但是需要求其他有效清洗溶剂不会与聚合物材料发生反应，破坏成品表面平整度。
在一些实施例中，芯片内嵌复合物的制备方法，包括如下步骤：
提供一复合结构，其中，复合结构包括第一基底、设置在所述第一基底表面的导电层和设置在所述导电层的背离所述第一基底的表面上的芯片阵列；
提供容器，在容器表面制备平整的保护层，将复合结构放置于保护层的表面，其中，保护层覆盖所述芯片阵列；
对复合结构施加压力并进行抽真空处理，在容器中加入聚合物溶液并进行封装固化处理；
除去保护层，得到芯片内嵌复合物。
在本申请具体实施例中，提供聚二甲基硅氧烷(PDMS)为聚合物材料，进行芯片内嵌复合物的制备，制备方法包括如下：
提供培养皿，清洗培养皿表面，用丙酮浸泡2分钟左右并倒至废液箱，再用异丁醇清洗培养皿表面残留的丙酮，最后用气枪干燥培养皿表面，得到洁净的培养皿表面；
配置PDMS溶液，提供质量比为10:1的A液(5ml左右)与B液的PDMS溶液，用玻璃棒将混合液搅拌至均匀，并将混合溶液倒入玻璃皿中，放入真空机抽真空至液面无气泡，最后将培养皿放置热板120℃加热30分钟，形成平整的保护层；
将两片小芯片与两片硅片表面利用丙酮和异丙醇清洗至洁净，将第一硅片用ECA-1003导电胶与两片小芯片衬底面对称粘合并压紧，用热板120℃加热固化，将第二硅片放在热板上180℃前烘90秒后用旋胶机旋涂PMMA电子胶，再在热板上150℃后烘60秒，得到均匀旋涂电子胶的第二硅片；将旋胶完的第二硅片正放至固化完PDMS的培养皿表面，并将固化好的小芯片-导电胶-硅片整体平压在旋胶的硅片上，在硅片上表面施加压力并放入真空机中抽真空，达到硅片与小芯片之间没有空气的效果；
配置质量比为10:1的PDMS溶液，A液用量在5ml左右，先将配好的PDMS溶液进行抽真空操作，再缓慢倒灌至夹心结构侧边，在操作时要保证上层硅片持续受到恒定压力作用，直至PDMS溶液稍微漫过上层硅片的上表面。将整个装置放置在热板上100℃加热35分钟至上层PDMS固化；
用洁净小刀将夹心结构切取出，将夹心结构放在丙酮中浸泡，至PMMA电子胶溶解，第二硅片从夹心结构中脱落，得到芯片内嵌复合物。
本申请实施例第二方面提供一种用于电子束曝光的芯片内嵌复合物，如附图3所示，芯片内嵌复合物包括第一基底1，设置在第一基底1表面的导电层2，设置在导电层2的背离第一基底1的芯片内嵌层5，且芯片内嵌层5包括与导电层接触的芯片阵列3以及分布在芯片阵列之间的内嵌层6。得到的芯片内嵌复合物的立体图如图5所示。
本申请实施例第二方面提供的用于电子束曝光的芯片内嵌复合物，由于芯片阵列以及设置在芯片阵列之间的内嵌层处于同一水平面，使得到的内嵌复合物可直接进行均匀旋胶，并进行电子束曝光，同时该芯片内嵌复合物能够最大程度利用芯片的光刻面积，不会造成浪费，且设置导电层能够实现导电的作用，保持了复合物整体的导电性，使得在电子束曝光机高压工作过程中，射出的电子穿过芯片表面不会在芯片内部聚集，该产品成品良率高、性能稳定、使用效果优异。
在一些实施例中，内嵌层比芯片阵列的厚度≤15微米，控制内嵌层和芯片的高度差较小，保证能够进行均匀地旋胶处理。
在一些实施例中，成品旋胶后，用SEM电镜观察检测整个结构，若芯片表面可进行SEM观察，则导电性良好，满足电子束曝光导电性的需求。
进一步，为了更好地旋胶，可在芯片内嵌层(即芯片与聚合物材料层)的表面旋涂一层附着促进剂，制造一个更好的平面。可选的，附着促进剂选自六甲基二硅氮烷，六甲基二硅氮烷能够提高个材料的附着力，同时与基底表面的二氧化硅作用，产生一层强力防水层，能有效的防止显影液穿透光刻胶。其厚度没有要求可根据芯片内嵌层的高度差进行调整。
本申请实施例第三方面提供了用于电子束曝光的芯片内嵌复合物在电子束曝光设计集成电路中的应用。
本申请第三方面提供的用于电子束曝光的芯片内嵌复合物应用于电子束曝光设计集成电路，基于该芯片内嵌复合物具有平整的表面，能够直接进行均匀旋胶，可广泛应用于电子束曝光，进行设计集成电路，提高了芯片的利用率。下面结合具体实施例进行说明。
实施例1
用于电子束曝光的芯片内嵌复合物及其制备方法
芯片内嵌复合物的制备方法
该制备方法包括如下步骤：
提供两片未旋胶的光电半导体小芯片(2mm*4mm)、两片(100)晶向P或N掺杂硅片(8mm*10mm)、一个直径为60mm的玻璃皿、10mlPDMS的A液、1mlPDMS的B液(固化剂)、ECA-1003导电胶、PMMA电子胶。所需用到的仪器：恒温热板、旋胶机、氮气枪、抽真空机、台阶仪；
如图5所示，提供一复合结构，其中，复合结构包括第一基底、设置在第一基底表面的导电层和设置在导电层的背离第一基底的表面上的芯片阵列；在芯片阵列的外表面铺设保护层，保护层覆盖芯片阵列：
将两片小芯片与两片硅片表面利用丙酮和异丙醇清洗至洁净，将第一硅片用ECA-1003导电胶与两片小芯片衬底面对称粘合并压紧，用热板120℃加热固化，将第二硅片放在热板上180℃前烘90秒后用旋胶机旋涂PMMA电子胶，再在热板上150℃后烘60秒，得到均匀旋涂电子胶的第二硅片；将旋胶完的第二硅片正放至固化完PDMS的培养皿表面，并将固化好的小芯片-导电胶-硅片整体平压在旋胶的硅片上，在硅片上表面施加压力并放入真空机中抽真空，达到硅片与小芯片之间没有空气的效果；
采用聚合物溶液对复合结构和保护层进行封装固化处理：
提供直径为60mm的玻璃培养皿，清洗培养皿表面，用丙酮浸泡2分钟左右并倒至废液箱，再用异丁醇清洗培养皿表面残留的丙酮，最后用气枪干燥培养皿表面，得到洁净的培养皿表面；
配置PDMS溶液，提供质量比为10:1的A液(5ml左右)与B液的PDMS溶液，用玻璃棒将混合液搅拌至均匀，并将混合溶液倒入玻璃皿中，放入真空机抽真空至液面无气泡，最后将培养皿放置热板100℃加热30分钟，形成平整的保护层；
配置质量比为10:1的PDMS溶液，A液用量在5ml左右，先将配好的PDMS溶液进行抽真空操作，再缓慢倒灌至夹心结构侧边，在操作时要保证上层硅片持续受到恒定压力作用，直至PDMS溶液稍微漫过上层硅片的上表面。将整个装置放置在热板上100℃加热30分钟至上层PDMS固化；
除去保护层，得到芯片内嵌复合物：
用洁净小刀将夹心结构切取出，将夹心结构放在丙酮中浸泡，至PMMA电子胶溶解，第二硅片从夹心结构中脱落，得到芯片内嵌复合物。
芯片内嵌复合物
芯片内嵌复合物包括第一基底，设置在第一基底表面的导电层，设置在导电层背离第一基底的芯片内嵌层，且芯片内嵌层包括芯片阵列以及设置在芯片阵列之间的内嵌层。
实施例2
用于电子束曝光的芯片内嵌复合物及其制备方法
芯片内嵌复合物的制备方法
该制备方法包括如下步骤：
提供两片未旋胶的光电半导体小芯片(2mm*4mm)、两片(100)晶向P或N掺杂硅片(8mm*10mm)、一个直径为60mm的玻璃皿、10mlPDMS的A液、1mlPDMS的B液(固化剂)、ECA-1003导电胶、PMMA电子胶。所需用到的仪器：恒温热板、旋胶机、氮气枪、抽真空机、台阶仪；
提供一复合结构，其中，复合结构包括第一基底、设置在第一基底表面的导电层和设置在导电层的背离第一基底的表面上的芯片阵列；在芯片阵列的外表面铺设保护层，保护层覆盖芯片阵列：
将两片小芯片与两片硅片表面利用丙酮和异丙醇清洗至洁净，将第一硅片用ECA-1003导电胶与两片小芯片衬底面对称粘合并压紧，用热板120℃加热固化，并将固化好的小芯片-导电胶-硅片整体平压在PDMS上，施加向下的压力后抽真空；
采用聚合物溶液对复合结构和保护层进行封装固化处理：
提供直径为60mm的玻璃培养皿，清洗培养皿表面，用丙酮浸泡2分钟左右并倒至废液箱，再用异丁醇清洗培养皿表面残留的丙酮，最后用气枪干燥培养皿表面，得到洁净的培养皿表面；
配置PDMS溶液，提供质量比为10:1.2的A液(5ml左右)与B液的PDMS溶液，用玻璃棒将混合液搅拌至均匀，并将混合溶液倒入玻璃皿中，放入真空机抽真空至液面无气泡，最后将培养皿放置热板100℃加热30分钟，形成平整的保护层；
配置质量比为10:1.2的PDMS溶液，A液用量在5ml左右，先将配好的PDMS溶液进行抽真空操作，再缓慢倒灌至夹心结构侧边，在操作时要保证上层硅片持续受到恒定压力作用，直至PDMS溶液稍微漫过上层硅片的上表面。将整个装置放置在热板上120℃加热35分钟至上层PDMS固化；
除去保护层，得到芯片内嵌复合物：
用洁净小刀将芯片内嵌复合物取出，将芯片内嵌复合物放在丙酮中浸泡清洗，得到芯片内嵌复合物。
芯片内嵌复合物
芯片内嵌复合物包括第一基底，设置在第一基底表面的导电层，设置在导电层背离第一基底的芯片内嵌层，且芯片内嵌层包括芯片阵列以及设置在芯片阵列之间的内嵌层。
实施例3
用于电子束曝光的芯片内嵌复合物及其制备方法
芯片内嵌复合物的制备方法
该制备方法包括如下步骤：
提供两片未旋胶的光电半导体小芯片(2mm*4mm)、两片(100)晶向P或N掺杂硅片(8mm*10mm)、一个直径为60mm的玻璃皿、苯并环丁烯混合液(BCB溶液)、ECA-1003导电胶、PMMA电子胶。所需用到的仪器：恒温热板、旋胶机、氮气枪、抽真空机、台阶仪；
提供一复合结构，其中，复合结构包括第一基底、设置在第一基底表面的导电层和设置在导电层的背离第一基底的表面上的芯片阵列；在芯片阵列的外表面铺设保护层，保护层覆盖芯片阵列：
将两片小芯片与两片硅片表面利用丙酮和异丙醇清洗至洁净，将第一硅片用ECA-1003导电胶与两片小芯片衬底面对称粘合并压紧，用热板120℃加热固化，将第二硅片放在热板上180℃前烘90秒后用旋胶机旋涂PMMA电子胶，再在热板上150℃后烘60秒，得到均匀旋涂电子胶的第二硅片；将旋胶完的第二硅片正放至固化完BCB的培养皿表面，并将固化好的小芯片-导电胶-硅片整体平压在旋胶的硅片上，在硅片上表面施加压力并放入真空机中抽真空，达到硅片与小芯片之间没有空气的效果；
采用聚合物溶液对复合结构和保护层进行封装固化处理：
提供直径为60mm的玻璃培养皿，清洗培养皿表面，用丙酮浸泡2分钟左右并倒至废液箱，再用异丁醇清洗培养皿表面残留的丙酮，最后用气枪干燥培养皿表面，得到洁净的培养皿表面；
配置BCB溶液，提供质量比为10:1的A液(5ml左右)与B液的BCB溶液，用玻璃棒将混合液搅拌至均匀，并将混合溶液倒入玻璃皿中，放入真空机抽真空至液面无气泡，最后将培养皿放置热板100℃加热30分钟，形成平整的保护层；
配置质量比为10:1的BCB溶液，A液用量在5ml左右，先将配好的BCB溶液进行抽真空操作，再缓慢倒灌至夹心结构侧边，在操作时要保证上层硅片持续受到恒定压力作用，直至BCB溶液稍微漫过上层硅片的上表面。将整个装置放置在热板上100℃加热30分钟至上层BCB固化；
除去保护层，得到芯片内嵌复合物：
用洁净小刀将夹心结构切取出，将夹心结构放在丙酮中浸泡，至PMMA电子胶溶解，第二硅片从夹心结构中脱落，得到芯片内嵌复合物。
芯片内嵌复合物
芯片内嵌复合物包括第一基底，设置在第一基底表面的导电层，设置在导电层背离第一基底的芯片内嵌层，且芯片内嵌层包括芯片阵列以及设置在芯片阵列之间的内嵌层。
性质测试：
如图6所示，将实施例1～3得到的芯片内嵌复合物进行旋胶处理，提供台阶仪，分别测定旋胶前聚合物和芯片表面的高度差，旋胶后聚合物和芯片表面的高度差以及旋胶后芯片表面的粗糙度，并进行统计和分析。
结果分析：
实施例1～3得到的芯片内嵌复合物分别测定旋胶前聚合物和芯片表面的高度差，旋胶后聚合物和芯片表面的高度差以及旋胶后芯片表面的粗糙度的数据如下表1所示，由下表1所示，实施例1中旋胶前聚合物与芯片表面为9837.06nm，旋胶后聚合物与芯片表面为3398.62nm，旋胶后芯片的粗糙度为3nm；实施例2中旋胶前聚合物与芯片表面为9830.06nm，旋胶后聚合物与芯片表面为3390.62nm，旋胶后芯片的粗糙度为4nm；实施例3中旋胶前聚合物与芯片表面为9835.06nm，旋胶后聚合物与芯片表面为3392.62nm，旋胶后芯片的粗糙度为5nm。
综上，本申请提供的用于电子束曝光的芯片内嵌复合物的制备方法，该制备方法以包 括芯片的复合结构为原材料，将该复合结构放置于容器中，且控制复合结构中的芯片与提供的容器的软底面接触，进一步加入聚合物溶液进行固化处理，在阵列芯片的间隔形成内嵌层，得到芯片内嵌复合物；该制备方法得到的芯片内嵌复合物包括设置在芯片阵列之间、且与芯片表面在同一水平线的内嵌层，使得芯片表面可直接进行均匀旋胶，并进行电子束曝光，可充分利用芯片的光刻面积，实现将小芯片进行固化过程中不会造成光刻面积的浪费，且能够充分利用小规格的芯片，提高芯片的利用率，同时复合结构中包括一导电层，能够实现地面导电，有利于应用与电子束曝光处理；该制备方法节约贵重耗材、用料成本低、制作工艺简单、操作便捷、操作时间短，得到的芯片内嵌复合物成品良率高、性能稳定、操作容错率高，有利于广泛使用。
表1
Figure PCTCN2022072513-appb-000001
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所做的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种用于电子束曝光的芯片内嵌复合物的制备方法，其特征在于，包括如下步骤：
    提供一复合结构，其中，所述复合结构包括第一基底、设置在所述第一基底表面的导电层和设置在所述导电层的背离所述第一基底的表面上的芯片阵列；
    在所述芯片阵列的外表面铺设保护层，所述保护层覆盖所述芯片阵列；
    采用聚合物溶液对所述复合结构和所述保护层进行封装固化处理；
    除去所述保护层，得到芯片内嵌复合物。
  2. 根据权利要求1所述的用于电子束曝光的芯片内嵌复合物的制备方法，其特征在于，所述保护层选自表面平整的软膜层或硬基底复合物；
    其中，所述硬基底复合物包括第二基底和连接层，且沿所述导电层至所述芯片阵列的延伸方向，所述连接层和所述第二基底依次层叠，且所述连接层覆盖所述芯片阵列。
  3. 根据权利要求1所述的用于电子束曝光的芯片内嵌复合物的制备方法，其特征在于，所述聚合物溶液的材料选自聚二甲基硅氧烷、苯并环丁烯、环氧树脂、二甲基硅氧烷，环甲基硅氧烷，氨基硅氧烷，聚甲基苯基硅氧烷，聚醚聚硅氧烷共聚物中的至少一种。
  4. 根据权利要求1～3任一所述的用于电子束曝光的芯片内嵌复合物的制备方法，其特征在于，采用聚合物溶液对所述复合结构和保护层进行封装固化处理的步骤中，包括：对所述复合结构和保护层施加压力，加入聚合物溶液填充后，进行封装固化处理。
  5. 根据权利要求4所述的用于电子束曝光的芯片内嵌复合物的制备方法，其特征在于，所述压力为10～40N。
  6. 根据权利要求1～3任一所述的用于电子束曝光的芯片内嵌复合物的制备方法，其特征在于，除去所述保护层的步骤中，包括：对所述保护层进行切割去除，并采用有机溶剂进行清洗。
  7. 根据权利要求1～3任一所述的用于电子束曝光的芯片内嵌复合物的制备方法，其特征在于，所述芯片的大小为(2～3)mm×(4～5)mm。
  8. 一种用于电子束曝光的芯片内嵌复合物，其特征在于，所述芯片内嵌复合物包括第一基底，设置在所述第一基底表面的导电层，设置在所述导电层的背离所述第一基底的芯片内嵌层，且所述芯片内嵌层包括与所述导电层接触的芯片阵列以及分布在芯片阵列之间的内嵌层。
  9. 根据权利要求8所述的用于电子束曝光的芯片内嵌复合物，其特征在于，所述内嵌层比所述芯片阵列的厚度≤15微米。
  10. 权利要求8或9所述的用于电子束曝光的芯片内嵌复合物在电子束曝光设计集成电路中的应用。
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