WO2022151711A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022151711A1
WO2022151711A1 PCT/CN2021/109964 CN2021109964W WO2022151711A1 WO 2022151711 A1 WO2022151711 A1 WO 2022151711A1 CN 2021109964 W CN2021109964 W CN 2021109964W WO 2022151711 A1 WO2022151711 A1 WO 2022151711A1
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metal layer
magnetic core
layer
substrate
dielectric layer
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PCT/CN2021/109964
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English (en)
French (fr)
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吴桐
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长鑫存储技术有限公司
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Priority to US17/662,257 priority Critical patent/US20220262556A1/en
Publication of WO2022151711A1 publication Critical patent/WO2022151711A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/04—Fixed inductances of the signal type  with magnetic core
    • H01F17/06—Fixed inductances of the signal type  with magnetic core with core substantially closed in itself, e.g. toroid
    • H01F17/062—Toroidal core with turns of coil around it
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/0206—Manufacturing of magnetic cores by mechanical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041—Printed circuit coils
    • H01F41/046—Printed circuit coils structurally combined with ferromagnetic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of fabricating the same.
  • Inductors are the basic components of electronic products, and micro-inductors are widely used in RF MEMS and micro-actuators.
  • the micro-inductor can be used as the energy storage element of the switch mode power supply (SMPS, Switch Mode Power Supply).
  • SMPS switch mode power supply
  • PwrSiP package power supply
  • PwrSoC Power Supply on Chip
  • the development direction of PwrSoC is to integrate all power electronic components on one chip to achieve higher integration, low cost, high efficiency and power density.
  • Inductor requirements for PwrSoC technology include compact physical size, high current capacity, and high quality factor.
  • the size of the chip is also continuously reduced, and higher requirements are placed on the size and electrical performance of the inductor integrated on the chip.
  • the present disclosure provides a semiconductor structure and a method for fabricating the same.
  • a first aspect of the present disclosure provides a semiconductor structure comprising: a base having opposing first and second faces; and a magnetic core in the base, the magnetic core in the base
  • the orthographic projection on the first surface is a closed annular figure; a dielectric layer, the dielectric layer is located on the second surface; a solenoid-shaped metal layer, the metal layer is located in the substrate and the dielectric layer and surrounds the It is arranged around the magnetic core, there is a space between the metal layer and the magnetic core, a part of the metal layer is exposed on the first surface, and a part of the metal layer is exposed on the surface of the dielectric layer away from the base.
  • Floor is arranged around the magnetic core, there is a space between the metal layer and the magnetic core, a part of the metal layer is exposed on the first surface, and a part of the metal layer is exposed on the surface of the dielectric layer away from the base.
  • a second aspect of the present disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate having opposite first and second surfaces, and having a magnetic core in the substrate, the magnetic core on the The orthographic projection on the first surface is a closed ring pattern; a dielectric layer is formed on the second surface; the substrate and the dielectric layer are etched to form a continuous groove in a solenoid shape, and the continuous groove is wound around the It is arranged around the magnetic core, there is a gap between the continuous groove and the magnetic core, the first surface exposes part of the continuous groove, and the surface of the dielectric layer away from the substrate exposes the part. the continuous trench; and a metal layer is formed in the continuous trench.
  • a magnetic core is provided in the substrate, and the orthographic projection of the magnetic core on the first surface of the substrate is a closed annular figure, and a medium is located on the second surface of the substrate
  • Both the layer and the substrate have a metal layer, and the metal layer is wound around the magnetic core, then the metal layer and the magnetic core together form a three-dimensional solenoid inductor in the semiconductor structure, which is beneficial to reduce the solenoid inductor on the surface of the substrate.
  • the solenoid inductor it is beneficial to realize the small and compact solenoid inductor, and improve the quality factor of the solenoid inductor by winding the metal layer on the magnetic core, thereby improving the electrical performance of the solenoid inductor and work efficiency.
  • the metal layer itself will generate heat due to the current heating effect. Since part of the metal layer is exposed on the first surface of the substrate, and part of the metal layer is exposed on the surface of the dielectric layer away from the substrate, then part of the metal layer is exposed. The metal layer is exposed to the air, which is beneficial to ensure the good heat dissipation effect of the solenoid inductor.
  • an embodiment of the present disclosure also provides a method for forming a semiconductor structure.
  • a magnetic core is formed in a substrate, a metal layer in a solenoid shape is formed in the substrate and a dielectric layer, and the metal layer is wound around the magnetic core.
  • the magnetic permeability of the solenoid inductor is improved, thereby helping to improve the inductance of the solenoid inductor, thereby improving the electrical performance of the solenoid inductor.
  • the method for forming the semiconductor structure provided by the embodiments of the present disclosure is highly compatible with the semiconductor fabrication process.
  • FIG. 1 is a schematic top-view structural diagram of a semiconductor structure provided by a first embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a stepped cross-sectional structure along the II1 direction of FIG. 1;
  • FIG. 3 is a schematic view of the stepped cross-sectional structure of FIG. 1 along the JJ1 direction;
  • FIG. 4 is a schematic top-view structural diagram of a first through hole in the first embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram after depositing a metal material layer on the first surface of the substrate and the trench;
  • FIG. 6 is a schematic top view of the structure shown in FIG. 5 after the structure shown in FIG. 5 is planarized to form a magnetic core;
  • FIG. 7 is a schematic view of the stepped cross-sectional structure of FIG. 6 along the AA1 direction;
  • FIG. 8 is a schematic top view of the structure after forming a plurality of second through holes in the substrate in the structure shown in FIG. 6;
  • FIG. 9 is a schematic view of the stepped cross-sectional structure of FIG. 8 along the BB1 direction;
  • FIG. 10 is a schematic top view of the structure shown in FIG. 8 after the first filling layer is formed in the second through hole;
  • FIG. 11 is a schematic view of the stepped cross-sectional structure of FIG. 10 along the CC1 direction;
  • FIG. 12 is a schematic view of the structure after forming a plurality of third through holes on the dielectric layer on the second surface of the substrate in the structure shown in FIG. 11;
  • FIG. 13 is a schematic top view of the structure after forming a second filling layer in the third through hole in the structure shown in FIG. 12;
  • FIG. 14 is a schematic view of the stepped cross-sectional structure of FIG. 13 along the DD1 direction;
  • FIG. 15 is a schematic top view of the structure after forming a plurality of first grooves and second grooves in the structure shown in FIG. 13;
  • FIG. 16 is a schematic view of the stepped cross-sectional structure of FIG. 15 along the EE1 direction;
  • FIG. 17 is a schematic view of the stepped cross-sectional structure of FIG. 15 along the FF1 direction;
  • FIG. 18 is a schematic top view of the structure shown in FIG. 15 after forming continuous trenches
  • FIG. 19 is a schematic view of the stepped cross-sectional structure of FIG. 18 along the GG1 direction;
  • FIG. 20 is a schematic structural diagram after forming a plurality of through holes according to an embodiment of the disclosure.
  • FIG. 21 is a schematic structural diagram of the through hole in the structure shown in FIG. 20 after forming a third filling layer
  • Figure 22 is a schematic view of the structure after forming a plurality of first grooves and second grooves in the structure shown in Figure 21;
  • FIG. 23 is a schematic view of the structure after forming the base metal layer in the structure shown in FIG. 22;
  • FIG. 24 is a schematic top view of the structure shown in FIG. 23 after the metal layer is formed;
  • FIG. 25 is a schematic diagram of a stepped cross-sectional structure along the HH1 direction of FIG. 24 .
  • the inductor is a basic power electronic component.
  • PwrSoC power supply on chip
  • the inductors used in semiconductor structures are usually planar inductors, that is, inductors in which a metal layer is wound on the surface of a substrate or a dielectric layer. It is not conducive to reducing the fabrication cost of the semiconductor structure and reducing the space occupied by the inductor in the semiconductor structure by removing the metal layer or increasing the thickness of the metal layer to reduce the resistance in the inductor.
  • Embodiments of the present disclosure provide a semiconductor structure with a magnetic core in a substrate, and the orthographic projection of the magnetic core on a first surface of the substrate is a closed annular pattern, and a dielectric layer on the second surface of the substrate and the substrate have Metal layer, and the metal layer is wound around the magnetic core, then the metal layer and the magnetic core together form a three-dimensional solenoid inductor in the semiconductor structure, which is beneficial to reduce the orthographic projection area of the solenoid inductor on the surface of the substrate, so It is beneficial to reduce the space occupied by the solenoid inductor in the semiconductor structure, and at the same time, the quality factor of the solenoid inductor is improved by winding the metal layer on the magnetic core, thereby improving the electrical performance and the electrical performance of the solenoid inductor.
  • part of the metal layer is exposed on the first surface of the substrate, and part of the metal layer is exposed on the surface of the dielectric layer away from the substrate, part of the metal layer is exposed to the air, which is beneficial to ensure the good heat dissipation effect of the solenoid inductor.
  • FIG. 1 is a schematic top view of the semiconductor structure provided by the first embodiment of the present disclosure
  • FIG. 2 is a schematic view of a stepped cross-sectional structure of FIG. 1 along the direction II1
  • FIG. 3 is a schematic view of the stepped cross-sectional structure of FIG. 1 along the direction of JJ1
  • the semiconductor structure includes: a substrate 100 having opposite first faces a and second faces b; a magnetic core 101 , the magnetic core 101 is located in the substrate 100 , and the magnetic core 101 is on the first face a
  • the orthographic projection on it is a closed ring pattern; the dielectric layer 102, the dielectric layer 102 is located on the second surface b; the solenoid-shaped metal layer 103, the metal layer 103 is located in the substrate 100 and the dielectric layer 102 and is wound around the magnetic core 101.
  • the metal layer 103 is integrally formed to prevent the metal layer 103 from having a large contact resistance in its own structure, thereby helping to improve the overall conductivity of the metal layer 103 and thus improving the quality of the solenoid inductor. factor.
  • preparing the metal layer 103 by one-time molding is beneficial to simplify the manufacturing process steps of the metal layer 103 .
  • the magnetic core 101 is located in the substrate 100 , and the orthographic projection of the magnetic core 101 on the first surface a of the substrate 100 is a closed annular shape, and the metal layer 103 is wound around the magnetic core 101 .
  • the orthographic projection area of the solenoid inductor on the substrate 100 is beneficial to realize the small and compact physical size of the solenoid inductor
  • By winding the metal layer 103 on the magnetic core 101 it is beneficial to improve the quality factor of the solenoid inductor, thereby improving the electrical performance and working efficiency of the solenoid inductor.
  • the orthographic projection of the magnetic core 101 on the first surface a is a closed circular shape.
  • the orthographic projection of the magnetic core 101 on the first surface may also be a closed elliptical ring shape or a closed square ring shape.
  • the material of the magnetic core 101 can be a high magnetic permeability material such as iron-nickel alloy, iron-nickel-zinc alloy or iron-nickel-molybdenum alloy, which is beneficial to further improve the inductance of the solenoid inductor, thereby further improving the quality of the solenoid inductor factor.
  • the materials of the substrate 100 and the dielectric layer 102 may be at least one of silicon-containing materials such as silicon, silicon germanium, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or silicon oxycarbide.
  • the material of the substrate 100 is silicon
  • the material of the dielectric layer 102 is silicon oxide, which is beneficial to improve the compatibility between the forming process of the solenoid inductor and the common semiconductor manufacturing process.
  • the material of the metal layer 103 may be at least one of metal materials such as copper, silver, tungsten, titanium, gold, nickel or palladium.
  • the material of the metal layer 103 is copper. Since copper has low cost and excellent electrical conductivity, it is beneficial to reduce the resistance of the metal layer 103 while avoiding the high cost of the material of the metal layer 103, which is conducive to further improving the The inductance of the solenoid inductor and the avoidance of excessive manufacturing cost of the solenoid inductor.
  • the metal layer 103 includes: a plurality of first metal layers 113 located in the substrate 100 , the first metal layers 113 are located on the side of the magnetic core 101 facing the first surface a, and the first metal layers 113
  • the orthographic projection on the first surface a intersects the orthographic projection of the magnetic core 101 on the first surface a; the plurality of second metal layers 123 penetrating the substrate 100 and the dielectric layer 102 ; and the plurality of third metal layers located in the dielectric layer 102 layer 133, and the orthographic projection of the third metal layer 133 on the first surface a intersects with the orthographic projection of the magnetic core 101 on the first surface a;
  • the first metal layers 113 are electrically connected.
  • a base 100 between the first metal layer 113 and the magnetic core 101 There is a base 100 between the first metal layer 113 and the magnetic core 101 ; a base 100 and a dielectric layer 102 between the second metal layer 123 and the magnetic core 101 ; and a dielectric layer 102 between the third metal layer 133 and the magnetic core 101 .
  • the first metal layer 113 and the third metal layer 133 are both elongated, and the width of the first metal layer 113 along the direction perpendicular to the extending direction of the first metal layer 113 is the same as the width of the third metal layer 133 along the direction perpendicular to the third metal layer 133.
  • the width of the metal layer 133 in the extending direction is the same
  • the orthographic projection of the second metal layer 123 on the first surface a is a circle
  • the diameter of the second metal layer 123 is the same as the width of the third metal layer 133 .
  • the orthographic projection of the second metal layer on the first surface may also be a square or an ellipse.
  • the distance between the first metal layer 113 and the magnetic core 101 is not less than 20 nm. In one example, the distance between the first metal layer 113 and the magnetic core 101 is 25 nm, which is beneficial to reduce the parasitic capacitance between the first metal layer 113 and the magnetic core 101 , thereby improving the filtering effect of the solenoid inductor. , to improve the working efficiency of the solenoid inductor.
  • the distance range between the second metal layer 123 and the magnetic core 101 is the same as the distance range between the first metal layer 113 and the magnetic core 101 , and the distance range between the third metal layer 133 and the magnetic core 101 is the same.
  • the range of the distance between the first metal layer 113 and the magnetic core 101 is also the same.
  • the distance between the second metal layer 123 and the magnetic core 101 and the distance between the third metal layer 133 and the magnetic core 101 are the same as the distance between the first metal layer 113 and the magnetic core 101 , both is 25nm, which is beneficial to reduce the parasitic capacitance between the second metal layer 123 and the magnetic core 101 and reduce the parasitic capacitance between the third metal layer 133 and the magnetic core 101, thereby helping to improve the filtering effect of the solenoid inductor, Improves the operating efficiency of solenoid inductors.
  • the thickness of the first metal layer 113 ranges from 50 nm to 400 nm. In an example, if the thickness of the first metal layer 113 is 100 nm, the resistance value of the first metal layer 113 is small, which is beneficial to reduce the solenoid inductance while ensuring the solenoid inductor has a high quality factor. This reduces the space occupied by the device in the semiconductor structure, which is beneficial to improve the space utilization of the semiconductor structure and facilitate the integration of more compact-sized power electronic components on the same chip.
  • the thickness range of the third metal layer 133 is the same as the thickness range of the first metal layer 113 ; the second metal layer 123 extends along the direction perpendicular to the second metal layer 123 The thickness range in the direction of the direction is the same as the thickness range of the first metal layer 113 .
  • the thicknesses of the second metal layer 123 and the third metal layer 133 are both the same as the thickness of the first metal layer 113, both being 100 nm, so the resistance values of the second metal layer 123 and the third metal layer 133 are both smaller, which is also beneficial to While ensuring that the solenoid inductor has a high quality factor, the space occupied by the solenoid inductor in the semiconductor structure is reduced, thereby helping to improve the space utilization rate of the semiconductor structure.
  • the spacing between adjacent first metal layers 113 is not less than 10 nm. In one example, the distance between the adjacent first metal layers 113 is 15 nm, which is beneficial to reduce the parasitic capacitance between the adjacent first metal layers 113, thereby helping to improve the filtering effect of the solenoid inductor and improve the solenoid effect. Line-pipe inductor operating efficiency.
  • the semiconductor structure further includes: a first through hole 104 , the first through hole 104 penetrates the substrate 100 and the dielectric layer 102 , and the first through hole 104 exposes part of the magnetic core 101 and part of the metal layer 103 , then part of the magnetic core 101 and part of the metal layer 103 are in contact with the substrate 100 and the dielectric layer 102, so that the magnetic core 101 and the metal layer 103 are fixed in the semiconductor structure, and the first through hole 104 is beneficial to increase the exposure of the solenoid inductor to the air.
  • the area is increased, that is, the heat dissipation area of the solenoid inductor is increased, which is beneficial to further improve the heat dissipation effect of the solenoid inductor.
  • the central axis of the first through hole 104 is coincident with the central axis of the magnetic core 101, so that the areas where the magnetic core 101 and the metal layer 103 are fixed by the substrate 100 and the dielectric layer 102 are evenly distributed in all directions, which is beneficial for increasing the size of the solenoid. While maintaining the heat dissipation area of the inductor, it is ensured that the magnetic core 101 and the metal layer 103 are uniformly stressed.
  • the orthographic projection of the magnetic core 101 on the surface of the substrate 100 is a ring. Referring to FIG.
  • the orthographic projection of the first through hole 104 on the substrate 100 consists of a circle 114 and at least one located at the edge of the circle 114 and protruding out of the circle 114
  • the diameter of the circle 114 is smaller than the maximum diameter of the ring, and the convex pattern 124 protrudes from the outer edge of the circle 114 .
  • the number of raised patterns 124 is 8, and the 8 raised patterns are evenly distributed around the circle 114.
  • the number of raised patterns may also be 1, 2, 4, and so on. It should be noted that, under the condition that the magnetic core 101 and the metal layer 103 are guaranteed to be fixed on the substrate 100 and the dielectric layer 102, the number of the raised patterns 124 is not limited.
  • the orthographic projection of the first through hole 104 on the substrate 100 is an axisymmetric figure, so that the area where the magnetic core 101 and the metal layer 103 are fixed by the substrate 100 and the dielectric layer 102 is symmetrically distributed, which is beneficial to increase the heat dissipation of the solenoid inductor. At the same time, it is ensured that the forces received by the magnetic core 101 and the metal layer 103 from the substrate 100 and the dielectric layer 102 are symmetrically distributed in the magnetic core 101 and the metal layer 103 .
  • the orthographic projection of the magnetic core on the surface of the base is a circle
  • the orthographic projection of the first through hole on the base may be a circle
  • the diameter of the circle is smaller than the maximum diameter of the circle.
  • the semiconductor structure may further include: a first lead 143 and a second lead 153, the first lead 143 is electrically connected to one end of the metal layer 103, the second lead 153 is electrically connected to the other end of the metal layer 103, and the first lead 143 is electrically connected to one end of the metal layer 103.
  • the first lead 143, the second lead 153 and the metal layer 103 are integrally formed into a structure, and the first lead 143, the second lead 153 and the metal layer 103 can be jointly prepared by one molding, avoiding the first lead 143 and the second lead 153 and the metal layer 103.
  • Contact resistance is generated between the layers 103 , which is beneficial to improve the electrical conductivity between the first lead 143 and the second lead 153 and the metal layer 103 .
  • the first lead 143 is electrically connected to a third metal layer 133
  • the second lead 153 is electrically connected to a second metal layer 123
  • the first lead, the second lead and the metal layer may not be integrally formed, the first lead may be electrically connected to the second metal layer or the first metal layer, and the second lead may be connected to the third metal layer Or the first metal layer is electrically connected.
  • the semiconductor structure provided by the first embodiment of the present disclosure there is a metal layer 103 wound around the magnetic core 101, and the metal layer 103 and the magnetic core 101 together constitute a three-dimensional solenoid inductor in the semiconductor structure.
  • the orthographic projection area of the solenoid inductor on the surface of the substrate 100 is small. Since the magnetic core 101 is beneficial to improve the magnetic permeability of the solenoid inductor, it is beneficial to improve the quality factor of the solenoid inductor at the same time. , to achieve a small and compact physical size of the solenoid inductor, so as to reduce the footprint of the solenoid inductor in the semiconductor structure.
  • the metal layer 103 since a part of the metal layer 103 is exposed on the first side a of the substrate 100 , a part of the metal layer 103 is exposed on the surface of the dielectric layer 102 away from the substrate 100 , and part of the magnetic core 101 and part of the metal layer 103 are exposed through the first through hole 104 .
  • the second embodiment of the present disclosure further provides a method for fabricating a semiconductor structure for fabricating the above-mentioned semiconductor structure.
  • 5 to 7 are schematic structural diagrams corresponding to each step of a method for fabricating a magnetic core in the second embodiment of the disclosure;
  • FIGS. 8 to 19 are structures corresponding to each step of a method for fabricating a continuous groove in the second embodiment of the disclosure.
  • FIGS. 20 to 22 are schematic structural diagrams corresponding to the steps of another method for fabricating a continuous trench in the second embodiment of the present disclosure;
  • FIGS. 23 to 25 are the steps of the fabrication method of the metal layer in the second embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a stepped cross-sectional structure along the AA1 direction of FIG. 6 , providing a substrate 100 , the substrate 100 has opposite first surfaces a and second surfaces b, and the substrate 100 has a magnetic core 101 inside the magnetic core 101 .
  • the orthographic projection of the core 101 on the first surface a is a closed annular figure.
  • the process steps of forming the magnetic core 101 include:
  • the second surface b is etched to form a trench, and the orthographic projection of the trench on the first surface a is a closed annular pattern; a layer of metal material 111 is deposited in the trench and on the second surface b; The material layer 111 is planarized to expose the surface of the substrate 100 to form the magnetic core 101 .
  • Methods of planarization include chemical mechanical polishing.
  • the method for forming the trench includes pattern-dry etching.
  • the method for depositing the metal material layer 111 includes physical vapor deposition (including PVD, sputtering, etc.), chemical vapor deposition or spraying, etc.
  • the metal material layer 111 may be a high-grade iron-nickel alloy, an iron-nickel-zinc alloy, or an iron-nickel-molybdenum alloy. Magnetic permeability material.
  • a solenoid-shaped continuous groove 105 is formed on the substrate 100 and the dielectric layer 102 , and the continuous groove 105 is wound around the magnetic core 101 .
  • the first surface a exposes part of the continuous trench 105
  • the surface of the dielectric layer 102 away from the substrate 100 exposes part of the continuous trench 105 .
  • a partial area of the continuous trench 105 is formed in the substrate 100 , and then a portion of the continuous trench 105 is formed in the substrate 100 .
  • a dielectric layer is formed on the face b, and the remaining area of the continuous trench 105 is formed in the dielectric layer 102 .
  • FIG. 9 is a schematic diagram of a stepped cross-sectional structure along the BB1 direction of FIG. 8 .
  • the substrate 100 is etched to form a plurality of second through holes 115 , the second through holes 115 penetrate through the substrate 100 , and the second through holes 115 are located on opposite sides of the magnetic core 101 .
  • the orthographic projection of the magnetic core 101 on the first surface is a closed annular figure, the orthographic projection of part of the second through holes 115 on the first surface a is located in the area enclosed by the closed annular figure, and the remaining second through holes 115 are in the first surface a.
  • the orthographic projection of face a is outside the area enclosed by the closed annular figure.
  • the method for forming the second through hole 115 includes pattern-dry etching.
  • a deep reactive ion etching process may be used to etch the substrate 100 to form the second through holes 115 .
  • other dry etching processes may also be used to etch the substrate to form the second through hole.
  • FIG. 11 is a schematic diagram of a stepped cross-sectional structure along the CC1 direction of FIG. 10 .
  • the first filling layer 116 is formed in the second through hole 115 to prevent the dielectric layer from being formed in the second through hole 115 when the dielectric layer is subsequently formed on the second surface of the substrate 100 , which is not conducive to the subsequent removal of the second through hole 115 impurities.
  • FIG. 14 is a schematic diagram of a stepped cross-sectional structure of FIG. 13 along the DD1 direction.
  • a dielectric layer 102 is formed on the second surface b; the dielectric layer 102 is etched to form a plurality of third through holes 125 , and the third through holes 125 penetrate through the dielectric layer 102 and expose the first filling layer 116 .
  • a second filling layer 126 is formed in the third through hole 125 with reference to FIGS. 13 and 14 .
  • FIG. 16 is a schematic view of the stepped cross-sectional structure of FIG. 15 along the direction of EE1
  • FIG. 17 is a schematic view of the stepped cross-sectional structure of FIG. 15 along the direction of FF1 .
  • the first surface a is etched to form a plurality of first grooves 135
  • the first filling layer 116 is exposed at both ends of the first grooves 135 .
  • a side of the dielectric layer 102 away from the substrate 100 is etched to form a plurality of second grooves 145
  • the second filling layer 126 is exposed at both ends of the second grooves 145 .
  • the first groove 135 when the first groove 135 is formed, part of the first filling layer 116 is also etched while the first surface a is etched; when the second groove 145 is formed, the etching medium layer 102 is far away from the substrate 100 . At the same time, the second filling layer 126 is also etched, after the subsequent removal of the first filling layer 116 and the second filling layer 126, the first groove 135 can be guaranteed within a certain process error range.
  • the continuous trench 105 has good connectivity, thereby ensuring good conductivity of the metal layer formed in the subsequent continuous trench 105.
  • FIG. 19 is a schematic diagram of a stepped cross-sectional structure of FIG. 18 along the GG1 direction.
  • the first filling layer 116 and the second filling layer 126 are removed, and the second through hole 115 , the third through hole 125 , the first groove 135 and the second groove 145 form the continuous trench 105 together.
  • the materials of the first filling layer 116 and the second filling layer 126 are the same, which facilitates the subsequent removal of the first filling layer 116 and the second filling layer 126 together.
  • the first filling layer 116 and the second filling layer 126 are both organic compounds, and the first filling layer 116 and the second filling layer 126 may be removed simultaneously by an ashing process. Pour oxygen into the chamber, and control the relevant parameters in the chamber, so that the first filling layer 116 and the second filling layer 126 react with oxygen to generate gas, so that the first filling layer 116 and the second filling layer 126 remove.
  • a dielectric layer 102 is first formed on the second surface b of the substrate 100 , and then the substrate 100 and the dielectric layer 102 are etched to form continuous trenches 105 .
  • the process steps of forming the continuous trench 105 are as follows:
  • the substrate 100 and the dielectric layer 102 are etched to form a plurality of through holes 155 .
  • the through holes 155 penetrate through the substrate 100 and the dielectric layer 102 , and the through holes 155 are located on both sides of the magnetic core 101 .
  • the third filling layer 136 is formed in the through hole 155, and in the subsequent process steps of etching the substrate 100 and the dielectric layer 102 again, the first surface a of the substrate 100 and the side of the dielectric layer 102 away from the substrate 100 are coated with
  • the material of the third filling layer 136 is an organic compound.
  • the first surface a of the substrate 100 is etched to form a plurality of first grooves 135; the side of the dielectric layer 102 away from the substrate 100 is etched to form a plurality of second grooves 145; the third filling layer 136 is removed , and the second grooves 145 are respectively communicated with two adjacent first grooves 135 through through holes 155 (refer to FIG. 20 ), a plurality of first grooves 135 , a plurality of through holes 155 and a plurality of second grooves
  • the grooves 145 constitute the continuous grooves 105 .
  • the first groove 135 and the second groove 145 can be guaranteed within a certain process error range.
  • the through holes 155 communicate with each other, thereby helping to ensure good connectivity of the continuous grooves 105 formed by the through holes 155 , the first grooves 135 and the second grooves 145 , thereby ensuring that the subsequent continuous grooves 105 are formed in the continuous grooves 105 . Good electrical conductivity of the metal layer.
  • the process steps of forming the first groove 135 and the second groove 145 include:
  • a first mask layer with a first mask pattern is formed on the first surface a.
  • the first mask layer is a photoresist treated with light and a developing solution. Then, using the first mask layer as a mask to etch the first surface a to form a plurality of first grooves 135; to form a second mask layer with a second mask pattern on the side of the dielectric layer 102 away from the substrate 100,
  • the material of the second mask layer is the same as that of the first mask layer; a plurality of second grooves 145 are formed by etching the dielectric layer 102 with the second mask layer as a mask; the first mask layer and the second mask layer are removed film layer.
  • the first mask layer, the second mask layer and the third filling layer 136 may be removed by an etching process or an ashing process.
  • an ashing process can be used to remove the first mask layer and the second mask layer at the same time and the third filling layer 136 .
  • the through hole may be formed first, and then the first groove and the second groove may be formed; or, at least one of the first groove and the second groove may be formed first, and then the through hole may be formed.
  • a third groove 165 and a fourth groove are also formed
  • the fourth groove 175 communicates with a through hole 155 adjacent to the third groove 165 .
  • the first lead is also formed in the third groove 165 and the second lead is formed in the fourth groove 175 .
  • the first lead, the second lead and the metal layer are formed at the same time, the first lead, the second lead and the metal layer are integrally formed, which can avoid the contact resistance between the first lead, the second lead and the metal layer. It is beneficial to improve the electrical conductivity between the first lead and the second lead and the metal layer.
  • the substrate is etched to form the first groove, at least one of the third groove and the fourth groove may also be formed; or after the metal layer is formed, the third groove and the fourth groove may be formed again. Fourth groove.
  • FIG. 25 is a schematic diagram of a stepped cross-sectional structure along the HH1 direction of FIG. 24 .
  • Metal layer 103 is formed in continuous trench 105 .
  • the semiconductor structure having the continuous trench 105 is immersed in a reaction solution for electroplating to form a base metal layer 163 in the continuous trench 105 (refer to FIG. 19 ), the surface of the dielectric layer 102 and the surface of the substrate 100 .
  • a reaction solution for electroplating to form a base metal layer 163 in the continuous trench 105 (refer to FIG. 19 ), the surface of the dielectric layer 102 and the surface of the substrate 100 .
  • an electroplating seed layer is deposited in the continuous trench 105, on the surface of the dielectric layer 102 and on the surface of the substrate 100, so as to facilitate the subsequent electroplating process of the semiconductor structure, in the continuous trench 105, the dielectric layer A base metal layer 163 is formed on both the surface of the substrate 102 and the surface of the substrate 100 .
  • the method for depositing the first electroplating seed layer includes physical vapor deposition (including PVD, sputtering, etc.), chemical vapor deposition, inkjet printing, printing, spraying or electroless plating, etc.
  • the reaction solution may be copper sulfate solution or silver sulfate solution.
  • the base metal layer 163 (refer to FIG. 23 ) is planarized to remove the base metal layer 163 located on the surface of the dielectric layer 102 and the surface of the substrate 100 to form the metal layer 103 .
  • the method for fabricating the semiconductor structure provided by the second embodiment of the present disclosure further includes: etching the dielectric layer 102 and the substrate 100 to form first through holes, the first through holes penetrate through the substrate 100 and the dielectric layer 102 , and the first through holes Exposing part of the magnetic core 101 and part of the metal layer 103 is beneficial to increase the area of the solenoid inductor exposed to the air, that is, to increase the heat dissipation area of the solenoid inductor, which is beneficial to further improve the heat dissipation of the solenoid inductor Effect.
  • the second embodiment of the present disclosure uses a semiconductor fabrication process to form a solenoid-shaped metal layer 103 in the substrate 100 and the dielectric layer 102 , and form a magnetic core 101 in the substrate 100 , and the metal layer 103 is wound around the magnetic core 101 .
  • the magnetic permeability of the solenoid inductor is improved, which is beneficial to improve the inductance of the solenoid inductor, so as to improve the electrical performance of the solenoid inductor.
  • the dielectric layer 102 and the substrate 100 are etched to form the first through holes, so that part of the magnetic core 101 and part of the metal layer 103 are exposed to the air, which is beneficial to ensure good heat dissipation effect of the solenoid inductor.
  • a magnetic core is provided in the substrate, and the orthographic projection of the magnetic core on the first surface of the substrate is a closed annular figure, and a medium is located on the second surface of the substrate
  • Both the layer and the substrate have a metal layer, and the metal layer is wound around the magnetic core, then the metal layer and the magnetic core together form a three-dimensional solenoid inductor in the semiconductor structure, which is beneficial to reduce the solenoid inductor on the surface of the substrate.
  • the metal layer itself will generate heat due to the current heating effect. Since part of the metal layer is exposed on the first surface of the substrate, and part of the metal layer is exposed on the surface of the dielectric layer away from the substrate, then part of the metal layer is exposed. The metal layer is exposed to the air, which is beneficial to ensure the good heat dissipation effect of the solenoid inductor.
  • a magnetic core is formed in the substrate, a solenoid-shaped metal layer is formed in the substrate and the dielectric layer, and the metal layer is wound around the magnetic core.
  • the magnetic permeability of the solenoid inductor is improved. rate, thereby helping to improve the inductance of the solenoid inductor, thereby improving the electrical performance of the solenoid inductor.
  • the method for forming the semiconductor structure provided by the embodiments of the present disclosure is highly compatible with the semiconductor fabrication process.

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Abstract

本公开提供一种半导体结构及其制作方法，半导体结构包括：基底，基底具有相对的第一面和第二面；磁芯，磁芯位于基底中，磁芯在第一面上的正投影为封闭环状图形；介质层，介质层位于第二面；螺线管状的金属层，金属层位于基底以及介质层内且绕设于磁芯的周围，且金属层为一体结构，金属层与磁芯之间具有间隔第一面露出部分金属层，介质层远离基底的表面露出部分金属层。

Description

半导体结构及其制作方法
本公开基于申请号为202110049102.2，申请日为2021年01月14日，申请名称为“半导体结构及其制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法。
背景技术
电感器是电子产品的基本组成部分，微电感器广泛用于射频微机电系统和微致动器中。其中，微电感器可以作为开关模式电源(SMPS，Switch Mode Power Supply)的储能元件。SMPS的小型化已成为开发下一代电源的主要重点，即封装电源(PwrSiP,Power Supply in Package)和片上电源(PwrSoC，Power Supply on Chip)。其中，PwrSoC的发展方向是将所有电力电子组件集成在一个芯片上以实现更高的集成度，低成本，高效率和功率密度。PwrSoC技术对电感器要求包括紧凑的物理尺寸，高电流容量以及高品质因素。
然而，随着半导体技术的不断发展，芯片的尺寸也在不断减小，对集成在芯片上的电感器的尺寸以及电学性能提出了更高的要求。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构及其制作方法。
本公开的第一方面提供一种半导体结构，包括：基底，所述基底具有相对的第一面和第二面；磁芯，所述磁芯位于所述基底中，所述磁芯在所述第一面上的正投影为封闭环状图形；介质层，所述介质层位于所述第二面；螺线管状的金属层，所述金属层位于所述基底以及所述介质层内且绕设于所述 磁芯的周围，所述金属层与所述磁芯之间具有间隔，所述第一面露出部分所述金属层，所述介质层远离所述基底的表面露出部分所述金属层。
本公开的第二方面提供一种半导体结构的制作方法，包括：提供基底，所述基底具有相对的第一面和第二面，且所述基底内具有磁芯，所述磁芯在所述第一面上的正投影为封闭环状图形；在所述第二面形成介质层；刻蚀所述基底和所述介质层形成呈螺线管状的连续沟槽，且所述连续沟槽绕设于所述磁芯的周围，所述连续沟槽与所述磁芯之间具有间隔，所述第一面露出部分所述连续沟槽，所述介质层远离所述基底的表面露出部分所述连续沟槽；在所述连续沟槽中形成金属层。
本公开实施例所提供的半导体结构及其制作方法中，基底中具有磁芯，且磁芯在基底的第一面上的正投影为封闭环状图形，以及位于基底的第二面上的介质层和基底中均具有金属层，且金属层绕设于磁芯周围，则金属层和磁芯共同构成半导体结构中立体的螺线管电感器，有利于降低螺线管电感器在基底表面上的正投影面积，因而有利于在实现螺线管电感器小型紧凑的同时，通过将金属层绕设在磁芯上提高螺线管电感器的品质因素，从而提高螺线管电感器的电学性能和工作效率。此外，当螺线管电感器在高频状态下工作时，金属层自身由于电流热效应会产生热量，由于基底的第一面露出部分金属层，介质层远离基底的表面露出部分金属层，则部分金属层暴露在空气中，有利于保证螺线管电感器良好的散热效果。
另外，本公开实施例还提供一种半导体结构的形成方法，在基底中形成磁芯，在基底和介质层中形成呈螺线管状的金属层，且金属层绕设于磁芯周围，在磁芯的作用下，提高螺线管电感器的磁导率，从而有利于提高螺线管电感器的电感量，从而提高螺线管电感器的电学性能。此外，本公开实施例提供的半导体结构的形成方法与半导体制作工艺的兼容性较高。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一 些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开第一实施例提供的半导体结构的俯视结构示意图；
图2为图1沿II1方向的阶梯剖面结构示意图；
图3为图1沿JJ1方向的阶梯剖面结构示意图；
图4为本公开第一实施例中第一通孔的俯视结构示意图；
图5为在基底的第一面和沟槽上沉积金属材料层后的结构示意图；
图6为图5所示出的结构进行平坦化处理形成磁芯后的俯视结构示意图；
图7为图6沿AA1方向的阶梯剖面结构示意图；
图8为图6所示的结构中在基底中形成多个第二通孔后的俯视结构示意图；
图9为图8沿BB1方向的阶梯剖面结构示意图；
图10为图8所示出的结构中在第二通孔中形成第一填充层后的俯视结构示意图；
图11为图10沿CC1方向的阶梯剖面结构示意图；
图12为图11所示出的结构中基底的第二面的介质层上形成多个第三通孔后的结构示意图；
图13为图12所示出的结构中的第三通孔中形成第二填充层后的俯视结构示意图；
图14为图13沿DD1方向的阶梯剖面结构示意图；
图15为图13所示出的结构中形成多个第一凹槽和第二凹槽后的俯视结构示意图；
图16为图15沿EE1方向的阶梯剖面结构示意图；
图17为图15沿FF1方向的阶梯剖面结构示意图；
图18为图15所示出的结构中形成连续沟槽后的俯视结构示意图；
图19为图18沿GG1方向的阶梯剖面结构示意图；
图20为本公开一实施例中形成多个贯穿孔后的结构示意图；
图21为图20所示出的结构中的贯穿孔形成第三填充层后的结构示意图；
图22为图21所示出的结构中形成多个第一凹槽和第二凹槽后的结构示 意图；
图23为图22所示出的结构中形成基础金属层后的结构示意图；
图24为图23所示出的结构中形成金属层后的俯视结构示意图；
图25为图24沿HH1方向的阶梯剖面结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，现有技术对集成在芯片上的电感器的尺寸以及电学性能提出了更高的要求。
经分析发现，电感器是一种基本的电力电子组件。在片上电源(PwrSoC)的制备工艺中，为将更多的电力电子组件集成在同一芯片上以实现更高的集成度，在保证电感器良好的工作性能的同时，需要将电感器的物理尺寸制作得更紧凑。目前半导体结构中采用的电感器通常为平面电感器，即金属层在衬底或者介质层表面绕制而成的电感器，为提高电感器的电学性能，通常需要采用材料成本较高的高导电性金属层或者增大金属层的厚度，以减小电感器中的电阻，不利于降低半导体结构的制作成本和不利于降低半导体结构中电感器的占位空间。
本公开实施提供一种半导体结构，基底中具有磁芯，且磁芯在基底的第一面上的正投影为封闭环状图形，以及位于基底的第二面上的介质层和基底中均具有金属层，且金属层绕设于磁芯周围，则金属层和磁芯共同构成半导体结构中立体的螺线管电感器，有利于降低螺线管电感器在基底表面上的正投影面积，因而有利于降低螺线管电感器在半导体结构中的占位空间的同时，通过将金属层绕设在磁芯上提高螺线管电感器的品质因素，从而提高螺线管电感器的电学性能和工作效率。此外，由于基底的第一面露出部分金属层，介质层远离基底的表面露出部分金属层，则部分金属层暴露在空气中，有利 于保证螺线管电感器良好的散热效果。
图1为本公开第一实施例提供的半导体结构的俯视结构示意图；图2为图1沿II1方向的阶梯剖面结构示意图；图3为图1沿JJ1方向的阶梯剖面结构示意图；图4为第一通孔的俯视结构示意图。
结合参考图1至图3，半导体结构包括：基底100，基底100具有相对的第一面a和第二面b；磁芯101，磁芯101位于基底100中，磁芯101在第一面a上的正投影为封闭环状图形；介质层102，介质层102位于第二面b；螺线管状的金属层103，金属层103位于基底100以及介质层102内且绕设于磁芯101的周围，金属层103与磁芯101之间具有间隔，第一面a露出部分金属层103，介质层102远离基底100的表面露出部分金属层103。金属层103与磁芯101之间具有基底100和介质层102。
本实施例中，金属层103为一体成型结构，避免金属层103自身结构中具有较大的接触电阻，从而有利于提高金属层103整体的导电性，从而有利于提高螺线管电感器的品质因数。此外，从制备工艺的角度而言，通过一次成型来制备金属层103，有利于简化金属层103的制备工艺步骤。
本实施例中，磁芯101位于基底100中，且磁芯101在基底100的第一面a上的正投影为封闭环状图形，金属层103绕设于磁芯101周围，则金属层103和磁芯101共同构成半导体结构中立体的螺线管电感器，有利于降低螺线管电感器在基底100上的正投影面积，因而有利于实现螺线管电感器物理尺寸的小型紧凑，且通过将金属层103绕设在磁芯101上，有利于提高螺线管电感器的品质因素，从而提高螺线管电感器的电学性能和工作效率。此外，第一面a露出部分金属层103，介质层102远离基底100的表面露出部分金属层103，有利于促进螺线管电感器散热。磁芯101在第一面a上的正投影为封闭圆环图形，在其他实施例中，磁芯在第一面上的正投影也可以为封闭椭圆环图形或者封闭方环图形。
磁芯101的材料可以为铁镍合金、铁镍锌合金或者铁镍钼合金等高磁导率材料，有利于进一步提高螺线管电感器的电感量，从而进一步提高螺线管电感器的品质因素。
基底100和介质层102的材料均可以为硅、锗硅、氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅或者碳氧化硅等含硅材料中的至少一种。在一个 例子中，基底100材料为硅，介质层102的材料为氧化硅，有利于提高螺线管电感器的形成工艺与常用的半导体制作工艺之间的兼容性。
金属层103的材料可以为铜、银、钨、钛、金、镍或者钯等金属材料中的至少一种。在一个例子中，金属层103的材料为铜，由于铜的成本低且导电性优良，则有利于在降低金属层103电阻的同时，避免金属层103的材料成本过高，因而有利于进一步提高螺线管电感器的电感量和避免螺线管电感器的制备成本过高。
继续参考图1至图3，金属层103包括：位于基底100中的多个第一金属层113，第一金属层113位于磁芯101朝向第一面a的一侧，且第一金属层113在第一面a的正投影与磁芯101在第一面a的正投影相交；贯穿基底100和介质层102的多个第二金属层123；以及位于介质层102中的多个第三金属层133，且第三金属层133在第一面a的正投影与磁芯101在第一面a的正投影相交；第三金属层133的两端通过第二金属层123分别与相邻两个第一金属层113电连接。
第一金属层113与磁芯101之间具有基底100；第二金属层123与磁芯101之间具有基底100和介质层102；第三金属层133与磁芯101之间具有介质层102。
第一金属层113和第三金属层133均呈长条状，第一金属层113在沿垂直于第一金属层113延伸方向的方向上的宽度与第三金属层133在沿垂直于第三金属层133延伸方向的方向上的宽度相同，且第二金属层123在第一面a上的正投影为圆形，第二金属层123的直径与第三金属层133的宽度相同。在其他实施例中，第二金属层在第一面上的正投影也可以为方形或者椭圆形。
第一金属层113与磁芯101之间的间距不低于20nm。在一个例子中第一金属层113与磁芯101之间的间距为25nm，有利于降低第一金属层113与磁芯101之间的寄生电容，从而有利于提高螺线管电感器的滤波效果，提高螺线管电感器的工作效率。
本实施例中，第二金属层123与磁芯101之间的间距范围和第一金属层113与磁芯101之间的间距范围相同，第三金属层133与磁芯101之间的间距范围和第一金属层113与磁芯101之间的间距范围也相同。在一个例子中，第二金属层123与磁芯101之间的间距和第三金属层133与磁芯101之间的 间距均与第一金属层113与磁芯101之间的间距相同，均为25nm，有利于降低第二金属层123与磁芯101之间的寄生电容和降低第三金属层133与磁芯101之间的寄生电容，从而有利于提高螺线管电感器的滤波效果，提高螺线管电感器的工作效率。
在垂直于第一面a的方向上，第一金属层113的厚度范围为50nm～400nm。在一个例子中，第一金属层113的厚度为100nm，则第一金属层113的电阻值较小，有利于在保证螺线管电感器具有较高的品质因数的同时，降低螺线管电感器在半导体结构中的占位空间，从而有利于提高半导体结构的空间利用率，有利于在同一芯片上集成更多尺寸紧凑的电力电子组件。
本实施例中，在垂直于第一面a的方向上，第三金属层133的厚度范围与第一金属层113的厚度范围相同；第二金属层123在沿垂直于第二金属层123延伸方向的方向上的厚度范围与第一金属层113的厚度范围相同。第二金属层123和第三金属层133的厚度均与第一金属层113的厚度相同，均为100nm，则第二金属层123和第三金属层133的电阻值均较小，同样有利于在保证螺线管电感器具有较高的品质因数的同时，降低螺线管电感器在半导体结构中的占位空间，从而有利于提高半导体结构的空间利用率。
相邻第一金属层113间的间距不低于10nm。在一个例子中，相邻第一金属层113之间的间距为15nm，有利于降低相邻第一金属层113之间的寄生电容，从而有利于提高螺线管电感器的滤波效果，提高螺线管电感器的工作效率。
继续参考图1，半导体结构还包括：第一通孔104，第一通孔104贯穿基底100和介质层102，且第一通孔104露出部分磁芯101和部分金属层103，则部分磁芯101和部分金属层103与基底100和介质层102相接触，使得磁芯101和金属层103固定在半导体结构中，另外第一通孔104有利于增大螺线管电感器暴露在空气中的面积，即增大螺线管电感器的散热面积，有利于进一步提高螺线管电感器的散热效果。
第一通孔104的中心轴线与磁芯101的中心轴线重合，使得磁芯101和金属层103被基底100和介质层102固定的区域均匀分布在各个方向上，有利于在增大螺线管电感器的散热面积的同时，保证磁芯101和金属层103受力均匀。磁芯101在基底100表面的正投影为圆环，参考图4，第一通孔104 在基底100上的正投影由一个圆形114和至少一个位于圆形114边缘且凸出于圆形114的凸起图形124构成，且圆形114的直径小于圆环的最大直径，凸起图形124凸出于圆形114的外边缘。本实施例中，凸起图形124为8个，且8个凸起图形均匀分布在圆形114的四周，在保证磁芯101和金属层103固定于基底100和介质层102上时，有利于进一步增大螺线管电感器的散热面积，从而进一步提高螺线管电感器的散热效果。在其他实施例中，凸起图形的数量也可以为1个、2个、4个等。需要说明的是，在保证磁芯101和金属层103固定于基底100和介质层102上的情况下，对凸起图形124的数量不做限制。
第一通孔104在基底100上的正投影为轴对称图形，使得磁芯101和金属层103被基底100和介质层102固定的区域对称分布，有利于在增大螺线管电感器的散热面积的同时，保证磁芯101和金属层103受到的来自基底100和介质层102的作用力对称分布在磁芯101和金属层103中。
在其他实施例中，磁芯在基底表面的正投影为圆环，第一通孔在基底上的正投影可以为圆形，且该圆形的直径小于圆环的最大直径。
本实施例中，半导体结构还可以包括：第一引线143和第二引线153，第一引线143与金属层103的一端电连接，第二引线153与金属层103的另一端电连接，且第一引线143和第二引线153与金属层103为一体成型结构，即可通过一次成型共同制备第一引线143、第二引线153以及金属层103，避免第一引线143和第二引线153与金属层103之间产生接触电阻，因而有利于提高第一引线143和第二引线153与金属层103之间的导电性。
参考图1至图3，第一引线143与一第三金属层133电连接，第二引线153与一第二金属层123电连接。在其他实施例中，第一引线和第二引线与金属层也可以不为一体成型结构，第一引线可以与第二金属层或者第一金属层电连接，第二引线可以与第三金属层或者第一金属层电连接。
综上所述，本公开第一实施例提供的半导体结构中，具有绕设于磁芯101周围的金属层103，金属层103和磁芯101共同构成半导体结构中立体的螺线管电感器，该螺线管电感器在基底100表面上的正投影面积较小，由于磁芯101有利于提高螺线管电感器的磁导率，则有利于在提高螺线管电感器的品质因素的同时，实现螺线管电感器物理尺寸的小型紧凑，以降低螺线管电 感器在半导体结构中的占位空间。此外，由于基底100的第一面a露出部分金属层103，介质层102远离基底100的表面露出部分金属层103，且第一通孔104露出部分磁芯101和部分金属层103，则在保证磁芯101和金属层103固定于基底100和介质层102上时，有利于进一步增大螺线管电感器的散热面积，从而进一步提高螺线管电感器的散热效果。
本公开第二实施例还提供一种半导体结构的制作方法，用于制备上述半导体结构。图5至7为本公开第二实施例中磁芯的制作方法各步骤对应的结构示意图；图8至图19为本公开第二实施例中连续沟槽的一种制作方法各步骤对应的结构示意图；图20至图22为本公开第二实施例中连续沟槽的又一种制作方法各步骤对应的结构示意图；图23至图25本公开第二实施例中金属层的制作方法各步骤对应的结构示意图。
参考图5至图7，图7为图6沿AA1方向的阶梯剖面结构示意图，提供基底100，基底100具有相对的第一面a和第二面b，且基底100内具有磁芯101，磁芯101在第一面a上的正投影为封闭环状图形。
形成磁芯101的工艺步骤包括：
对第二面b进行刻蚀以形成沟槽，沟槽在第一面a上的正投影为封闭环状图形；在沟槽中和第二面b上沉积一层金属材料层111；对金属材料层111进行平坦化处理至露出基底100表面，以形成磁芯101。平坦化处理的方法包括化学机械研磨。
本实施例中，形成沟槽的方法包括图案-干法刻蚀。此外，沉积金属材料层111的方法包括物理气相沉积(包括PVD、溅射等)、化学气相沉积或者喷涂等，金属材料层111可以为铁镍合金、铁镍锌合金或者铁镍钼合金等高磁导率材料。
参考图18和图19，在基底100和介质层102形成呈螺线管状的连续沟槽105，且连续沟槽105绕设于磁芯101的周围，连续沟槽105与磁芯101之间具有间隔，第一面a露出部分连续沟槽105，介质层102远离基底100的表面露出部分连续沟槽105。
在一个例子中，在基底100中形成磁芯101之后，在基底100的第二面b上形成介质层102之前，在基底100中形成连续沟槽105的部分区域，然后在基底100的第二面b上形成介质层，在介质层102中形成连续沟槽105 的剩余区域。形成连续沟槽105的工艺步骤如下：
参考图8和图9，图9为图8沿BB1方向的阶梯剖面结构示意图。刻蚀基底100形成多个第二通孔115，第二通孔115贯穿基底100，且第二通孔115位于磁芯101相对的两侧。磁芯101在第一面的正投影为封闭环状图形，部分第二通孔115在第一面a的正投影位于封闭环状图形围成的区域内，剩余第二通孔115在第一面a的正投影位于封闭环状图形围成的区域外。
本实施例中，形成第二通孔115的方法包括图案-干法刻蚀。在垂直于第一面a的方向上，当基底100的厚度较大时，可采用深反应离子刻蚀工艺刻蚀基底100以形成第二通孔115。在其他实施例中，也可采用其他干法刻蚀工艺对基底进行刻蚀以形成第二通孔。
参考图10和图11，图11为图10沿CC1方向的阶梯剖面结构示意图。在第二通孔115中形成第一填充层116，避免后续在基底100第二面上形成介质层时，介质层在第二通孔115中形成，不利于后续去除第二通孔115中的杂质。
参考图12至图14，图14为图13沿DD1方向的阶梯剖面结构示意图。参考图12，在第二面b形成介质层102；刻蚀介质层102形成多个第三通孔125，第三通孔125贯穿介质层102且露出第一填充层116。
参考图13和图14在第三通孔125中形成第二填充层126。
参考图15至图17，图16为图15沿EE1方向的阶梯剖面结构示意图，图17为图15沿FF1方向的阶梯剖面结构示意图。刻蚀第一面a以形成多个第一凹槽135，第一凹槽135的两端露出第一填充层116。刻蚀介质层102远离基底100的一侧以形成多个第二凹槽145，且第二凹槽145的两端露出第二填充层126。
本实施例中，形成第一凹槽135时，刻蚀第一面a的同时还对部分第一填充层116进行了刻蚀；形成第二凹槽145时，刻蚀介质层102远离基底100的一侧的同时还对第二填充层126进行了刻蚀，则在后续去除第一填充层116和第二填充层126后，在一定的工艺误差范围内，均能保证第一凹槽135和第二凹槽145通过第二通孔115和第三通孔125相连通，从而有利于保证第二通孔115、第三通孔125、第一凹槽135和第二凹槽145共同构成的连续沟槽105良好的连通性，从而保证后续在来连续沟槽105中形成的金属层良好 的导电性。
参考图18至图19，图19为图18沿GG1方向的阶梯剖面结构示意图。去除第一填充层116和第二填充层126，第二通孔115、第三通孔125、第一凹槽135和第二凹槽145共同构成的连续沟槽105。
本实施例中，第一填充层116和第二填充层126的材料相同，便于后续一同去除第一填充层116和第二填充层126。第一填充层116和第二填充层126均为有机化合物，可采用灰化工艺同时去除第一填充层116和第二填充层126。往腔室中通入氧气，并控制腔室中的相关参数，使得第一填充层116和第二填充层126与氧气发生反应，生成气体，从而将第一填充层116和第二填充层126去除。
在又一个例子中，在基底100中形成磁芯101之后，先在基底100的第二面b上形成介质层102，然后刻蚀基底100和介质层102形成连续沟槽105。形成连续沟槽105的工艺步骤如下：
参考图20，刻蚀基底100和介质层102以形成多个贯穿孔155，贯穿孔155贯穿基底100和介质层102，且贯穿孔155位于磁芯101两侧。
参考图21，在贯穿孔155形成第三填充层136，则后续再次刻蚀基底100和介质层102的工艺步骤中，在基底100的第一面a和介质层102远离基底100的一侧涂敷光刻胶时，由于介质层102和第三填充层136共同构成一个较平坦的表面，有利于光刻胶涂敷均匀，避免后续光刻时的散焦现象。此外，第三填充层136的材料为有机化合物。
参考图22，刻蚀基底100的第一面a以形成多个第一凹槽135；刻蚀介质层102远离基底100的一侧以形成多个第二凹槽145；去除第三填充层136，且第二凹槽145通过贯穿孔155(参考图20)分别与相邻的两个第一凹槽135相连通，多个第一凹槽135、多个贯穿孔155和多个第二凹槽145构成连续沟槽105。
本实施例中，形成第一凹槽135时，刻蚀第一面a的同时还对部分第三填充层136进行了刻蚀；形成第二凹槽145时，刻蚀介质层102远离基底100的一侧的同时还对第三填充层136进行了刻蚀，则在后续去除第三填充层136后，在一定的工艺误差范围内，均能保证第一凹槽135和第二凹槽145通过贯穿孔155相连通，从而有利于保证贯穿孔155、第一凹槽135和第二凹槽 145共同构成的连续沟槽105良好的连通性，从而保证后续在来连续沟槽105中形成的金属层良好的导电性。
本实施例中，形成第一凹槽135和第二凹槽145的工艺步骤包括：
在第一面a形成具有第一掩膜图案的第一掩膜层，本实施例中，第一掩膜层为经过光照和显影液处理后的光刻胶。然后，以第一掩膜层为掩膜刻蚀第一面a形成多个第一凹槽135；在介质层102远离基底100的一侧形成具有第二掩膜图案的第二掩膜层，第二掩膜层的材料与第一掩膜层的材料相同；以第二掩膜层为掩膜刻蚀介质层102形成多个第二凹槽145；去除第一掩膜层和第二掩膜层。
本实施例中，可采用刻蚀工艺或者灰化工艺去除第一掩膜层、第二掩膜层和第三填充层136。在一个例子中，当第一掩膜层、第二掩膜层和第三填充层136的材料均为光刻胶时，可采用灰化工艺同时去除第一掩膜层、第二掩膜层和第三填充层136。往腔室中通入氧气，并控制腔室中的相关参数，使得第一掩膜层、第二掩膜层和第三填充层136与氧气发生反应，生成气体，从而将第一掩膜层、第二掩膜层和第三填充层136去除。
在其他实施例中，也可以先形成贯穿孔，然后形成第一凹槽和第二凹槽；或者，先形成第一凹槽和第二凹槽中的至少一者，然后形成贯穿孔。
此外，参考图18，本实施例中，以第二掩膜层为掩膜刻蚀介质层102形成多个第二凹槽145的工艺步骤中，还形成有第三凹槽165和第四凹槽175，第三凹槽165与一个第二凹槽145相连通，第四凹槽175与一个贯穿孔155相连通。在一个例子中，第四凹槽175和与第三凹槽165相邻的一个贯穿孔155相连通。后续在连续沟槽105中形成金属层的工艺步骤中，还在第三凹槽165中形成第一引线，在第四凹槽175中形成第二引线。由于第一引线、第二引线和金属层同时形成，则第一引线、第二引线和金属层为一体成型结构，可以避免第一引线和第二引线与金属层之间产生接触电阻，因而有利于提高第一引线和第二引线与金属层之间的导电性。在其他实施例中，在刻蚀基底形成第一凹槽的时候，也可形成第三凹槽和第四凹槽中的至少一者；或者在金属层形成之后，再形成第三凹槽和第四凹槽。
参考图23至图25，图25为图24沿HH1方向的阶梯剖面结构示意图。在连续沟槽105中形成金属层103。
参考图23，将具有连续沟槽105的半导体结构浸入反应溶液中进行电镀，以在连续沟槽105(参考图19)中、介质层102表面和基底100表面形成基础金属层163。在形成基础金属层163之前，在连续沟槽105中、介质层102表面和基底100表面均沉积有一层电镀种子层，促使后续对半导体结构进行电镀工艺时，在连续沟槽105中、介质层102表面和基底100表面均形成基础金属层163。本实施例中，沉积第一电镀种子层的方法包括物理气相沉积(包括PVD、溅射等)、化学气相沉积、喷墨打印、印刷、喷涂或者化学镀等，反应溶液可以为硫酸铜溶液或者硫酸银溶液。
参考图24和图25，对基础金属层163(参考图23)进行平坦化处理以去除位于介质层102表面和基底100表面的基础金属层163，形成金属层103。
本公开第二实施例提供的半导体结构的制作方法还包括：对介质层102和基底100进行刻蚀以形成第一通孔，第一通孔贯穿基底100和介质层102，且第一通孔露出部分磁芯101和部分金属层103，有利于增大螺线管电感器暴露在空气中的面积，即增大螺线管电感器的散热面积，有利于进一步提高螺线管电感器的散热效果。
本公开第二实施例通过半导体制作工艺，在基底100和介质层102中形成呈螺线管状的金属层103，在基底100中形成磁芯101，且金属层103绕设于磁芯101周围，在磁芯101的作用下，提高螺线管电感器的磁导率，从而有利于提高螺线管电感器的电感量，以提高螺线管电感器的电学性能。此外，对介质层102和基底100进行刻蚀以形成第一通孔，使得部分磁芯101和部分金属层103均暴露在空气中，有利于保证螺线管电感器良好的散热效果。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或 多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制作方法中，基底中具有磁芯，且磁芯在基底的第一面上的正投影为封闭环状图形，以及位于基底的第二面上的介质层和基底中均具有金属层，且金属层绕设于磁芯周围，则金属层和磁芯共同构成半导体结构中立体的螺线管电感器，有利于降低螺线管电感器在基底表面上的正投影面积，因而有利于在实现螺线管电感器小型紧凑的同时，通过将金属层绕设在磁芯上提高螺线管电感器的品质因素，从而提高螺线管电感器的电学性能和工作效率。此外，当螺线管电感器在高频状态下工作时，金属层自身由于电流热效应会产生热量，由于基底的第一面露出部分 金属层，介质层远离基底的表面露出部分金属层，则部分金属层暴露在空气中，有利于保证螺线管电感器良好的散热效果。另外，在基底中形成磁芯，在基底和介质层中形成呈螺线管状的金属层，且金属层绕设于磁芯周围，在磁芯的作用下，提高螺线管电感器的磁导率，从而有利于提高螺线管电感器的电感量，从而提高螺线管电感器的电学性能。此外，本公开实施例提供的半导体结构的形成方法与半导体制作工艺的兼容性较高。

Claims (16)

  1. 一种半导体结构，包括：
    基底，所述基底具有相对的第一面和第二面；
    磁芯，所述磁芯位于所述基底中，所述磁芯在所述第一面上的正投影为封闭环状图形；
    介质层，所述介质层位于所述第二面；
    螺线管状的金属层，所述金属层位于所述基底以及所述介质层内且绕设于所述磁芯的周围，所述金属层与所述磁芯之间具有间隔，所述第一面露出部分所述金属层，所述介质层远离所述基底的表面露出部分所述金属层。
  2. 根据权利要求1所述的半导体结构，其中，所述金属层包括：位于所述基底中的多个第一金属层，所述第一金属层位于所述磁芯朝向所述第一面的一侧，且所述第一金属层在所述第一面的正投影与所述磁芯在所述第一面的正投影相交；贯穿所述基底和所述介质层的多个第二金属层；以及位于所述介质层中的多个第三金属层，且所述第三金属层在所述第一面的正投影与所述磁芯在所述第一面的正投影相交；所述第三金属层的两端通过所述第二金属层分别与相邻两个所述第一金属层电连接。
  3. 根据权利要求2所述的半导体结构，其中，所述第二金属层与所述磁芯之间的间距范围和所述第一金属层与所述磁芯之间的间距范围相同，所述第三金属层与所述磁芯之间的间距范围和所述第一金属层与所述磁芯之间的间距范围也相同。
  4. 根据权利要求2所述的半导体结构，其中，在垂直于所述基底表面的方向上，所述第三金属层的厚度范围与所述第一金属层的厚度范围相同；所述第二金属层在沿垂直于所述第二金属层延伸方向的方向上厚度范围与所述第一金属层的厚度范围相同。
  5. 根据权利要求1所述的半导体结构，还包括：第一通孔，所述第一通孔贯穿所述基底和所述介质层，且所述第一通孔露出部分所述磁芯和部分所述金属层。
  6. 根据权利要求5所述的半导体结构，其中，所述第一通孔的中心轴线与所述磁芯的中心轴线重合。
  7. 根据权利要求6所述的半导体结构，其中，所述磁芯在所述基底表面的正投影为圆环，所述第一通孔在所述基底上的正投影由一个圆形和至少一个位于所述圆形边缘且凸出于所述圆形的凸起图形构成，且所述圆形的直径小于所述圆环的最大直径，所述凸起图形凸出于所述圆环的外边缘。
  8. 根据权利要求7所述的半导体结构，其中，所述第一通孔在所述基底上的正投影为轴对称图形。
  9. 一种半导体结构的制作方法，包括：
    提供基底，所述基底具有相对的第一面和第二面，且所述基底内具有磁芯，所述磁芯在所述第一面上的正投影为封闭环状图形，所述基底的第二面上具有介质层；
    在所述基底和所述介质层中形成呈螺线管状的连续沟槽，且所述连续沟槽绕设于所述磁芯的周围，所述连续沟槽与所述磁芯之间具有间隔，所述第一面露出部分所述连续沟槽，所述介质层远离所述基底的表面露出部分所述连续沟槽；
    在所述连续沟槽中形成金属层。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，形成所述连续沟槽的工艺步骤包括：
    刻蚀所述基底和所述介质层以形成多个贯穿孔，所述贯穿孔贯穿所述基底和所述介质层，且所述贯穿孔位于所述磁芯两侧；
    刻蚀所述第一面以形成多个第一凹槽；
    刻蚀所述介质层远离所述基底的一侧以形成多个第二凹槽，且所述第二凹槽通过所述贯穿孔分别与相邻的两个所述第一凹槽相连通，多个所述第一凹槽、多个所述贯穿孔和多个所述第二凹槽构成所述连续沟槽。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，在形成所述贯穿孔之后，形成所述第一凹槽和所述第二凹槽；或者，在形成所述第一凹槽和所述第二凹槽中的至少一者之后，形成所述贯穿孔。
  12. 根据权利要求9所述的半导体结构的制作方法，其中，形成所述连续沟槽的步骤包括：
    刻蚀所述基底形成多个第二通孔，所述第二通孔贯穿所述基底；
    在所述第二通孔中形成第一填充层；
    在所述第二面形成所述介质层；
    刻蚀所述介质层形成多个第三通孔，所述第三通孔贯穿所述介质层且露出所述第一填充层；
    在所述第三通孔中形成第二填充层；
    刻蚀所述第一面以形成多个第一凹槽，所述第一凹槽的两端露出所述第一填充层；
    刻蚀所述介质层远离所述基底的一侧以形成多个第二凹槽，且所述第二凹槽的两端露出所述第二填充层；
    去除所述第一填充层和所述第二填充层，所述第二通孔、所述第三通孔、所述第一凹槽和所述第二凹槽共同构成所述连续沟槽。
  13. 根据权利要求10或12所述的半导体结构的制作方法，其中，形成所述第一凹槽和所述第二凹槽的工艺步骤包括：
    在所述第一面形成具有第一掩膜图案的第一掩膜层；
    以所述第一掩膜层为掩膜刻蚀所述第一面形成多个所述第一凹槽；
    在所述介质层远离基底的一侧形成具有第二掩膜图案的第二掩膜层；
    以所述第二掩膜层为掩膜刻蚀所述介质层形成多个所述第二凹槽；
    去除所述第一掩膜层和所述第二掩膜层。
  14. 根据权利要求9所述的半导体结构的制作方法，还包括：对所述介质层和所述基底进行刻蚀以形成第一通孔，所述第一通孔贯穿所述基底和所述介质层，且所述第一通孔露出部分所述磁芯和部分所述金属层。
  15. 根据权利要求9所述的半导体结构的制作方法，其中，形成所述磁芯的工艺步骤包括：
    对所述第二面进行刻蚀以形成沟槽，所述沟槽在所述第一面上的正投影为封闭环状图形；
    在所述沟槽中和所述第二面上沉积一层金属材料层；
    对所述金属材料层进行平坦化处理至露出所述基底表面，以形成所述磁芯。
  16. 根据权利要求9所述的半导体结构的制作方法，其中，在所述连续沟槽中形成所述金属层的工艺步骤包括：
    将具有所述连续沟槽的所述半导体结构浸入反应溶液中进行电镀，以在 所述连续沟槽中、所述介质层表面和所述基底表面形成基础金属层；
    对所述基础金属层进行平坦化处理以去除位于所述介质层表面和所述基底表面的所述基础金属层，形成所述金属层。
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