WO2022143121A1 - 改善刻蚀均匀性的双挡板装置 - Google Patents

改善刻蚀均匀性的双挡板装置 Download PDF

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WO2022143121A1
WO2022143121A1 PCT/CN2021/137436 CN2021137436W WO2022143121A1 WO 2022143121 A1 WO2022143121 A1 WO 2022143121A1 CN 2021137436 W CN2021137436 W CN 2021137436W WO 2022143121 A1 WO2022143121 A1 WO 2022143121A1
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etching
baffle
sector
energy
wafer
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PCT/CN2021/137436
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English (en)
French (fr)
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张瑶瑶
刘小波
胡冬冬
张怀东
刘海洋
李娜
郭颂
李晓磊
许开东
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江苏鲁汶仪器有限公司
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Priority to KR1020237023600A priority Critical patent/KR20230118172A/ko
Publication of WO2022143121A1 publication Critical patent/WO2022143121A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02—Details
    • H01J37/04—Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
    • H01J37/08—Ion sources; Ion guns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H01J37/3211—Antennas, e.g. particular shapes of coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32623—Mechanical discharge control means
    • H01J37/32633—Baffles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of ion beam etching, and in particular, to a double baffle device for improving etching uniformity.
  • Ion beam etching uses the principle of glow discharge to decompose argon gas into argon ions, and the argon ions are accelerated by the anode electric field to physically bombard the surface of the sample to achieve the effect of etching.
  • the etching process is to fill the ion source discharge chamber with an inert gas such as argon (Ar), ionize it to form a plasma, transmit the plasma to the target substrate in the form of an ion beam through the grid, and shoot at the solid surface to bombard the solid surface atoms.
  • the material atoms are sputtered to achieve the purpose of etching.
  • Ion beam etching can be widely used for etching various metals and their alloys, as well as non-metals, oxides, nitrides, carbides, semiconductors, polymers, ceramics, infrared and superconducting materials.
  • the uniformity of ion beam etching mainly depends on the performance of the ion source. Since the radio frequency (RF) ion source is cylindrical, when the RF power supply is loaded on the RF coil, the current is mainly in the discharge cavity due to the skin effect of the current. It flows through the cavity wall and gradually attenuates in the skin layer, so the plasma density in the discharge cavity generally shows a trend of high on both sides and low in the middle. Affected by radio frequency power and working pressure, the plasma density distribution in the discharge chamber also has a saddle-shaped trend. Due to the uneven plasma density distribution, the etching rate is uneven and the etching uniformity is affected.
  • RF radio frequency
  • the etching rate of the middle area of the wafer surface is greater than that of the edge area.
  • the gate loading voltage increases, the area with faster etching rate gradually moves outward.
  • the etch rate is significantly larger in the edge region than in the center region.
  • Exemplary embodiments of the present application provide a double baffle device for improving etching uniformity.
  • the double baffle device for improving etching uniformity is etched through the cooperation of two baffle plates, thereby improving the overall etching of a finished wafer. Etch uniformity and increase wafer utilization.
  • Exemplary embodiments of the present application provide a double baffle device for improving etching uniformity, including a first baffle and a second baffle both installed in an etching reaction chamber.
  • the first baffle is a full-circle plate, which can completely shield the ion beam generated by the ion source under the action of the first baffle driving device.
  • the wafer is etched twice, the first etching is the etching without shielding, and the second etching is the etching that is shielded by the second shield.
  • the structure of the second baffle is selected according to the etching conditions, and under the action of the second baffle driving device, the area of the surface of the wafer where the etching rate is fast during the first etching can be blocked, so that the crystal The etch rate for the round surface remains the same.
  • the etching conditions include low energy conditions, medium energy conditions and high energy conditions.
  • the second baffle plate when the etching working condition is a low-energy working condition, includes a central circular plate and a plurality of first fan-shaped blocks evenly distributed along the circumferential direction of the central circular plate; wherein the central circular plate is used for Blocks the low-energy center region of the wafer surface where the etching rate is fast.
  • a first sector gap is formed between two adjacent first sector blocks, and at the radius r, the arc length of the first sector block is L1, and the arc length of the first sector gap is L2, where L1 ⁇ L2.
  • the second stopper further includes a first connecting ring concentrically sleeved on the outer circumference of the central circular plate, and a plurality of first sector-shaped blocks are uniformly arranged between the central circular plate and the first connecting ring along the circumferential direction.
  • the second baffle plate when the etching working condition is the medium-energy working condition, includes a second connecting ring and a plurality of second sector-shaped blocks; On the inner side of the ring, each second sector-shaped block is connected with the inner wall surface of the second connecting ring directly or through connecting ribs; a second sector-shaped gap is formed between two adjacent second sector-shaped blocks.
  • the arc length of the second sector-shaped block is L3
  • the arc length of the second sector-shaped gap is L4, where L3>L4.
  • each of the second sector-shaped blocks are chamfered with circular arcs.
  • the second baffle plate is the first annular plate.
  • the second baffle plate when the etching working condition is a high-energy working condition, includes a second annular plate and an inverted fan-shaped gap evenly distributed along the circumferential direction of the second annular plate, and the arc of the inverted fan-shaped gap is long. The end faces the circular cavity of the second annular plate.
  • the present application has the following beneficial effects: the present application uses the first baffle to perform one-time etching, selects second baffles with different structures according to different etching conditions, and uses the second baffle to perform secondary etching, thereby effectively improving the The overall etching uniformity of the finished wafer increases the utilization rate of the wafer.
  • Figures 1a-1c show schematic diagrams of the uniformity of the etching rate on the wafer surface under different etching conditions in the prior art, wherein Figures 1a, 1b and 1c show the low-energy condition, the medium-energy condition and the high-energy condition, respectively Schematic diagram of the uniformity of the etching rate on the wafer surface under working conditions.
  • FIG. 2 shows a schematic diagram of the overall structure of an ion etching system according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram showing the state of the two baffles when the wafer does not reach the etching position according to an embodiment of the present application.
  • FIG. 4 shows a schematic diagram of the state of two baffles during the first etching of an embodiment of the present application.
  • FIG. 5 is a schematic diagram showing the state of two baffles during the second etching process according to an embodiment of the present application.
  • FIG. 6 shows a schematic structural diagram of a first baffle according to an embodiment of the present application.
  • Figures 7a-7f show schematic structural diagrams of a second baffle according to an embodiment of the present application, wherein Figures 7a and 7b show two example diagrams of the second baffle under low energy conditions; Figures 7c and 7d show Figures 7e and 7f show two examples of the second baffle in high energy conditions.
  • Figures 8a-8b are schematic diagrams showing the state of two baffles in cooperation for the second etching according to an embodiment of the present application, wherein Figures 8a and 8b respectively show two types of matching examples.
  • FIG. 9 shows a schematic diagram of the flow of wafer etching with two baffle plates.
  • the second baffle; 21a The central circular plate; 21b. The first sector block; 21c. The first sector gap; 21d. The first connecting ring;
  • 22a The second connecting ring; 22b. The second sector block; 22c. The second sector gap; 22d. The connecting rib;
  • 31a Low-energy central region; 31b. Low-energy edge region; 32a. Middle-energy central region; 32b. Middle-energy middle region; 32c.
  • Electrode 5. Ion source; 6. Second baffle driving device; 61. First baffle driving device; 7. Second baffle limiting device; 71. First baffle limiting device; 8. Engraving Etch the reaction chamber.
  • connection may be a direct connection between components or an indirect connection between components through other components.
  • connection when an element is described in this application as being “connected” to another element, it means that the one element is in electrical connection with the other element.
  • each exemplary embodiment of the present application proposes a double baffle device for improving etching uniformity, including a first baffle 1 and a second baffle installed in the etching reaction chamber 8 Baffle 2.
  • the first baffle is a full-circle plate, which can completely shield the ion beam generated by the ion source under the action of the first baffle driving device 61 and the first baffle limiting device 71 .
  • the wafer is etched twice, the first etching is the etching without shielding, and the second etching is the etching that is shielded by the second shield.
  • the etching uniformity meets the requirements after one etching, the etching is ended. If the process requirements are not met, secondary etching is required.
  • the first baffle 1 shields the ion beam generated by the ion source 5 under the action of the first baffle driving device 61 and the first baffle limiting device 71 .
  • the first baffle 1 falls down, and the ion beam etches the surface of the wafer 3 until the first process is completed.
  • the unevenness causes uneven etching of the entire wafer 3, and a second process needs to be performed to perform secondary etching on the uneven area.
  • the second baffle 2 partially shields the ion beam generated by the ion source 5 under the action of the second baffle driving device 6 and the second baffle limiting device 7 (that is, during one etching The area with a fast etching rate on the wafer surface is blocked), and the area with a slower etching rate in the first process (one-time etching) is etched for a short period of time until the uniformity of the entire wafer meets the requirements.
  • the material of the first baffle 1 and the second baffle 2 is preferably graphite or molybdenum.
  • the first baffle 1 can be an overall circular structure, and its diameter is at least larger than that of the grid component in the ion source 5 .
  • the beam aperture is more than 30% larger, and at the same time, it should be ensured that the first baffle 1 does not block the ion beam when it falls.
  • the structure of the second baffle is selected according to the etching conditions.
  • the etching conditions in the above embodiments include low-energy conditions (Beamvoltage ⁇ 300V), medium-energy conditions (300V ⁇ Beamvoltage ⁇ 600V), and high-energy conditions (Beamvoltage>600V).
  • the etching rate of the wafer surface is that the low-energy central region 31a is greater than the low-energy edge region 31b, and along the The radial etch rate gradually decreases.
  • the second baffle 2 shields the low-energy central region 31a to avoid excessive etching of the low-energy central region 31a of the wafer 3 by the ion beam.
  • the shielding area of the second baffle should gradually decrease from the inside to the outside.
  • the second baffle plate includes a central circular plate 21a and a plurality of first sector-shaped blocks 21b uniformly distributed along the circumferential direction of the central circular plate.
  • the central circular plate is used to shield the low-energy central region 31a with a fast etching rate on the wafer surface, so the area of the central circular plate is 4/5-1 of the area of the low-energy central region 31a (considering the divergence angle).
  • a first sector gap 21c is formed between two adjacent first sector blocks 21b.
  • the number of the first sector-shaped blocks 21b may be three.
  • the arc length of the first sector-shaped block is L1
  • the arc length of the first sector-shaped gap is L2, and L1 ⁇ L2.
  • the maximum outer diameter of the second baffle plate (ie, the outer diameter of the first sector) is preferably 1.5 times or more the outer diameter of the wafer.
  • the second baffle plate includes a central circular plate 21a, a plurality of first sector blocks 21b and a first connecting ring 21d.
  • the number of the first sector-shaped blocks 21b may be three, but other numbers may also be used.
  • the first connecting ring 21d is concentrically provided on the outer periphery of the central circular plate 21a, and the area of the central circular plate and the area of the low-energy central region 31a are preferably the same.
  • the plurality of first sector-shaped blocks are uniformly arranged between the central circular plate and the first connecting ring along the circumferential direction.
  • the etching rate of the surface of the wafer 3 is the medium energy central region 32a and the medium energy edge region 32c are lower, while the etching rate of the middle-energy middle region 32b is higher. Therefore, under the medium-energy process conditions, the second baffle 2 should perform secondary etching on the middle-energy central region 32a and the middle-energy edge region 32c, and the baffles can be selected from the two preferred styles shown in FIG. 7c and FIG. 7d.
  • the second baffle plate includes a second connecting ring 22a and a plurality of second sector-shaped blocks 22b.
  • the inner diameter of the second connecting ring is preferably larger than the outer diameter of the middle-energy edge region 32c, so as to avoid the shielding of the middle-energy edge region 32c.
  • the number of the second sector-shaped blocks 22b may be three.
  • the second fan-shaped blocks are evenly arranged on the inner side of the second connecting ring along the circumferential direction, and each second fan-shaped block is integrally formed with the inner wall surface of the second connecting ring; a second fan-shaped gap 22c is formed between two adjacent second fan-shaped blocks .
  • a circular arc chamfer is preferably set at the corner of each second sector block, so that the inner arc and outer arc of each second sector block are substantially equal, thereby expanding the arc length of the outer arc of the second sector gap, so as to maximize the The shielding of the centering energy edge region 32c is reduced to facilitate secondary etching.
  • the inner diameter of the second fan-shaped block 22b preferably corresponds to the inner diameter of the middle-energy intermediate region 32b, so as to shield the ion beam in the middle-energy middle region 32b to the greatest extent.
  • the central cavity in the second sector-shaped block 22b preferably corresponds to the area of the middle-energy center region 32a, so that the middle-energy center region 32a is subjected to secondary etching.
  • the second baffle plate includes a second connecting ring 22a and a plurality of second sector-shaped blocks 22b.
  • the number of second sector blocks 22b is preferably three.
  • the second sector-shaped blocks are evenly arranged on the inner side of the second connecting ring along the circumferential direction, and each second sector-shaped block is preferably connected to the inner wall surface of the second connecting ring through a thin strip-shaped connecting rib 22d.
  • the radial position of the connecting ribs preferably corresponds to the mid-energy edge region 32c, and the radial length is preferably the same as the mid-energy edge region 32c.
  • the axial length of the connecting rib is as small as possible, so that the annular gap where the connecting rib is located is as large as possible, the ion beam for secondary etching of the intermediate energy edge region 32c is the largest, and the etching effect is good.
  • a second sector gap 22c is formed between two adjacent second sector blocks.
  • the arrangement of the second fan-shaped gap and the inner circular cavity of the second fan-shaped block 22b refer to the above-mentioned embodiment.
  • the etching rate on the surface of the wafer 3 is the fastest in the high-energy edge region 33b, from the high-energy edge region to the high-energy center region. 33a gradually decreased. Therefore, the pattern shown in FIG. 7e and FIG. 7f can be selected for the second baffle 2 to perform secondary etching on the central area.
  • the second baffle plate includes a second annular plate 23b and an inverted fan-shaped gap 23c uniformly distributed along the circumferential direction of the second annular plate, and the arc long end of the inverted fan-shaped gap faces the circle of the second annular plate. shaped cavity.
  • the second baffle is the first annular plate.
  • the present application can also work in combination with the first baffle plate 1 and the second baffle plate 2 according to the situation to meet the etching uniformity requirement.
  • etching can be performed for more situations to meet the overall etching uniformity requirements.
  • the first baffle 1 can act alone during the second process to block the plasma density in other regions, and only the edge is etched. To meet the overall etching uniformity.
  • the second baffle plate 2 is used for secondary etching, which can improve the overall etching uniformity of the finished wafer and increase the utilization rate of the wafer.

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Abstract

本申请公开了一种改善刻蚀均匀性的双挡板装置，包括均安装在刻蚀反应腔内的第一挡板和第二挡板；第一挡板为整圆板，能在第一挡板驱动装置的作用下，对离子源产生的离子束进行全遮挡；晶圆采用两次刻蚀，第一次刻蚀为无挡板遮挡下的刻蚀，第二次刻蚀为采用第二挡板遮挡的刻蚀；第二挡板的结构根据刻蚀工况进行选择，能在第二挡板驱动装置的作用下，对第一次刻蚀时晶圆表面刻蚀速率快的区域进行遮挡，使得晶圆表面刻蚀速率保持一致。刻蚀工况包括低能工况、中能工况和高能工况。本申请通过两块挡板的配合刻蚀，从而提高晶圆成品的整体刻蚀均匀性，增加晶圆的利用率。

Description

改善刻蚀均匀性的双挡板装置
相关申请
本申请要求于2021年1月4日提交中国专利局、申请号为202110002167.1、申请名称为“一种改善刻蚀均匀性的双挡板装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及离子束刻蚀领域，特别是涉及一种改善刻蚀均匀性的双挡板装置。
背景技术
离子束刻蚀是利用辉光放电原理将氩气分解为氩离子，氩离子经过阳极电场的加速对样品表面进行物理轰击，以达到刻蚀的作用。刻蚀过程是把氩(Ar)等惰性气体充入离子源放电室，经电离形成等离子体，通过栅极将等离子体以离子束的形式传送至目标基板，射向固体表面轰击固体表面原子，使材料原子发生溅射，达到刻蚀目的。离子束刻蚀可广泛用于刻蚀加工各种金属及其合金，以及非金属、氧化物、氮化物、碳化物、半导体、聚合物、陶瓷、红外和超导等材料。
离子束刻蚀均匀性主要取决于离子源性能，由于射频(Radio Frequency,RF)离子源为圆筒形，当射频电源加载在射频线圈上时，由于电流的趋肤效应，电流主要在放电腔腔壁内流过，在趋肤层内逐渐衰减，故放电腔内的等离子体密度一般呈现两边高，中间低的趋势。受射频功率和工作压力的影响，放电腔内的等离子体密度分布也会出现马鞍形趋势，由于等离子体密度分布不均匀，导致刻蚀速率不均，影响刻蚀均匀性。如图1所示，当离子源在低能工况下工作时，晶圆表面刻蚀速率中间区域大于边缘区域，随着栅极加载电压增加，刻蚀速率较快的区域逐渐向外移动，当在高能情况下时，刻蚀速率明显呈现边缘区域大于中心区域。现有晶圆在计算刻蚀均匀性时，一般是对晶圆进行切边后计算，如何节约成本，增加晶圆的利用率是一个亟待解决的难题。
发明内容
本申请各示例性实施例提供一种改善刻蚀均匀性的双挡板装置，该改善刻蚀均匀性的双挡板装置通过两块挡板的配合刻蚀，从而提高晶圆成品的整体刻蚀均匀性，增加晶圆的利用率。
本申请各示例性实施例提供一种改善刻蚀均匀性的双挡板装置，包括均安装在刻蚀反应腔内的第一挡板和第二挡板。
第一挡板为整圆板，能在第一挡板驱动装置的作用下，对离子源产生的离子束进行全遮挡。
晶圆采用两次刻蚀，第一次刻蚀为无挡板遮挡下的刻蚀，第二次刻蚀为采用第二挡板遮挡的刻蚀。
第二挡板的结构根据刻蚀工况进行选择，能在第二挡板驱动装置的作用下，对第一次刻蚀时的晶圆的表面的刻蚀速率快的区域进行遮挡，使得晶圆表面的刻蚀速率保持一致。
在一实施例中，刻蚀工况包括低能工况、中能工况和高能工况。
在一实施例中，当刻蚀工况为低能工况时，第二挡板包括中心圆板和沿中心圆板的周向均匀布设的多个第一扇形块；其中，中心圆板用于遮挡晶圆表面刻蚀速率快的低能中心区域。
在一实施例中，相邻两个第一扇形块之间形成第一扇形间隙，在半径r处，第一扇形块的弧长为L1，第一扇形间隙的弧长为L2，其中，L1＜L2。
在一实施例中，第二挡块还包括同心套设在中心圆板外周的第一连接环，多个第一扇形块沿周向均匀设置在中心圆板和第一连接环之间。
在一实施例中，当刻蚀工况为中能工况时，第二挡板包括第二连接环和多个第二扇形块；多个第二扇形块沿周向均匀布设在第二连接环的内侧，每块第二扇形块直接或通过连接筋与第二连接环的内壁面相连接；相邻两块第二扇形块之间形成第二扇形间隙。
在一实施例中，在半径r处，第二扇形块的弧长为L3，第二扇形间隙的弧长为L4，其中L3＞L4。
在一实施例中，每个第二扇形块的拐角均为圆弧倒角。
在一实施例中，当刻蚀工况为高能工况时，第二挡板为第一圆环板。
在一实施例中，当刻蚀工况为高能工况时，第二挡板包括第二圆环板和沿第二圆环板周向均匀布设的倒扇形间隙，倒扇形间隙的弧长大端朝向第二圆环板的圆形空腔。
本申请具有如下有益效果：本申请利用第一挡板进行一次刻蚀，根据刻蚀工况的不同，选择不同结构的第二挡板，利用第二挡板进行二次刻蚀，从而有效提高晶圆成品的整体刻蚀均匀性，增加晶圆的利用率。
附图说明
图1a-1c显示了现有技术的不同刻蚀工况下的晶圆表面刻蚀速率均匀性示意图，其中，图1a、图1b和图1c分别显示了低能工况、中能工况和高能工况下的晶圆表面刻蚀速率均匀性示意图。
图2显示了本申请一实施例的离子刻蚀系统的整体结构示意图。
图3显示了本申请一实施例的晶圆未达到刻蚀位置时两块挡板的状态示意图。
图4显示了本申请一实施例的第一次刻蚀时两块挡板的状态示意图。
图5显示了本申请一实施例的第二次刻蚀时两块挡板的状态示意图。
图6显示了本申请一实施例的第一挡板的结构示意图。
图7a-7f显示了本申请一实施例的第二挡板的结构示意图，其中，图7a和图7b显示了低能工况下第二挡板的两种实例图；图7c和图7d显示了中能工况下第二挡板的两种实例图；图7e和图7f显示了高能工况下第二挡板的两种实例图。
图8a-8b显示了本申请一实施例的两块挡板配合进行第二次刻蚀的状态示意图，其中，图8a和图8b分别显示了两种配合实例图。
图9显示了两块挡板配合进行晶圆刻蚀的流程示意图。
附图标记：
1.第一挡板；
2.第二挡板；21a.中心圆板；21b.第一扇形块；21c.第一扇形间隙；21d.第一连接环；
22a.第二连接环；22b.第二扇形块；22c.第二扇形间隙；22d.连接筋；
23a.第一圆环板；23b.第二圆环板；23c.倒扇形间隙；
3.晶圆；
31a.低能中心区域；31b.低能边缘区域；32a.中能中心区域；32b.中能中间区域；32c.中能边缘区域；33a.高能中心区域；33b.高能边缘区域；
4.电极；5.离子源；6.第二挡板驱动装置；61.第一挡板驱动装置；7.第二挡板限位装置；71.第一挡板限位装置；8.刻蚀反应腔。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。以下所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解，本申请的说明书和权利要求书中使用的术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元件和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元件、组件和/或其集合的存在或添加。
本申请的描述中，需要理解的是，术语“左侧”、“右侧”、“上部”、“下部”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，“第一”、“第二”等并不表示零部件的重要程度，因此不能理解为对本申请的限制。本实施例中采用的具体尺寸只是为了举例说明技术方案，并不限制本申请的保护范围。
本申请中所述的“连接”的含义可以是部件之间的直接连接也可以是部件间通过其它部件的间接连接。为了便于简要的表述，除非另有定义，本申请中当一元件被描述为“连接”另一个元件是指该一元件与该另一元件为电连接。
如图2至图5所示，本申请各示例性实施例提出了一种改善刻蚀均匀性的双挡板装置，包括均安装在刻蚀反应腔8内的第一挡板1和第二挡板2。
如图6所示，第一挡板为整圆板，能在第一挡板驱动装置61和第一挡板限位装置71的作用下，对离子源产生的离子束进行全遮挡。
本申请中，晶圆采用两次刻蚀，一次刻蚀为无挡板遮挡下的刻蚀，二次刻蚀为采用第二挡板遮挡的刻蚀。
当一次刻蚀后，刻蚀均匀性满足要求时，结束刻蚀。若不满足工艺要求，则需进行二次刻蚀。
当晶圆需要刻蚀时，离子源5内产生等离子体并以离子束的形式轰击晶圆3，如图3所示，当晶圆3尚未到达工艺位置时，为避免离子束对晶圆3和电极4的伤害，第一挡板1在第一挡板驱动装置61和第一挡板限位装置71的作用下，对离子源5产生的离子束进行遮挡。如图4所示，当晶圆3到达工艺位置时，第一挡板1落下，离子束对晶圆3表面进行刻蚀，直至第一工艺完成，此时，由于离子源5产生的离子束不均匀造成整个晶圆3刻蚀的不均匀，需要进行第二工艺对不均匀的区域进行二次刻蚀。
如图5所示，第二挡板2在第二挡板驱动装置6和第二挡板限位装置7的作用下，对离子源5产生的离子束进行局部遮挡(即对一次刻蚀时晶圆表面刻蚀速率快的区域进行遮挡)，对第一工艺(一次刻蚀)过程中刻蚀速率较慢的区域进行短时间的刻蚀，直至整个晶圆的均匀性满足要求。
为避免刻蚀反应腔室污染，第一挡板1与第二挡板2的材质优选为石墨或钼等。
为保证晶圆3未到达工艺位置时，第一挡板1可以完全遮蔽离子束，第一挡板1可以为一整体圆状结构，且其直径至少比离子源5内栅格(Grid)组件束流口径大30％以上，同时，应保证第一挡板1落下时可以不遮挡离子束。
第二挡板的结构根据刻蚀工况进行选择。
上述实施例中的刻蚀工况包括低能工况(Beamvoltage束电压<300V)、中能工况(300V<Beamvoltage<600V)和高能工况(Beamvoltage>600V)。
当工艺条件在低能条件下(low beam voltage低束电压)时，如图1a所示，当第一工艺完成后，晶圆表面的刻蚀速率为低能中心区域31a大于低能边缘区31b，且沿着径向刻蚀速率逐渐降低。
如图7a和图7b所示，在进行第二工艺时，第二挡板2对低能中心区域31a进行遮挡，以避免离子束对晶圆3的低能中心区域31a的过度刻蚀，对于低能边缘区31b，第二挡板遮挡区域应由内向外逐渐减小。
在如图7a所示的实施例中，第二挡板包括中心圆板21a和沿中心圆板周向均匀布设的多个第一扇形块21b。
其中，中心圆板用于遮挡晶圆表面刻蚀速率快的低能中心区域31a，故而，中心圆板的面积为低能中心区域31a面积的4/5～1(考虑发散角)。
相邻两个第一扇形块21b之间形成第一扇形间隙21c。
在本实施例中，第一扇形块21b可以为三块。
假设在半径r处，第一扇形块的弧长为L1，第一扇形间隙的弧长为L2，且L1＜L2。
第二挡板的最大外径(即第一扇形块的外径)优选为晶片外径的1.5倍以上。
在如图7b所示的实施例中，第二挡板包括中心圆板21a、多个第一扇形块21b和第一连接环21d。
在本实施例中，第一扇形块21b可以为三块，但也可以为其他数量。
第一连接环21d同心设在中心圆板21a外周，中心圆板的面积与低能中心区域31a的面积优选相同。
多个第一扇形块沿周向均匀设置在中心圆板和第一连接环之间。
当工艺条件在中能条件(medium beam voltage中束电压)下时，如图1b所示，第一工艺结束后，晶圆3表面的刻蚀速率为中能中心区域32a和中能边缘区域32c均较低，而中能中间区域32b的刻蚀速率较高。因此，在中能工艺条件下，第二挡板2应对中能中心区域32a和中能边缘区域32c进行二次刻蚀，挡板可选择图7c和图7d所示的两种优选样式。
在如图7c所示的实施例中，第二挡板包括第二连接环22a和多个第二扇形块22b。
第二连接环的内径优选大于中能边缘区域32c的外径，避免对中能边缘区域32c的遮挡。
在本实施例中，第二扇形块22b可以为三块。第二扇形块沿周向均匀布设在第二连接环的内侧，每块第二扇形块与第二连接环的内壁面一体设置；相邻两块第二扇形块之间形成第二扇形间隙22c。
每个第二扇形块的拐角处均优选设置圆弧倒角，从而使得每个第二扇形块的内弧和外弧基本相当，从而扩大第二扇形间隙的外弧的弧长，从而能尽量减少对中能边缘区域32c的遮挡，便于二次刻蚀。
假设在半径r处，第二扇形块的弧长为L3，第二扇形间隙的弧长为L4，则L3＞L4。
第二扇形块22b的内径优选与中能中间区域32b的内径相对应，用于最大程度对中能中 间区域32b的离子束进行遮挡。
第二扇形块22b内的圆心空腔，优选与中能中心区域32a面积相对应，从而对中能中心区域32a进行二次刻蚀。
在如图7d所示的实施例中，第二挡板包括第二连接环22a和多个第二扇形块22b。
在本实施例中，第二扇形块22b优选为三块。第二扇形块沿周向均匀布设在第二连接环的内侧，每块第二扇形块均优选通过一个细条形的连接筋22d与第二连接环的内壁面相连接。
连接筋的径向位置优选与中能边缘区域32c相对应，径向长度优选与中能边缘区域32c相同。连接筋的轴向长度尽可能小，从而使得连接筋所在的环缝空隙尽量大，对中能边缘区域32c进行二次刻蚀的离子束最大，刻蚀效果好。
相邻两块第二扇形块之间形成第二扇形间隙22c。第二扇形间隙以及第二扇形块22b内圆心空腔的设置方式，参照上述实施例。
当工艺条件在高能条件(high beam voltage)下时，如图1c所示，第一工艺结束后，晶圆3表面的刻蚀速率为高能边缘区域33b最快，由高能边缘区域向高能中心区域33a逐渐降低。因此，第二挡板2可选择图7e和图7f所示样式，对中心区域进行二次刻蚀。
如图7e所示，第二挡板包括第二圆环板23b和沿第二圆环板周向均匀布设的倒扇形间隙23c，倒扇形间隙的弧长大端朝向第二圆环板的圆形空腔。
在如图7f所示的实施例中，第二挡板为第一圆环板。
在进行第二工艺时，除单独利用第二挡板2外，本申请还可根据情况将第一挡板1和第二挡板2组合工作，以满足刻蚀均匀性要求。利用两个挡板进行遮挡，可以针对更多情况进行刻蚀，以满足整体刻蚀均匀性需求。
如图8a所示，当边缘区刻蚀速率较慢时，在进行第二工艺时，可以由第一挡板1单独作用，对其他区域的等离子体密度进行遮挡，仅对边缘进行刻蚀，以满足整体刻蚀均匀性。
如图8b所示，当边缘和中心区域的刻蚀速率较快，中间出现一环状区域刻蚀速率较慢时，可以利用两个挡板，对环状区域进行二次刻蚀(见图中阴影区)。
本申请利用第二挡板2进行二次刻蚀，可以提高晶圆成品的整体刻蚀均匀性，增加晶圆的利用率。
以上详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种等同变换，这些等同变换均属于本申请的保护范围。

Claims (10)

  1. 一种改善刻蚀均匀性的双挡板装置，包括安装在刻蚀反应腔内的第一挡板和第二挡板；
    其中，所述第一挡板为整圆板，能在第一挡板驱动装置的作用下，对离子源产生的离子束进行全遮挡；
    晶圆采用两次刻蚀，第一次刻蚀为无挡板遮挡下的刻蚀，第二次刻蚀为采用所述第二挡板遮挡的刻蚀；
    所述第二挡板的结构根据刻蚀工况进行选择，能在第二挡板驱动装置的作用下，对所述第一次刻蚀时的所述晶圆的表面的刻蚀速率快的区域进行遮挡，使得所述晶圆的所述表面的所述刻蚀速率保持一致。
  2. 根据权利要求1所述的装置，其中，所述刻蚀工况包括低能工况、中能工况和高能工况。
  3. 根据权利要求2所述的装置，其中，当所述刻蚀工况为所述低能工况时，所述第二挡板包括中心圆板和沿所述中心圆板的周向均匀布设的多个第一扇形块，其中，所述中心圆板用于遮挡所述晶圆的所述表面的所述刻蚀速率快的低能中心区域。
  4. 根据权利要求3所述的装置，其中，相邻两个第一扇形块之间形成第一扇形间隙，在半径r处，所述第一扇形块的弧长为L1，所述第一扇形间隙的弧长为L2，其中L1＜L2。
  5. 根据权利要求3所述的装置，其中，所述第二挡板还包括同心套，所述同心套设在所述中心圆板的外周的第一连接环，所述多个第一扇形块沿周向均匀设置在所述中心圆板和所述第一连接环之间。
  6. 根据权利要求1所述的装置，其中，当所述刻蚀工况为中能工况时，所述第二挡板包括第二连接环和多个第二扇形块；所述多个第二扇形块沿周向均匀布设在所述第二连接环的内侧，每块所述第二扇形块直接或通过连接筋与所述第二连接环的内壁面相连接；相邻两块第二扇形块之间形成第二扇形间隙。
  7. 根据权利要求6所述的装置，其中，在半径r处，所述第二扇形块的弧长为L3，所述第二扇形间隙的弧长为L4，其中L3＞L4。
  8. 根据权利要求6所述的装置，其中，每个所述第二扇形块的拐角均为圆弧倒角。
  9. 根据权利要求1所述的装置，其中，当所述刻蚀工况为高能工况时，所述第二挡板为第一圆环板。
  10. 根据权利要求1所述的装置，其中，当所述刻蚀工况为高能工况时，所述第二挡板包括第二圆环板和沿所述第二圆环板的周向均匀布设的倒扇形间隙，所述倒扇形间隙的弧长大的一端朝向所述第二圆环板的圆形空腔。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116623184A (zh) * 2023-07-19 2023-08-22 西安精谐科技有限责任公司 一种半球谐振子的离子束刻蚀工装及离子束刻蚀修调方法

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CN116779412B (zh) * 2023-08-25 2023-11-24 江苏鲁汶仪器股份有限公司 离子源挡板装置和离子束刻蚀机
CN116959947B (zh) * 2023-09-21 2023-12-08 青禾晶元(天津)半导体材料有限公司 一种等离子体刻蚀装置及一种刻蚀碳膜的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207503916U (zh) * 2017-07-21 2018-06-15 武汉新芯集成电路制造有限公司 一种遮挡装置以及刻蚀机台
CN110047724A (zh) * 2019-04-22 2019-07-23 江苏鲁汶仪器有限公司 一种离子束刻蚀用双层挡板
US20200075294A1 (en) * 2018-07-31 2020-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. Baffle plate for controlling wafer uniformity and methods for making the same
CN211062693U (zh) * 2019-12-05 2020-07-21 德淮半导体有限公司 一种刻蚀设备
CN211208386U (zh) * 2019-11-29 2020-08-07 长春百纳光电子产品有限公司 一种离子束加工的修正装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9095038B2 (en) * 2011-10-19 2015-07-28 Advanced Micro-Fabrication Equipment, Inc. Asia ICP source design for plasma uniformity and efficiency enhancement
US10049862B2 (en) * 2015-04-17 2018-08-14 Lam Research Corporation Chamber with vertical support stem for symmetric conductance and RF delivery
US11749537B2 (en) * 2018-10-26 2023-09-05 Applied Materials, Inc. Side storage pods, equipment front end modules, and methods for operating equipment front end modules
CN109935513B (zh) * 2019-03-29 2021-08-06 江苏鲁汶仪器有限公司 一种离子束刻蚀系统
CN110571120B (zh) * 2019-09-17 2022-09-02 江苏鲁汶仪器有限公司 一种配置清洗设备的离子源刻蚀腔室及离子束清洗方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207503916U (zh) * 2017-07-21 2018-06-15 武汉新芯集成电路制造有限公司 一种遮挡装置以及刻蚀机台
US20200075294A1 (en) * 2018-07-31 2020-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. Baffle plate for controlling wafer uniformity and methods for making the same
CN110047724A (zh) * 2019-04-22 2019-07-23 江苏鲁汶仪器有限公司 一种离子束刻蚀用双层挡板
CN211208386U (zh) * 2019-11-29 2020-08-07 长春百纳光电子产品有限公司 一种离子束加工的修正装置
CN211062693U (zh) * 2019-12-05 2020-07-21 德淮半导体有限公司 一种刻蚀设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116623184A (zh) * 2023-07-19 2023-08-22 西安精谐科技有限责任公司 一种半球谐振子的离子束刻蚀工装及离子束刻蚀修调方法

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