WO2022141800A1 - 阻抗校准电路和方法 - Google Patents

阻抗校准电路和方法 Download PDF

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Publication number
WO2022141800A1
WO2022141800A1 PCT/CN2021/079751 CN2021079751W WO2022141800A1 WO 2022141800 A1 WO2022141800 A1 WO 2022141800A1 CN 2021079751 W CN2021079751 W CN 2021079751W WO 2022141800 A1 WO2022141800 A1 WO 2022141800A1
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Prior art keywords
pull
calibration
calibrated
resistor
voltage
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PCT/CN2021/079751
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English (en)
French (fr)
Inventor
王齐尉
梁爱梅
温长清
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深圳市紫光同创电子有限公司
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Priority to KR1020237015849A priority Critical patent/KR102715777B1/ko
Publication of WO2022141800A1 publication Critical patent/WO2022141800A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks
    • H03H11/30—Automatic matching of source impedance to load impedance

Definitions

  • the embodiments of the present application relate to the field of integrated circuit design, in particular, but not limited to, an impedance calibration circuit and method.
  • the impedance calibration circuit and method provided by the embodiments of the present application mainly solve the technical problem of how to simplify the process of impedance calibration.
  • an embodiment of the present application provides an impedance calibration circuit, and the method includes: a pull-up resistor device to be calibrated, a first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, and the pull-up resistor device to be calibrated is connected to the calibration unit.
  • the second connection end of the pull-up resistance device is connected to the power supply end; the pull-down resistance device to be calibrated, the first connection end of the pull-down resistance device to be calibrated is connected to the calibration unit, and the second connection of the pull-down resistance device to be calibrated
  • the terminal is connected to the third connection terminal of the pull-up resistance device to be calibrated, and the third connection terminal of the pull-down resistance device to be calibrated is grounded;
  • the calibration unit includes a voltage receiving end and a calibration code output end, and the calibration unit includes a voltage receiving end and a calibration code output end.
  • the calibration unit receives a first voltage and a second voltage through the voltage receiving terminal, the first voltage is the output voltage of the pull-up resistance device to be calibrated, and the second voltage is the output of the pull-down resistance device to be calibrated voltage, the calibration unit is configured to obtain a first calibration code and a second calibration code according to the first voltage and the second voltage, and the calibration unit is configured to use the first calibration code to The resistance value of the pull-down resistance device is calibrated, and the second calibration code is used to calibrate the resistance value of the pull-down resistance device to be calibrated.
  • the impedance calibration circuit further includes a calibration resistor, the first connection end of the calibration resistor is respectively connected to the pull-up resistor device to be calibrated and the calibration unit, and the second connection end of the calibration resistor is grounded .
  • the pull-up resistor device to be calibrated includes a plurality of pull-up sub-resistor devices, each of the pull-up sub-resistor devices includes a first switch element and a first resistor, and the first connection of the first switch element is The terminal is connected to the power terminal, the control terminal of the first switch element is connected to the calibration unit, the second connection terminal of the first switch element is connected to the first connection terminal of the first resistor, and the The second connection end of the first resistor is respectively connected with the calibration resistor and the pull-down resistor device to be calibrated.
  • the first switching element is a PMOS transistor
  • the source of the PMOS transistor is connected to the power supply terminal
  • the gate of the PMOS transistor is connected to the calibration unit
  • the drain of the PMOS transistor is connected to the calibration unit.
  • the first connection end of the first resistor is connected.
  • the pull-down resistor device to be calibrated includes a plurality of pull-down sub-resistor devices, each of the pull-down sub-resistor devices includes a second resistor and a second switch element, and the first connection end of the second resistor is connected to the the first resistor is connected, the second connection end of the second resistor is connected to the first connection end of the second switch element, the control end of the second switch element is connected to the calibration unit, the second switch The second connection terminal of the element is grounded.
  • the second switch element is an NMOS transistor
  • the source of the NMOS transistor is connected to the second connection end of the second resistor
  • the gate of the NMOS transistor is connected to the calibration unit
  • the The drain terminal of the NMOS transistor is grounded.
  • the impedance calibration circuit further includes a calibration resistor, a first connection end of the calibration resistor is respectively connected to the pull-down resistor device to be calibrated and the calibration unit, and a second connection end of the calibration resistor is grounded.
  • the calibration unit includes a comparator, a logic processing unit, a converter and a latch;
  • the comparator includes a first voltage receiving end and a second voltage receiving end, and the first voltage receiving end is used for receiving the first voltage or the second voltage, the second voltage receiving end is configured to receive the reference voltage, and the comparator is configured to compare the first voltage with the reference voltage to obtain the first calibration code, and comparing the second voltage with the reference voltage to obtain the second calibration code;
  • the first connection end of the logic processing unit is connected to the comparator, and the second connection end of the logic processing unit is connected to the comparator.
  • connection end is connected to the first connection end of the converter
  • second connection end of the converter is connected to the first connection end or the second connection end of the latch
  • the second connection end of the latch is connected
  • the terminal is connected to the pull-up resistor device to be calibrated, and the latch is used for storing the first calibration code or the second calibration code transmitted by the converter.
  • an embodiment of the present application further provides an impedance calibration method, the method is applied to the impedance calibration circuit of the first aspect, the method includes: receiving a first voltage and a second voltage, the first voltage being the The output voltage of the pull-up resistor device to be calibrated, the second voltage is the output voltage of the pull-down resistor device to be calibrated; the first calibration code and the second calibration code are obtained according to the first voltage and the second voltage; The resistance value of the to-be-calibrated pull-up resistor device is calibrated using the first calibration code, and the resistance value of the to-be-calibrated pull-down resistor device is calibrated using the second calibration code.
  • the use of the first calibration code to calibrate the resistance value of the pull-up resistance device to be calibrated, and the use of the second calibration code to calibrate the resistance value of the pull-down resistance device to be calibrated includes: determining the number of effective resistances according to the first calibration code and the second calibration code, and adjusting the resistance values of the pull-up resistance device to be calibrated and the pull-down resistance device to be calibrated according to the number of effective resistances Perform calibration.
  • An impedance calibration circuit and method provided by embodiments of the present application include a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated, and a calibration unit, wherein a first connection end of the pull-up resistor device to be calibrated is connected to the The calibration unit is connected, the second connection end of the pull-up resistance device to be calibrated is connected to the power supply end, the first connection end of the pull-down resistance device to be calibrated is connected to the calibration unit, and the second connection end of the pull-down resistance device to be calibrated is connected to the calibration unit.
  • the connection end is connected to the third connection end of the pull-up resistance device to be calibrated, the third connection end of the pull-down resistance device to be calibrated is grounded, the calibration unit includes a voltage receiving end and a calibration code output end, and the calibration unit passes through the The voltage receiving end receives a first voltage and a second voltage, the first voltage is the output voltage of the pull-up resistor device to be calibrated, the second voltage is the output voltage of the pull-down resistor device to be calibrated, and the The calibration unit is configured to obtain a first calibration code and a second calibration code according to the first voltage and the second voltage, and the calibration unit is configured to use the first calibration code to perform calibration of the pull-up resistor device to be calibrated.
  • the resistance value is calibrated, and the resistance value of the pull-down resistance device to be calibrated is calibrated by using the second calibration code.
  • 1 is a schematic structural diagram of a basic impedance calibration circuit
  • Figure 2 is a schematic diagram of the pull-up resistor calibration structure in the basic impedance calibration circuit
  • FIG. 3 is a schematic diagram of the structure corresponding to the pull-up resistor calibration in the basic impedance calibration circuit
  • FIG. 4 is a schematic structural diagram corresponding to the pull-down resistance calibration in the basic impedance calibration circuit
  • FIG. 5 is a schematic structural diagram of an impedance calibration circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a physical structure of an impedance calibration circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a pull-up resistor device to be calibrated in an impedance calibration circuit provided by an embodiment of the present application
  • FIG. 8 is a schematic diagram of a pull-down resistor device to be calibrated in an impedance calibration circuit provided by an embodiment of the present application
  • FIG. 9 is a method flowchart of an impedance calibration method provided by an embodiment of the present application.
  • FIG. 10 is a circuit block diagram corresponding to a pull-up resistor device to be calibrated in an impedance calibration method provided by an embodiment of the present application;
  • FIG. 11 is a circuit block diagram corresponding to a pull-down resistance device to be calibrated in an impedance calibration method provided by an embodiment of the present application.
  • the high-speed IO (Input Output) of the chip usually requires the impedance of the transmitting end and the receiving end to match the impedance with the characteristic impedance of the channel.
  • the characteristic impedance of the channel is generally 50 ⁇ .
  • the impedance needs to be calibrated.
  • the IO in FPGA Field-Programmable Gate Array, Field Programmable Gate Array
  • FPGA Field-Programmable Gate Array, Field Programmable Gate Array
  • the level standards of different protocols make the transistor work in different voltage regions, and the output impedance of the transistor will also be different. . Therefore, a single impedance calibration condition cannot be guaranteed to be generally applicable or to meet accuracy requirements.
  • choosing different calibration adjustments for different protocols will consume a lot of costs.
  • the fewer the number of IOs allowed for calibration the more resources can be provided to the application side. Therefore, reducing the IO resources used for calibration is an urgent problem to be solved.
  • R u and R d are the pull-up and pull-down output impedances respectively
  • MP ⁇ m:0> is the control code for adjusting the pull-up impedance
  • MP ⁇ m:0> is used to control the number of branches that are turned on and turned on.
  • MP ⁇ m:0> 11000, which means that 2 channels are turned on and the other 3 channels are turned off
  • MN ⁇ m:0> is used to adjust the pull-down impedance.
  • Control code, MN ⁇ m:0> is used to control the number of branches that are turned on. Due to the requirements of impedance matching, it is necessary to ensure that R u and R d reach a reliable accuracy range, so the pull-up and pull-down resistors need to be calibrated separately.
  • the existing calibration method is shown in Figure 2, where V ref in Figure 2 is the reference voltage, V out is the output voltage, and the calibration circuit module The function is to compare the voltages of V out and V ref , determine the magnitude of the two values, and then adjust the number of conduction paths by comparing the obtained control code MP ⁇ m:0> to adjust the driving strength, so that the output voltage of V out is equal to The set reference voltage V ref .
  • V CCIO 1.2V
  • the external VC needs to be grounded.
  • Vout is calibrated to 0.5*V CCIO
  • R u R ref
  • Flat is 0.5*V CCIO .
  • the calibration circuits of protocol 1 and protocol 2 are shown in Figure 3 and Figure 4. It can be seen from Figure 3 and Figure 4 that when the common mode level is required to be 0.5*V CCIO , the external VC needs to be connected to V CCIO , and the common mode voltage When the level requirement is 0.5*V CCIO , you need to connect the external VC to 0.75V CCIO .
  • the inventor proposes the impedance calibration circuit and method provided by the embodiments of the present application.
  • the embodiments of the present application can simplify the implementation conditions of impedance calibration by combining the pull-up resistor device to be calibrated, the pull-down resistor device to be calibrated, and the calibration unit. To a certain extent, the plate making requirements can be reduced.
  • the impedance calibration circuit 100 may include a pull-up resistor device to be calibrated 110 , a pull-down resistor device to be calibrated 120 , and a calibration unit 130 .
  • the first connection terminal 111 of the pull-up resistor device 110 to be calibrated is connected to the calibration unit 130
  • the second connection terminal 112 of the pull-up resistor device to be calibrated 110 is connected to the power terminal 114 .
  • the first connection end 121 of the pull-down resistance device 120 to be calibrated is connected to the calibration unit 130
  • the second connection end 122 of the pull-down resistance device to be calibrated 120 is connected to the third connection of the pull-up resistance device 110 to be calibrated
  • the terminal 113 is connected, and the third connection terminal 123 of the pull-down resistance device 120 to be calibrated is grounded.
  • the calibration unit 130 may include a voltage receiving end 131 and a calibration code output end 132, the calibration unit 130 receives a first voltage and a second voltage through the voltage receiving end 131, and the first voltage is the the output voltage of the pull-up resistor device 110 to be calibrated, the second voltage is the output voltage of the pull-down resistor device 120 to be calibrated, and the calibration unit 130 obtains the first voltage according to the first voltage and the second voltage
  • the calibration unit 130 is configured to use the first calibration code to calibrate the resistance value of the pull-up resistor device 110 to be calibrated, and use the second calibration code to calibrate the resistance value of the to-be-calibrated pull-up resistor device 110 Calibration is performed by calibrating the resistance value of the pull-down resistor device 120 .
  • the embodiment of the present application provides a physical structure diagram of a calibration circuit as shown in FIG. 6 .
  • the impedance calibration circuit 100 may further include a calibration resistor 140 in addition to the pull-up resistor device 110 to be calibrated, the pull-down resistor device 120 to be calibrated, and the calibration unit 130 .
  • the first connection end of the calibration resistor 140 is respectively connected to the pull-up resistor device to be calibrated 110 and the calibration unit 130 , and the second connection end of the calibration resistor 140 is grounded (GND).
  • the pull-up resistor device 110 to be calibrated includes a plurality of pull-up sub-resistor devices 115 , each of the pull-up sub-resistor devices 115 (R u ) includes a first switch element 1151 and a first resistor 1152 , the The first connection terminal of the first switching element 1151 is connected to the power terminal 114 (V CCIO ), the control terminal of the first switching element 1151 is connected to the calibration unit 130 , and the second switching element 1151 is connected to the calibration unit 130 .
  • the connection end is connected to the first connection end of the first resistor 1152 , and the second connection end of the first resistor 1152 is respectively connected to the calibration resistor 140 (R ref ) and the pull-down resistor device 120 to be calibrated.
  • the first switching element 1151 is a PMOS transistor, the source of the PMOS transistor is connected to the power supply terminal, the gate of the PMOS transistor is connected to the calibration unit 130, the The drain of the PMOS transistor is connected to the first connection terminal of the first resistor 1152 .
  • the first switch element 1152 may also be an NMOS transistor, and the specific type of the switch of the first switch element 1152 is not specifically limited here, and can be selected according to the actual situation.
  • the pull-down resistor device 120 to be calibrated includes a plurality of pull-down sub-resistor devices 124 (R d ), each of the pull-down sub-resistor devices 124 includes a second resistor 1241 and a second switch element 1242 , the The first connection end of the second resistor 1241 is connected to the first resistor 1152 , the second connection end of the second resistor 1241 is connected to the first connection end of the second switch element 1242 , and the second switch element 1242 The control terminal of the second switch element 1242 is connected to the calibration unit 130, and the second connection terminal of the second switch element 1242 is grounded (GND).
  • the second switching element 1242 is an NMOS transistor, the source of the NMOS transistor can be connected to the second connection terminal of the second resistor 1241, and the gate of the NMOS transistor can be connected to the second connection terminal of the second resistor 1241.
  • the calibration unit 130 is connected, and the drain terminal of the NMOS transistor is grounded.
  • the second switching element 1242 may also be a PMOS transistor.
  • the specific switch of the second switching element 1242 is not specifically limited here, and can be selected according to the actual situation.
  • FIG. 7 is a schematic structural diagram of the pull-up resistor device to be calibrated. It can be seen from FIG. 7 that the calibration unit 130 may include a comparator 133 , a logic processing unit 134 , a converter 135 and a latch 136 .
  • the comparator 133 may include a first voltage receiving terminal and a second voltage receiving terminal, the first voltage receiving terminal is configured to receive the first voltage or the second voltage (V out ), the first voltage receiving terminal Two voltage receiving terminals are used to receive the reference voltage (V ref ).
  • the first voltage receiving terminal may include a first sub-voltage receiving terminal and a second sub-voltage receiving terminal.
  • the calibration unit 130 communicates with the to-be-calibrated voltage receiving terminal through the first sub-voltage receiving terminal.
  • the pull-up resistor device 110 is connected and receives the output voltage of the pull-up resistor device to be calibrated, and the output voltage can be used as the first voltage;
  • the calibration unit 130 is connected to the pull-down resistor device to be calibrated 120 through the second sub-voltage receiving terminal, and receives the to-be-calibrated pull-down resistor device 120 The output voltage of the pull-down resistor device can be used as the second voltage.
  • the comparator 133 is configured to compare the first voltage with the reference voltage, obtain the first calibration code (Mp ⁇ m:0>), and compare the second voltage with the reference voltage. By comparison, the second calibration code (Mn ⁇ m:0>) is obtained.
  • the impedance calibration circuit may further include a clock generating sub-circuit, and the clock generating sub-circuit is connected to the logic processing unit 134 for providing a clock signal to the logic processing unit 134 .
  • the second connection end of the converter 135 is connected to the first connection end or the second connection end of the latch, and the function of the converter 135 is to control the calibration of the resistance value of the pull-up resistor device 110 to be calibrated.
  • the impedance calibration circuit 100 is used to calibrate the pull-up branch in the pull-up branch.
  • the resistance value of the pull-up resistor device 110 is calibrated and adjusted.
  • the pull-down branch is in a closed state, that is, the second calibration code (Mn ⁇ m:0>) of the pull-down branch is set to 0.
  • the pull-down resistor device to be calibrated is set to 0.
  • the pull-down branch where 120 is located is closed.
  • the second connection end of the latch 136 is connected to the pull-up resistor device 110 to be calibrated, and the latch 136 is used to transmit the first calibration code or the second calibration code transmitted by the converter 135 to store.
  • the inputs of the comparator 133 are the reference voltage (Vref) and the first voltage (Vout1), wherein the first voltage is the pull-up resistor device 110 to be calibrated
  • the converter 135 is connected to the first calibration code value (Mp ⁇ m:0>) of the IO1 corresponding to the pull-up resistor device 110 to be calibrated.
  • the internal pull-down branch (the branch where the pull-down resistor device 120 to be calibrated is located) is turned off by setting the second calibration code value (Mn ⁇ m:0>) to 0.
  • a first calibration code (Mp ⁇ m:0>) can be obtained through the comparator 133 and the logic processing unit 134, and then the resistance in the pull-up resistor device 110 to be calibrated can be adjusted to a high level based on the first calibration code.
  • the adjustment to the low bit causes the first voltage Vout to gradually approach the reference voltage Vref until the last bit is quantized.
  • the acquired value of the first calibration code Mp ⁇ m:0> is stored by the latch. In this way, the calibration of the resistance value of the pull-up resistor device to be calibrated can be realized.
  • the converter 130 switches to Mn ⁇ m:0> of IO2 (the branch where the pull-down resistor device 120 to be calibrated is located), and one end of the comparator 133 is connected to the reference voltage at this time.
  • the other end of Vref is connected to the voltage output end of the pull-down resistor device 120 to be calibrated for receiving the second voltage.
  • the structure of the pull-down resistor device 120 to be calibrated is shown in FIG. 8 . It can be seen from FIG. 8 that when calibrating the resistance value of the pull-down resistor device 120 to be calibrated, it is mainly based on the pull-up resistor device 110 to be calibrated. to obtain the first calibration code.
  • the first calibration code Mp ⁇ m:0> obtained by the calibration of the pull-up resistor device 110 to be calibrated is mainly mapped to Mp ⁇ m:0> of IO2.
  • the second calibration code Mn ⁇ m:0> is obtained through the comparator 133 and the logic processing unit 134, and then, based on the second calibration code, the resistance in the pull-down resistor 120 to be calibrated can be adjusted from high to low, so that the second voltage Vout gradually approaches the reference voltage Vref until the last bit is quantized. At this time, the acquired second calibration code Mn ⁇ m:0> is stored by the latch.
  • the first calibration code value Mp ⁇ m:0> and the second calibration code value Mn ⁇ m:0> output by the calibration unit 130 correspond to the driving of each segment, and the output impedance is a calibrated pull-up The resistance value of the resistor R u and the pull-down resistor R d .
  • the calibration resistor 140 included in the impedance calibration circuit 100 may also be connected to the pull-down resistor device 120 to be calibrated (not shown). Specifically, the first connection end of the calibration resistor 140 They are respectively connected to the pull-down resistor device 120 to be calibrated and the calibration unit 130 , and the second connection end of the calibration resistor 140 is grounded.
  • the pull-down resistor device 120 to be calibrated includes a plurality of pull-down sub-resistor devices 124, each of the pull-down sub-resistor devices 124 may include a second switch element 1242 and a second resistor 1241, the second switch element 1242 The first connection end of the second switch element 1242 is connected to the power supply end 114 , the control of the second switch element 1242 is connected to the calibration unit 130 , and the second connection end of the second switch element 1242 is connected to the second connection end of the second resistor 1241 The first connection end is connected, and the second connection end of the second resistor 1242 is respectively connected to the calibration resistor 140 and the to-be-calibrated pull-up resistor device 110 .
  • the second switching element 1242 may be a PMOS transistor or an NMOS transistor.
  • the to-be-calibrated pull-up resistor device 110 includes a plurality of pull-up sub-resistor devices 115 , each of the pull-up sub-resistor devices 115 (R u ) includes a first switch element 1151 and a first resistor 1152 , the first connection end of the first resistor 1152 is connected to the second resistor 1242, the second connection end of the first resistor 1152 is connected to the first connection end of the first switching element 1151, the A control terminal of a switch element 1151 is connected to the calibration unit 130 , and a connection terminal of the first switch element 1151 is grounded.
  • the first switching element 1242 may be a PMOS transistor or an NMOS transistor.
  • a calibration resistor 140 can be connected to the pull-up resistor device 110 to be calibrated, and the resistance value of the pull-up resistor device 110 to be calibrated can be calibrated through the calibration resistor 140, and then based on the pull-up resistor to be calibrated
  • the calibration result of the device 110 calibrates the resistance value of the pull-down resistor device 120 to be calibrated; alternatively, in this embodiment of the present invention, a calibration resistor 140 may be connected to the pull-down resistor device 120 to be calibrated, and the pull-down resistor device 120 to be calibrated can be connected through the calibration resistor 140 Then, the resistance value of the pull-up resistor device 110 to be calibrated is calibrated based on the calibration result of the pull-down resistor device 120 to be calibrated.
  • the calibration resistor 140 can be connected to the pull-up resistor device 110 to be calibrated or the pull-down resistor device 120 to be calibrated. Specifically, it is not connected to the pull-up resistor device 110 to be calibrated or the pull-down resistor device 120 to be calibrated. Explicit restrictions can be selected according to the actual situation.
  • An impedance calibration circuit provided by an embodiment of the present application includes a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated, and a calibration unit, wherein a first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit.
  • the calibration unit includes a voltage receiving end and a calibration code output end, and the calibration unit passes the voltage The receiving end receives a first voltage and a second voltage, the first voltage is the output voltage of the pull-up resistor device to be calibrated, the second voltage is the output voltage of the pull-down resistor device to be calibrated, the calibration unit for obtaining a first calibration code and a second calibration code according to the first voltage and the second voltage, and the calibration unit is configured to use the first calibration code to determine the resistance value of the pull-up resistor device to be calibrated Perform calibration, and use the second calibration code to calibrate the resistance value of the pull-
  • FIG. 9 is a method flowchart of an impedance calibration method provided by an embodiment of the present application.
  • the flowchart is applied to the above impedance calibration circuit. It can be seen from FIG. 9 that the method may include steps S110 to S130 .
  • Step S110 Receive a first voltage and a second voltage, where the first voltage is the output voltage of the pull-up resistor device to be calibrated, and the second voltage is the output voltage of the pull-down resistor device to be calibrated.
  • Step S120 Obtain a first calibration code and a second calibration code according to the first voltage and the second voltage.
  • the embodiment of the present invention can compare the first voltage with the reference voltage when the first voltage is obtained, and determine whether the first voltage is greater than the reference voltage, and if it is greater, the number of bits corresponding to the first calibration code value is 1, and if the first voltage is less than the reference voltage, the number of bits corresponding to the first calibration code value is 0.
  • the embodiment of the present invention may adjust the first voltage, that is, increase the first voltage, and then compare the increased first voltage with the reference voltage again to obtain the first voltage
  • Another digit value corresponding to the calibration code how many times are compared, the number of digits of the corresponding code value is the number of digits, and the specific number of comparisons can be selected according to the actual situation, and there is no explicit limit here.
  • MP ⁇ m:0> controls the corresponding branch of the pull-up resistor to be calibrated that is turned on. number of roads.
  • the embodiment of the present invention can also determine whether the first voltage is greater than the reference voltage, and if it is less than the reference voltage, the first voltage is correspondingly increased, so as to realize the calibration of the pull-up resistor or the pull-down resistor.
  • the embodiment of the present invention can also compare the second voltage with the reference voltage when the second voltage is acquired, and determine whether the second voltage is greater than the reference voltage, and if it is greater than the reference voltage, the second calibration code The digit corresponding to the value is 1, and if the second voltage is less than the reference voltage, the digit corresponding to the second calibration code value is 0.
  • the embodiment of the present invention may adjust the second voltage, that is, increase the second voltage, and then compare the increased second voltage with the reference voltage again to obtain the second voltage
  • the other digit value corresponding to the calibration code how many times the comparison is made, the number of digits of the corresponding code value is the number of digits.
  • the reference voltage and the second voltage are compared and adjusted five times, and the second voltage is greater than the reference voltage for the first three times, and the second voltage is smaller than the reference voltage for the second two times.
  • Step S130 Use the first calibration code to calibrate the resistance value of the pull-up resistance device to be calibrated, and use the second calibration code to calibrate the resistance value of the pull-down resistance device to be calibrated.
  • the implementation of the present invention can use the first calibration code to calibrate the resistance of the pull-up resistor device to be calibrated, and can use the second calibration code to pull down the pull-down device to be calibrated The resistance value of the resistive device is calibrated.
  • the embodiment of the present invention can also obtain the number N p of the first resistors connected in the pull-up resistor to be calibrated and the pull-down resistor to be calibrated according to a preset formula
  • the number N n of the second resistors connected in the device is obtained, and the resistance value R ref of the calibration resistor is obtained.
  • R ref a*R u
  • V ref b*V CCIO
  • R ref the calibration resistor
  • R u the pull-up resistor
  • V CCIO the first voltage
  • a the resistivity coefficient
  • b the voltage coefficient, where b ⁇ (0,1).
  • Vref the reference voltage
  • N p refers to the number of effective resistors in the pull-up resistor device to be calibrated, that is, the number of segments in the pull-up resistor device to be calibrated.
  • the number of segments is Np +1.
  • R u refers to the pull-up resistor value
  • R ref refers to the calibration resistor value
  • V CCIO refers to the output voltage value of the pull-up resistor device to be calibrated, that is, the first voltage value
  • V ref refers to the reference voltage value .
  • the embodiment of the present invention can convert it into the solution of a and b, that is, the following formula is obtained:
  • the Converting the numerator and denominator to the smallest irreducible integer we get It can be known from the above description that the reference voltage V ref is known, so the b value is known.
  • the first voltage V CCIO 1V
  • the reference voltage V ref 0.7V
  • the obtained b value is brought into the above formula
  • the number of effective resistances may be determined according to the first calibration code and the second calibration code, and the pull-up resistance device to be calibrated and the The resistance value of the pull-down resistor device to be calibrated is calibrated.
  • schematic diagrams of calibration results as shown in Figure 10 and Figure 11 can be obtained.
  • the embodiment of the present invention can fully utilize configurable resources and achieve an optimal solution of convenience and resource utilization, considering comprehensively the IO configurable driving capability.
  • the embodiment of the present invention aims at the calibration function under different common-mode levels (reference voltage), which is integrated inside the chip and can be easily realized through configuration without the need to provide an external voltage source, which simplifies the realization conditions of impedance calibration. Plate making requirements can be reduced.
  • an impedance calibration circuit and method provided by the embodiments of the present application can be used to calibrate impedance more simply and efficiently by using an impedance calibration circuit
  • the impedance calibration circuit includes a pull-up resistor device to be calibrated, A pull-down resistor device to be calibrated and a calibration unit, wherein a first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, a second connection end of the pull-up resistor device to be calibrated is connected to a power supply end, and a pull-down resistor device to be calibrated is pulled down
  • the first connection end of the resistance device is connected to the calibration unit
  • the second connection end of the pull-down resistance device to be calibrated is connected to the third connection end of the pull-up resistance device to be calibrated
  • the pull-down resistance device to be calibrated is connected to the third connection end of the pull-down resistance device to be calibrated.
  • the third connection end is grounded
  • the calibration unit includes a voltage receiving end and a calibration code output end
  • the calibration unit receives a first voltage and a second voltage through the voltage receiving end
  • the first voltage is the pull-up resistor to be calibrated the output voltage of the device
  • the second voltage is the output voltage of the pull-down resistor device to be calibrated
  • the calibration unit is configured to obtain a first calibration code and a second calibration code according to the first voltage and the second voltage
  • the calibration unit is configured to use the first calibration code to calibrate the resistance value of the pull-up resistance device to be calibrated
  • use the second calibration code to calibrate the resistance value of the pull-down resistance device to be calibrated .
  • the present application can realize the calibration of the resistance more simply and effectively, which simplifies the conditions of impedance calibration to a certain extent.
  • the embodiment of the present invention only needs one calibration resistor during calibration, and part of the IO can be released after the calibration is completed, which saves the IO and enhances the general applicability of customers.
  • communication media typically embodies computer readable instructions, data structures, computer program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery, as is well known to those of ordinary skill in the art medium. Therefore, the present invention is not limited to any particular combination of hardware and software.

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Abstract

一种阻抗校准电路和方法，该阻抗校准电路(100)包括：待校准上拉电阻器件(110)，所述待校准上拉电阻器件(110)的第一连接端(111)与所述校准单元(130)连接，所述待校准上拉电阻器件(110)的第二连接端(112)与电源端(114)连接；待校准下拉电阻器件(120)，所述待校准下拉电阻器件(120)的第一连接端(121)与所述校准单元(130)连接，所述待校准下拉电阻器件(120)的第二连接端(122)与所述待校准上拉电阻器件(110)的第三连接端(113)连接，所述待校准下拉电阻器件(120)的第三连接端(123)接地；校准单元(130)，所述校准单元(130)包括电压接收端(131)和校准码输出端(132)，所述校准单元(130)通过所述电压接收端(131)接收第一电压和第二电压。通过利用待校准上拉电阻器件(110)、待校准下拉电阻器件(120)以及校准单元(130)可以更加简单高效的实现对电阻的校准。

Description

阻抗校准电路和方法
相关申请的交叉引用
本申请要求于2020年12月30日提交的申请号为202011612009.X的中国申请的优先权，其在此处于所有目的通过引用将其全部内容并入本文。
技术领域
本申请实施例涉及集成电路设计领域，具体而言，涉及但不限于一种阻抗校准电路和方法。
背景技术
随着电子信息技术的发展，对芯片内部晶体管阻值的要求越来越高，如在各种晶体管的制作过程中，由于晶体管内电阻的阻值随工艺变化较大，通常难以直接制作出具有精确阻值的片内电阻，因此需要另外对芯片内电阻的阻值进行校准，因此如何更好的对芯片内的阻抗进行校准是亟待解决的问题。
发明内容
本申请实施例提供的一种阻抗校准电路和方法，主要解决的技术问题如何简化阻抗校准的过程。
第一方面，本申请实施例提供一种阻抗校准电路，该方法包括：待校准上拉电阻器件，所述待校准上拉电阻器件的第一连接端与所述校准单元连接，所述待校准上拉电阻器件的第二连接端与电源端连接；待校准下拉电阻器件，所述待校准下拉电阻器件的第一连接端与所述校准单元连接，所述待校准下拉电阻器件的第二连接端与所述待校准上拉电阻器件的第三连接端连接，所述待校准下拉电阻器件的第三连接端接地；校准单元，所述校准单元包括电压接收端和校准码输出端，所述校准单元通过所述电压接收端接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压，所述校准单元用于根据所述第一电压和所述第二电压得到第一校准码和第二校准码，所述校准单元用于利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。
可选的，所述阻抗校准电路还包括校准电阻，所述校准电阻的第一连接端分别与所述待校准上拉电阻器件和所述校准单元连接，所述校准电阻的第二连接端接地。
可选的，所述待校准上拉电阻器件包括多个上拉子电阻器件，每个所述上拉子电阻器件包括第一开关元件和第一电阻，所述第一开关元件的第一连接端与所述电源端连接，所述第一开关元件的控制端与所述校准单元连接，所述第一开关元件的第二连接端与所述第一电阻的第一连接端连接， 所述第一电阻的第二连接端分别与所述校准电阻和所述待校准下拉电阻器件连接。
可选的，所述第一开关元件为PMOS晶体管，所述PMOS晶体管的源极与所述电源端连接，所述PMOS晶体管的栅极与所述校准单元连接，所述PMOS晶体管的漏极与所述第一电阻的第一连接端连接。
可选的，所述待校准下拉电阻器件包括多个下拉子电阻器件，每个所述下拉子电阻器件包括第二电阻和第二开关元件，所述第二电阻的第一连接端与所述第一电阻连接，所述第二电阻的第二连接端与所述第二开关元件的第一连接端连接，所述第二开关元件的控制端与所述校准单元连接，所述第二开关元件的第二连接端接地。
可选的，所述第二开关元件为NMOS晶体管，所述NMOS晶体管的源极与所述第二电阻的第二连接端连接，所述NMOS晶体管的栅极与所述校准单元连接，所述NMOS晶体管的漏极端接地。
可选的，所述阻抗校准电路还包括校准电阻，所述校准电阻的第一连接端分别与所述待校准下拉电阻器件和所述校准单元连接，所述校准电阻的第二连接端接地。
可选的，所述校准单元包括比较器、逻辑处理单元、转换器和锁存器；所述比较器包括第一电压接收端和第二电压接收端，所述第一电压接收端用于接收所述第一电压或者第二电压，所述第二电压接收端用于接收所述参考电压，所述比较器用于将所述第一电压和所述参考电压进行比较，得到所述第一校准码，以及将所述第二电压与所述参考电压进行比较，得到所述第二校准码；所述逻辑处理单元的第一连接端与所述比较器连接，所述逻辑处理单元的第二连接端与所述转换器的第一连接端连接，所述转换器的第二连接端与所述锁存器的第一连接端或者第二连接端连接，所述锁存器的第二连接端与所述待校准上拉电阻器件连接，所述锁存器用于将所述转换器传输的第一校准码或者第二校准码进行存储。
第二方面，本申请实施例还提供一种阻抗校准方法，该方法应用于第一方面的阻抗校准电路，所述方法包括：接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压；根据所述第一电压和所述第二电压得到第一校准码和第二校准码；利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。
可选的，所述利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准，包括：根据所述第一校准码和所述第二校准码确定有效电阻的数量，并根据所述有效电阻的数量对所述待校准上拉电阻器件和所述待校准下拉电阻器件的电阻值进行校准。
本申请实施例提供的一种阻抗校准电路和方法，该阻抗校准电路包括待校准上拉电阻器件、待校准下拉电阻器件以及校准单元，其中，待校准上拉电阻器件的第一连接端与所述校准单元连接，所述待校准上拉电阻器件的第二连接端与电源端连接，待校准下拉电阻器件的第一连接端与所述校 准单元连接，所述待校准下拉电阻器件的第二连接端与所述待校准上拉电阻器件的第三连接端连接，所述待校准下拉电阻器件的第三连接端接地，校准单元包括电压接收端和校准码输出端，所述校准单元通过所述电压接收端接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压，所述校准单元用于根据所述第一电压和所述第二电压得到第一校准码和第二校准码，所述校准单元用于利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。本申请通过结合待校准上拉电阻器件、待校准下拉电阻器件以及校准单元可以更加简单有效的实现对电阻的校准，在一定程度上可以简化阻抗校准的条件。
本发明其他特征和相应的有益效果在说明书的后面部分进行阐述说明，且应当理解，至少部分有益效果从本发明说明书中的记载变的显而易见。
附图说明
图1为一种基础阻抗校准电路的结构示意图；
图2为基础阻抗校准电路中上拉电阻校准结构示意图；
图3为基础阻抗校准电路中上拉电阻校准对应的结构示意图；
图4为基础阻抗校准电路中下拉电阻校准对应的结构示意图；
图5为本申请一实施例提供的一种阻抗校准电路的结构示意图；
图6为本申请一实施例提供的一种阻抗校准电路的实体结构示意图；
图7为本申请一实施例提供的一种阻抗校准电路中待校准上拉电阻器件的示意图；
图8为本申请一实施例提供的一种阻抗校准电路中待校准下拉电阻器件的示意图；
图9为本申请一实施例提供的一种阻抗校准方法的方法流程图；
图10为本申请一实施例提供的一种阻抗校准方法中待校准上拉电阻器件对应的电路框图；
图11为本申请一实施例提供的一种阻抗校准方法中待校准下拉电阻器件对应的电路框图。
具体实施方式
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
目前为了保证信号完整性需求，芯片高速IO(Input Output)通常会要求发射端和接收端阻抗，以使该阻抗与信道特征阻抗相匹配，其中，信道特征阻抗一般为50Ω。然而由于工艺制作的差异会导致芯片内部晶体管与电阻之间存在偏差，该偏差上下约为20％，所以为了避免该偏差对信号完整 性的影响，需要对该阻抗进行校准。由于FPGA(Field-Programmable Gate Array，现场可编程门阵列)中IO通常需要支持非常多协议要求，而不同协议的电平标准，使得晶体管工作于不同电压区域，且晶体管输出阻抗也会有所不同。因此，单一的阻抗校准条件，不能保证普通适用或满足精度要求。并且，不同的协议选择不同的校准调节会消耗很多的成本。此外，由于IO资源有限，用于校准的准用IO数量越少，能提供给应用端的资源便更多，所以减少校准使用的IO资源是亟待解决的问题。
现有的阻抗校准电路的基础结构如图1所示，图1中的R u和R d分别为上拉和下拉输出阻抗，MP<m:0>为调整上拉阻抗的控制码，MP<m:0>用于控制打开导通的支路个数，如MP<m:0>＝11000，表示打开2个通道，以及关闭另外3个通道；MN<m:0>为调整下拉阻抗的控制码，MN<m:0>用于控制打开导通的支路个数。由于阻抗匹配的要求，需要保证R u和R d达到可靠的精度范围，所以需要分别对上拉电阻和下拉电阻进行校准。
以校准上拉输出阻抗R u为例(此时下拉路径为关闭状态)，现有的校准方式如图2所示，图2中的V ref为参考电压，V out为输出电压，校准电路模块的作用是比较V out与V ref的电压，判断两者值的大小，再通过比较获取的控制码MP<m:0>调整导通路径的个数以调整驱动强度，使得V out输出电压等于设定的参考电压V ref。
现有技术在对不同协议的阻抗进行校准时，其需要外接不同的电阻和电压，其在一定程度上增大了芯片配置的成本，适用性比较低。如协议1要求共模电平为0.5*V CCIO(V CCIO＝1.2V)，那么需要将外接VC接地，当Vout校准至0.5*V CCIO，此时R u＝R ref，且符合共模电平为0.5*V CCIO。又如协议2要求共模电平为0.75*V CCIO(V CCIO＝1.2V)，需要将外接VC接0.5*V CCIO，当Vout校准至0.75*V CCIO，那么此时R u＝R ref，且符合共模电平为0.75*V CCIO。协议1和协议2的校准电路如图3和图4所示，通过图3和图4可以看出，共模电平要求为0.5*V CCIO时需要将外接VC接V CCIO，而共模电平要求为0.5*V CCIO时则需要将外接VC接0.75V CCIO。
综上，现有技术在对阻抗进行校准时，协议不同则需要系统提供不同的电位，并且上拉IO和下拉IO需要同时外接电阻，才能够实现分别对上拉电阻和下拉电阻的校准，如此在一定程度上增大了芯片环境配置成本，用户的使用体验不高，并且适用性也比较低。
针对上述问题，发明人提出了本申请实施例提供的阻抗校准电路和方法，本申请实施例通过结合待校准上拉电阻器件、待校准下拉电阻器件以及校准单元可简化阻抗校准的实现条件，在一定程度上可以降低制版要求。
请参阅图5，为本申请一实施例提供的一种阻抗校准电路，该阻抗校准电路100可以包括待校准上拉电阻器件110、待校准下拉电阻器件120以及校准单元130。
在一些实施方式中，待校准上拉电阻器件110的第一连接端111与所述校准单元130连接，所述待校准上拉电阻器件110的第二连接端112与电源端114连接。另外，待校准下拉电阻器件120的第一连接端121与所述校准单元130连接，所述待校准下拉电阻器件120的第二连接端122与所述待校准上拉电阻器件110的第三连接端113连接，所述待校准下拉电阻器件120的第三连接端123 接地。
本申请实施例中，校准单元130可以包括电压接收端131和校准码输出端132，所述校准单元130通过所述电压接收端131接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件110的输出电压，所述第二电压为所述待校准下拉电阻器件120的输出电压，所述校准单元130根据所述第一电压和所述第二电压得到第一校准码和第二校准码，所述校准单元130用于利用所述第一校准码对所述待校准上拉电阻器件110的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件120的阻值进行校准。
为了更清楚的理解，待校准上拉电阻器件110、待校准下拉电阻器件120以及校准单元130的关系，本申请实施例给出了如图6所示的校准电路的实体结构图。从图6可以看出，在另一些实施方式中，阻抗校准电路100除了包括待校准上拉电阻器件110、待校准下拉电阻器件120以及校准单元130以外，其还可以包括校准电阻140，所述校准电阻140的第一连接端分别与所述待校准上拉电阻器件110和所述校准单元130连接，所述校准电阻140的第二连接端接地(GND)。
作为一种方式，待校准上拉电阻器件110包括多个上拉子电阻器件115，每个所述上拉子电阻器件115(R u)包括第一开关元件1151和第一电阻1152，所述第一开关元件1151的第一连接端与所述电源端114(V CCIO)连接，所述第一开关元件1151的控制端与所述校准单元130连接，所述第一开关元件1151的第二连接端与所述第一电阻1152的第一连接端连接，所述第一电阻1152的第二连接端分别与所述校准电阻140(R ref)和所述待校准下拉电阻器件120连接。
在一个具体的实施方式中，所述第一开关元件1151为PMOS晶体管，所述PMOS晶体管的源极与所述电源端连接，所述PMOS晶体管的栅极与所述校准单元130连接，所述PMOS晶体管的漏极与所述第一电阻1152的第一连接端连接。另外，所述第一开关元件1152也可以为NMOS晶体管，第一开关元件1152具体是哪种类型的开关这里不进行明确限制，可以根据实际情况进行选择。
在另一些实施方式中，待校准下拉电阻器件120包括多个下拉子电阻器件124(R d)，每个所述下拉子电阻器件124包括第二电阻1241和第二开关元件1242，所述第二电阻1241的第一连接端与所述第一电阻1152连接，所述第二电阻1241的第二连接端与所述第二开关元件1242的第一连接端连接，所述第二开关元件1242的控制端与所述校准单元130连接，所述第二开关元件1242的第二连接端接地(GND)。
作为另一种方式，所述第二开关元件1242为NMOS晶体管，所述NMOS晶体管的源极可以与所述第二电阻1241的第二连接端连接，所述NMOS晶体管的栅极可以与所述校准单元130连接，所述NMOS晶体管的漏极端接地。另外，所述第二开关元件1242也可以是PMOS晶体管，第二开关元件1242具体是哪种开关这里不进行明确限制，可以根据实际情况进行选择。
为了更清楚的理解待校准上拉电阻器件和待校准下拉电阻器件对应阻值的校准过程，现给出了如图7和图8所示的结构示意图。图7为待校准上拉电阻器件的结构示意图，从图7可以看出校准单元130可以包括比较器133、逻辑处理单元134、转换器135和锁存器136。
在一些实施方式中，比较器133可以包括第一电压接收端和第二电压接收端，所述第一电压接收端用于接收所述第一电压或者第二电压(V out)，所述第二电压接收端用于接收所述参考电压(V ref)第一电压接收端可以包括第一子电压接收端和第二子电压接收端，校准单元130通过第一子电压接收端与待校准上拉电阻器件110连接，并接收待校准上拉电阻器件的输出电压，该输出电压可以作为第一电压；校准单元130通过第二子电压接收端与待校准下拉电阻器件120连接，并接收待校准下拉电阻器件的输出电压，该输出电压可以作为第二电压。所述比较器133用于将所述第一电压和所述参考电压进行比较，得到所述第一校准码(Mp<m:0>)，以及将所述第二电压与所述参考电压进行比较，得到所述第二校准码(Mn<m:0>)。
另外，逻辑处理单元134的第一连接端与所述比较器133连接，所述逻辑处理单元134的第二连接端与所述转换器135的第一连接端连接，逻辑处理单元134也可以称作是逐次逼近逻辑，所述逻辑处理单元134用于接收比较器133发送的比较结果，以及接收时钟信号(CLK)，并在比较器133发送的比较结果不符合预设条件时，对第一电压或者第二电压进行逐次调节。因此，本发明实施例中阻抗校准电路还可以包括时钟产生子电路，所述时钟产生子电路与所述逻辑处理单元134连接，用于为所述逻辑处理单元134提供时钟信号。
作为一种方式，转换器135的第二连接端与所述锁存器的第一连接端或者第二连接端连接，转换器135的作用是控制对待校准上拉电阻器件110的阻值进行校准，还是对待校准下拉电阻器件120的阻值进行校准，即当所述转换器135连接于IO1(待校准上拉电阻器件110的输出)时，阻抗校准电路100是对上拉支路中的待校准上拉电阻器件110的阻值进行调整，此时下拉支路处于关闭状态，即将下拉支路的第二校准码(Mn<m:0>)置为0，此时的待校准下拉电阻器件120所在的下拉支路处于关闭状态。可选地，锁存器136的第二连接端与所述待校准上拉电阻器件110连接，所述锁存器136用于将所述转换器135传输的第一校准码或者第二校准码进行存储。
综上，在对待校准上拉电阻器件110的阻值进行校准时，比较器133的输入是参考电压(Vref)和第一电压(Vout1)，其中，第一电压是待校准上拉电阻器件110的输出电压，转换器135连接于待校准上拉电阻器件110对应的IO1的第一校准码值(Mp<m:0>)。内部下拉支路(待校准下拉电阻器件120所在支路)通过对第二校准码值(Mn<m:0>)置0处于关闭状态。
本发明实施例可以通过比较器133和逻辑处理单元134得到第一校准码(Mp<m:0>)，而后可以基于所述第一校准码对待校准上拉电阻器件110中的电阻进行由高位至低位的调整，令第一电压Vout逐渐逼近参考电压Vref，直到最后一位完成量化。此时由锁存器对获取的第一校准码Mp<m:0>值进行保存。如此便可以实现对待校准上拉电阻器件阻值的校准。当待校准上拉电阻器件110的阻值校准完成之后，转换器130切换至IO2的Mn<m:0>(待校准下拉电阻器件120所在支路)，此时比较器133的一端连接参考电压Vref，另一端连接待校准下拉电阻器件120的电压输出端，用于接收第二电压。
作为一种方式，待校准下拉电阻器件120的结构如图8所示，从图8可以看出，在对待校准下 拉电阻器件120阻值进行校准时，其主要是基于对待校准上拉电阻器件110获取的第一校准码进行的。在对待校准下拉电阻器件120的阻值进行校准时，主要是将待校准上拉电阻器件110校准获取的第一校准码Mp<m:0>映射至IO2的Mp<m:0>。通过比较器133和逻辑处理单元134得到第二校准码Mn<m:0>，而后，可以基于所述第二校准码对待校准下拉电阻器120中的电阻由高位至低位调整，令第二电压Vout逐渐逼近参考电压Vref，直到最后一位完成量化。此时由锁存器对获取的第二校准码Mn<m:0>进行保存。
在一些实施方式，校准单元130输出的第一校准码值Mp<m:0>和第二校准码值Mn<m:0>，对应到每一段的驱动，输出阻抗均为校准后的上拉电阻R u与下拉电阻R d的阻值。
在另一些实施方式中，所述阻抗校准电路100包括的所述校准电阻140也可以与待校准下拉电阻器件120连接(未给出示图)，具体的，所述校准电阻140的第一连接端分别与所述待校准下拉电阻器件120和所述校准单元130连接，且所述校准电阻140的第二连接端接地。另外，所述待校准下拉电阻器件120包括多个下拉子电阻器件124，每个所述下拉子电阻器件124可以包括一个第二开关元件1242和一个第二电阻1241，所述第二开关元件1242的第一连接端与所述电源端114连接，所述第二开关元件1242的控制与所述校准单元130连接，所述第二开关元件1242的第二连接端与所述第二电阻1241的第一连接端连接，所述第二电阻1242的第二连接端分别与所述校准电阻140和所述待校准上拉电阻器件110连接。其中，第二开关元件1242可以是PMOS晶体管，也可以是NMOS晶体管。
作为另一种方式，所述待校准上拉电阻器件110包括多个上拉子电阻器件115，每个所述上拉子电阻器件115(R u)包括第一开关元件1151和第一电阻1152，所述第一电阻1152的第一连接端与所述第二电阻1242连接，所述第一电阻1152的第二连接端与所述第一开关元件1151的第一连接端连接，所述第一开关元件1151的控制端与所述校准单元130连接，所述第一开关元件1151的连接端接地。其中，第一开关元件1242可以是PMOS晶体管，也可以是NMOS晶体管。
综上，本发明实施例可以在待校准上拉电阻器件110上连接一个校准电阻140，并通过该校准电阻140对待校准上拉电阻器件110的阻值进行校准，然后再基于待校准上拉电阻器件110的校准结果对待校准下拉电阻器件120的阻值进行校准；或者本发明实施例也可以在待校准下拉电阻器件120上连接一个校准电阻140，并通过该校准电阻140对待校准下拉电阻器件120的阻值进行校准，然后再基于待校准下拉电阻器件120的校准结果对待校准上拉电阻器件110的阻值进行校准。可见，校准电阻140可以与待校准上拉电阻器件110连接，也可以与待校准下拉电阻器件120连接，具体是与待校准上拉电阻器件110连接还是与待校准下拉电阻器件120连接，这里不进行明确限制可以根据实际情况进行选择。
本申请实施例提供的一种阻抗校准电路，该阻抗校准电路包括待校准上拉电阻器件、待校准下拉电阻器件以及校准单元，其中，待校准上拉电阻器件的第一连接端与所述校准单元连接，所述待校准上拉电阻器件的第二连接端与电源端连接，待校准下拉电阻器件的第一连接端与所述校准单元 连接，所述待校准下拉电阻器件的第二连接端与所述待校准上拉电阻器件的第三连接端连接，所述待校准下拉电阻器件的第三连接端接地，校准单元包括电压接收端和校准码输出端，所述校准单元通过所述电压接收端接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压，所述校准单元用于根据所述第一电压和所述第二电压得到第一校准码和第二校准码，所述校准单元用于利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。本申请通过结合待校准上拉电阻器件、待校准下拉电阻器件以及校准单元可以更加简单有效的实现对电阻的校准，在一定程度上简化了阻抗校准的条件。
请参阅图9，为本申请实施例提供的一种阻抗校准方法的方法流程图，该流程图应用于上述阻抗校准电路，通过图9可知该方法可以包括步骤S110至步骤S130。
步骤S110：接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压。
步骤S120：根据所述第一电压和所述第二电压得到第一校准码和第二校准码。
作为一种方式，本发明实施例在获取到第一电压时可以将第一电压与参考电压进行比较，并判断第一电压是否大于参考电压，若大于，则第一校准码值对应的位数就为1，若第一电压小于参考电压，则第一校准码值对应的位数就为0。
另外，当第一电压大于参考电压时，本发明实施例可以对第一电压进行调整，即增大第一电压，而后将增大后的第一电压再次与参考电压进行比较，进而得到第一校准码对应的另一位值，比较多少次，则对应的码值位数就是几位，具体比较多少次可以根据实际情况进行选择，这里不进行明确限制。例如，在对上拉电阻进行校准时将参考电压和第一电压比较并调整了五次后第一电压等于参考电压，且前两次第一电压大于参考电压，而后三次第一电压则小于参考电压，此时得到的第一校准码即为11000，即MP<m:0>＝11000，通过上述介绍知道，MP<m:0>控制的是打开导通的待校准上拉电阻器对应支路个数。另外，本发明实施例也可以判断第一电压是否大于参考电压，若小于，则对应增大第一电压，以此实现对上拉电阻或者下拉电阻的校准。
与第一校准码获取过程类似，本发明实施例在获取到第二电压时也可以将第二电压与参考电压进行比较，并判断第二电压是否大于参考电压，若大于，则第二校准码值对应的位数就为1，若第二电压小于参考电压，则第二校准码值对应的位数就为0。另外，当第二电压大于参考电压时，本发明实施例可以对第二电压进行调整，即增大第二电压，而后将增大后的第二电压再次与参考电压进行比较，进而得到第二校准码对应的另一位值，比较多少次，则对应的码值位数就是几位。例如，在对下拉电阻进行校准时将参考电压和第二电压比较并调整了五次，且前三次第二电压大于参考电压，而后两次第二电压则小于参考电压，此时得到的第二校准码即为11100，即MN<m:0>＝11100，通过上述介绍知道，MN<m:0>控制的是打开导通的待校准下拉电阻器对应支路个数。下拉电阻的调整与上拉电阻的调整类似，这里就不进行一一赘述了。
步骤S130：利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。
在一些实施方式中，获取到第一校准码和第二校准码之后，本发明实施可以利用第一校准码对待校准上拉电阻器件的阻值进行校准，以及可以利用第二校准码对待校准下拉电阻器件的阻值进行校准。
在另一些实施方式中，获取到参考电压和输出电压后，本发明实施例也可以根据预设的公式来获取待校准上拉电阻器中连接的第一电阻的数量N p和待校准下拉电阻器中连接的第二电阻的数量N n，以及获取校准电阻的阻值R ref。具体的，在对上拉电阻进行校准时，本发明实施例可以令R ref＝a*R u，V ref＝b*V CCIO，其中，R ref为校准电阻，R u为上拉电阻，V CCIO为第一电压，a为电阻系数，b为电压系数，其中，b∈(0,1)。另外，对参考电压Vref满足下列公式：
Figure PCTCN2021079751-appb-000001
上述公式表示的是电压和电阻值之间的关系式，其中N p指的是待校准上拉电阻器件中有效电阻的数量，即指的是待校准上拉电阻器件中分段数，实际的分段个数是N p+1。R u指的是上拉电阻值，R ref指的是校准电阻值，V CCIO指的是待校准上拉电阻器件的输出电压值，即第一电压值，V ref则指的是参考电压值。
在一些实施方式中，获取到上述公式之后，本发明实施例可以将其转换为对a、b的求解，即得到如下公式：
Figure PCTCN2021079751-appb-000002
本发明实施例可以将
Figure PCTCN2021079751-appb-000003
分子和分母换算成最小不可约整数，得到
Figure PCTCN2021079751-appb-000004
通过上述介绍可以知道，参考电压V ref是已知的，所以b值便是已知的。例如，第一电压V CCIO＝1V，参考电压V ref＝0.7V，通过计算可以得到b＝0.7，将获取的b值带入上述公式，将
Figure PCTCN2021079751-appb-000005
换算成最小不可约整数，就可以得到
Figure PCTCN2021079751-appb-000006
令N p+1＝b 2，
Figure PCTCN2021079751-appb-000007
由上述公式便可以计算得到N p和R ref，同时可以得到N n＝b 1。
作为一种方式，本发明实施例可以根据所述第一校准码和所述第二校准码确定有效电阻的数量，并根据所述有效电阻的数量对所述待校准上拉电阻器件和所述待校准下拉电阻器件的电阻值进行校准。
为了更好的理解本发明实施例，现给出一个具体的实施方式。参考电压V ref为0.75*V CCIO，其 中，第一电压V CCIO＝1.2V，需要校准后上拉电阻R u等于下拉电阻R d，且阻值为50Ω。利用上面介绍的方法可以计算出b＝V ref/V CCIO＝0.75，
Figure PCTCN2021079751-appb-000008
即
Figure PCTCN2021079751-appb-000009
如此可以得到b 2＝3，b 1＝1，进而可以知道N p+1＝3，即N p＝2，而N n＝1。为此，可以得到如图10和图11的校准结果示意图。
本发明实施例对于FPGA这类可编程器件，与IO可配置驱动能力综合考虑，可以充分利用可配置资源，达到便利度与资源利用率的最优解。并且本发明实施例针对不同共模电平(参考电压)下的校准功能，集成于芯片内部，可以轻易通过配置实现，不需要外部提供额外电压源，简化了阻抗校准的实现条件，在一定程度上可以降低制版要求。
综上所述，本申请实施例提供的一种阻抗校准电路和方法，该方法通过利用阻抗校准电路可以更加简单高效的实现对阻抗的校准，其中，阻抗校准电路包括待校准上拉电阻器件、待校准下拉电阻器件以及校准单元，其中，待校准上拉电阻器件的第一连接端与所述校准单元连接，所述待校准上拉电阻器件的第二连接端与电源端连接，待校准下拉电阻器件的第一连接端与所述校准单元连接，所述待校准下拉电阻器件的第二连接端与所述待校准上拉电阻器件的第三连接端连接，所述待校准下拉电阻器件的第三连接端接地，校准单元包括电压接收端和校准码输出端，所述校准单元通过所述电压接收端接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压，所述校准单元用于根据所述第一电压和所述第二电压得到第一校准码和第二校准码，所述校准单元用于利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。本申请通过结合待校准上拉电阻器件、待校准下拉电阻器件以及校准单元可以更加简单有效的实现对电阻的校准，在一定程度上简化了阻抗校准的条件。另外，本发明实施例在校准时只需要一个校准电阻，校准完成后可释放部分IO，节约了IO，增强了客户的普遍适用性。
可见，本领域的技术人员应该明白，上文中所公开方法中的全部或某些步骤、系统、系统中的功能模块/单元可以被实施为软件(可以用计算系统可执行的计算机程序代码来实现)、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。
此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、计算机程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。所以，本发明不限制于任何特定的硬件和软件结合。
以上内容是结合具体的实施方式对本发明实施例所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种阻抗校准电路，其特征在于，所述阻抗校准电路包括：
    待校准上拉电阻器件，所述待校准上拉电阻器件的第一连接端与所述校准单元连接，所述待校准上拉电阻器件的第二连接端与电源端连接；
    待校准下拉电阻器件，所述待校准下拉电阻器件的第一连接端与所述校准单元连接，所述待校准下拉电阻器件的第二连接端与所述待校准上拉电阻器件的第三连接端连接，所述待校准下拉电阻器件的第三连接端接地；
    校准单元，所述校准单元包括电压接收端和校准码输出端，所述校准单元通过所述电压接收端接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压，所述校准单元用于根据所述第一电压和所述第二电压得到第一校准码和第二校准码，所述校准单元用于利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。
  2. 根据权利要求1所述的阻抗校准电路，其特征在于，所述阻抗校准电路还包括校准电阻，所述校准电阻的第一连接端分别与所述待校准上拉电阻器件和所述校准单元连接，所述校准电阻的第二连接端接地。
  3. 根据权利要求2所述的阻抗校准电路，其特征在于，所述待校准上拉电阻器件包括多个上拉子电阻器件，每个所述上拉子电阻器件包括第一开关元件和第一电阻，所述第一开关元件的第一连接端与所述电源端连接，所述第一开关元件的控制端与所述校准单元连接，所述第一开关元件的第二连接端与所述第一电阻的第一连接端连接，所述第一电阻的第二连接端分别与所述校准电阻和所述待校准下拉电阻器件连接。
  4. 根据权利要求3所述的阻抗校准电路，其特征在于，所述第一开关元件为PMOS晶体管，所述PMOS晶体管的源极与所述电源端连接，所述PMOS晶体管的栅极与所述校准单元连接，所述PMOS晶体管的漏极与所述第一电阻的第一连接端连接。
  5. 根据权利要求3所述的阻抗校准电路，其特征在于，所述待校准下拉电阻器件包括多个下拉子电阻器件，每个所述下拉子电阻器件包括第二电阻和第二开关元件，所述第二电阻的第一连接端与所述第一电阻连接，所述第二电阻的第二连接端与所述第二开关元件的第一连接端连接，所述第二开关元件的控制端与所述校准单元连接，所述第二开关元件的第二连接端接地。
  6. 根据权利要求5所述的阻抗校准电路，其特征在于，所述第二开关元件为NMOS晶体管，所述NMOS晶体管的源极与所述第二电阻的第二连接端连接，所述NMOS晶体管的栅极与所述校准单元连接，所述NMOS晶体管的漏极端接地。
  7. 根据权利要求1所述阻抗校准电路，其特征在于，所述阻抗校准电路还包括校准电阻，所述校准电阻的第一连接端分别与所述待校准下拉电阻器件和所述校准单元连接，所述校准电阻的第二连接端接地。
  8. 根据权利要求1所述的阻抗校准电路，其特征在于，所述校准单元包括比较器、逻辑处理单元、转换器和锁存器；
    所述比较器包括第一电压接收端和第二电压接收端，所述第一电压接收端用于接收所述第一电压或者第二电压，所述第二电压接收端用于接收所述参考电压，所述比较器用于将所述第一电压和所述参考电压进行比较，得到所述第一校准码，以及将所述第二电压与所述参考电压进行比较，得到所述第二校准码；
    所述逻辑处理单元的第一连接端与所述比较器连接，所述逻辑处理单元的第二连接端与所述转换器的第一连接端连接，所述转换器的第二连接端与所述锁存器的第一连接端或者第二连接端连接，所述锁存器的第二连接端与所述待校准上拉电阻器件连接，所述锁存器用于将所述转换器传输的第一校准码或者第二校准码进行存储。
  9. 一种阻抗校准方法，其特征在于，应用于权利要求1至8任一所述的阻抗校准电路，所述方法包括：
    接收第一电压和第二电压，所述第一电压为所述待校准上拉电阻器件的输出电压，所述第二电压为所述待校准下拉电阻器件的输出电压；
    根据所述第一电压和所述第二电压得到第一校准码和第二校准码；
    利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准。
  10. 根据权利要求9所述的方法，其特征在于，所述利用所述第一校准码对所述待校准上拉电阻器件的阻值进行校准，以及利用所述第二校准码对所述待校准下拉电阻器件的阻值进行校准，包括：
    根据所述第一校准码和所述第二校准码确定有效电阻的数量，并根据所述有效电阻的数量对所述待校准上拉电阻器件和所述待校准下拉电阻器件的电阻值进行校准。
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