WO2022141432A1 - 光敏元件及其制备方法、显示装置 - Google Patents

光敏元件及其制备方法、显示装置 Download PDF

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WO2022141432A1
WO2022141432A1 PCT/CN2020/142235 CN2020142235W WO2022141432A1 WO 2022141432 A1 WO2022141432 A1 WO 2022141432A1 CN 2020142235 W CN2020142235 W CN 2020142235W WO 2022141432 A1 WO2022141432 A1 WO 2022141432A1
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layer
electrode
molybdenum oxide
oxide layer
disposed
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PCT/CN2020/142235
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English (en)
French (fr)
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蔡广烁
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Tcl华星光电技术有限公司
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Priority to US17/261,581 priority Critical patent/US11894479B2/en
Publication of WO2022141432A1 publication Critical patent/WO2022141432A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/109—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN heterojunction type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14678—Contact-type imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
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    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0328—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032
    • H01L31/0336—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032 in different semiconductor regions, e.g. Cu2X/CdX hetero- junctions, X being an element of Group VI of the Periodic Table
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    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of display technology, and in particular, to a photosensitive element, a preparation method thereof, and a display device.
  • the use of fingerprint, voice, face, hand, retina or iris as a personal identification system has become a safe and reliable biometric technology.
  • fingerprint recognition has become the leading method for verifying identity, replacing conventional passwords and keys.
  • the photosensitive element in the traditional fingerprint recognition optical sensor has problems such as high cost, large volume and image distortion.
  • Photosensitive elements based on silicon chips are favored because they can be made very small and cheap.
  • the photosensitive element structure based on silicon chip usually needs to use P-type material to form a homojunction or heterojunction structure, but the preparation of P-type material increases the cost, and at the same time, due to the low hole transport efficiency of P-type material, it will affect the performance of photosensitive elements.
  • the present invention provides a photosensitive element, a preparation method thereof, and a display device, which are used to solve the technical problems of high cost and low hole transport efficiency caused by the use of P-type materials in the prior art photosensitive element.
  • the present invention provides a photosensitive element, comprising:
  • a first electrode disposed on the substrate
  • an insulating layer disposed on the molybdenum oxide layer and the substrate, and a first opening is formed on the insulating layer to expose the molybdenum oxide layer;
  • the second electrode is disposed on the insulating layer and the molybdenum oxide layer, and is in contact with the molybdenum oxide layer through the first opening.
  • the first electrode includes a first region for bonding with a lead and a second region for contacting the N-type doped silicon layer, the N-type doped silicon layer , the undoped silicon layer, the molybdenum oxide layer and the second electrode are arranged corresponding to the second region.
  • the first electrode includes a single-layer or multi-layer structure formed of at least one metal material selected from molybdenum, copper, aluminum, titanium, nickel and cadmium
  • the second electrode includes a metal material made of oxide
  • the work function of the molybdenum oxide layer is in the range of 5.2eV-6.8eV.
  • the forbidden band of the molybdenum oxide layer is in the range of 2.8eV-3.6eV.
  • the present invention also provides a preparation method of a photosensitive element, comprising the following steps:
  • Step S1 forming a plurality of first electrodes on the substrate
  • Step S2 forming a stacked N-type doped silicon layer, an undoped silicon layer and a molybdenum oxide layer in sequence on the first electrode;
  • Step S3 preparing an insulating layer on the molybdenum oxide layer and the substrate, and forming a first opening on the insulating layer exposing the molybdenum oxide layer;
  • Step S4 a second electrode corresponding to the molybdenum oxide layer is formed on the insulating layer, and the second electrode is in contact with the molybdenum oxide layer through the first opening.
  • the first electrode includes a single-layer or multi-layer structure formed of at least one metal material selected from molybdenum, copper, aluminum, titanium, nickel and cadmium, and the first electrode includes a metal material for A first area for bonding with a lead and a second area for contacting the N-type doped silicon layer, the N-type doped silicon layer, the undoped silicon layer, the molybdenum oxide layer, and the The second electrode is disposed corresponding to the second region.
  • the material of the first electrode of the single-layer structure is a molybdenum-titanium alloy, or a sublayer of the first electrode of the multi-layer structure close to the side of the N-type doped silicon layer
  • the material is molybdenum-titanium alloy
  • the following steps are also included:
  • the material of the first electrode of the single-layer structure is a material other than molybdenum-titanium alloy, or the first electrode of the multi-layer structure is close to the N-type doped silicon layer
  • the material of the sub-layer on the side is a material other than molybdenum-titanium alloy
  • the following steps are further included:
  • the insulating layer is patterned for the first time to form first openings exposing the molybdenum oxide layer, and the molybdenum oxide layer is annealed; after that, the insulating layer is patterned for the second time, A second opening is formed exposing the second region of the first electrode.
  • the work function of the molybdenum oxide layer ranges from 5.2 eV to 6.8 eV.
  • the forbidden band of the molybdenum oxide layer is in the range of 2.8eV-3.6eV.
  • the present invention also provides a display device, comprising a photosensitive element and a pixel unit, wherein the photosensitive element is located between two adjacent pixel units; wherein, the photosensitive element includes:
  • a first electrode disposed on the substrate
  • an insulating layer disposed on the molybdenum oxide layer and the substrate, and a first opening is formed on the insulating layer to expose the molybdenum oxide layer;
  • the second electrode is disposed on the insulating layer and the molybdenum oxide layer, and is in contact with the molybdenum oxide layer through the first opening.
  • the display device includes a first substrate and a second substrate disposed opposite to each other, and the first substrate includes:
  • a first electrode layer disposed on the first substrate, including the first electrode and the gate electrode in the same layer and spaced apart;
  • a gate insulating layer disposed on the first electrode layer, the gate insulating layer exposing the first electrode
  • the N-type doped silicon layer, the non-doped silicon layer and the molybdenum oxide layer are sequentially stacked and disposed on the first electrode;
  • an active layer disposed at a position where the gate insulating layer faces the gate, and the active layer includes an undoped part and a doped part;
  • a source electrode and a drain electrode disposed on the active layer, the source electrode and the drain electrode are respectively in contact with the doping part;
  • a dielectric layer disposed on the molybdenum oxide layer, the source electrode and the drain electrode, and the dielectric layer exposes the molybdenum oxide layer and the drain electrode;
  • a second electrode is disposed on the dielectric layer, one end of the second electrode is in contact with the molybdenum oxide layer, and the other end of the second electrode is in contact with the drain electrode.
  • the gate electrode, the active layer, the source electrode and the drain electrode constitute a switching thin film transistor, and the photosensitive element is electrically connected to the switching thin film transistor.
  • a side of the second substrate facing the first substrate is provided with a black matrix, and the switching thin film transistors are provided corresponding to the black matrix.
  • the first substrate further includes a scan line and a read line
  • the gate electrode of the switch thin film transistor is electrically connected to the scan line
  • the source electrode of the switch thin film transistor is connected to the scan line.
  • the read line is electrically connected
  • the drain of the switching thin film transistor is electrically connected to the second electrode of the photosensitive element.
  • the first electrode includes a first region for bonding with a lead and a second region for contacting the N-type doped silicon layer, the N-type doped silicon layer , the undoped silicon layer, the molybdenum oxide layer and the second electrode are arranged corresponding to the second region.
  • the first electrode includes a single-layer or multi-layer structure formed of at least one metal material selected from molybdenum, copper, aluminum, titanium, nickel, and cadmium
  • the second electrode includes an oxide A single-layer or multi-layer structure formed of at least one metal oxide material among indium zinc, indium tin oxide, zinc oxide and gallium zinc oxide.
  • the work function of the molybdenum oxide layer ranges from 5.2 eV to 6.8 eV.
  • the forbidden band of the molybdenum oxide layer is in the range of 2.8eV-3.6eV.
  • the beneficial effects of the present invention are as follows: the photosensitive element, the preparation method thereof, and the display device provided by the present invention use a molybdenum oxide layer to replace the P-type material of the homojunction or heterojunction structure in the prior art, thereby reducing the impact on the P-type material.
  • the preparation requirements not only save the cost, but also improve the hole transport efficiency of the photosensitive element, thereby improving the performance of the photosensitive element.
  • Fig. 1 is the structural representation of the photosensitive element provided by the present invention.
  • Fig. 2 is the IV characteristic curve diagram of photosensitive element of the present invention under different white light intensity
  • Fig. 3 is the parameter diagram of the response photocurrent of different white light intensity under the voltage of -0.5V of the photosensitive element of the present invention
  • Fig. 4 is the preparation method flow chart of the photosensitive element provided by the present invention.
  • 5A-5E are schematic flowcharts of the preparation method of the photosensitive element provided by the present invention.
  • FIG. 6 is a front view of a display device provided by the present invention.
  • FIG. 7 is a schematic cross-sectional view of the display device provided by the present invention.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present invention, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the present invention aims at the technical problems of high cost and low hole transport efficiency caused by the use of P-type materials in the photosensitive element in the prior art, and the embodiments of the present invention can solve the defects.
  • the present invention provides a photosensitive element, which includes: a substrate 10; a first electrode 20 disposed on the substrate 10; an N-type doped silicon layer 30 disposed on the first electrode 20; an undoped silicon layer 40, disposed on the N-type doped silicon layer 30; a molybdenum oxide layer 50, disposed on the undoped silicon layer 40; an insulating layer 60, disposed on the molybdenum oxide On the layer 50 and the substrate 10, the insulating layer 60 is provided with a first opening to expose the molybdenum oxide layer 50; a second electrode 70 is provided on the insulating layer 60 and the molybdenum oxide layer 50, and contact with the molybdenum oxide layer 50 through the first opening.
  • the photosensitive element can be applied to various scenarios, and exemplarily, the photosensitive element can be applied to a sensor for fingerprint recognition.
  • the N-type doped silicon layer 30 is used as the electron transport layer of the photosensitive element
  • the undoped silicon layer 40 is used as the light absorption layer of the photosensitive element
  • the molybdenum oxide layer 50 is used as the photosensitive element the hole transport layer.
  • the N-type doped silicon layer 30 , the undoped silicon layer 40 and the molybdenum oxide layer 50 form a heterojunction structure of the photosensitive element.
  • a molybdenum oxide layer with high work function is used to replace the P-type material in the homojunction or heterojunction structure of the prior art, and while the hole transport efficiency of the photosensitive element is effectively improved, the impact on the P-type material is reduced. Production requirements, and therefore cost savings.
  • FIG. 1 is a schematic structural diagram of the photosensitive element provided by the present invention.
  • the photosensitive element includes a first electrode 20 , an N-type doped silicon layer 30 , an undoped silicon layer 40 , a molybdenum oxide layer 50 , an insulating layer 60 and a second electrode 70 that are stacked on the substrate 10 .
  • the material of the substrate 10 includes at least one of glass, alumina, silicon, polyethylene naphthalate, polyethylene terephthalate and polyimide.
  • the first electrode 20 includes a single layer or multiple layers formed of at least one metal material selected from molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni) and cadmium (Cd). layer structure.
  • the first electrode 20 may include at least two sub-layers, and the materials of the at least two sub-layers may be the same or different.
  • the first electrode 20 includes a molybdenum metal sublayer, a copper metal sublayer, and a molybdenum metal sublayer stacked from bottom to top, or a molybdenum metal sublayer, an aluminum metal sublayer, and a molybdenum metal sublayer stacked on top of each other.
  • stacked aluminum metal sublayers and molybdenum metal sublayers or stacked molybdenum-titanium alloy sublayers, copper metal sublayers, and molybdenum-titanium alloy sublayers, or stacked nickel metal sublayers, copper metal sublayers and Nickel metal sub-layers, or multiple metal stacks such as cadmium metal sub-layers, aluminum metal sub-layers, and cadmium metal sub-layers.
  • the first electrode 20 includes a first region 201 for bonding with a lead and a second region 202 for contacting the N-type doped silicon layer, the N-type doped silicon layer 30, the non- The doped silicon layer 40 , the molybdenum oxide layer 50 and the second electrode 70 are stacked corresponding to the second region 202 , and the first region 201 of the first electrode 20 is used for subsequent photosensitive elements and other structures of the sensor Conduct lead bonding.
  • the non-doped silicon layer 40 is an intrinsic semiconductor silicon layer, and the N-type doped silicon layer 30 contains N-type impurities, for example, doped with pentavalent elements phosphorus, arsenic, antimony and the like.
  • the materials of the N-type doped silicon layer 30 and the non-doped silicon layer 40 are not limited to amorphous silicon, microcrystalline silicon, and polycrystalline silicon.
  • the work function of the molybdenum oxide layer 50 is in the range of 8.3 ⁇ 10 ⁇ 19 Joules to 10.9 ⁇ 10 ⁇ 19 Joules (ie, 5.2eV-6.8eV), and the forbidden band width thereof is in the range of 4.5 Between ⁇ 10 -19 joules to 5.8 ⁇ 10 -19 joules (ie 2.8eV-3.6eV).
  • the molybdenum oxide layer 50 with a work function in this range can greatly improve the efficiency of hole injection as a hole transport layer.
  • the second electrode 70 includes a single-layer or multi-layer structure formed of at least one metal oxide material selected from indium zinc oxide, indium tin oxide, zinc oxide, and gallium zinc oxide.
  • the second electrode 70 and the molybdenum oxide layer 50 all need to be transparent materials to reduce additional absorption of light, thereby increasing the effective absorption of light by the undoped silicon layer 40 and generating more photo-generated carriers.
  • the first electrode 20 is used to load a first polarity voltage and is used to provide a first type of carriers
  • the second electrode 70 is used to load a second polarity voltage and used to provide Carriers of the second type.
  • the N-type doped silicon layer 30 acts as an electron transport layer for transporting the first type of carriers to the undoped silicon layer 40
  • the molybdenum oxide layer 50 acts as a hole transport layer for transporting the first type of carriers to the non-doped silicon layer 40.
  • the doped silicon layer 40 transports carriers of the second type.
  • the undoped silicon layer 40 acts as a light absorption layer for generating photogenerated carriers.
  • the photosensitive element using molybdenum oxide as the hole transport layer replaces the homojunction or heterojunction photodiode formed of P-type material in the prior art, which can effectively improve the hole transport efficiency of the device.
  • the photosensitive element has higher quantum efficiency, and at the same time, the photoresponse rate can be improved, thereby improving the sensitivity of the photosensitive element; and the working voltage of the photosensitive element can be reduced to realize low power consumption.
  • Fig. 2 is the IV characteristic curve diagram of the photosensitive element of the present invention under different white light intensities
  • Fig. 3 is the response of the photosensitive element of the present invention under the voltage of -0.5V with different white light intensities Parameter plot of photocurrent.
  • the test is carried out under the operating voltage range of -2V ⁇ 2V, the intensity of white light is between 0lx ⁇ 1240lx, and the figure shows that the light intensity of white light is 0lx, 37.56lx, 41.26lx, 63.49lx respectively , 89.72lx, 140.1lx, 277.8lx, 747.9lx, 1240lx IV characteristic curve of the photosensitive element.
  • the photocurrent also increases.
  • the photocurrent when the light intensity is 0lx, the photocurrent is 10-12 amps; when the light intensity is 63.49lx, the photocurrent is 10-11 amps; when the light intensity is 277.8lx, the light The current is 10-10 amps.
  • the photocurrent parameters of the above 9 kinds of white light intensities are given when the operating voltage of the photosensitive element is -0.5V. It can be seen that with the increase of the white light intensity, the photocurrent also increases. , so that the photoresponse also increases.
  • the photocurrent difference of the photosensitive element of the present invention is larger than that of the photosensitive element of the prior art.
  • the working voltage of the photosensitive element of the present invention is less than 1V, as shown in FIG. 3 , it can work normally at a voltage of -0.5V, and can realize low power consumption.
  • the N-type doped silicon layer 30 , the non-doped silicon layer 40 and the molybdenum oxide layer 50 can be used as dielectric layers, between the first electrode 20 and the second electrode 70 . Capacitance will be formed. Since the junction capacitance of the heterojunction itself is relatively large, it can be used as a storage capacitor in the circuit, and the photosensitive element can be used in a fingerprint sensor to improve the resolution of the fingerprint sensor and identify finer patterns.
  • the present invention also provides a method for preparing a photosensitive element, please refer to FIG. 4 , which is a flow chart of the method for preparing the photosensitive element provided by the present invention.
  • the preparation method comprises the following steps:
  • Step S1 forming a plurality of first electrodes on the substrate.
  • a first metal thin film is prepared on the substrate 10 by a sputtering or evaporation process.
  • the material of the substrate 10 includes at least one of glass, alumina, silicon, polyethylene naphthalate, polyethylene terephthalate and polyimide.
  • the first metal film includes a single-layer metal film formed of at least one metal material selected from molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni), and cadmium (Cd). or multilayer metal films. Then, the first metal thin film is patterned to form a plurality of first electrodes 20 .
  • the first electrode 20 is Mo, Mo/Cu/Mo, Mo/Al/Mo, Al, Al/Mo, MoTi/Cu/MoTi, MoTi/Al/MoTi, Ni/Cu/Ni, Ni /A single-layer or multi-layer structure of Al/Ni, Al/Ni, Cd/Cu/Cd, Cd/Al/Cd, Al/Cd, Ti/Cu/Ti, Ti/Al/Ti, Al/Ti .
  • MoTi/Cu/MoTi here means that the first electrode 20 is a three-layered structure composed of molybdenum-titanium alloy, copper metal, and molybdenum-titanium alloy from bottom to top, and the above-mentioned other structures are similar. It will not be repeated here.
  • step S2 a stacked N-type doped silicon layer, an undoped silicon layer and a molybdenum oxide layer are sequentially formed on the first electrode.
  • an N-type doped silicon film 30 ′ and a non-doped silicon film 40 ′ are grown on the first electrode 20 and the substrate 10 in sequence, wherein the first layer of silicon material (ie N-type doped silicon film) can simultaneously complete the doping of N + impurities during the growth process.
  • impurity gases such as phosphine (PH 3 ) and arsine (AsH 3 ) are doped during the growth of the first layer of silicon material to form the N-type doped silicon thin film 30 ′.
  • the second layer of silicon material ie, the undoped silicon thin film
  • the growth method of the silicon material is not limited to chemical vapor deposition, atomic layer deposition, and plasma-enhanced chemical vapor deposition, and the silicon material is not limited to amorphous silicon, microcrystalline silicon, and polycrystalline silicon.
  • a transparent oxide film 50' is grown to cover the non-doped silicon film 40', and the material growth method is not limited to magnetron sputtering, chemical vapor deposition and evaporation.
  • the transparent oxide film 50' is a molybdenum oxide film.
  • the N-type doped silicon film 30 ′, the undoped silicon film 40 ′ and the transparent oxide film 50 ′ are patterned by dry etching or wet etching to form the N-type doped silicon film 30 ′ corresponding to the first electrode 20 Doped silicon layer 30 , undoped silicon layer 40 and molybdenum oxide layer 50 .
  • the first electrode 20 includes a first region 201 for bonding with a lead and a second region 202 for contacting the N-type doped silicon layer.
  • the N-type doped silicon layer 30, the The non-doped silicon layer 40 and the molybdenum oxide layer 50 are disposed corresponding to the second region 202 , and the first region 201 is reserved for subsequent lead bonding between the photosensitive element and other structures of the sensor.
  • Step S3 preparing an insulating layer on the molybdenum oxide layer and the substrate, and forming a first opening on the insulating layer exposing the molybdenum oxide layer.
  • an insulating layer 60 is grown on the molybdenum oxide layer 50 and the substrate 10, and the growth method is not limited to magnetron sputtering, chemical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor phase
  • the deposition method the material of which includes but is not limited to at least one of aluminum oxide, silicon nitride, silicon dioxide, and aluminum nitride.
  • the insulating layer 60 is patterned to form first openings 601 exposing the molybdenum oxide layer 50 .
  • Step S4 a second electrode corresponding to the molybdenum oxide layer is formed on the insulating layer, and the second electrode is in contact with the molybdenum oxide layer through the first opening.
  • a metal oxide film is prepared on the insulating layer 60 , and the metal oxide film includes but is not limited to at least one metal oxide selected from the group consisting of indium zinc oxide, indium tin oxide, zinc oxide and gallium zinc oxide.
  • the metal oxide film is patterned to form a second electrode 70 corresponding to the molybdenum oxide layer, thereby forming the first electrode 20 , the N-type doped silicon layer 30 and the undoped silicon layer.
  • the layer 40 , the molybdenum oxide layer 50 and the second electrode 70 constitute a photosensitive element of a photodiode structure.
  • the material of the first electrode of the single-layer structure is molybdenum-titanium alloy, or the first electrode of the multi-layer structure is close to the side of the N-type doped silicon layer.
  • the material of the layer is a molybdenum-titanium alloy
  • the following steps are also included:
  • the molybdenum oxide layer is annealed, and the annealing temperature is less than or equal to 350°C.
  • the annealing atmosphere includes but is not limited to at least one of oxygen, nitrogen, air and argon.
  • the annealing treatment of the molybdenum oxide layer can increase the oxygen content in the molybdenum oxide layer, and can improve the hole transport performance of the molybdenum oxide layer.
  • the annealing temperature is too high, such as exceeding 350°C, it will affect the characteristics of the undoped silicon layer.
  • the annealing treatment The temperature does not exceed 350°C, such as 150°C, 200°C, 250°C or 300°C, etc.
  • molybdenum-titanium alloy Since molybdenum-titanium alloy has excellent high temperature resistance, it is not easy to be oxidized in the annealing process. Therefore, when the material of the first electrode of the single-layer structure is a molybdenum-titanium alloy, or the first electrode of the multi-layer structure is close to the When the material of the sub-layer on one side of the N-type doped silicon layer is molybdenum-titanium alloy, the first opening and the second opening can be formed simultaneously in the same process, so that one mask process can be saved. save costs.
  • titanium metal can provide excellent adhesion, which can improve the adhesion between the first electrode and the N-type doped silicon layer and the conductive layer that is subsequently overlapped with the first electrode through the second opening. adhesion, thereby improving the stability of the device.
  • the step S3 further includes the following steps after preparing the insulating layer on the molybdenum oxide layer and the substrate:
  • the insulating layer is patterned for the first time to form first openings exposing the molybdenum oxide layer, and the molybdenum oxide layer is annealed; after that, the insulating layer is patterned for the second time, A second opening is formed exposing the first region of the first electrode.
  • the annealing temperature and time are not limited in the annealing process, and the annealing atmosphere includes but is not limited to at least one of oxygen, nitrogen, air and argon.
  • the high temperature resistance and oxidation resistance of molybdenum-titanium alloy are better than other materials, and the first electrode is close to the sub-layer or single layer on the side of the N-type doped silicon layer.
  • the first electrode of the layer structure is made of other materials than molybdenum-titanium alloy, and the exposed part is easily oxidized during the annealing process. Describe the contact performance between the first electrode and the conductive layer that is subsequently overlapped.
  • the photosensitive element of the present invention can be applied to the field of display technology, and specifically can be used as a photosensitive element in a fingerprint identification sensor, but is not limited thereto.
  • the present invention also provides a display device, as shown in FIG. 6 , the display device includes the above-mentioned photosensitive element 100 and a pixel unit 200 , wherein the photosensitive element 100 is located between two adjacent pixel units 200 , the pixel arrangement and display effect of the pixel unit 200 will not be affected by adopting this method.
  • the display device may be one of an organic light-emitting electro-display device, a liquid crystal display device, a quantum dot display device or a micro-light emitting diode display device.
  • the display device includes a first substrate 1 and a second substrate 2 , and the first substrate 1 and the second substrate 2 are disposed opposite to each other.
  • the first substrate 1 includes a first substrate 11 on which a first electrode layer is provided, and the first electrode layer includes a first electrode 20 and a gate electrode 12 that are arranged in the same layer and spaced apart.
  • a gate insulating layer 13 is disposed on the first electrode layer, and a portion of the gate insulating layer 13 corresponding to the first electrode 20 is etched away to expose the first electrode 20 .
  • a heterojunction is provided on the first electrode 20, and the heterojunction includes an N-type doped silicon layer 30, an undoped silicon layer 40 and a molybdenum oxide layer 50 that are stacked and arranged, wherein the N-type doped silicon layer
  • the layer 30 is in contact with the first electrode 20 .
  • the gate insulating layer 13 is provided with an active layer 14 at a position facing the gate 12 , and the active layer 14 includes an undoped portion 141 and a doped portion 142 .
  • a source/drain 15 is disposed on the active layer 14 , and the source/drain 15 is in contact with the doped portion 142 .
  • a dielectric layer 16 (insulating layer 60 ) is disposed on the heterojunction and the source/drain 15 , and the dielectric layer 16 exposes the molybdenum oxide layer 50 and the drain 15 .
  • a second electrode 70 is disposed on the dielectric layer 16 , one end of the second electrode 70 is in contact with the molybdenum oxide layer 50 , and the other end of the second electrode 70 is in contact with the drain electrode 15 .
  • the first electrode 20 , the N-type doped silicon layer 30 , the undoped silicon layer 40 , the molybdenum oxide layer 50 and the second electrode 70 constitute a photosensitive element
  • the gate 12 , the active layer 14 , the source electrode and the drain electrode constitute a switching thin film transistor.
  • the side of the second substrate 2 facing the first substrate 1 is provided with a black matrix 21 , the switching thin film transistors are arranged corresponding to the black matrix 21 , and the photosensitive elements are arranged in the area covered by the black matrix 21 . In addition, ambient light directed to the photosensitive element can be sensed.
  • the first substrate 1 also includes scan lines and read lines not shown in the figure, the photosensitive element is electrically connected to the switch thin film transistor, and the gate 12 of the switch thin film transistor is electrically connected to the scan line , the source of the switching thin film transistor is electrically connected to the read line, the drain of the switch thin film transistor is electrically connected to the second electrode 70 of the photosensitive element, and the read line is used to read the The photocurrent signal sensed by the photosensitive element realizes the photoelectric sensing function of the photosensitive element.
  • a molybdenum oxide layer with high work function is used to replace the P-type material in the homojunction or heterojunction of the photosensitive element in the prior art, thereby reducing the preparation requirement for the P-type material, Not only the cost is saved, but also the hole transport efficiency of the photosensitive element can be improved, thereby improving the performance of the photosensitive element.
  • the display device of the present invention can realize fingerprint identification with high resolution and high sensitivity without affecting the normal display.

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Abstract

一种光敏元件及其制备方法、显示装置，该光敏元件包括：衬底（10）；第一电极（20），设置于衬底（10）上；N型掺杂硅层（30），设置于第一电极（20）上；非掺杂硅层（40），设置于N型掺杂硅层（40）上；氧化钼层（50），设置于非掺杂硅层（40）上；绝缘层（60），设置于氧化钼层（50）以及衬底（10）上，绝缘层（60）上设有第一开孔以暴露氧化钼层（50）；第二电极（70），设置于绝缘层（60）和氧化钼层（50）上，且通过第一开孔与氧化钼层（50）接触。

Description

光敏元件及其制备方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种光敏元件及其制备方法、显示装置。
 背景技术
随着科技的发展，利用指纹、语音、面部、手、视网膜或虹膜作为个人识别系统已经成为安全可靠的生物识别技术。从成本、易用性和准确性等层面上看，指纹识别已经成为用于验证身份的领先方法，以替代常规密码和密钥。传统的指纹识别光学传感器中的光敏元件存在成本高，体积大和图像失真等问题。基于硅芯片的光敏元件因为可以做得非常小而且便宜，受到了人们的青睐。然而，基于硅芯片的光敏元件结构通常需要用P型材料形成同质结或异质结结构，但是P型材料的制备增加了成本，同时由于P型材料的空穴传输效率较低，会影响光敏元件的性能。
因此，有必要提供一种光敏元件及其制备方法以及显示装置，以解决现有技术所存在的问题。
 技术问题
本发明提供一种光敏元件及其制备方法、显示装置，用以解决现有技术中的光敏元件因采用P型材料导致的成本较高以及空穴传输效率较低的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种光敏元件，包括：
衬底；
第一电极，设置于所述衬底上；
N型掺杂硅层，设置于所述第一电极上；
非掺杂硅层，设置于所述N型掺杂硅层上；
氧化钼层，设置于所述非掺杂硅层上；
绝缘层，设置于所述氧化钼层以及所述衬底上，所述绝缘层上设有第一开孔以暴露所述氧化钼层；
第二电极，设置于所述绝缘层和氧化钼层上，且通过所述第一开孔与所述氧化钼层接触。
在本发明的光敏元件中，所述第一电极包括用于与引线搭接的第一区域和用于与所述N型掺杂硅层接触的第二区域，所述N型掺杂硅层、所述非掺杂硅层、所述氧化钼层以及所述第二电极对应所述第二区域设置。
在本发明的光敏元件中，所述第一电极包括由钼、铜、铝、钛、镍和镉中的至少一种金属材料形成的单层或多层结构，所述第二电极包括由氧化铟锌、氧化铟锡、氧化锌和氧化镓锌中的至少一种金属氧化物材料形成的单层或多层结构。
在本发明的光敏元件中，所述氧化钼层的功函数的范围为5.2eV-6.8eV之间。
在本发明的光敏元件中，所述氧化钼层的禁带宽的范围为2.8eV-3.6eV之间。
为解决上述问题，本发明还提供了一种光敏元件的制备方法，包括以下步骤：
步骤S1，在衬底上形成多个第一电极；
步骤S2，在所述第一电极上依次形成层叠的N型掺杂硅层、非掺杂硅层以及氧化钼层；
步骤S3，在所述氧化钼层以及所述衬底上制备绝缘层，并在所述绝缘层上形成暴露所述氧化钼层的第一开孔；
步骤S4，在所述绝缘层上形成对应所述氧化钼层的第二电极，且所述第二电极通过所述第一开孔与所述氧化钼层接触。
在本发明的制备方法中，所述第一电极包括由钼、铜、铝、钛、镍和镉中的至少一种金属材料形成的单层或多层结构，所述第一电极包括用于与引线搭接的第一区域和用于与所述N型掺杂硅层接触的第二区域，所述N型掺杂硅层、所述非掺杂硅层、所述氧化钼层以及所述第二电极对应所述第二区域设置。
在本发明的制备方法中，当单层结构的所述第一电极的材料为钼钛合金，或者多层结构的所述第一电极中靠近所述N型掺杂硅层一侧的子层的材料为钼钛合金时，所述步骤S3中在所述氧化钼层以及所述衬底上制备绝缘层之后，还包括以下步骤：
对所述绝缘层进行图案化，形成暴露所述氧化钼层的第一开孔以及同时形成暴露所述第一电极的第二区域的第二开孔，之后对所述氧化钼层进行退火处理，且退火温度小于或等于350℃。
在本发明的制备方法中，当单层结构的所述第一电极的材料为钼钛合金之外的材料，或者多层结构的所述第一电极中靠近所述N型掺杂硅层一侧的子层的材料为钼钛合金之外的材料时，所述步骤S3中在所述氧化钼层以及所述衬底上制备绝缘层之后，还包括以下步骤：
对所述绝缘层进行第一次图案化，形成暴露所述氧化钼层的第一开孔，并对所述氧化钼层进行退火处理；之后再对所述绝缘层进行第二次图案化，形成暴露所述第一电极的第二区域的第二开孔。
在本发明的制备方法中，所述氧化钼层的功函数的范围为5.2eV-6.8eV之间。
在本发明的制备方法中，所述氧化钼层的禁带宽的范围为2.8eV-3.6eV之间。
为解决上述问题，本发明还提供一种显示装置，包括光敏元件和像素单元，所述光敏元件位于相邻两个所述像素单元之间；其中，所述光敏元件包括：
衬底；
第一电极，设置于所述衬底上；
N型掺杂硅层，设置于所述第一电极上；
非掺杂硅层，设置于所述N型掺杂硅层上；
氧化钼层，设置于所述非掺杂硅层上；
绝缘层，设置于所述氧化钼层以及所述衬底上，所述绝缘层上设有第一开孔以暴露所述氧化钼层；
第二电极，设置于所述绝缘层和氧化钼层上，且通过所述第一开孔与所述氧化钼层接触。
在本发明的显示装置中，所述显示装置包括相对设置的第一基板和第二基板，所述第一基板包括：
第一基底；
第一电极层，设置于所述第一基底上，包括同层并间隔设置的所述第一电极和栅极；
栅极绝缘层，设置于所述第一电极层上，所述栅极绝缘层露出所述第一电极；
所述N型掺杂硅层、所述非掺杂硅层和所述氧化钼层依次层叠的设置于所述第一电极上；
有源层，设置于所述栅极绝缘层正对所述栅极的位置，所述有源层包括非掺杂部和掺杂部；
源极和漏极，设置于所述有源层上，所述源极和所述漏极分别与所述掺杂部接触；
介电层，设置于所述氧化钼层、所述源极和所述漏极上，所述介电层露出所述氧化钼层和所述漏极；
第二电极，设置于所述介电层上，所述第二电极的一端与所述氧化钼层接触，所述第二电极的另一端与所述漏极接触。
在本发明的显示装置中，所述栅极、所述有源层、所述源极和所述漏极构成开关薄膜晶体管，所述光敏元件与所述开关薄膜晶体管电连接。
在本发明的显示装置中，所述第二基板面向所述第一基板的一侧设有黑色矩阵，所述开关薄膜晶体管对应所述黑色矩阵设置。
在本发明的显示装置中，所述第一基板中还包括扫描线和读取线，所述开关薄膜晶体管的栅极与所述扫描线电连接，所述开关薄膜晶体管的源极与所述读取线电连接，所述开关薄膜晶体管的漏极与所述光敏元件的第二电极电连接。
在本发明的显示装置中，所述第一电极包括用于与引线搭接的第一区域和用于与所述N型掺杂硅层接触的第二区域，所述N型掺杂硅层、所述非掺杂硅层、所述氧化钼层以及所述第二电极对应所述第二区域设置。
在本发明的显示装置中，所述第一电极包括由钼、铜、铝、钛、镍和镉中的至少一种金属材料形成的单层或多层结构，所述第二电极包括由氧化铟锌、氧化铟锡、氧化锌和氧化镓锌中的至少一种金属氧化物材料形成的单层或多层结构。
在本发明的显示装置中，所述氧化钼层的功函数的范围为5.2eV-6.8eV之间。
在本发明的显示装置中，所述氧化钼层的禁带宽的范围为2.8eV-3.6eV之间。
 有益效果
本发明的有益效果为：本发明提供的光敏元件及其制备方法、显示装置，采用氧化钼层代替现有技术中同质结或异质结结构的P型材料，减少了对P型材料的制备需求，不仅节约了成本，而且能够提升光敏元件的空穴传输效率，进而提升光敏元件的性能。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本发明提供的光敏元件的结构示意图；
图2为本发明光敏元件在不同白光强度下的IV特性曲线图；
图3为本发明的光敏元件在-0.5V的电压下不同白光光强的响应光电流的参数图；
图4为本发明提供的光敏元件的制备方法流程图；
图5A-图5E为本发明提供的光敏元件的制备方法流程示意图；
图6为本发明提供的显示装置的正视图；
图7为本发明提供的显示装置的截面示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“纵向”、“横向”、“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
本发明针对现有技术中的光敏元件由于采用P型材料导致的成本较高以及空穴传输效率较低的技术问题，本发明的实施例能够解决该缺陷。
请参阅图1，本发明提供了一种光敏元件，其包括：衬底10；第一电极20，设置于所述衬底10上；N型掺杂硅层30，设置于所述第一电极20上；非掺杂硅层40，设置于所述N型掺杂硅层30上；氧化钼层50，设置于所述非掺杂硅层40上；绝缘层60，设置于所述氧化钼层50以及所述衬底10上，所述绝缘层60上设有第一开孔以暴露所述氧化钼层50；第二电极70，设置于所述绝缘层60和氧化钼层50上，且通过所述第一开孔与所述氧化钼层50接触。其中，所述光敏元件可应用于多种场景，示例性的，所述光敏元件可应用于指纹识别的传感器中。
其中，所述N型掺杂硅层30作为所述光敏元件的电子传输层，所述非掺杂硅层40作为所述光敏元件的光吸收层，所述氧化钼层50作为所述光敏元件的空穴传输层。且所述N型掺杂硅层30、所述非掺杂硅层40以及所述氧化钼层50形成所述光敏元件的异质结结构。
本发明采用高功函数的氧化钼层代替现有技术的同质结或异质结结构中的P型材料，在有效提升光敏元件的空穴传输效率的同时，由于减少了对P型材料的制备需求，因此还可节约成本。
以下结合具体实施例对本发明的光敏元件及其制备方法进行详细描述。
请参阅图1，为本发明提供的光敏元件的结构示意图。所述光敏元件包括在衬底10上层叠设置的第一电极20、N型掺杂硅层30、非掺杂硅层40、氧化钼层50、绝缘层60以及第二电极70。
其中，所述衬底10的材料包括玻璃、氧化铝、硅、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯以及聚酰亚胺中的至少一种。
所述第一电极20包括由钼（Mo）、铜（Cu）、铝（Al）、钛（Ti）、镍（Ni）和镉（Cd）中的至少一种金属材料形成的单层或多层结构。具体地，所述第一电极20可包括至少两层子层，至少两层子层的材料可以相同，也可以不同。示例性地，所述第一电极20包括从下至上层叠设置的钼金属子层、铜金属子层和钼金属子层，或者层叠设置的钼金属子层、铝金属子层和钼金属子层，或者层叠设置的铝金属子层和钼金属子层，或者层叠设置的钼钛合金子层、铜金属子层和钼钛合金子层，或者层叠设置的镍金属子层、铜金属子层和镍金属子层，或者层叠设置的镉金属子层、铝金属子层和镉金属子层等多种金属叠层。
所述第一电极20包括用于与引线搭接的第一区域201和用于与所述N型掺杂硅层接触的第二区域202，所述N型掺杂硅层30、所述非掺杂硅层40、所述氧化钼层50以及所述第二电极70对应所述第二区域202层叠设置，所述第一电极20的第一区域201用于后续光敏元件与传感器的其他结构进行引线搭接。
其中，所述非掺杂硅层40为本征半导体硅层，所述N型掺杂硅层30中含有N型杂质，例如掺入五价元素磷、砷、锑等。所述N型掺杂硅层30以及所述非掺杂硅层40的材料不限于非晶硅、微晶硅、以及多晶硅。
在本实施例中，所述氧化钼层50的功函数的范围为8.3×10 -19焦耳至10.9×10 -19焦耳之间（即5.2eV-6.8eV），并且其禁带宽的范围为4.5×10 -19焦耳至5.8×10 -19焦耳之间（即2.8eV-3.6eV）。与现有技术的同质结或异质结结构中的P型材料相比，功函数在此范围内的所述氧化钼层50作为空穴传输层可大大提高空穴注入的效率。
所述第二电极70包括由氧化铟锌、氧化铟锡、氧化锌和氧化镓锌中的至少一种金属氧化物材料形成的单层或多层结构。
其中，在本实施例的光敏元件中，光需要穿过所述第二电极70以及所述氧化钼层50到达所述非掺杂硅层40，因此所述第二电极70以及所述氧化钼层50的材料均需要为透明材料，以减少对光的额外吸收，从而可以增大所述非掺杂硅层40对光的有效吸收，产生更多的光生载流子。
在本实施例中，所述第一电极20用于加载第一极性电压，并用于提供第一类型的载流子，所述第二电极70用于加载第二极性电压，并用于提供第二类型的载流子。所述N型掺杂硅层30作为电子传输层用于向所述非掺杂硅层40传输第一类型的载流子，所述氧化钼层50作为空穴传输层用于向所述非掺杂硅层40传输第二类型的载流子。所述非掺杂硅层40作为光吸收层用于产生光生载流子。
在本实施例中，以氧化钼作为空穴传输层的光敏元件取代了现有技术中采用P型材料形成的同质结或异质结的光电二极管，可有效提升器件的空穴传输效率，使光敏元件具有更高的量子效率，同时可提升光响应速率，进而提升光敏元件的灵敏度；并且还能降低光敏元件的工作电压，实现低功耗。
具体请参阅图2-图3所示，图2为本发明光敏元件在不同白光强度下的IV特性曲线图，图3为本发明的光敏元件在-0.5V的电压下不同白光光强的响应光电流的参数图。在图2中，以工作电压为-2V~2V的区间下进行测试，白光的强度在0lx~1240lx之间，图中给出的是白光光强分别在0lx、37.56lx、41.26lx、63.49lx、89.72lx、140.1lx、277.8lx、747.9lx、1240lx下光敏元件的IV特性曲线。由图2可以看出，随着白光强度的增强，光电流也随之增大。例如，在-2V的工作电压下，当光强度为0lx时，光电流为10 -12安培；当光强度为63.49lx时，光电流为10 -11安培；当光强度为277.8lx时，光电流为10 -10安培。
如图3所示，给出了光敏元件在工作电压为-0.5V时，上述9种白光光强下的光电流参数，可以看出，随着白光强度的增强，光电流也随之增大，从而光响应也随之增大。
与现有技术的光敏元件相比，在两个不同白光光强下，本发明的光敏元件的光电流差异比现有技术的光敏元件的光电流差异大，由于光电流差异越大，光敏元件的分辨率越高，因此使得本发明的光敏元件的分辨率大大提升，同时可提升光敏元件的光响应速率，进而提升光敏元件的灵敏度。另外，本发明的光敏元件的工作电压小于1V，如图3中在-0.5V的电压下即可正常工作，可实现低功耗。
在本发明中，所述N型掺杂硅层30、所述非掺杂硅层40以及所述氧化钼层50可作为介质层，所述第一电极20与所述第二电极70之间会形成电容。由于该异质结本身的结电容较大，因此可充当电路中的存储电容使用，该光敏元件应用于指纹传感器中可提升指纹传感器的分别率，识别出更精细的图案。
本发明还提供了一种光敏元件的制备方法，请参阅图4，图4为本发明提供的光敏元件的制备方法流程图。该制备方法包括以下步骤：
步骤S1，在衬底上形成多个第一电极。
请参阅图5A，在衬底10上采用溅射或蒸镀的工艺制备一层第一金属薄膜。其中，所述衬底10的材料包括玻璃、氧化铝、硅、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯以及聚酰亚胺中的至少一种。所述第一金属薄膜包括由钼（Mo）、铜（Cu）、铝（Al）、钛（Ti）、镍（Ni）、镉（Cd）中的至少一种金属材料形成的单层金属薄膜或多层金属薄膜。之后对所述第一金属薄膜进行图案化，以形成多个第一电极20。
示例性的，所述第一电极20为Mo、Mo/Cu/Mo、Mo/Al/Mo、Al、Al/Mo、MoTi/Cu/MoTi、MoTi/Al/MoTi、Ni/Cu/Ni、Ni/Al/Ni、Al/Ni、Cd/Cu/Cd、Cd/Al/Cd、Al/Cd、Ti/Cu/Ti、Ti/Al/Ti、Al/Ti中的一种单层或多层结构。可以理解的是，这里的“MoTi/Cu/MoTi”表示的是第一电极20从下至上为钼钛合金、铜金属、钼钛合金所构成的三层叠层结构，上述其他结构与之类似，此处不再赘述。
步骤S2，在所述第一电极上依次形成层叠的N型掺杂硅层、非掺杂硅层以及氧化钼层。
请参阅图5B和图5C，在所述第一电极20以及所述衬底10上依次生长N型掺杂硅薄膜30’和非掺杂硅薄膜40’，其中，第一层硅材料（即N型掺杂硅薄膜）在生长的过程中即可同时完成N +杂质的掺杂。具体地，在第一层硅材料生长的过程中掺入杂质气体，如磷烷(PH 3)和砷烷(AsH 3)，以形成N型掺杂硅薄膜30’。第二层硅材料（即非掺杂硅薄膜）为本征硅，生长在所述N型掺杂硅薄膜30’表面。其中，硅材料的生长方式不限于化学气相沉积、原子层沉积、等离子体增强化学的气相沉积法，且硅材料不限于非晶硅、微晶硅以及多晶硅。
接着生长一层透明氧化物薄膜50’覆盖在所述非掺杂硅薄膜40’上，其材料生长方式不限于磁控溅射、化学气相沉积和蒸镀等。在本实施例中，所述透明氧化物薄膜50’为氧化钼薄膜。
之后利用干法刻蚀或湿法刻蚀将N型掺杂硅薄膜30’、非掺杂硅薄膜40’和透明氧化物薄膜50’进行图形化，形成对应所述第一电极20的N型掺杂硅层30、非掺杂硅层40以及氧化钼层50。
其中，所述第一电极20包括用于与引线搭接的第一区域201和用于与所述N型掺杂硅层接触的第二区域202，所述N型掺杂硅层30、所述非掺杂硅层40、所述氧化钼层50对应所述第二区域202设置，所述第一区域201预留出用于后续光敏元件与传感器的其他结构进行引线搭接。
步骤S3，在所述氧化钼层以及所述衬底上制备绝缘层，并在所述绝缘层上形成暴露所述氧化钼层的第一开孔。
请参阅图5D，在所述氧化钼层50以及所述衬底10上生长一层绝缘层60，其生长方式不限于磁控溅射、化学气相沉积、原子层沉积、等离子体增强化学的气相沉积法，其材料包括但不限于氧化铝、氮化硅、二氧化硅、氮化铝中的至少一种。之后对所述绝缘层60进行图案化，以形成暴露所述氧化钼层50的第一开孔601。
步骤S4，在所述绝缘层上形成对应所述氧化钼层的第二电极，且所述第二电极通过所述第一开孔与所述氧化钼层接触。
请参阅图5E，在所述绝缘层60上制备金属氧化物薄膜，所述金属氧化物薄膜包括但不限于氧化铟锌、氧化铟锡、氧化锌和氧化镓锌中的至少一种金属氧化物材料形成的单层或多层结构。之后对所述金属氧化物薄膜图案化后形成对应所述氧化钼层的第二电极70，从而形成由所述第一电极20、所述N型掺杂硅层30、所述非掺杂硅层40、所述氧化钼层50以及所述第二电极70构成的光电二极管结构的光敏元件。
在本发明的上述制备方法中，当单层结构的所述第一电极的材料为钼钛合金，或者多层结构的所述第一电极中靠近所述N型掺杂硅层一侧的子层的材料为钼钛合金时，则所述步骤S3中在所述氧化钼层以及所述衬底上制备绝缘层之后，还包括以下步骤：
对所述绝缘层进行图案化，形成暴露所述氧化钼层的第一开孔以及同时形成暴露所述第一电极的第一区域的第二开孔（如图5D中的602所示），之后对所述氧化钼层进行退火处理，且退火温度小于或等于350℃。
其中，退火气氛包括但不限于氧气、氮气、空气和氩气中的至少一种。
对所述氧化钼层进行退火处理可提高所述氧化钼层中的氧含量，可以提升所述氧化钼层的空穴传输性能。在上述退火处理的过程中，若退火温度过高，比如超过于350℃，会对所述非掺杂硅层的特性产生影响，为了避免影响所述非掺杂硅层的特性，因此退火处理的温度不超过350℃，比如可以为150℃、200℃、250℃或300℃等。
由于钼钛合金耐高温性能优异，在退火工艺中不容易被氧化，因此当单层结构的所述第一电极的材料为钼钛合金时，或者多层结构的所述第一电极中靠近所述N型掺杂硅层一侧的子层的材料为钼钛合金时，所述第一开孔和所述第二开孔可在同一工艺中同时形成，如此便可节省一道光罩制程，节约成本。
其中，钛金属可提供优异的附着性，可提高所述第一电极与所述N型掺杂硅层以及后续通过所述第二开孔与所述第一电极搭接的导电层之间的粘合力，从而提高器件的稳定性。
在本发明的上述制备方法中，当单层结构的所述第一电极的材料为钼钛合金之外的材料，或者多层结构的所述第一电极中靠近所述N型掺杂硅层一侧的子层的材料为钼钛合金之外的材料时，则所述步骤S3中在所述氧化钼层以及所述衬底上制备绝缘层之后，还包括以下步骤：
对所述绝缘层进行第一次图案化，形成暴露所述氧化钼层的第一开孔，并对所述氧化钼层进行退火处理；之后再对所述绝缘层进行第二次图案化，形成暴露所述第一电极的第一区域的第二开孔。
其中，该退火工艺中对退火温度和时间不做限制，退火气氛包括但不限于氧气、氮气、空气和氩气中的至少一种。
在本发明上述提供的第一电极的材料中，钼钛合金的耐高温、耐氧化性能要优于其他材料，所述第一电极靠近所述N型掺杂硅层一侧的子层或者单层结构的第一电极采用钼钛合金之外的其他材料，则被暴露出的部分在退火工艺中容易被氧化，例如钼金属单质在空气中加热到约300℃就开始被氧化，进而影响所述第一电极与后续搭接的导电层的接触性能。
本发明的光敏元件可应用于显示技术领域，具体可以用作为指纹识别传感器中的光敏元件，但并不以此为限。本发明还提供了一种显示装置，如图6所示，该显示装置包括如上所述的光敏元件100以及像素单元200，其中，所述光敏元件100位于相邻两所述像素单元200之间，采用这种方式不会影响到所述像素单元200的像素排布及显示效果。
所述显示装置可以为有机发光致电显示装置、液晶显示装置、量子点显示装置或微发光二极管显示装置中的一种。
如图7所示，该显示装置包括第一基板1和第二基板2，所述第一基板1与所述第二基板2相对设置。所述第一基板1包括第一基底11，所述第一基底11上设有第一电极层，所述第一电极层包括同层并间隔设置的第一电极20和栅极12。所述第一电极层上设有栅极绝缘层13，并且所述栅极绝缘层13对应所述第一电极20的部分被蚀刻掉，以露出所述第一电极20。所述第一电极20上设有异质结，所述异质结包括层叠设置的N型掺杂硅层30、非掺杂硅层40和氧化钼层50，其中所述N型掺杂硅层30与所述第一电极20接触。所述栅极绝缘层13正对所述栅极12的位置设有有源层14，所述有源层14包括非掺杂部141和掺杂部142。所述有源层14上设有源/漏极15，所述源/漏极15与所述掺杂部142接触。所述异质结与所述源/漏极15上设有介电层16（绝缘层60），所述介电层16露出所述氧化钼层50和所述漏极15。所述介电层16上设有第二电极70，所述第二电极70的一端与所述氧化钼层50接触，所述第二电极70的另一端与所述漏极15接触。
其中，所述第一电极20、所述N型掺杂硅层30、所述非掺杂硅层40、所述氧化钼层50和所述第二电极70构成光敏元件，所述栅极12、所述有源层14、所述源极和所述漏极构成开关薄膜晶体管。
所述第二基板2面向所述第一基板1的一侧设有黑色矩阵21，所述开关薄膜晶体管对应所述黑色矩阵21设置，所述光敏元件设置于所述黑色矩阵21覆盖的范围之外，可以感知射向所述光敏元件的外界光线。
所述第一基板1中还包括图中未示意的扫描线和读取线，所述光敏元件与所述开关薄膜晶体管电连接，所述开关薄膜晶体管的栅极12与所述扫描线电连接，所述开关薄膜晶体管的源极与所述读取线电连接，所述开关薄膜晶体管的漏极与所述光敏元件的第二电极70电连接，所述读取线用于读取所述光敏元件感应的光电流信号，从而实现光敏元件的光电传感功能。
本发明提供的光敏元件及其制备方法，采用高功函数的氧化钼层代替现有技术中光敏元件的同质结或异质结中的P型材料，减少了对P型材料的制备需求，不仅节约了成本，而且能够提升光敏元件的空穴传输效率，进而提升光敏元件的性能。本发明的显示装置在不影响正常显示的情况下，可以实现高分别率、高灵敏度的指纹识别。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种光敏元件，其包括：
    衬底；
    第一电极，设置于所述衬底上；
    N型掺杂硅层，设置于所述第一电极上；
    非掺杂硅层，设置于所述N型掺杂硅层上；
    氧化钼层，设置于所述非掺杂硅层上；
    绝缘层，设置于所述氧化钼层以及所述衬底上，所述绝缘层上设有第一开孔以暴露所述氧化钼层；
    第二电极，设置于所述绝缘层和氧化钼层上，且通过所述第一开孔与所述氧化钼层接触。
  2. 根据权利要求1所述的光敏元件，其中，所述第一电极包括用于与引线搭接的第一区域和用于与所述N型掺杂硅层接触的第二区域，所述N型掺杂硅层、所述非掺杂硅层、所述氧化钼层以及所述第二电极对应所述第二区域设置。
  3. 根据权利要求1所述的光敏元件，其中，所述第一电极包括由钼、铜、铝、钛、镍和镉中的至少一种金属材料形成的单层或多层结构，所述第二电极包括由氧化铟锌、氧化铟锡、氧化锌和氧化镓锌中的至少一种金属氧化物材料形成的单层或多层结构。
  4. 根据权利要求1所述的光敏元件，其中，所述氧化钼层的功函数的范围为5.2eV-6.8eV之间。
  5. 根据权利要求1所述的光敏元件，其中，所述氧化钼层的禁带宽的范围为2.8eV-3.6eV之间。
  6. 一种光敏元件的制备方法，其中，包括以下步骤：
    步骤S1，在衬底上形成多个第一电极；
    步骤S2，在所述第一电极上依次形成层叠的N型掺杂硅层、非掺杂硅层以及氧化钼层；
    步骤S3，在所述氧化钼层以及所述衬底上制备绝缘层，并在所述绝缘层上形成暴露所述氧化钼层的第一开孔；
    步骤S4，在所述绝缘层上形成对应所述氧化钼层的第二电极，且所述第二电极通过所述第一开孔与所述氧化钼层接触。
  7. 根据权利要求6所述的制备方法，其中，所述第一电极包括由钼、铜、铝、钛、镍和镉中的至少一种金属材料形成的单层或多层结构，所述第一电极包括用于与引线搭接的第一区域和用于与所述N型掺杂硅层接触的第二区域，所述N型掺杂硅层、所述非掺杂硅层、所述氧化钼层以及所述第二电极对应所述第二区域设置。
  8. 根据权利要求7所述的制备方法，其中，当单层结构的所述第一电极的材料为钼钛合金，或者多层结构的所述第一电极中靠近所述N型掺杂硅层一侧的子层的材料为钼钛合金时，所述步骤S3中在所述氧化钼层以及所述衬底上制备绝缘层之后，还包括以下步骤：
    对所述绝缘层进行图案化，形成暴露所述氧化钼层的第一开孔以及同时形成暴露所述第一电极的第二区域的第二开孔，之后对所述氧化钼层进行退火处理，且退火温度小于或等于350℃。
  9. 根据权利要求7所述的制备方法，其中，当单层结构的所述第一电极的材料为钼钛合金之外的材料，或者多层结构的所述第一电极中靠近所述N型掺杂硅层一侧的子层的材料为钼钛合金之外的材料时，所述步骤S3中在所述氧化钼层以及所述衬底上制备绝缘层之后，还包括以下步骤：
    对所述绝缘层进行第一次图案化，形成暴露所述氧化钼层的第一开孔，并对所述氧化钼层进行退火处理；之后再对所述绝缘层进行第二次图案化，形成暴露所述第一电极的第二区域的第二开孔。
  10. 根据权利要求6所述的制备方法，其中，所述氧化钼层的功函数的范围为5.2eV-6.8eV之间。
  11. 根据权利要求6所述的制备方法，其中，所述氧化钼层的禁带宽的范围为2.8eV-3.6eV之间。
  12. 一种显示装置，其包括光敏元件和像素单元，所述光敏元件位于相邻两个所述像素单元之间；其中，所述光敏元件包括：
    衬底；
    第一电极，设置于所述衬底上；
    N型掺杂硅层，设置于所述第一电极上；
    非掺杂硅层，设置于所述N型掺杂硅层上；
    氧化钼层，设置于所述非掺杂硅层上；
    绝缘层，设置于所述氧化钼层以及所述衬底上，所述绝缘层上设有第一开孔以暴露所述氧化钼层；
    第二电极，设置于所述绝缘层和氧化钼层上，且通过所述第一开孔与所述氧化钼层接触。
  13. 根据权利要求12所述的显示装置，其中，所述显示装置包括相对设置的第一基板和第二基板，所述第一基板包括：
    第一基底；
    第一电极层，设置于所述第一基底上，包括同层并间隔设置的所述第一电极和栅极；
    栅极绝缘层，设置于所述第一电极层上，所述栅极绝缘层露出所述第一电极；
    所述N型掺杂硅层、所述非掺杂硅层和所述氧化钼层依次层叠的设置于所述第一电极上；
    有源层，设置于所述栅极绝缘层正对所述栅极的位置，所述有源层包括非掺杂部和掺杂部；
    源极和漏极，设置于所述有源层上，所述源极和所述漏极分别与所述掺杂部接触；
    介电层，设置于所述氧化钼层、所述源极和所述漏极上，所述介电层露出所述氧化钼层和所述漏极；
    第二电极，设置于所述介电层上，所述第二电极的一端与所述氧化钼层接触，所述第二电极的另一端与所述漏极接触。
  14. 根据权利要求13所述的显示装置，其中，所述栅极、所述有源层、所述源极和所述漏极构成开关薄膜晶体管，所述光敏元件与所述开关薄膜晶体管电连接。
  15. 根据权利要求14所述的显示装置，其中，所述第二基板面向所述第一基板的一侧设有黑色矩阵，所述开关薄膜晶体管对应所述黑色矩阵设置。
  16. 根据权利要求14所述的显示装置，其中，所述第一基板中还包括扫描线和读取线，所述开关薄膜晶体管的栅极与所述扫描线电连接，所述开关薄膜晶体管的源极与所述读取线电连接，所述开关薄膜晶体管的漏极与所述光敏元件的第二电极电连接。
  17. 根据权利要求12所述的显示装置，其中，所述第一电极包括用于与引线搭接的第一区域和用于与所述N型掺杂硅层接触的第二区域，所述N型掺杂硅层、所述非掺杂硅层、所述氧化钼层以及所述第二电极对应所述第二区域设置。
  18. 根据权利要求12所述的显示装置，其中，所述第一电极包括由钼、铜、铝、钛、镍和镉中的至少一种金属材料形成的单层或多层结构，所述第二电极包括由氧化铟锌、氧化铟锡、氧化锌和氧化镓锌中的至少一种金属氧化物材料形成的单层或多层结构。
  19. 根据权利要求12所述的显示装置，其中，所述氧化钼层的功函数的范围为5.2eV-6.8eV之间。
  20. 根据权利要求12所述的显示装置，其中，所述氧化钼层的禁带宽的范围为2.8eV-3.6eV之间。
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