WO2022141353A1 - 背栅晶体管及其制备方法 - Google Patents

背栅晶体管及其制备方法 Download PDF

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WO2022141353A1
WO2022141353A1 PCT/CN2020/141975 CN2020141975W WO2022141353A1 WO 2022141353 A1 WO2022141353 A1 WO 2022141353A1 CN 2020141975 W CN2020141975 W CN 2020141975W WO 2022141353 A1 WO2022141353 A1 WO 2022141353A1
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substrate
hole
periodic
periodic hole
gate transistor
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PCT/CN2020/141975
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English (en)
French (fr)
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卢红亮
陈金鑫
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光华临港工程应用技术研发(上海)有限公司
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Publication of WO2022141353A1 publication Critical patent/WO2022141353A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

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  • the present invention relates to the field of semiconductors, in particular to a back-gate transistor and a preparation method thereof.
  • ⁇ -Ga 2 O 3 In recent years, the wide-bandgap semiconductor ⁇ -Ga 2 O 3 has attracted extensive attention of researchers due to its extremely high critical breakdown field strength, large forbidden band width, good thermal stability and chemical inertness.
  • High-quality ⁇ -Ga 2 O 3 substrates can be used in high-temperature, high-voltage and high-power electronic devices.
  • ⁇ -Ga 2 O 3 Combined with the carrier mobility of about 300cm 2 V -1 s -1 , ⁇ -Ga 2 O 3 exhibits a large Baliga figure of merit (BFOM, about 3444), which is much higher than that of similar materials SiC and GaN. This makes ⁇ - Ga2O3 ideal for next - generation power electronic devices.
  • BFOM Baliga figure of merit
  • ⁇ -Ga 2 O 3 single crystal growth methods such as the guided mode method, the floating zone method and the Bridgman method.
  • the effective electron concentration of ⁇ -Ga 2 O 3 single crystal material can be effectively modulated in a wide range of 1016-1019 cm -3 .
  • another unique property of ⁇ -Ga 2 O 3 compared to other wide-bandgap materials is that quasi-two-dimensional ⁇ -Ga 2 O 3 nanosheets can be obtained by common tape lift-off techniques. All this makes ⁇ -Ga 2 O 3 widely feasible in future applications.
  • ⁇ -Ga 2 O 3 channel devices is still in the early stage of development, there are still many technical difficulties.
  • the thermal conductivity of ⁇ -Ga 2 O 3 material is obviously low, and the industry generally uses flat SiO 2 /p ++ -Si as the substrate of two-dimensional (2D) and quasi-2D back-gate transistors, and the SiO 2 gate
  • the thickness of the dielectric layer is 285-300nm, which will inevitably aggravate the heat dissipation problem of the ⁇ -Ga 2 O 3 device and affect the high temperature working state of the device.
  • the interface properties between the gate dielectric and the ⁇ -Ga 2 O 3 channel layer can significantly affect the channel transport, field-effect mobility, threshold voltage stability and transistor reliability of Ga 2 O 3 based devices.
  • ⁇ -Ga 2 O 3 has an ultra-wide bandgap
  • ohmic contact needs to be formed by subsequent annealing.
  • the above-mentioned device process will inevitably cause a large contact resistance of ⁇ -Ga 2 O 3 and affect the performance of the transistor. Therefore, Not suitable for ⁇ -Ga 2 O 3 channel material.
  • the technical problem to be solved by the present invention is that it is difficult to apply ⁇ -Ga 2 O 3 to channel materials and to prepare high-efficiency transistors.
  • a back-gate transistor and a preparation method thereof are provided.
  • the present invention provides a back-gate transistor, comprising: a periodic hole base, the periodic hole base is composed of a silicon substrate and a dielectric layer on the surface of the silicon substrate, the dielectric
  • the surface of the electrical layer has a periodic hole array; a source electrode, the source electrode is located on the periodic hole substrate; a drain electrode, the drain electrode is located on the periodic hole substrate and is separate from the source electrode On both sides of a hole; a gate, which is a suspended ⁇ -Ga 2 O 3 nanobelt, connecting the source and the drain.
  • the present invention also provides a method for preparing a back-gate transistor, including the following steps: providing a substrate, the substrate is composed of a silicon substrate and a dielectric layer on the surface of the silicon substrate; etching the substrate, forming a periodic hole substrate with a periodic hole array; transferring the ⁇ -Ga 2 O 3 nanobelt to a hole of the periodic hole substrate; etching the periodic hole substrate to form Photolithographic patterns of source and drain electrodes on both sides of the ⁇ - Ga2O3 nanoribbons; depositing a metal stack on the photolithographic patterns to form the source and drain electrodes of the transistors; annealing in a N2 atmosphere.
  • the invention solves the problem that ⁇ -Ga 2 O 3 is difficult to apply to the channel material, and provides a high-efficiency back-gate transistor.
  • FIG. 1 is a schematic diagram of the steps described in a specific embodiment of the present invention.
  • 2A-2E are schematic diagrams of the processes of steps S10-S14 in FIG. 1 .
  • FIG. 3 shows an optical microscope image of the periodic hole substrate according to an embodiment of the present invention.
  • FIG. 4 shows an optical microscope image of the ⁇ -Ga 2 O 3 nanoribbons transferred to the periodic hole substrate according to an embodiment of the present invention.
  • FIG. 5 shows an optical microscope image of the back-gate transistor according to an embodiment of the present invention.
  • Fig. 6 shows a current-voltage electrical measurement image of the back-gate transistor according to an embodiment of the present invention.
  • 7A-7F are schematic diagrams illustrating the process of the periodic hole substrate according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of the steps according to a specific embodiment of the present invention, including: step S10, providing a substrate, the substrate is composed of a silicon substrate and a dielectric layer on the surface of the silicon substrate; step S11, Etch the substrate to form a periodic hole substrate with a periodic hole array; step S12, transfer the ⁇ -Ga 2 O 3 nanobelt to a hole of the periodic hole substrate; step S13, etch the The periodic hole substrate is formed to form a lithographic pattern of source and drain electrodes on both sides of the ⁇ -Ga 2 O 3 nanobelt; step S14, a metal stack is deposited on the lithographic pattern to form the source and drain of the transistor ; Step S15, annealing in N 2 atmosphere.
  • a substrate 21 is provided, and the substrate 21 is composed of a silicon substrate 201 and a dielectric layer 202 on the surface of the silicon substrate 201 .
  • the silicon substrate 201 is a heavily doped P-type silicon substrate
  • the dielectric layer 202 is a SiO 2 material layer with a thickness of 110 nm.
  • the substrate 21 is etched to form a periodic hole substrate 22 with a periodic hole array.
  • the hole diameter of the periodic hole array is 5 ⁇ m, and the depth can be modulated by changing the reactive ion etching time; the distance between adjacent 5 ⁇ 5 circular arrays is 100 ⁇ m, and each The spacing between adjacent circles in each array is 10 ⁇ m.
  • FIG. 3 is an optical microscope image of the periodic hole substrate according to an embodiment of the present invention.
  • the ⁇ -Ga 2 O 3 nanobelt 203 is transferred to a hole of the periodic hole substrate 22 .
  • the above-mentioned transfer step is completed by using a two-dimensional material transfer platform, and the ⁇ -Ga 2 O 3 nanobelt 203 is obtained by mechanically peeling off the ⁇ -Ga 2 O 3 single crystal bulk body using 3M tape.
  • the effective carrier concentration of the ⁇ -Ga 2 O 3 single crystal bulk is 10 17 -10 19 cm -3 .
  • FIG. 4 is an optical microscope image of the ⁇ -Ga 2 O 3 nanoribbons 203 transferred to the periodic hole substrate according to an embodiment of the present invention.
  • the periodic hole substrate 22 is etched to form source-drain electrode lithography patterns 204 and 205 on both sides of the ⁇ -Ga 2 O 3 nanobelt 203 .
  • the boxes marked by the dotted lines are the lithography patterns 204 and 205 .
  • metal stacks are deposited on the lithographic patterns 204 and 205 to form the source electrode 206 and the drain electrode 207 of the transistor.
  • the source electrode 206 and the drain electrode 207 use an electron beam evaporation method to deposit metal stacks, and the metal stacks are sequentially a metal Ti layer, a metal Al layer, a metal Ni layer, and The thickness of the metal Au layer is successively 20 nm, 100 nm, 40 nm, and 80 nm, and the formation temperature is 50°C.
  • Step S15 annealing in N2 atmosphere.
  • the annealing process uses rapid thermal annealing equipment, annealing in N 2 atmosphere to achieve good ohmic contact of the transistor, the annealing temperature is 470°C, and the annealing time is 70s.
  • the back-gate transistor according to a specific embodiment of the present invention is obtained.
  • the structure of the back-gate transistor is shown in FIG. 2E , including: a periodic hole substrate 22 , the periodic The hole base 22 is composed of a silicon substrate 201 and a dielectric layer 202 on the surface of the silicon substrate 201, the surface of the dielectric layer 202 has a periodic hole array; a source electrode 206, the source electrode 206 is located in the On the periodic hole substrate 22; a drain 207, the drain 207 is located on the periodic hole substrate 22, and is separated from the source 206 on both sides of a hole; a gate 203, the gate 203 is a suspended ⁇ -Ga 2 O 3 nanoribbon, connecting the source electrode 206 and the drain electrode 207 .
  • the silicon substrate 201 is a heavily doped P-type silicon substrate, and the dielectric layer 202 is a SiO 2 material layer with a thickness of 110 nm.
  • the periodic holes on the substrate 22 are arranged in a 5 ⁇ 5 hole array, the distance between adjacent arrays is 100 ⁇ m, and the distance between adjacent holes in the array is 10 ⁇ m; the holes are circular holes with a diameter of 5 ⁇ m.
  • FIG. 5 shows an optical microscope image of the back-gate transistor according to an embodiment of the present invention.
  • the graph a on the left is the drain current-source-drain voltage (I d -V d ) ohmic characteristic detection curve of the transistor
  • the graph on the right b is the drain current-gate voltage (I d -V bg ) transfer characteristic curve of the above transistor, and the switching current ratio is higher than 104, indicating that the sample has good device characteristics.
  • the above technical solution solves the problem that ⁇ -Ga 2 O 3 is difficult to apply to the channel material, and provides a high-performance back-gate transistor.
  • the first step is to clean the substrate: take a flat, heavily doped P-type Si (100 ) layer with a 110nm SiO layer as the substrate, and use acetone, ethanol, and deionized water for ultrasonic cleaning for 15 minutes in turn to remove organic matter on the surface of Si, Finally blow dry with nitrogen.
  • the second step the preparation method of the SiO 2 (110-nm)/p ++ -Si periodic hole substrate, with reference to the schematic diagrams of the periodic hole substrate process according to an embodiment of the present invention shown in FIGS. 7A-7F , the The method includes the following steps:
  • step (2) placing the sample in step (1) on the glue drying table for soft drying, the heating temperature of the glue drying table is 100°C, and the glue drying time is 90s;
  • the method of magnetron sputtering is used to deposit about 60nm thick metal nickel on the side of the sample with the lithography pattern, for etching the mask, the power is 75W, and the working pressure is 0.35 in the Ar atmosphere Pa;
  • the sample in step (6) was subjected to reactive ion etching (RIE), the etching gas SF 6 /O 2 , the flow rates were 20 and 30 sccm, the etching power was 150 W, and the working pressure was is 3Pa, the etching time is 60s;
  • RIE reactive ion etching
  • the third step is a preparation method of a ⁇ -Ga 2 O 3 nanobelt suspended back-gate transistor based on a SiO 2 (110-nm)/p ++ -Si periodic hole substrate, the method comprising the following steps:
  • ⁇ -Ga 2 O 3 nanobelts were mechanically peeled off from ⁇ -Ga 2 O 3 single crystal bulks using 3M tape, and the thickness of the nanobelts was ⁇ 200 nm;
  • step (1) using a two-dimensional material transfer platform to transfer the ⁇ -Ga 2 O 3 nanobelt in step (1) to a certain hole of the SiO 2 (110-nm)/p ++ -Si periodic hole substrate;
  • step (3) The sample in step (2) is fixed on the tray of the spinner, and the electron beam photoresist is spin-coated.
  • Rotation speed of the glue homogenizer 500rad/min for forward rotation, 5s for forward rotation; 4000rad/min for rear rotation, 60s for backward rotation;
  • step (3) place the sample in step (3) on the glue drying table for soft drying, the heating temperature of the glue drying table is 170°C, and the glue drying time is 3min30s;
  • EBL electron beam exposure
  • EBE electron beam evaporation
  • step (8) Immerse the sample in step (7) in acetone solution, and use an ultrasonic bath to carry out ultrasonic cleaning to peel off the remaining photoresist until the surface pattern of the sample completely appears, then take out the sample and rinse it with deionized water. After drying, the ⁇ -Ga 2 O 3 nanobelt suspended back-gate transistor based on SiO 2 (110-nm)/p ++ -Si periodic hole substrate is obtained.
  • annealing temperature is 470 °C
  • annealing time is 70 s.

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Abstract

本发明提供了一种背栅晶体管，包括：一周期性孔洞基底，所述周期性孔洞基底由一硅衬底以及所述硅衬底表面的介电层组成，所述介电层表面具有周期性孔洞阵列；一源极，所述源极位于所述周期性孔洞基底上；一漏极，所述漏极位于所述周期性孔洞基底上，且与所述源极分立于一孔洞两侧；一栅极，所述栅极为悬空的β-Ga 2O 3纳米带，连接所述源极和漏极。本发明解决了β-Ga 2O 3难以应用于沟道材料的问题，并提供了一种高效能的背栅晶体管。

Description

背栅晶体管及其制备方法 技术领域
本发明涉及半导体领域，尤其涉及一种背栅晶体管及其制备方法。
背景技术
近年来，宽禁带半导体β-Ga 2O 3由于具备极高的临界击穿场强、超大的禁带宽度、良好的热稳定性和化学惰性，受到了研究人员广泛的关注。高质量的β-Ga 2O 3衬底可应用在高温、高压及大功率电子设备。结合大约300cm 2V -1s -1的载流子迁移率，β-Ga 2O 3展现出很大的Baliga优值(BFOM，约为3444)，远高于同类型材料SiC和GaN。这使得β-Ga 2O 3成为下一代电力电子器件的理想选择。目前，科研人员已报道了多种简易且成本低廉的β-Ga 2O 3单晶生长方式，例如导模法、浮区法及Bridgman法等。β-Ga 2O 3单晶材料的有效电子浓度可以在1016-1019cm -3这一宽广的区间内实现有效的调制。此外，相比于其他宽带隙材料，β-Ga 2O 3的另一个独特性质在于可以通过常见的胶带剥离技术获得准二维的β-Ga 2O 3纳米片。这一切使得β-Ga 2O 3在未来应用中具备广泛的可行性。但是，由于β-Ga 2O 3沟道器件的研制仍处于发展初期，还面临着众多的技术性难题。例如β-Ga 2O 3材料的热导率明显偏低，而业界普遍使用平整的SiO 2/p ++-Si作为二维(2D)及准2D背栅晶体管的衬底，且SiO 2栅介质层的厚度为285-300nm，这势必加重β-Ga 2O 3器件的散热问题，影响器件的高温工作状态。此外，还存在着栅介质/β-Ga 2O 3沟道之间界面陷阱密度的问题。栅介质与β-Ga 2O 3沟道层之间的界面特性会显著地影响Ga 2O 3基器件的沟道输运、场效应迁移率、阈值电压稳定性以及晶体管的可靠性。
近年来，为了研究沟道材料的物理属性，避免受到衬底表面缺陷对沟道的影响，科研人员在2D材料器件领域提出了悬空器件的概念，即将晶体管的沟道材料悬浮，避免与底部的介电层完全接触。Chen和Lodha等人分别使用相同的器件工艺研制了局部悬空的MoS 2及ReS 2背栅场效应晶体管(FET)。他们预先在平整的SiO 2(300-nm)/p ++-Si衬底上制备好源漏电极，随后将沟道材料直接干法转移至两电极上。制备的悬空FET具有良好的欧姆接触并展现出较好的电学及光电性能。
但是，由于β-Ga 2O 3具有超宽的带隙，需要借助后续的退火来形成欧姆接触，上述的器件工艺势必造成β-Ga 2O 3很大的接触电阻，影响晶体管的性能，因此并不适合应用在β-Ga 2O 3沟道材料上。
发明内容
本发明所要解决的技术问题是β-Ga 2O 3难以应用于沟道材料并制备高效能晶体管的问题，提供一种背栅晶体管及其制备方法。
为了解决上述问题，本发明提供了一种背栅晶体管，包括：一周期性孔洞基底，所述周期性孔洞基底由一硅衬底以及所述硅衬底表面的介电层组成，所述介电层表面具有周期性孔洞阵列；一源极，所述源极位于所述周期性孔洞基底上；一漏极，所述漏极位于所述周期性孔洞基底上，且与所述源极分立于一孔洞两侧；一栅极，所述栅极为悬空的β-Ga 2O 3纳米带，连接所述源极和漏极。
为了解决上述问题，本发明还提供了一种背栅晶体管的制备方法，包括如下步骤：提供一基底，所述基底由一硅衬底以及所述硅衬底表面的介电层组成；刻蚀所述基底，形成带有周期性孔洞阵列的周期性孔洞基底；将β-Ga 2O 3纳米带转移至所述周期性孔洞基底的一个孔洞上；刻蚀所述周期性孔洞基底，以形成位于β-Ga 2O 3纳米带两侧的源漏电极光刻图案；在所述光刻图案上沉积金属叠层，以形成晶体管的源极和漏极；在N2气氛中退火。
本发明解决了β-Ga 2O 3难以应用于沟道材料的问题，并提供了一种高效能的背栅晶体管。
附图说明
附图1所示是本发明一具体实施方式所述步骤示意图。
附图2A-2E所示是附图1中步骤S10-S14工艺示意图。
附图3所示是本发明一具体实施方式所述周期性孔洞基底光学显微镜图像。
附图4所示是本发明一具体实施方式所述转移至周期性孔洞基底上的β-Ga 2O 3纳米带的光学显微镜图像。
附图5所示是本发明一具体实施方式所述背栅晶体管光学显微镜图像。
附图6所示是本发明一具体实施方式所述背栅晶体管的电流-电压电学测 量图像。
附图7A-7F所示是本发明一具体实施方式所述周期性孔洞基底工艺示意图。
具体实施方式
下面结合附图对本发明提供的一种背栅式晶体管及其制备方法的具体实施方式做详细说明。
附图1所示是本发明一具体实施方式所述步骤示意图，包括：步骤S10，提供一基底，所述基底由一硅衬底以及所述硅衬底表面的介电层组成；步骤S11，刻蚀所述基底，形成带有周期性孔洞阵列的周期性孔洞基底；步骤S12，将β-Ga 2O 3纳米带转移至所述周期性孔洞基底的一个孔洞上；步骤S13，刻蚀所述周期性孔洞基底，以形成位于β-Ga 2O 3纳米带两侧的源漏电极光刻图案；步骤S14，在所述光刻图案上沉积金属叠层，以形成晶体管的源极和漏极；步骤S15，在N 2气氛中退火。
附图2A所示，参考步骤S10，提供一基底21，所述基底21由一硅衬底201以及所述硅衬底201表面的介电层202组成。在本发明的一个具体实施方式中，所述硅衬底201为重掺杂P型硅衬底，所述介电层202为厚度为110nm的SiO 2材料层。
附图2B所示，参考步骤S11，刻蚀所述基底21，形成带有周期性孔洞阵列的周期性孔洞基底22。在本发明的一个具体实施方式中，所述周期性孔洞阵列的孔洞直径5μm，且深度可以通过改变反应离子刻蚀时间来调制；相邻的5×5圆形阵列之间距离为100μm，每个阵列中相邻圆的间距为10μm。
为了更清楚的表示周期性孔洞基底22的结构，采用扫描电子显微镜进行图像扫描。附图3所示即为本发明一具体实施方式所述周期性孔洞基底光学显微镜图像。
附图2C所示，参考步骤S12，将β-Ga 2O 3纳米带203转移至所述周期性孔洞基底22的一个孔洞上。在本发明的一个具体实施方式中，利用二维材料转移平台完成上述转移步骤，所述β-Ga 2O 3纳米带203使用3M胶带从β-Ga 2O 3单晶块体上机械剥离得到；所述β-Ga 2O 3单晶块体的有效载流子浓度为10 17 -10 19cm -3。
为了更清楚的表示β-Ga 2O 3纳米带203的转移位置，采用扫描电子显微镜进行图像扫描。附图4所示即为本发明一具体实施方式所述转移至周期性孔洞基底上的β-Ga 2O 3纳米带203的光学显微镜图像。
附图2D所示，参考步骤S13，刻蚀所述周期性孔洞基底22，以形成位于β-Ga 2O 3纳米带203两侧的源漏电极光刻图案204、205，在本发明的一个具体实施方式中，所示虚线标出的方框即为光刻图案204、205。
附图2E所示，参考步骤S14，在所述光刻图案204、205上沉积金属叠层，以形成晶体管的源极206和漏极207。在本发明的一个具体实施方式中，所述源极206和漏极207采用电子束蒸发的方法沉积金属叠层，所述金属叠层依次为金属Ti层、金属Al层、金属Ni层、以及金属Au层，厚度依次为20nm、100nm、40nm、以及80nm，形成温度为50℃。
步骤S15，在N 2气氛中退火。在本发明的一个具体实施方式中，所述退火过程使用快速热退火设备，在N 2气氛中退火，以实现晶体管良好的欧姆接触，退火温度为470℃，退火时间为70s。
上述步骤实施完毕后，即获得本发明一具体实施方式所述的背栅式晶体管，所述背栅式晶体管的结构如附图2E所示，包括：一周期性孔洞基底22，所述周期性孔洞基底22由一硅衬底201以及所述硅衬底201表面的介电层202组成，所述介电层202表面具有周期性孔洞阵列；一源极206，所述源极206位于所述周期性孔洞基底22上；一漏极207，所述漏极207位于所述周期性孔洞基底22上，且与所述源极206分立于一孔洞两侧；一栅极203，所述栅极203为悬空的β-Ga 2O 3纳米带，连接所述源极206和漏极207。在本发明的一个具体实施方式中，所述硅衬底201为重掺杂P型硅衬底，所述介电层202为厚度为110nm的SiO 2材料层。所述基底22上的周期性孔洞以5×5的孔洞阵列排列，相邻阵列之间距离100μm，阵列中相邻孔洞之间距离为10μm；所述孔洞为直径5μm的圆形孔洞。
附图5所示是本发明一具体实施方式所述背栅晶体管光学显微镜图像。
使用半导体器件分析仪测定上述样品的电学特性，如附图6所示，左侧的 图a是晶体管的漏极电流-源漏电压(I d-V d)欧姆特性检测曲线，右侧的图b是上述晶体管的漏极电流-栅极电压(I d-V bg)转移特性曲线，开关电流比高于104，显示样品具有良好的器件特性。
上述技术方案解决了β-Ga 2O 3难以应用于沟道材料的问题，并提供了一种高效能的背栅晶体管。
以下结合具体工艺场景给出上述技术方案的一个实施例。
基于SiO 2(110-nm)/p ++-Si周期性孔洞基底的β-Ga 2O 3纳米带悬空背栅晶体管的制备，孔洞深度55nm。
第一步骤，衬底清洗：以平整的长有110nm SiO 2层的重掺杂P型Si(100)为衬底，依次用丙酮、乙醇、去离子水超声波清洗15min，去除Si表面的有机物，最后用氮气吹干。
第二步骤，SiO 2(110-nm)/p ++-Si周期性孔洞基底的制备方法，参考附图7A-7F所示的本发明一具体实施方式所述周期性孔洞基底工艺示意图，所述方法包括以下步骤：
(1)附图7A所示，将清洗好的平整衬底SiO 2(110-nm)/p ++-Si固定在匀胶机托盘上，旋涂正性光刻胶。匀胶机转速：前转500rad/min，前转时间5s；后转3000rad/min，后转时间60s；
(2)将步骤(1)中的样品放置在烘胶台上软烘，烘胶台加热温度100℃，烘胶时间90s；
(3)用光刻机对样品进行紫外曝光，将掩膜版上的周期性圆形阵列微图案转移到样品光刻胶上，曝光时间18s，且掩膜版上的周期性圆形阵列微图案的圆形直径5μm，相邻的5×5圆形阵列之间距离为100μm，每个阵列中相邻圆的间距为10μm；
(4)将样品浸泡在显影液中显影，显影时间45s，然后立刻取出样品用去离子水冲净，用N 2吹干；得到附图7B所示的结构。
(5)附图7C所示，用磁控溅射的方法在样品有光刻图案的一面沉积约60nm厚的金属镍，用于刻蚀掩膜，功率75W，工作气压为在Ar氛围中0.35Pa；
(6)附图7D所示，将样品浸泡于丙酮溶液中，使用超声池进行超声波清 洗剥离剩余的光刻胶，直至样品表面图案完全出现；
(7)附图7E所示，对步骤(6)中的样品进行反应离子刻蚀(RIE)，刻蚀气体SF 6/O 2，流量分别为20和30sccm，刻蚀功率为150W，工作气压为3Pa，刻蚀时间60s；
(8)附图7F所示，将样品浸泡于混合溶液(体积比HNO 3:HCl:H 2O＝1:1:3)中，超声波清洗15min，以去除残留的掩膜金属镍，即获得所述的SiO 2(110-nm)/p ++-Si周期性孔洞基底。
第三步骤，基于SiO 2(110-nm)/p ++-Si周期性孔洞基底的β-Ga 2O 3纳米带悬空背栅晶体管的制备方法，所述方法包括以下步骤：
(1)使用3M胶带从β-Ga 2O 3单晶块体上机械剥离出β-Ga 2O 3纳米带，纳米带厚度～200nm；
(2)利用二维材料转移平台将步骤(1)中的β-Ga 2O 3纳米带转移至SiO 2(110-nm)/p ++-Si周期性孔洞基底的某一孔洞上；
(3)将步骤(2)中的样品固定在匀胶机托盘上，旋涂电子束光刻胶。匀胶机转速：前转500rad/min，前转时间5s；后转4000rad/min，后转时间60s；
(4)将步骤(3)中的样品放置在烘胶台上软烘，烘胶台加热温度170℃，烘胶时间3min 30s；
(5)对步骤(4)中的样品进行电子束曝光(EBL)，以制作源漏电极图案；
(6)将曝光后的样品浸泡在显影液中显影，显影时间60s，然后立刻取出样品用N 2吹干，再将样品浸泡在异丙醇中定影，定影时间60s，随后立刻取出样品并用N 2吹干；
(7)用电子束蒸发(EBE)的方法在样品有光刻图案的一面沉积Ti/Al/Ni/Au叠层金属，用作晶体管的电极，叠层金属电极厚度为20/100/40/80nm，生长温度为50℃；
(8)将步骤(7)中的样品浸泡于丙酮溶液中，使用超声池进行超声波清洗剥离剩余的光刻胶，直至样品表面图案完全出现，随后取出样品用去离子水冲净，用N 2吹干，即获得所述的基于SiO 2(110-nm)/p ++-Si周期性孔洞基底的 β-Ga 2O 3纳米带悬空背栅晶体管。
(9)使用快速热退火(RTP)设备对步骤g中的样品进行N 2气氛退火，以实现晶体管良好的欧姆接触，退火温度470℃，退火时间70s。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (9)

  1. 一种背栅晶体管，其特征在于，包括：
    一周期性孔洞基底，所述周期性孔洞基底由一硅衬底以及所述硅衬底表面的介电层组成，所述介电层表面具有周期性孔洞阵列；
    一源极，所述源极位于所述周期性孔洞基底上；
    一漏极，所述漏极位于所述周期性孔洞基底上，且与所述源极分立于一孔洞两侧；
    一栅极，所述栅极为悬空的β-Ga 2O 3纳米带，连接所述源极和漏极。
  2. 根据权利要求1中所述的背栅晶体管，其特征在于，所述硅衬底为重掺杂P型硅衬底，所述介电层为厚度为110nm的SiO 2材料层。
  3. 根据权利要求1中所述的背栅晶体管，其特征在于，所述基底上的周期性孔洞以5×5的孔洞阵列排列，相邻阵列之间距离100μm，阵列中相邻孔洞之间距离为10μm。
  4. 根据权利要求3中所述的背栅晶体管，其特征在于，所述孔洞为直径5μm的圆形孔洞。
  5. 一种背栅晶体管的制备方法，其特征在于，包括如下步骤：
    提供一基底，所述基底由一硅衬底以及所述硅衬底表面的介电层组成；
    刻蚀所述基底，形成带有周期性孔洞阵列的周期性孔洞基底；
    将β-Ga 2O 3纳米带转移至所述周期性孔洞基底的一个孔洞上；
    刻蚀所述周期性孔洞基底，以形成位于β-Ga 2O 3纳米带两侧的源漏电极光刻图案；
    在所述光刻图案上沉积金属叠层，以形成晶体管的源极和漏极；
    在N 2气氛中退火。
  6. 根据权利要求5中所述的方法，其特征在于，所述周期性孔洞阵列的孔洞直径5μm，且深度可以通过改变反应离子刻蚀时间来调制；相邻的5×5圆形阵列之间距离为100μm，每个阵列中相邻圆的间距为10μm。
  7. 根据权利要求5所述的方法，其特征在于，所述β-Ga 2O 3纳米带使用3M胶带从β-Ga 2O 3单晶块体上机械剥离得到；所述β-Ga 2O 3单晶块体的有效载流 子浓度为10 17-10 19cm -3。
  8. 根据权利要求6中所述的方法，其特征在于，所述源极和漏极采用电子束蒸发的方法沉积金属叠层，所述金属叠层依次为金属Ti层、金属Al层、金属Ni层、以及金属Au层，厚度依次为20nm、100nm、40nm、以及80nm，形成温度为50℃。
  9. 根据权利要求5所述的方法，其特征在于，所述退火过程使用快速热退火设备，在N 2气氛中退火，以实现晶体管良好的欧姆接触，退火温度为470℃，退火时间为70s。
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