WO2018214119A1 - 一种石墨烯场效应晶体管及其制备方法 - Google Patents

一种石墨烯场效应晶体管及其制备方法 Download PDF

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Publication number
WO2018214119A1
WO2018214119A1 PCT/CN2017/085988 CN2017085988W WO2018214119A1 WO 2018214119 A1 WO2018214119 A1 WO 2018214119A1 CN 2017085988 W CN2017085988 W CN 2017085988W WO 2018214119 A1 WO2018214119 A1 WO 2018214119A1
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layer
graphene channel
graphene
channel layer
substrate
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PCT/CN2017/085988
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English (en)
French (fr)
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梁晨
秦旭东
张臣雄
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华为技术有限公司
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Priority to PCT/CN2017/085988 priority Critical patent/WO2018214119A1/zh
Priority to CN201780091174.5A priority patent/CN110663117B/zh
Publication of WO2018214119A1 publication Critical patent/WO2018214119A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present disclosure relates to the field of field effect transistors, and in particular, to a graphene field effect transistor and a method of fabricating the same.
  • FETs Field Effect Transistors
  • GFET field effect transistor
  • It includes a substrate 1, a graphene channel layer 2 formed on the substrate 1, and a source electrode 3 and a drain electrode 4 respectively formed at both ends of the graphene channel layer 2, which are formed on the graphene channel layer 2
  • Contact of the substrate 1 (especially a silicon oxide substrate) with the graphene channel layer 2 causes scattering of carriers, resulting in a decrease in carrier mobility of graphene. Therefore, how to prepare graphene field effect transistors in order to exert the excellent electrical properties of graphene is a key issue of current research and development personnel.
  • the prior art provides a graphene field effect transistor and a preparation method thereof, and the structure thereof is as shown in FIG. 2, which is prepared by first forming a graphene channel layer 2 on a substrate 1 in a graphene channel.
  • the source electrode 3 and the drain electrode 4 are formed at both ends of the layer 2; then the portion of the substrate 1 is removed by wet etching to form the cavity 7, thereby obtaining a suspended graphene channel layer structure; finally, depositing on the graphene channel layer 2
  • the gate dielectric layer 5 and the gate electrode 6 obtain a graphene field effect transistor.
  • the suspended graphene channel layer structure Since the suspended graphene channel layer structure is liable to collapse or deform at the cavity, it causes failure or performance degradation of the field effect transistor.
  • a technical problem to be solved by embodiments of the present disclosure is to provide a graphene field effect transistor capable of preventing collapse or deformation of a graphene channel layer and a method of fabricating the same.
  • the specific technical solutions are as follows:
  • a graphene field effect transistor comprising: a substrate, a graphene channel layer formed on the substrate, and a source respectively located on both ends of the graphene channel layer An electrode and a drain electrode, a gate dielectric layer and a gate electrode on the graphene channel layer between the source electrode and the drain electrode;
  • the substrate has a support composed of two or more recesses and one or more bosses, at least one of the bosses of the support being in contact with the graphene channel layer.
  • the graphene channel layer is physically supported by the support on the substrate, ie at least one protrusion on the support supports the graphene channel layer between the source electrode and the drain electrode, avoiding the graphene channel layer In the case of unsupported dangling Collapse or deformation that occurs due to gravity or the like.
  • the transistor provided by the present disclosure reduces the contact area between the substrate and the graphene channel layer and reduces the lining in the case where the substrate is completely covered on the substrate with a large area contact therebetween.
  • the effect of the bottom on the graphene channel layer increases the carrier mobility.
  • more than two of said depressions are elongated.
  • two or more of the depressed portions are rectangular, and two or more of the depressed portions have a longitudinal direction parallel to each other.
  • the length of the depressed portion means the length of the longest side of the rectangular depressed portion.
  • more than one raised portion is rectangular, and the depressed portion and the raised portion form a uniform support for the graphene channel layer in a regular shape.
  • the widths of the two or more recesses are equal such that the support force distribution of the at least one raised portion on the support member to the graphene channel layer is uniform.
  • the "width of the depressed portion” means the vertical distance from one side wall of the depressed portion to the other side wall, as shown in FIG.
  • the supporting force of the convex portion should act in the middle of the graphene channel layer, where the middle finger is from the position to the source electrode and the drain electrode. The distance between them is equal.
  • the distance between each raised portions should be equal.
  • the ratio of the width of two or more of the depressed portions to the depth of the depressed portion is 1:1-2.
  • the depth of the depressed portion means a vertical distance from the bottom of the depressed portion to the opening of the depressed portion, as shown in FIG. 4 as D.
  • the recess has a width of 30-60 nm and the recess has a depth of 30-120 nm.
  • the width of the depressed portion may also be 40-50 nm, and the depth of the depressed portion may also be 40-110 nm, 50-100 nm, 60-90 nm, 70-80 nm.
  • the direction of the graphene channel layer is perpendicular to the length direction of the recess to form a mid-section lateral support.
  • the direction of the graphene channel layer described herein refers to the direction from the source electrode to the drain electrode at one end of the graphene channel layer.
  • the direction of the graphene channel layer is the same as the length direction of the recess to form a support from the start end to the end end of the graphene channel layer, that is, from the source electrode end to the drain electrode end. Longitudinal support.
  • the substrate is a silicon-based substrate, a sapphire substrate, or a quartz substrate to form a substrate of a graphene field effect transistor, the silicon-based substrate including a silicon oxide layer and a silicon layer.
  • the silicon oxide layer has a thickness of 250-350 nm to satisfy the formation of depressed portions and protrusions on the silicon oxide layer having a sufficient thickness, and the thickness of the silicon oxide layer may also be the remaining possible range or value, for example, 260-340 nm. 270-330 nm, 280-320 nm, 290-310 nm, 300 nm.
  • the gate dielectric layer is a composite gate dielectric layer of a ruthenium oxide layer on the graphene channel layer and a ruthenium dioxide layer on the ruthenium oxide layer, or An aluminum oxide layer on the graphene channel layer to form an insulating layer to isolate the gate electrode from the graphene channel layer.
  • the yttrium oxide layer is used as the first layer in the composite gate dielectric layer in direct contact with the graphene channel layer to form a uniform dielectric layer on the graphene lacking dangling bonds;
  • the ruthenium dioxide layer acts as a second layer of the composite gate dielectric layer overlying the first layer to provide good coverage.
  • the gate dielectric layer also covers the top and sides of the source and drain electrodes to form isolation of the gate electrode from the graphene channel layer, the source electrode, and the drain electrode, respectively.
  • the composite gate dielectric layer comprises a yttria layer having a thickness of 1-10 nm and a ruthenium dioxide layer having a thickness of 5-15 nm.
  • the thickness of the ruthenium oxide layer and the ruthenium dioxide layer may also be other possible ranges or values.
  • the thickness of the ruthenium oxide layer may also be 2-9 nm, 3-8 nm, 4-7 nm, 5-6 nm, ruthenium dioxide.
  • the thickness of the layer can also be 6-14 nm. 7-13 nm, 8-12 nm, 9-11 nm, 10 nm.
  • the aluminum oxide layer has a thickness of 15-30 nm, optionally 20 nm.
  • the gate electrode is a composite metal layer comprising a titanium layer and a gold layer, and the thickness ratio of the titanium layer to the gold layer in the composite metal layer is 1:5-20.
  • a metal having a relatively high melting point can be selected, and the metal can withstand high temperature on the basis of good electrical conductivity, and the metal can be selected from at least tungsten, cobalt, nickel, molybdenum, titanium, and gold.
  • the material of the gate electrode may also be selected from metal nitrides, metal nitrides, and the like, such as tungsten nitride, titanium nitride, tantalum nitride, molybdenum nitride, tungsten oxynitride, molybdenum oxynitride, and the like.
  • the source electrode and the drain electrode are both a composite metal layer comprising a titanium layer, a palladium layer, a gold layer, or a composite metal layer comprising a titanium layer and a gold layer.
  • a metal having a higher melting point can be selected, and at least one selected from the group consisting of tungsten, cobalt, nickel, molybdenum, titanium, and gold can be selected.
  • the thickness ratio of the titanium layer, the palladium layer, and the gold layer in the composite metal layer including the titanium layer, the palladium layer, and the gold layer is 1: (30-70): (80-120), Optional 1:50:100.
  • the thickness ratio of the titanium layer to the gold layer in the composite metal layer comprising the titanium layer and the gold layer is 1:5-10.
  • the source electrode and the drain electrode have a thickness of 100-200 nm
  • the gate dielectric layer has a thickness of 5-50 nm
  • the gate electrode has a thickness of 5-50 nm.
  • the thickness of the source electrode and the drain electrode is formed to be large to form a stepped structure.
  • a method of fabricating a graphene field effect transistor comprising:
  • a gate electrode is formed on the gate dielectric layer.
  • a support member composed of two or more depressed portions and one or more convex portions is first formed on the substrate, and a graphene channel layer is formed on the support member, and a graphene channel is formed in this order.
  • the layer does not contaminate the graphene channel layer.
  • the collapse or deformation of the graphene channel layer due to gravity or the like in the unsupported floating state is avoided.
  • the support is obtained by a combination of coherent diffractive lithography and dry etching, or a combination of coherent diffractive lithography and wet etching. That is, the dry etching method is applied on the basis of the coherent diffraction lithography method, or the wet etching method is applied on the basis of the dry diffraction lithography method to obtain the depressed portion and the convex portion of the support member.
  • the coherent diffractive lithography method comprises: forming light and dark rays by two coherent lights having an angle range of 10-60° and a wavelength range of 140-200 nm, and using the bright and dark rays to the lining The bottom is lithographically obtained to obtain the recess of the support.
  • the forming a graphene channel layer on the support comprises: obtaining graphene by chemical vapor deposition, micro-mechanical stripping, or epitaxy, and transferring the graphene through the transfer The method transfers to the support to form a graphene channel layer.
  • the source electrode and the drain electrode are formed on both ends of the graphene channel layer, including: a method of combining electron beam evaporation and lift-off, or a metal sputtering method and a stripping method Combined method in the stone
  • the source electrode and the drain electrode are formed on both ends of the urethane channel layer.
  • the source electrode and the drain electrode are connected by a graphene channel layer.
  • the forming a gate dielectric layer on the graphene channel layer between the source and the drain comprises:
  • the ruthenium layer is then oxidized to a ruthenium oxide layer by thermal oxidation;
  • a ruthenium dioxide layer is deposited on the yttrium oxide layer, the source electrode, and the drain electrode by an atomic layer deposition method to form the gate dielectric layer.
  • a uniform and stable coating layer is formed on the graphene channel layer by the ruthenium oxide layer and the ruthenium dioxide layer which are sequentially covered, thereby functioning as insulation and isolation.
  • the forming a gate dielectric layer on the graphene channel layer between the source and the drain comprises: forming the graphene channel by atomic layer deposition An aluminum oxide layer is deposited on the source electrode and the drain electrode on the layer to form the gate dielectric layer, which functions as insulation and isolation.
  • the forming a gate electrode on the gate dielectric layer includes: on an electron beam evaporation method, or a metal sputtering method on the gate dielectric layer, and at the source electrode and the The gate electrode is formed between the drain electrodes.
  • FIG. 1 is a cross-sectional view of a conventional graphene field effect transistor provided by the prior art
  • FIG. 2 is a cross-sectional view of a graphene field effect transistor provided by the prior art
  • FIG. 3 is a cross-sectional view of a graphene field effect transistor provided by an embodiment of the present disclosure
  • FIG. 4 is an enlarged view of a portion A of the graphene field effect transistor provided in FIG. 3 according to an embodiment of the present disclosure
  • FIG. 5 is a top perspective view of a graphene channel layer and a substrate provided by an embodiment of the present disclosure, wherein a direction of the graphene channel layer is perpendicular to a length direction of the recess;
  • FIG. 6 is a top perspective view of a graphene channel layer and a substrate provided by another embodiment of the present disclosure, wherein the direction of the graphene channel layer is the same as the length direction of the recess;
  • FIG. 7 is a schematic diagram of a coherent diffraction lithography method according to an embodiment of the present disclosure.
  • FIG. 8 is a scanning electron micrograph of a support member according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural view of forming a depressed portion and a raised portion on a substrate when preparing a graphene field effect transistor according to an embodiment of the present disclosure
  • FIG. 10 is a schematic structural view of forming a graphene channel layer on a depressed portion and a raised portion when preparing a graphene field effect transistor according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural view showing formation of a source electrode and a drain electrode at both ends of a graphene channel layer when preparing a graphene field effect transistor according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural view of forming a yttrium oxide layer on the structure of FIG. 11 when preparing a graphene field effect transistor according to an embodiment of the present disclosure
  • FIG. 13 is a schematic structural view of forming a ruthenium dioxide layer on the structure of FIG. 12 when preparing a graphene field effect transistor according to an embodiment of the present disclosure
  • FIG. 14 is a schematic structural view of forming a gate electrode on the structure of FIG. 13 when preparing a graphene field effect transistor according to an embodiment of the present disclosure
  • FIG. 15 is a comparison diagram of a gate electrode voltage-operating current provided by Embodiment 4 of the effect of the present disclosure:
  • FIG. 16 is a comparison diagram of a gate electrode voltage-transconductance provided by Embodiment 4 of the effect of the present disclosure.
  • a depressed portion 101, a depressed portion; 102, a raised portion; L, a length of the depressed portion; D, a depth of the depressed portion; W, a width of the depressed portion.
  • an embodiment of the present disclosure provides a graphene field effect transistor having a structure as shown in FIG. 3, the transistor including: a substrate 1, a graphene channel layer 2 formed on the substrate 1. a source electrode 3 and a drain electrode 4 respectively located on both ends of the graphene channel layer 2, and a gate dielectric on the graphene channel layer 2 between the source electrode 3 and the drain electrode 4 Layer 5 and gate electrode 6.
  • the substrate 1 has a support composed of two or more recesses 101 and one or more bosses 102, at least one of the bosses 102 of the support being in contact with the graphene channel layer 2 .
  • the depressed portion 101 starts from the surface of the substrate 1 and terminates inside the substrate 1, and the convex portions 102 are formed between the two depressed portions 101.
  • the graphene channel layer is physically supported by the support on the substrate 1, that is, at least one of the protrusions 102 on the support supports the graphene channel layer 2 between the source electrode 3 and the drain electrode 4, avoiding The graphene channel layer 2 collapses or deforms due to the action of gravity or the like without a supporting dangling.
  • the recessed portion 101 of the transistor reduces the substrate 1 and the graphene channel layer with respect to the case where the graphene channel layer 2 is completely covered on the substrate and the two are in contact with each other in a large area.
  • the contact area between 2 reduces the influence of the substrate 1 on the graphene channel layer 2 and improves the carrier mobility.
  • the graphene channel layer 2 is physically supported by the at least one protrusion 102 of the support, and the recess 101 does not support the graphene channel layer 2, a semi-suspended structure is employed to effectively support the graphene channel.
  • the contact area of the graphene channel layer 2 and the substrate 1 is reduced, thereby reducing leakage current and high frequency loss.
  • the mechanism for enhancing the carrier mobility by the two or more recesses 101 and the one or more protrusions 102 on the substrate 1 is exemplified by a silicon oxide substrate, when silicon oxide and graphene are used.
  • a silicon oxide substrate when silicon oxide and graphene are used.
  • remote interfacial phonon scattering in the silicon oxide substrate and Coulomb scattering generated by charged impurities are one of the main factors affecting the decrease of graphene carrier mobility. .
  • the reason why the carrier 1 of different materials may cause a decrease in carrier mobility caused by the graphene channel layer 2 may be different, but the present disclosure is based on the substrate 1 and the graphene channel layer.
  • two or more of the depressed portions 101 are elongated. Specifically, two or more of the depressed portions 101 are rectangular, and the length L directions of the depressed portions 101 are parallel to each other.
  • the length of the depressed portion 101 means the length of the longest side of the rectangular depressed portion 101.
  • more than one raised portion 102 is rectangular, and the depressed portion 101 and the raised portion 102 form a uniform support for the graphene channel layer 2 in a regular shape.
  • the widths of the two or more recessed portions 101 are equal.
  • the width of the recessed portion 101 refers to the vertical distance from one side wall of the recessed portion 101 to the other side wall, as shown in an enlarged view at A in FIG.
  • the vertical distance is W as shown in FIG.
  • the supporting force of the convex portion 102 to the graphene channel layer 2 is made more uniform by the recess portions 101 which are parallel to each other and have the same pitch.
  • the substrate 1 has only one boss 102
  • the supporting force of the boss 102 should act in the middle of the graphene channel layer 2, where the middle finger is from this position to the source electrode 3.
  • the distance to the drain electrode 4 is equal.
  • the distance between each raised portion 102 should be equal.
  • the ratio of the width of the two or more recessed portions 101 to the depth of the recessed portion 101 is 1:1 - 2, where the depth of the recessed portion 101 means from the bottom of the recessed portion 101 to the depressed portion.
  • the vertical distance at the opening of 101 is D as shown in FIG.
  • the recess portion 101 has a width of 30-60 nm, and the recess portion 101 has a depth of 30-120 nm.
  • the width of the depressed portion 101 may also be 40-50 nm, and the depth of the depressed portion 101 may also be 40-110 nm, 50-100 nm, 60-90 nm, 70-80 nm.
  • the ratio of the width to the depth of the depressed portion 101 on the one hand makes the structure of the depressed portion 101 more stable, and on the other hand, the depressed portion 101 which is not in contact with the graphene channel layer 2 is away from the graphene channel layer 2.
  • the number of the depressed portions 101 is one more than the number of the convex portions 102, and the specific number thereof is determined by the distance between the source electrode 3 and the drain electrode 4 and the width of the depressed portion 101, for example, the number of the depressed portions 101. It can be 20, 30, 40, 50, 60, 70, 80, 90, 100, 150, 200, 250, 300, and the like.
  • the direction of the graphene channel layer 2 is perpendicular to the length direction of the recess 101, unless otherwise defined, the graphene channel layer 2 described herein
  • the direction refers to a direction from the source electrode 3 located at one end of the graphene channel layer 2 to the drain electrode 4.
  • the length direction of the depressed portion 101 is as shown by L in FIG. 5 to form a middle portion lateral support, where the lateral direction refers to a direction perpendicular to the direction of the graphene channel layer 2, from the source at one end of the graphene channel layer 2.
  • the electrode 3 ends are segmentally supported at a predetermined distance until reaching the drain electrode 4 end at the other end of the graphene channel layer 2 to prevent collapse or deformation of the graphene channel layer 2 due to gravity or the like.
  • the direction of the graphene channel layer 2 is the same as the length direction of the depressed portion 101, where the length direction of the depressed portion 101 is as shown by L in FIG.
  • the portion 102 is cut off from the end of the source electrode 3 at one end of the graphene channel layer 2 to the end of the drain electrode 4 at the other end to prevent collapse or deformation of the graphene channel layer 2 due to gravity or the like.
  • the substrate 1 is a silicon-based substrate, a sapphire substrate, or a quartz substrate.
  • the silicon-based substrate includes a silicon oxide layer and a silicon layer, or only a silicon layer.
  • the silicon-based substrate including the silicon oxide layer and the silicon layer is a silicon-based substrate grown on the surface of the silicon layer to form a silicon-based substrate having a surface layer of a silicon oxide layer having a thickness of 250-350 nm, the oxidation
  • the thickness of the silicon layer may also be the remaining possible range or value, such as 260-340 nm, 270-330 nm, 280-320 nm, 290-310 nm, 300 nm. It is satisfied that the depressed portion 101 and the raised portion 102 are formed on the silicon oxide layer having a sufficient thickness.
  • the present disclosure does not specifically limit the material of the substrate 1, and it may be any material that can be applied to a graphene field effect transistor substrate.
  • the gate electrode 6 is isolated from the graphene channel layer 2, and the gate dielectric layer 5 is uniformly covered on the graphene channel layer 2.
  • the gate dielectric layer 5 is a composite gate dielectric layer of a ruthenium oxide layer on the graphene channel layer 2 and a ruthenium dioxide layer on the ruthenium oxide layer.
  • the yttrium oxide layer is used as the first layer in the composite gate dielectric layer in direct contact with the graphene channel 2 layer to form a uniform dielectric layer on the graphene lacking dangling bonds.
  • the term "dangling bond" refers to a chemical bond.
  • the crystal is abruptly terminated at the surface by the crystal lattice.
  • Each atom in the outermost layer of the surface will have an unpaired electron, that is, an unsaturated bond, which is a dangling bond.
  • a ruthenium oxide layer acts as a second layer of the composite gate dielectric layer overlying the first layer to provide good coverage.
  • the composite gate dielectric layer includes a ruthenium oxide layer having a thickness of 1-10 nm and a ruthenium dioxide layer having a thickness of 5-15 nm.
  • the thickness of the yttrium oxide layer may also be 2-9 nm, 3-8 nm, 4-7 nm, 5-6 nm, and the thickness of the ruthenium dioxide layer may also be 6-14 nm, 7-13 nm, 8-12 nm, 9-11 nm. , 10nm.
  • the gate dielectric layer 5 may also be an aluminum oxide layer on the graphene channel layer 2 having a thickness of 15-30 nm, optionally 20 nm.
  • the gate electrode 6 may also be separated from the graphene channel layer 2, the source electrode 3, and the drain electrode 4 by the gate dielectric layer 5, and in still another example of the present disclosure, the gate dielectric layer 5 covers the graphene channel layer 2 Above, the top and sides of the source electrode 3 and the drain electrode 4 are also covered.
  • the gate electrode 6 is isolated from the graphene channel layer 2 by a gate dielectric layer 5 overlying the graphene channel layer 2, through a gate dielectric layer 5 covering the top and sides of the source electrode 3 and the drain electrode 4
  • the gate electrode 6 is isolated from the source electrode 3 and the drain electrode 4.
  • the materials of the gate electrode 6, the source electrode 3 and the drain electrode 4 are generally selected to have a higher melting point metal, and the metal can withstand good electrical conductivity. high temperature.
  • the gate electrode 6 is a composite metal layer including a titanium layer and a gold layer, and a thickness ratio of the titanium layer to the gold layer in the composite metal layer is 1:5-20.
  • the source electrode 3 and the drain electrode 4 are each a composite metal layer including a titanium layer, a palladium layer, and a gold layer, and the thickness ratio of the titanium layer, the palladium layer, and the gold layer in the composite metal layer including the titanium layer, the palladium layer, and the gold layer is 1: (30-70): (80-120), optionally 1:50:100; the source electrode 3 and the drain electrode 4 may also be a composite metal layer including a titanium layer and a gold layer, the titanium layer The thickness ratio of the titanium layer to the gold layer in the composite metal layer of the gold layer is 1:5-10.
  • the embodiment of the present disclosure does not specifically define the materials of the gate electrode 6, the source electrode 3, and the drain electrode 4, and may be any material applicable to the three electrodes of the graphene field effect transistor, for example, as the gate electrode 6.
  • the metal may also be selected from at least one of tungsten, cobalt, nickel, molybdenum, titanium, and gold.
  • the material of the gate electrode 6 may also be selected from metal nitrides, metal nitrides, and the like, such as tungsten nitride and titanium nitride. , tantalum nitride, molybdenum nitride, tungsten oxynitride, molybdenum oxynitride, and the like.
  • the material of the source electrode 3 and the drain electrode 4 at least one selected from the group consisting of tungsten, cobalt, nickel, molybdenum, titanium, and gold may be selected.
  • the source electrode 3 and the drain electrode 4 have a thickness of 100 to 200 nm
  • the gate dielectric layer 5 has a thickness of 5 to 50 nm
  • the gate electrode 6 has a thickness of 5 to 50 nm.
  • the thickness of the gate electrode 6 is smaller than the thickness of the source electrode 3 and the drain electrode 4, it forms a step-like transition structure from the gate electrode 6 to the source electrode 3 or the drain electrode 4.
  • the graphene field effect transistor provided by the embodiment of the present disclosure works in the application principle: when the voltage applied to the gate electrode 6 is a negative voltage (Vg ⁇ 0) At the time, a certain amount of positive charge is induced in the graphene channel layer 2 to balance the electric field of the gate point 6 when the Fermi level of the graphene channel layer 2 is in the valence band (below the Dirac point), and the graphene channel
  • the conductive charge in layer 2 is a hole.
  • the Fermi level of the graphene channel layer 2 also moves upward to reach the Dirac point, and the carrier concentration in the graphene channel layer 2 The minimum is reached at this time the maximum resistance value (or minimum conductance) is reached.
  • the voltage applied to the gate electrode 6 is a positive voltage (Vg>0) and further increases, the Fermi level of the graphene channel layer 2 continues to move upward to the conduction band, and the conductive load in the graphene channel layer 2
  • the flow rate changes from a hole to an electron, and the electron concentration increases as the voltage applied to the gate electrode 6 increases, so that the resistance of the graphene channel layer 2 also decreases.
  • the graphene channel layer 2 can be converted from hole conduction to electron conduction by modulation of a voltage applied on the gate electrode 6, and the graphene channel layer 2 is connected to the source electrode 3 and the drain electrode 4, and the source electrode can be realized. The current between the 3 and the drain electrode 4 is conducted.
  • an embodiment of the present disclosure provides a method for fabricating a graphene field effect transistor, the method comprising:
  • Step 101 Acquire a substrate 1;
  • Step 102 forming two or more concave portions 101 and one or more convex portions 102 on the substrate 1 Support member
  • Step 103 forming a graphene channel layer 2 on the support
  • Step 104 forming a source electrode 3 and a drain electrode 4 on both ends of the graphene channel layer 2;
  • Step 105 forming a gate dielectric layer 5 on the graphene channel layer 2 between the source electrode 3 and the drain electrode 4;
  • Step 106 Form a gate electrode 6 on the gate dielectric layer 5.
  • a support member composed of two or more recessed portions 101 and one or more boss portions 102 is first formed on the substrate, and then a graphene channel layer 2 is formed on the support member, and graphite is formed in this order.
  • the olefin channel layer 2 does not cause contamination of the graphene channel layer 2.
  • the support of the support member to the graphene channel layer 2 the collapse or deformation of the graphene channel layer 2 due to the action of gravity or the like without the support dangling is avoided.
  • FIG. 14 show a flow chart of an exemplary preparation of a graphene field effect transistor of the present disclosure, and the preparation method of the present disclosure will be described below with reference to the structures shown in FIGS. 9 to 14.
  • the configuration of the support member involved in step 102 includes:
  • the support member is obtained by a combination of coherent diffraction lithography and dry etching, or a combination of coherent diffraction lithography and wet etching.
  • the coherent diffractive lithography comprises forming light and dark rays by two coherent lights having an angle range of 10-60° and a wavelength range of 140-200 nm, and the substrate 1 is photolithographically obtained by the bright and dark rays to obtain the support.
  • the depressed portion 101 of the piece obtains the structure shown in FIG.
  • FIG. 7 is a schematic diagram of the coherent diffraction lithography method, in which two coherent lights having a wavelength ⁇ and an angle ⁇ are incident according to the direction indicated by the arrow in FIG. Interference will occur at the intersection, forming a bright area and a dark area. These bright areas and dark areas are periodically arranged, that is, the light and dark stripes in Figure 7, forming light and dark rays.
  • the embodiment of the present disclosure adopts the coherent diffraction lithography method to avoid the influence of the flatness and surface topography of the semiconductor surface on the lithography quality in the conventional lithography, and the method can form an interference pattern on any surface, and can form a large area. Graphics.
  • a photoresist is coated on the substrate 1, and the photoresist is selectively exposed by two beams of coherent light having an angle range of 10-60° and a wavelength range of 140-200 nm, using a developer solution.
  • the photoresist is etched to remove the photoresist coated on the depressed portion 101, and the photoresist coated on the convex portion 102 is left to be formed; then the surface is dried by dry etching or wet etching.
  • the substrate 1 from which the coated photoresist has been removed is subjected to pattern etching to form the depressed portion 101; finally, the photoresist remaining on the substrate 1 is removed to form the convex portion 102.
  • etching mechanism and process are common in the field, for example, see Lu Jingjun's "Nano-grating phase mask coherent photolithography method and process research".
  • the microstructure of the obtained support member can be obtained by scanning electron microscopy, and as shown in FIG. 8, clear recesses and protrusions can be seen.
  • the formation of the support member is formed on the surface of the substrate 1 to extend inside the substrate 1, that is, the recess portion 101 starts from the surface of the substrate 1 and ends at the inside of the substrate 1.
  • the ratio of the width of the depressed portion 101 to the depth of the depressed portion 101 described above can be achieved by changing the exposure dose and the thickness of the adhesive layer, or by adjusting the deposition angle of the shadow deposition layer used as an etching mask.
  • the person in the field can refer to the above mentioned documents.
  • Step 103 relates to forming a graphene channel layer 2 on the support, comprising:
  • the graphene is obtained by a chemical vapor deposition method, a micro mechanical lift-off method, or an epitaxial method, and the graphene is transferred to the support by a transfer method to form a graphene channel layer 2.
  • the length direction of the depressed portion 101 of the support member and the graphene groove The direction of the track layer 2 is vertical or the same, which is achieved by the formation of the graphene channel layer 2, and the structure as shown in FIG. 10 is obtained.
  • the growth of graphene by chemical vapor deposition is to use hydrocarbons to be cracked into carbon atoms and hydrogen atoms in a high temperature environment, and carbon atoms are deposited on the surface of the metal to form a graphene film.
  • the metal may be nickel, copper, rhodium, platinum or the like.
  • the micromechanical stripping method is a method in which a graphene film having a weak interatomic force is delaminated by a physical method to obtain a graphene film.
  • the epitaxial method refers to sublimation of silicon atoms by high temperature heating on silicon carbide, and formation of a graphitized surface layer in a silicon layer or a carbon layer, which is a graphene film.
  • the graphene film is transferred to the substrate 1 by a transfer method to form a graphene channel layer 2, and the graphene film on the copper obtained by chemical vapor deposition is transferred as an example.
  • the transfer process may be a spin coating of a layer of polymethyl methacrylate (PMMA) on a graphene layer having a graphene layer on copper, and placing the film in a ferric chloride or ferric nitrate solution to form copper. Corrosion clean, then clean the graphene film supported by polymethyl methacrylate (PMMA) with deionized water, then transfer the graphene film to the corresponding substrate (such as substrate 1), and finally remove the graphite with acetone.
  • PMMA polymethyl methacrylate
  • the graphene film obtained by the above three methods may be a single layer graphene, a double layer graphene and a multilayer graphene, and the above three methods for obtaining a graphene film and graphene film transfer
  • the method of the present disclosure is not described in detail herein, and the method for forming the graphene channel layer 2 is not specifically limited, and may be any feasible method in the prior art.
  • Step 104 involves forming source electrode 3 and drain electrode 4 on both ends of graphene channel layer 2, including: a method of combining electron beam evaporation method and stripping method, or a combination of metal sputtering method and stripping method.
  • the source electrode 3 and the drain electrode 4 are formed on both ends of the graphene channel layer 2, and a structure as shown in FIG. 11 is obtained.
  • the electron beam evaporation method refers to directly heating and evaporating the metal material, and vaporizing the metal material to form a film on the substrate.
  • Metal sputtering processes the surface of a metal solid by a certain energy particle (ion or atom, molecule), so that the atom or molecule near the surface of the metal solid obtains sufficient energy to finally escape the solid surface.
  • Lift-off means that in order to obtain a desired structure of the source electrode 3 and the drain electrode 4, unnecessary metal is peeled off from the substrate.
  • the methods for forming the source electrode 3 and the drain electrode 4 in the present disclosure are all prior art, and the embodiments of the present disclosure are not described in detail herein, nor are they limited to the above methods.
  • the graphene channel layer 2 utilizes the migration of carriers so that current can flow from the source electrode 3 to the drain electrode 4 or from the drain electrode 4 to the source electrode 3, so the source electrode 3 of the drain electrode 4 should be formed. Partially overlying both ends of the graphene channel layer 2, such as that shown in FIG. 11, to connect the source electrode 3 and the drain electrode 4 through the graphene channel layer 2.
  • the gate dielectric layer 5 is formed on the graphene channel layer 2 between the source electrode 3 and the drain electrode 4 in step 105, including:
  • a germanium layer is obtained by electron beam evaporation on the graphene channel layer 2, the source electrode 3, and the drain electrode 4.
  • the ruthenium layer is then oxidized to a ruthenium oxide layer by thermal oxidation, that is, the ruthenium layer is heated in an oxygen-containing atmosphere to obtain a structure as shown in FIG.
  • cerium oxide is deposited on the yttrium oxide layer, the source electrode 3, and the drain electrode 4 by a method of atomic layer deposition (a method of plating a substance layer by layer on a surface of a substrate in the form of a monoatomic film).
  • the gate dielectric layer 5 is formed to obtain a structure as shown in FIG.
  • the gate dielectric layer 5 is formed by the above-mentioned preparation process, and the yttrium oxide layer is used as the composite gate dielectric layer and the graphene channel layer 2
  • the first layer is in direct contact to form a uniform dielectric layer on the graphene lacking dangling bonds.
  • the ruthenium dioxide layer is used as the second layer of the composite gate dielectric layer overlying the first layer to form good coverage, and the gate electrode 6 is formed separately from the graphene channel layer 2, the source electrode 3, and the drain electrode
  • the pole 4 is isolated to prevent leakage.
  • the formation of the gate dielectric layer 5 may also deposit an aluminum oxide layer on the graphene channel layer 2, the source electrode 3, and the drain electrode 4 by a method of atomic layer deposition, Thereby, the gate electrode is isolated from the graphene channel layer 2, the source electrode 3, and the drain electrode 4 to prevent occurrence of electric leakage.
  • the gate electrode 6 is formed on the gate dielectric layer 5 and between the source electrode 3 and the drain electrode 4 by electron beam evaporation or metal sputtering to obtain The structure shown in FIG.
  • the “deposited ruthenium dioxide layer” or the “deposited aluminum oxide layer” covers the top and sides of the source electrode 3 and the drain electrode 4, that is, at the source.
  • a tantalum dioxide layer or an aluminum oxide layer is formed on the entirety of the top and both sides of the electrode 3 and the drain electrode 4.
  • the gate electrode 6 when the gate electrode 6 is formed, the gate electrode 6 can be formed directly at the recess between the source electrode 3 and the drain electrode 4, and the gate electrode 6 is passed through the gate dielectric layer 5 covering the sides of the source electrode 3 and the drain electrode 4 Isolating from the source electrode 3 and the drain electrode 4, so that the width of the gate electrode 6 may be equal to or substantially equal to the width of the recess between the source electrode 3 and the drain electrode 4, as compared with the case shown in FIG. 1 in the prior art.
  • the width of the gate electrode 6 employed in the present disclosure is increased, and when a voltage is applied to the gate electrode 6, since the contact area of the gate electrode 6 with the graphene channel layer 2 is increased, in the case of having an increased contact area, The carrier in the graphene channel layer 2 can be more strongly controlled, thereby enhancing the control ability of the gate electrode, that is, the transconductance is increased.
  • This embodiment provides a method for preparing a graphene field effect transistor, which is specifically as follows.
  • a silicon oxide layer having a thickness of 300 nm is formed on the silicon surface by thermal oxidation on a silicon substrate to form a silicon-silicon oxide composite substrate.
  • a support member composed of two or more recessed portions 101 and one or more bosses 102 is formed on the substrate 1:
  • a positive photoresist on the silicon oxide layer of the substrate 1 (such as the photosensitive material shown in Chemical Formula 5 shown in CN101256358A, the synthesis method is as shown in the preparation example in CN101256358A), and the angle is 35°.
  • two beams of coherent light having a wavelength of 193 nm selectively expose the photoresist, and an alkaline developer is used to irradiate the photoresist portion corresponding to the bright portion of the interference light of the two coherent lights (the photoresist portion is to be used) Removing the recessed portion 101), retaining a photoresist portion corresponding to a dark portion of the interference light of the two coherent light (the photoresist portion is to be used to form the convex portion 102);
  • the substrate 1 was immersed in a buffered oxide etching solution (Buffered Oxide Etch, BOE) for 15 seconds to form a depressed portion 101 in which the buffered oxide etching solution was passed through a hydrogen fluoride solution having a mass fraction of 49% and A NH4F ammonium fluoride solution having a mass fraction of 40% is obtained by mixing in a volume ratio of 1:6;
  • a buffered oxide etching solution Buffered Oxide Etch, BOE
  • the photoresist remaining on the substrate 1 is removed with acetone to form the convex portion 102.
  • the recessed portion 101 had a width of 50 nm and a depth of 50 nm.
  • graphene is grown on copper by chemical vapor deposition to obtain a film having a graphene layer on copper.
  • the specific growth conditions are: in a chemical vapor deposition tube furnace, under argon protection, the temperature is raised to 1000 ° C, and then respectively introduced at a flow rate of 1000 sccm (Standard Cubic Centimeter per Minute), 40 sccm and 1 sccm. Argon, hydrogen and methane were grown for 30 min.
  • a layer of polymethyl methacrylate (PMMA) resin was spin-coated on the graphene layer of the above film having a graphene layer on copper, and the film was placed in a ferric chloride solution for 4 hours to completely dissolve the copper. Then, the opposite side of the graphene layer of the film is washed with deionized water, and then the film is transferred onto the substrate 1, the graphene layer of the film is placed against the substrate 1, and then the polymethyl group is removed with acetone.
  • Methyl methacrylate (PMMA) A composite structure of the graphene channel layer 2 having a channel length of 50 ⁇ m and the substrate 1 was obtained, and the longitudinal direction of the graphene channel layer 2 was made the same as the length direction of the depressed portion 101 at the time of transfer.
  • an electron beam evaporation coating machine is used to sequentially deposit a titanium layer having a thickness of 1 nm, a palladium layer having a thickness of 50 nm, and a gold layer having a thickness of 100 nm on the entire surface of the sample obtained in the above step, thereby forming a three-layer composite metal.
  • a titanium layer having a thickness of 1 nm, a palladium layer having a thickness of 50 nm, and a gold layer having a thickness of 100 nm on the entire surface of the sample obtained in the above step, thereby forming a three-layer composite metal.
  • the remaining photoresist is removed by using acetone to remove the photoresist located above the graphene channel layer 2 and the three-layer composite metal layer above the portion of the photoresist, thereby removing the graphene channel layer 2
  • the source electrode 3 and the drain electrode 4 are formed at both ends, respectively.
  • an erbium layer having a thickness of 2 nm is deposited on the graphene channel layer 2, the source electrode 3, and the drain electrode 4 by using an electron beam evaporation coating apparatus;
  • the ruthenium layer having a thickness of 2 nm is oxidized in an air atmosphere at a temperature of 120 ° C for 5 minutes to obtain a ruthenium oxide layer having a thickness of 4 nm;
  • a layer of germanium oxide having a thickness of 10 nm is deposited on the yttrium oxide layer, the source electrode 3 and the drain electrode 4 by an atomic layer deposition system to form a gate dielectric layer 5.
  • the ruthenium dioxide layer is also formed on both sides of the source electrode 3 and the drain electrode 4 as a whole. . As can be seen from Figure 13, the ruthenium dioxide layer already covers the entire upper surface of the substrate.
  • a gate electrode 6 is formed on the gate dielectric layer 5.
  • An electron beam evaporation coating device is used to deposit a titanium layer having a thickness of 1 nm between the source electrode 3 and the drain electrode 4 on the gate dielectric layer 5, and a gold layer having a thickness of 20 nm is deposited on the titanium layer to form two layers.
  • a composite metal layer which is the gate electrode 6.
  • the difference between the present embodiment and the graphene field effect transistor provided in the first embodiment is that the longitudinal direction of the graphene channel layer 2 is perpendicular to the longitudinal direction of the depressed portion 101 when the graphene film is transferred onto the support.
  • This embodiment provides a method for preparing a graphene field effect transistor, which is specifically as follows:
  • a quartz substrate was taken as the substrate 1.
  • a support member composed of two or more recessed portions 101 and one or more bosses 102 is formed on the substrate 1:
  • a positive photoresist on the silicon oxide layer of the substrate 1 (such as the photosensitive material shown in Chemical Formula 5 shown in CN101256358A, the synthesis method is as shown in the preparation example in CN101256358A), and adopting an angle of 31°.
  • a two-coherent light having a wavelength of 154 nm selectively exposing the photoresist, and using a basic portion of the photoresist corresponding to the bright portion of the interference light of the two coherent light (the photoresist portion is to be used for formation)
  • the recessed portion 101) is removed, and the photoresist portion corresponding to the dark portion of the interference light of the two coherent light is retained (the photoresist portion is to be used to form the convex portion 102);
  • the substrate 1 was immersed in a buffered oxide etching solution (Buffered Oxide Etch, BOE) for 18 seconds to form a depressed portion 101 in which a buffered oxide etching solution was passed through a hydrogen fluoride solution having a mass fraction of 49% and A NH4F ammonium fluoride solution having a mass fraction of 40% is obtained by mixing in a volume ratio of 1:6;
  • a buffered oxide etching solution Buffered Oxide Etch, BOE
  • the photoresist remaining on the substrate 1 is removed with acetone to form the convex portion 102.
  • the recessed portion 101 had a width of 40 nm and a depth of 60 nm.
  • the thin layered graphene is peeled off by micro mechanical peeling, and the thin layered graphene is directly transferred onto the substrate 1.
  • a composite structure of the graphene channel layer 2 having a channel length of 20 ⁇ m and the substrate 1 was obtained.
  • an electron beam evaporation coating machine is used to sequentially deposit a titanium layer having a thickness of 15 nm and a gold layer having a thickness of 100 nm on the entire surface of the sample obtained in the above step, thereby forming a two-layer composite metal layer;
  • the remaining photoresist is removed by using acetone to remove the photoresist located above the graphene channel layer 2 and the two composite metal layers above the portion of the photoresist, thereby removing the graphene channel layer 2
  • the source electrode 3 and the drain electrode 4 are formed at both ends, respectively.
  • a gate dielectric layer 5 is formed by depositing an aluminum oxide layer having a thickness of 20 nm on the graphene channel layer 2, the source electrode 3, and the drain electrode 4 by an atomic layer deposition system.
  • the aluminum oxide layer in this step forms an aluminum oxide layer on the entirety of the top and both sides of the source electrode 3 and the drain electrode 4, and the aluminum oxide layer covers the graphene channel layer 2, the source electrode 3, and the drain electrode 4. The entire upper surface.
  • a gate electrode 6 is formed on the gate dielectric layer 5.
  • a metal sputter coater is used on the gate dielectric layer 5, and a thickness of 15 nm is deposited between the source electrode 3 and the drain electrode 4.
  • a titanium layer is further deposited on the titanium layer to form a two-layer composite metal, which is the gate electrode 6.
  • the graphene field effect transistor obtained by the preparation method of Example 1 and the graphene field effect transistor of Comparative Example 1 were subjected to electrical property simulation using a Comsol device simulation tool.
  • Comparative Example 1 The specific structure of Comparative Example 1 is as shown in FIG. 1 , which includes a silicon-silicon oxide composite substrate 1 and a graphene channel layer 2 formed on the silicon oxide substrate 1 respectively formed on a graphene channel layer.
  • the specific parameters are: the channel length of the graphene channel layer 2 is 10 ⁇ m, the source electrode 3 is a titanium metal layer having a thickness of 15 nm and 100 nm, a composite metal layer of a gold layer, the material composition of the drain electrode 4, and the metal thickness and source.
  • the material composition of the electrode 3 and the metal thickness are the same, the gate dielectric layer 5 is an aluminum oxide layer having a thickness of 30 nm, and the material composition of the gate electrode layer 6 is the same as that of the source electrode 3.
  • FIG. 15 is a comparison diagram of a gate electrode voltage-operating current according to Embodiment 4 of the present disclosure.
  • the working current of the graphene field effect transistor prepared by the embodiment 1 is larger than that of the comparative example 1.
  • the operating current refers to a current after conduction between the source electrode and the drain electrode.
  • FIG. 16 is a comparison diagram of a gate electrode voltage-transconductance provided by Embodiment 4 of the present disclosure. As can be seen from FIG. 16, the transconductance ratio of the graphene field effect transistor prepared by the embodiment 1 is large, which is It shows that the control performance of the gate electrode voltage on the operating current is enhanced.
  • the graphene field effect transistor obtained by the preparation method in the embodiment 2 and the comparative example 1 in the effect example 4 were respectively subjected to electrical characteristic simulation using a Comsol device simulation tool.
  • the electrical properties of the device of the graphene field effect transistor prepared by the method of Example 2 are better than that of the comparative example 1, that is, the device operating current of the graphene field effect transistor prepared by the example 2 is in the comparative example 1
  • the device operating current of the graphene field effect transistor is large, and the transconductance of the graphene field effect transistor prepared by the second embodiment is larger than that of the graphene field effect transistor in the comparative example 1.
  • the graphene field effect transistors obtained by the method of the embodiment 1 and the method of the second embodiment were respectively subjected to electrical characteristics simulation using a Comsol device simulation tool.
  • the electrical properties of the device of the graphene field effect transistor prepared by the embodiment 1 are better than those of the embodiment 2, that is, the device operating current ratio of the graphene field effect transistor prepared by the embodiment 1 is the same as that of the embodiment 2
  • the device operating current of the prepared graphene field effect transistor was large, and the transconductance of the graphene field effect transistor prepared by the example 1 was larger than that of the graphene field effect transistor prepared by the example 2.

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Abstract

提供了一种石墨烯场效应晶体管及其制备方法，属于场效应晶体管领域。晶体管包括：衬底（1）、形成于衬底栅的石墨烯沟道层（2）、分别位于石墨烯沟道层（2）的两端上的源电极（3）和漏电极（4）、位于源电极（3）和漏电极（4）之间的石墨烯沟道层（2）上的栅介质层（5）和栅电极（6）；衬底（1）具有由两个以上的凹陷部（101）和一个以上的凸起部（102）构成的支撑件，支撑件的至少一个凸起部（102）与石墨烯沟道层（2）接触。通过衬底（1）上的支撑件对石墨烯沟道层（2）形成物理支撑，避免了石墨烯沟道层（2）在无支撑悬空的情况下由于重力等作用而出现的塌陷或者变形，并且减少了衬底（1）与石墨烯沟道层（2）之间的接触面积，减少了衬底（1）对石墨烯沟道层（2）的影响，提升载流子迁移率。

Description

一种石墨烯场效应晶体管及其制备方法 技术领域
本公开涉及场效应晶体管领域，特别涉及一种石墨烯场效应晶体管及其制备方法。
背景技术
场效应晶体管(Field Effect Transistors，FET)指由多数载流子参与导电，通过电压控制的半导体器件，其中载流子指承载电荷的、能够自由移动以形成电流的物质粒子(例如电子和空穴)。石墨烯作为新型的半导体材料具有远远高于普通半导体材料(如硅、砷化镓)的载流子迁移率，已被应用于场效应晶体管中，制备形成石墨烯场效应晶体管(Graphene Fie1d Effect Transistor，GFET)，其中石墨烯用于形成石墨烯场效应晶体管的沟道。如图1所示，图1示出了一种常规石墨烯场效应晶体管的剖面图。其包括衬底1、形成在所述衬底1上的石墨烯沟道层2、分别形成在石墨烯沟道层2的两端的源电极3和漏电极4、形成于石墨烯沟道层2上的栅介质层5以及栅电极6。由于衬底1(尤其是氧化硅衬底)与石墨烯沟道层2接触会导致载流子的散射，造成石墨烯的载流子迁移率的降低。因此如何制备石墨烯场效应晶体管才能发挥石墨烯的优良电学特性是目前研发人员关注的重点问题。
目前的现有技术提供了一种石墨烯场效应晶体管及其制备方法，其结构如图2所示，其制备方法为首先在衬底1上形成石墨烯沟道层2，在石墨烯沟道层2两端形成源电极3和漏电极4；随后使用湿法腐蚀去除部分衬底1形成空腔7，从而获得悬空的石墨烯沟道层结构；最后，在石墨烯沟道层2上沉积栅介质层5和栅电极6得到石墨烯场效应晶体管。
在实现本公开的过程中，发明人发现现有技术至少存在以下问题：
由于悬空的石墨烯沟道层结构容易在空腔处出现塌陷或变形，从而引起场效应晶体管的失效或者性能降低。
公开内容
本公开实施例所要解决的技术问题在于，提供了一种能够防止石墨烯沟道层塌陷或者变形的石墨烯场效应晶体管及其制备方法。具体技术方案如下：
一方面，提供了一种石墨烯场效应晶体管，所述晶体管包括：衬底、形成于所述衬底上的石墨烯沟道层、分别位于所述石墨烯沟道层的两端上的源电极和漏电极、位于所述源电极和所述漏电极之间的所述石墨烯沟道层上的栅介质层和栅电极；
所述衬底具有由两个以上的凹陷部和一个以上的凸起部构成的支撑件，所述支撑件的至少一个所述凸起部与所述石墨烯沟道层接触。
通过衬底上的支撑件对石墨烯沟道层形成物理支撑，即支撑件上的至少一个凸起部支撑位于源电极和漏电极之间的石墨烯沟道层，避免了石墨烯沟道层在无支撑悬空的情况下由于 重力等作用而出现的塌陷或者变形。
并且，本公开提供的晶体管相对于完全将衬底覆盖于衬底上，两者大面积接触的情况而言，凹陷部减少了衬底与石墨烯沟道层之间的接触面积，减少了衬底对石墨烯沟道层的影响，提升载流子迁移率。
在一个可能的设计中，两个以上的所述凹陷部为长条形。
在一个可能的设计中，两个以上的所述凹陷部为长方形，两个以上的所述凹陷部的长度方向互相平行。此处，凹陷部的长度是指，长方形凹陷部的最长边的长度。那么相应地，一个以上的凸起部为长方形，凹陷部和凸起部以规则的形状形成对石墨烯沟道层的均匀支撑。
在一个可能的设计中，两个以上的所述凹陷部的宽度相等，以使支撑件上的至少一个凸起部对石墨烯沟道层的支撑力分布均匀。此处“凹陷部的宽度”是指从凹陷部的一个侧壁至另一个侧壁的垂直距离，如图4中所示为W。例如，当所述衬底上只具有一个凸起部时，凸起部的支撑力应作用于石墨烯沟道层的中间，此处的中间指从该位置处到源电极和到漏电极之间的距离相等。当所述衬底上具有两个以上的凸起部时，每个凸起部之间的距离应相等。
在一个可能的设计中，两个以上的所述凹陷部的宽度与所述凹陷部的深度的比值为1:1-2。此处，凹陷部的深度是指，从凹陷部的底部至凹陷部的开口处的垂直距离，如图4中所示为D。
在一个可能的设计中，所述凹陷部的宽度为30-60nm，所述凹陷部的深度为30-120nm。所述凹陷部的宽度的范围还可以为40-50nm，所述凹陷部的深度的范围还可以为40-110nm,50-100nm，60-90nm，70-80nm。
在一个可能的设计中，所述石墨烯沟道层的方向与所述凹陷部的长度方向垂直，以形成中段横向支撑。除另有定义之外，本文所述的石墨烯沟道层的方向指从位于石墨烯沟道层上一端的源电极到漏电极的方向。
在一个可能的设计中，所述石墨烯沟道层的方向与所述凹陷部的长度方向相同，以形成从石墨烯沟道层起始端至末尾端的支撑，即形成从源电极端到漏电极端的纵向支撑。
在一个可能的设计中，所述衬底为硅基衬底、蓝宝石衬底、或者石英衬底，以形成石墨烯场效应晶体管的基底，所述硅基衬底包括氧化硅层和硅层。所述氧化硅层厚度为250-350nm，以满足在足够厚度的氧化硅层上形成凹陷部和凸起部，该氧化硅层厚度还可以为其余可能的范围或取值，例如260-340nm，270-330nm，280-320nm，290-310nm，300nm。
在一个可能的设计中，所述栅介质层为位于所述石墨烯沟道层上的氧化钇层与位于所述氧化钇层上的二氧化铪层的复合栅介质层，或者为位于所述石墨烯沟道层上的氧化铝层，以形成绝缘层，将栅电极与石墨烯沟道层隔离。并且在上述复合栅介质层的设计中，将氧化钇层作为复合栅介质层中与石墨烯沟道层直接接触的第一层，以在缺乏悬挂键的石墨烯上形成均匀的介质层；将二氧化铪层作为覆盖在所述第一层上的复合栅介质层的第二层，以形成良好的覆盖性。
在一个可能的设计中，所述栅介质层还覆盖于所述源电极和所述漏电极的顶部和侧面，以形成将栅电极分别与石墨烯沟道层、源电极和漏电极隔离。
在一个可能的设计中，所述复合栅介质层包括厚度为1-10nm的氧化钇层与厚度为5-15nm的二氧化铪层。该氧化钇层和二氧化铪层的厚度还可以为其余可能的范围或取值，例如氧化钇层的厚度还可以为2-9nm，3-8nm，4-7nm，5-6nm，二氧化铪层的厚度还可以为6-14nm， 7-13nm，8-12nm，9-11nm,10nm。
在一个可能的设计中，所述氧化铝层的厚度为15-30nm，可选为20nm。
在一个可能的设计中，所述栅电极为包含钛层和金层的复合金属层，所述复合金属层中的钛层和金层的厚度比为1:5-20。作为栅电极的材料通常可选择熔点较高的金属，该类金属在具备良好的导电性能的基础上，能够耐受高温，金属可以选自钨、钴、镍、钼、钛、金中的至少一种。另外栅电极的材料还可以选自金属氮化物、金属氮硅化物等，例如氮化钨、氮化钛、氮化钽、氮化钼、氮硅化钨、氮硅化钼等。
在一个可能的设计中，所述源电极和所述漏电极均为包含钛层、钯层、金层的复合金属层，或者均为包含钛层和金层的复合金属层。作为源电极和漏电极的材料同样可选择熔点较高的金属，可以选自钨、钴、镍、钼、钛、金中的至少一种。
在一个可能的设计中，所述包含钛层、钯层、金层的复合金属层中的钛层、钯层、金层的厚度比为1:(30-70):(80-120)，可选为1:50:100。
在一个可能的设计中，所述包含钛层和金层的复合金属层中钛层和金层的厚度比为1:5-10。
在一个可能的设计中，所述源电极和所述漏电极的厚度为100-200nm，所述栅介质层的厚度为5-50nm，所述栅电极的厚度为5-50nm。以形成源电极和漏电极的厚度较大，形成台阶结构。
另一方面，提供了一种石墨烯场效应晶体管的制备方法，所述方法包括：
获取衬底；
在所述衬底上形成由两个以上的凹陷部和一个以上的凸起部构成的支撑件；
在所述支撑件上形成石墨烯沟道层；
在所述石墨烯沟道层的两端上形成源电极和漏电极；
在所述源电极和所述漏电极之间的所述石墨烯沟道层上形成栅介质层；
在所述栅介质层上形成栅电极。
通过上述制备方法，先在衬底上形成由两个以上的凹陷部和一个以上的凸起部构成的支撑件，再在支撑件上形成石墨烯沟道层，以该顺序形成石墨烯沟道层不会对石墨烯沟道层造成污染。并且通过支撑件对石墨烯沟道层的支撑作用，避免了石墨烯沟道层在无支撑悬空的情况下由于重力等作用而出现的塌陷或者变形。
在一个可能的设计中，通过相干衍射光刻法和干法刻蚀法相结合、或者相干衍射光刻法和湿法腐蚀法相结合的方法获取所述支撑件。即在相干衍射光刻法的基础上再运用干法刻蚀法，或者在干衍射光刻法的基础上再运用湿法腐蚀法，以获取支撑件的凹陷部和凸起部。
在一个可能的设计中，所述相干衍射光刻法包括：通过夹角范围为10-60°，波长范围为140-200nm的两束相干光形成明暗光线，利用所述明暗光线对所述衬底进行光刻获取所述支撑件的所述凹陷部。
在一个可能的设计中，所述在所述支撑件上形成石墨烯沟道层，包括：通过化学气相沉积法、微机械剥离法、或外延法获取石墨烯，将所述石墨烯通过转移的方法转移到所述支撑件上形成石墨烯沟道层。
在一个可能的设计中，所述在所述石墨烯沟道层的两端上形成源电极和漏电极，包括：通过电子束蒸发法和剥离法相结合的方法,或者金属溅射法和剥离法相结合的方法在所述石 墨烯沟道层的两端上形成所述源电极和所述漏电极。使得源电极和漏电极通过石墨烯沟道层进行连接。
在一个可能的设计中，所述在所述源极和所述漏极之间的所述石墨烯沟道层上形成栅介质层，包括：
首先在所述石墨烯沟道层、所述源电极和所述漏电极上通过电子束蒸发的方法获取钇层；
然后通过热氧化的方法将所述钇层氧化成为氧化钇层；
最后通过原子层沉积的方法在所述氧化钇层、所述源电极和所述漏电极上沉积二氧化铪层，形成所述栅介质层。
以通过依次覆盖的氧化钇层和二氧化铪层，在石墨烯沟道层上形成均匀、稳定的覆盖层，起到绝缘、隔离的作用。
在一个可能的设计中，所述在所述源极和所述漏极之间的所述石墨烯沟道层上形成栅介质层，包括：通过原子层沉积的方法在所述石墨烯沟道层上所述源电极和所述漏电极上沉积氧化铝层，形成所述栅介质层，起到绝缘、隔离的作用。
在一个可能的设计中，所述在所述栅介质层上形成栅电极，包括：通过电子束蒸发法、或金属溅射法在所述栅介质层上、且在所述源电极和所述漏电极之间形成所述栅电极。
附图说明
图1是现有技术提供的常规石墨烯场效应晶体管的剖面图；
图2是现有技术提供的石墨烯场效应晶体管的剖面图；
图3是本公开实施例提供的石墨烯场效应晶体管的剖面图；
图4是本公开实施例图3提供的石墨烯场效应晶体管中A处放大图；
图5是本公开一个实施例提供的石墨烯沟道层与衬底的俯视透视图，其中石墨烯沟道层的方向与凹陷部的长度方向垂直；
图6是本公开另一个实施例提供的石墨烯沟道层与衬底的俯视透视图，其中石墨烯沟道层的方向与凹陷部的长度方向相同；
图7是本公开实施例采用相干衍射光刻法的原理图；
图8是本公开实施例提供的支撑件的扫描电镜图；
图9是本公开实施例提供的制备石墨烯场效应晶体管时，在衬底上形成凹陷部和凸起部的结构示意图；
图10是本公开实施例提供的制备石墨烯场效应晶体管时，在凹陷部和凸起部上形成石墨烯沟道层的结构示意图；
图11是本公开实施例提供的制备石墨烯场效应晶体管时，在石墨烯沟道层的两端形成源电极和漏电极的结构示意图；
图12是本公开实施例提供的制备石墨烯场效应晶体管时，在图11的结构上形成氧化钇层的结构示意图；
图13是本公开实施例提供的制备石墨烯场效应晶体管时，在图12的结构上形成二氧化铪层的结构示意图；
图14是本公开实施例提供的制备石墨烯场效应晶体管时，在图13的结构上形成栅电极的结构示意图；
图15是本公开效果实施例4提供的栅电极电压-工作电流对比图：
图16是本公开效果实施例4提供的栅电极电压-跨导对比图。
其中，附图标记为：
1、衬底；2、石墨烯沟道层；3、源电极；4、漏电极；5、栅介质层；6、栅电极；7、空腔；
101、凹陷部；102、凸起部、；L、凹陷部的长度；D、凹陷部的深度；W、凹陷部的宽度。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
一方面，本公开实施例提供了一种石墨烯场效应晶体管，其结构如附图3所示，该晶体管包括：衬底1、形成于所述衬底1上的石墨烯沟道层2、分别位于所述石墨烯沟道层2的两端上的源电极3和漏电极4、位于所述源电极3和所述漏电极4之间的所述石墨烯沟道层2上的栅介质层5和栅电极6。
所述衬底1具有由两个以上的凹陷部101和一个以上的凸起部102构成的支撑件，所述支撑件的至少一个所述凸起部102与所述石墨烯沟道层2接触。具体地，凹陷部101起始于衬底1的表面而终止于衬底1内部，两个所述凹陷部101之间构成了凸起部102。
通过衬底1上的支撑件对石墨烯沟道层形成物理支撑，即支撑件上的至少一个凸起部102支撑位于源电极3和漏电极4之间的石墨烯沟道层2，避免了石墨烯沟道层2在无支撑悬空的情况下由于重力等作用而出现的塌陷或者变形。
并且，相对于完全将石墨烯沟道层2覆盖于衬底上，两者大面积接触的情况而言，本公开实施例提供的晶体管的凹陷部101减少了衬底1与石墨烯沟道层2之间的接触面积，减少了衬底1对石墨烯沟道层2的影响，提升了载流子迁移率。同时由于通过支撑件的至少一个凸起部102对石墨烯沟道层2形成物理支撑，且凹陷部101不支撑石墨烯沟道层2，即采用了半悬空结构，在有效支撑石墨烯沟道层2的同时，石墨烯沟道层2和衬底1的接触面积减小，从而减少了漏电流和高频损耗。
其中，通过衬底1上的两个以上的凹陷部101和一个以上的凸起部102实现提升载流子迁移率的机理是，以氧化硅衬底为例举例说明，当氧化硅与石墨烯沟道层2接触时，氧化硅衬底中的远程界面声子散射(remote interfacial phonon scattering)和带电杂质产生的库仑散射(Coulomb scattering)是影响石墨烯载流子迁移率降低的主要因素之一。本领域技术人员可以理解的是，不同材料的衬底1对石墨烯沟道层2造成的载流子迁移率降低的原因可能不尽相同，但本公开基于衬底1与石墨烯沟道层2大面积接触会造成石墨烯载流子迁移率降低的原理，通过采用凹陷部101减少了衬底1与石墨烯沟道层2之间的接触面积，减少衬底1导致的石墨烯散射的影响，避免了由于衬底1与石墨烯沟道层2大面积接触而造成石墨烯载流子迁移率降低。
作为本公开的一个示例，两个以上的所述凹陷部101为长条形。具体地，两个以上的所述凹陷部101为长方形，该凹陷部101的长度L方向互相平行。此处，凹陷部101的长度是指，长方形凹陷部101的最长边的长度。那么相应地，一个以上的凸起部102为长方形，凹陷部101和凸起部102以规则的形状形成对石墨烯沟道层2的均匀支撑。
两个以上的所述凹陷部101的宽度相等，此处，凹陷部101的宽度是指，从凹陷部101的一个侧壁至另一个侧壁的垂直距离，以图3中A处的放大图为图4为例，该垂直距离如图4中所示为W。通过互相平行以及间距相等的凹陷部101使凸起部102对石墨烯沟道层2的支撑力更为均匀。例如，当所述衬底1上只具有一个凸起部102时，凸起部102的支撑力应作用于石墨烯沟道层2的中间，此处的中间指从该位置处到源电极3和到漏电极4之间的距离相等。当所述衬底1上具有两个以上的凸起部102时，每个凸起部102之间的距离应相等。
其中，两个以上的所述凹陷部101的宽度与所述凹陷部101的深度的比值为1:1-2，此处，凹陷部101的深度是指，从凹陷部101的底部至凹陷部101的开口处的垂直距离，如图4中所示为D。具体地，所述凹陷部101的宽度为30-60nm，所述凹陷部101的深度为30-120nm。所述凹陷部101的宽度的范围还可以为40-50nm，所述凹陷部101的深度的范围还可以为40-110nm，50-100nm，60-90nm，70-80nm。上述凹陷部101的宽度与深度的比值范围一方面使得凹陷部101结构更稳定，另一方面使不与石墨烯沟道层2接触的凹陷部101远离石墨烯沟道层2。凹陷部101的个数比凸起部102的个数多一个，其具体的个数由源电极3和漏电极4之间的距离以及凹陷部101的宽度决定，例如，凹陷部101的个数可以为20个、30个、40个、50个、60个、70个、80个、90个、100个、150个、200个、250个、300个等。
作为本公开的一个示例，参见图5，所述石墨烯沟道层2的方向与所述凹陷部101的长度方向垂直，除另有定义之外，本文所述的石墨烯沟道层2的方向指从位于石墨烯沟道层2上一端的源电极3到漏电极4的方向。此处凹陷部101的长度方向如图5中L所示，以形成中段横向支撑，此处横向指垂直于所述石墨烯沟道层2的方向，从石墨烯沟道层2上一端的源电极3端开始间隔预设的距离进行分段支撑，直至到达石墨烯沟道层2上另一端的漏电极4端，以防止石墨烯沟道层2由于重力等作用而出现的塌陷或者变形。
作为本公开的一个示例，参见图6，所述石墨烯沟道层2的方向与所述凹陷部101的长度方向相同，此处凹陷部101的长度方向如图6中L所示，以形成从石墨烯沟道层2起始端至末尾端的支撑，即从源电极3到漏电极4的支撑，形成纵向的支撑，此处纵向指平行于所述石墨烯沟道层2的方向，凸起部102从石墨烯沟道层2上一端的源电极3端开始直至另一端的漏电极4端截止，以防止石墨烯沟道层2由于重力等作用而出现的塌陷或者变形。
在上文所述的实施例中，所述衬底1为硅基衬底、蓝宝石衬底、或者石英衬底。所述硅基衬底包括氧化硅层和硅层，或者只包括硅层。其中，包括氧化硅层和硅层的硅基衬底为在硅层表面生长二氧化硅薄膜，形成表面层为氧化硅层的硅基衬底，该氧化硅层厚度为250-350nm，该氧化硅层厚度还可以为其余可能的范围或取值，例如260-340nm，270-330nm，280-320nm，290-310nm，300nm。以满足在足够厚度的氧化硅层上形成凹陷部101和凸起部102。本公开对衬底1材料不作具体限定，其可以为任何一种可应用于石墨烯场效应晶体管衬底的材料。
为了形成绝缘层，将栅电极6与石墨烯沟道层2隔离，在石墨烯沟道层2上均匀覆盖栅介质层5。作为本公开的一个示例，所述栅介质层5为位于所述石墨烯沟道层2上的氧化钇层与位于所述氧化钇层上的二氧化铪层的复合栅介质层。并且在上述复合栅介质层中，将氧化钇层作为复合栅介质层中与石墨烯沟道2层直接接触的第一层，以在缺乏悬挂键的石墨烯上形成均匀的介质层，本文所述“悬挂键”是指化学键，晶体因晶格在表面处突然终止，在表面的最外层的每个原子将有一个未配对的电子，即有一个未饱和的键，即为悬挂键。将二 氧化铪层作为覆盖在所述第一层上的复合栅介质层的第二层，以形成良好的覆盖性。具体地，所述复合栅介质层包括厚度为1-10nm的氧化钇层与厚度为5-15nm的二氧化铪层。该氧化钇层的厚度还可以为2-9nm，3-8nm，4-7nm，5-6nm，该二氧化铪层的厚度还可以为6-14nm，7-13nm，8-12nm，9-11nm,10nm。作为本公开的另一个示例，所述栅介质层5还可以为位于所述石墨烯沟道层2上的氧化铝层，其厚度为15-30nm，可选为20nm。
通过栅介质层5还可以将栅电极6分别与石墨烯沟道层2、源电极3和漏电极4隔离，在本公开的又一个示例中，栅介质层5覆盖于石墨烯沟道层2上，还覆盖于所述源电极3和所述漏电极4的顶部和侧面。通过覆盖于石墨烯沟道层2上的栅介质层5将栅电极6与石墨烯沟道层2隔离，通过覆盖于源电极3和所述漏电极4的顶部和侧面的栅介质层5将栅电极6与源电极3和漏电极4进行隔离。
为了实现三个电极的电流导通功能，作为栅电极6、源电极3和漏电极4的材料通常可选择熔点较高的金属，该类金属在具备良好的导电性能的基础上，能够耐受高温。具体地，栅电极6为包含钛层和金层的复合金属层，所述复合金属层中的钛层和金层的厚度比为1:5-20。源电极3和漏电极4均为包含钛层、钯层、金层的复合金属层，包含钛层、钯层、金层的复合金属层中的钛层、钯层、金层的厚度比为1:(30-70):(80-120)，可选为1:50:100；源电极3和漏电极4还可以均为包含钛层和金层的复合金属层，所述包含钛层和金层的复合金属层中钛层和金层的厚度比为1:5-10。本公开实施例不对栅电极6、源电极3和漏电极4的材料作出具体限定，其可以为任何一种可应用于石墨烯场效应晶体管三个电极的材料，举例来说，作为栅电极6的金属还可以选自钨、钴、镍、钼、钛、金中的至少一种，栅电极6的材料还可以选自金属氮化物、金属氮硅化物等，例如氮化钨、氮化钛、氮化钽、氮化钼、氮硅化钨、氮硅化钼等。另外作为源电极3和漏电极4的材料同样，可以选自钨、钴、镍、钼、钛、金中的至少一种。
所述源电极3和所述漏电极4的厚度为100-200nm，所述栅介质层5的厚度为5-50nm，所述栅电极6的厚度为5-50nm。如图3所示，由于栅电极6的厚度小于源电极3和漏电极4的厚度，所以其形成了由栅电极6至源电极3或漏电极4的类似于台阶形的跃迁结构。
基于上文所述的石墨烯场效应晶体管的结构，本公开实施例提供的石墨烯场效应晶体管在应用时的工作原理是：当施加在栅电极6上的电压为负电压(Vg<0)时，石墨烯沟道层2中感应出一定量的正电荷以平衡栅点极6电场，此时石墨烯沟道层2费米能级处于价带(狄拉克点下方)，石墨烯沟道层2中的导电电荷为空穴。当施加在栅电极6上的电压朝正电压方向移动经过零点时，石墨烯沟道层2的费米能级也向上移动达到了狄拉克点，石墨烯沟道层2中的载流子浓度最小，此时达到最大电阻值(或最小电导)。当施加在栅电极6上的电压为正电压(Vg>0)并且进一步增大时，石墨烯沟道层2的费米能级继续向上移动到导带，石墨烯沟道层2中导电载流子从空穴变为电子，并且电子浓度随栅电极6上施加的电压的增大而增大，因此石墨烯沟道层2的电阻也随之减小。通过栅电极6上施加的电压的调制，石墨烯沟道层2可以从空穴导电转变到电子导电，将石墨烯沟道层2与源电极3以及漏电极4进行连接，可以实现将源电极3和漏电极4之间的电流导通。
另一方面，本公开实施例提供了一种石墨烯场效应晶体管的制备方法，所述方法包括：
步骤101：获取衬底1；
步骤102：在所述衬底1上形成由两个以上的凹陷部101和一个以上的凸起部102构成 的支撑件；
步骤103：在所述支撑件上形成石墨烯沟道层2；
步骤104：在所述石墨烯沟道层2的两端上形成源电极3和漏电极4；
步骤105：在所述源电极3和所述漏电极4之间的所述石墨烯沟道层2上形成栅介质层5；
步骤106：在所述栅介质层5上形成栅电极6。
通过上述制备方法，先在衬底上形成由两个以上的凹陷部101和一个以上的凸起部102构成的支撑件，再在支撑件上形成石墨烯沟道层2，以该顺序形成石墨烯沟道层2不会对石墨烯沟道层2造成污染。并且通过支撑件对石墨烯沟道层2的支撑作用，避免了石墨烯沟道层2在无支撑悬空的情况下由于重力等作用而出现的塌陷或者变形。
附图9-附图14示出了本公开一个示例制备石墨烯场效应晶体管的流程图，下面结合图9-图14中所示的结构说明本公开的制备方法。
作为本公开的一个示例，步骤102涉及的支撑件的构成，包括：
通过相干衍射光刻法和干法刻蚀法相结合，或者相干衍射光刻法和湿法腐蚀法相结合的方法获取所述支撑件。其中相干衍射光刻法包括通过夹角范围为10-60°，波长范围为140-200nm的两束相干光形成明暗光线，利用所述明暗光线对所述衬底1进行光刻获取所述支撑件的所述凹陷部101，获得图9中所示的结构。
相干衍射光刻法是基于相干光干涉效应，通过频率相同、偏振方向相同、具有稳定的相位差的两束相干光在衬底1表面干涉，然后会产生如图7所示的由光亮区和暗区得到的干涉图形，图7为相干衍射光刻法的原理图，通过两束波长为λ，夹角为θ的相干光按照图7中箭头所示的方向入射，在上述两束相干光的交汇处会发生干涉，形成光亮区与暗区，这些光亮区与暗区周期性排列，即为图7中明暗条纹，形成明暗光线。本公开实施例采用相干衍射光刻法可避免传统光刻中由于半导体表面的平整度和表面形貌对光刻质量的影响，这种方法可在任意表面形成干涉图形，而且可形成大面积的图形。
具体而言，首先在衬底1上涂覆光刻胶，利用夹角范围为10-60°，波长范围为140-200nm的两束相干光对光刻胶进行选择性曝光，使用显影液对光刻胶形成腐蚀，将待形成凹陷部101上涂覆的光刻胶去除，保留待形成凸起部102上涂覆的光刻胶；然后通过干法刻蚀法或者湿法腐蚀法对表面已经去除涂覆的光刻胶的衬底1进行图形刻蚀，形成凹陷部101；最后将衬底1上保留的光刻胶去除，形成凸起部102。对于上述刻蚀中的作用机理和过程为本领域所常见的，例如可参见陆静君所著的《纳米光栅的位相掩膜相干光光刻方法与工艺研究》。
其中，在对得到的支撑件进行扫描电镜测量可以得到其微观结构，如图8所示，可以看到清晰的凹陷部和凸起部。
需要说明的是，支撑件的形成是在衬底1表面上往衬底1内部延伸而形成的，即凹陷部101起始于衬底1的表面，结束于衬底1的内部。另外，上文所述的凹陷部101的宽度与凹陷部101的深度的比值大小，可以通过改变曝光剂量与胶层厚度来实现，或者通过调节用作刻蚀掩模的遮蔽沉积层的沉积角度等来实现的，具体的实施过程，本领域人员可以参考上文所述文献。
步骤103涉及的在支撑件上形成石墨烯沟道层2，包括：
通过化学气相沉积法、微机械剥离法、或外延法获取石墨烯，将所述石墨烯通过转移的方法转移到所述支撑件上形成石墨烯沟道层2。支撑件的凹陷部101的长度方向与石墨烯沟 道层2的方向是垂直或是相同，通过石墨烯沟道层2的形成来实现，获得如图10中所示的结构。
其中，化学气相沉积法生长石墨烯是利用烃在高温的环境下裂解成碳原子和氢原子，碳原子在金属表面沉积形成石墨烯薄膜。该金属可以采用镍、铜、钌、铂等。微机械剥离法是通过物理方法将原子层间作用力较弱的石墨烯进行层间剥离，得到石墨烯薄膜。外延法指在碳化硅上高温加热使硅原子升华，在硅层或碳层形成一个石墨化表面层，这层表面层即为石墨烯薄膜。通过上述方法得到石墨烯薄膜之后，通过转移的方法将石墨烯薄膜转移到衬底1上形成石墨烯沟道层2，下面以化学气相沉积法得到的铜上的石墨烯薄膜进行转移为例进行说明，其转移过程可以为在铜上具有石墨烯层的薄膜的石墨烯层上旋涂一层聚甲基丙烯酸甲酯(PMMA)，把该薄膜放入氯化铁或硝酸铁溶液中将铜腐蚀干净，接着用去离子水将聚甲基丙烯酸甲酯(PMMA)承载的石墨烯薄膜进行清洗，然后将石墨烯薄膜转移到相应的基片(例如衬底1)上，最后用丙酮去除石墨烯表面的聚甲基丙烯酸甲酯(PMMA)。本领域技术人员可以理解的是，通过上述三种方法得到石墨烯薄膜可以是单层石墨烯、双层石墨烯以及多层石墨烯，并且上述三种得到石墨烯薄膜的方法以及石墨烯薄膜转移的方法均为现有技术，本公开实施例在此不进行详细赘述，并且本公开对石墨烯沟道层2的形成方法不作具体限定，其可以是现有技术中任一种可行的方法。
步骤104涉及的在石墨烯沟道层2的两端上形成源电极3和漏电极4，包括：通过电子束蒸发法和剥离法相结合的方法,或者金属溅射法和剥离法相结合的方法在所述石墨烯沟道层2的两端上形成所述源电极3和所述漏电极4，获得如图11所示的结构。
其中，电子束蒸发法指直接加热蒸发金属材料，使金属材料气化后在基底上凝结形成薄膜。金属溅射法通过一定能量的粒子(离子或原子、分子)轰击金属固体表面，使金属固体近表面的原子或分子获得足够大的能量而最终逸出固体表面的过程。剥离法(lift-off)指为了得到源电极3和漏电极4期望的结构，将不需要的金属从基底上剥离。本公开形成源电极3和漏电极4的方法均为现有技术，本公开实施例在此不进行详细赘述，也不局限于上述方法。
值得注意的是，石墨烯沟道层2利用载流子的迁移使电流可以从源电极3流向漏电极4，或者从漏电极4流向源电极3，因此漏电极4源电极3在形成时应部分覆盖于石墨烯沟道层2的两端之上，例如图11中所示的方式，以使源电极3、漏电极4通过石墨烯沟道层2进行连接。
在上文所述的示例中，步骤105中在所述源电极3和所述漏电极4之间的所述石墨烯沟道层2上形成栅介质层5，包括：
首先在所述石墨烯沟道层2、所述源电极3和所述漏电极4上通过电子束蒸发的方法获取钇层。
然后通过热氧化的方法将所述钇层氧化成为氧化钇层，即在含氧氛围下对钇层进行加热，以获得如图12所示的结构；
最后通过原子层沉积的方法(将物质以单原子膜形式一层一层的镀在基底表面的方法)在所述氧化钇层、所述源电极3和所述漏电极4上沉积二氧化铪层，形成所述栅介质层5，以获得如图13所示的结构。
通过上述制备过程形成栅介质层5，将氧化钇层作为复合栅介质层中与石墨烯沟道层2 直接接触的第一层，以在缺乏悬挂键的石墨烯上形成均匀的介质层。将二氧化铪层作为覆盖在所述第一层上的复合栅介质层的第二层，以形成良好的覆盖性，形成将栅电极6分别与石墨烯沟道层2、源电极3、漏电极4进行隔离，防止漏电的发生。
在本公开的另一个示例中，栅介质层5的形成还可以通过原子层沉积的方法在所述石墨烯沟道层2、所述源电极3和所述漏电极4上沉积氧化铝层，从而将栅电极与石墨烯沟道层2、源电极3、漏电极4进行隔离，防止漏电的发生。
在上述栅介质层5形成之后：通过电子束蒸发法、或金属溅射法在所述栅介质层5上、且在源电极3和漏电极4之间形成所述栅电极6，以获得如图14所示的结构。
需要说明的是，作为本公开示例的一种可能的实现方式，上述“沉积二氧化铪层”或者“沉积氧化铝层”将源电极3和漏电极4的顶部、侧面均覆盖，即在源电极3和漏电极4的顶部和两个侧面的整体上均形成了二氧化铪层或氧化铝层。因此在形成栅电极6时，可以直接在源电极3和漏电极4之间的凹陷处形成栅电极6，栅电极6通过在源电极3和漏电极4的侧面覆盖的栅介质层5将其与源电极3和漏电极4进行隔离，因此栅电极6的宽度可以与源电极3和漏电极4之间的凹陷处的宽度相等或基本相等，相对于现有技术中图1所示的情况而言，本公开采用的栅电极6的宽度增加，当在栅电极6上施加电压时，由于栅电极6与石墨烯沟道层2的接触面积增加，在具有增加的接触面积的情况下，可以对石墨烯沟道层2中的载流子进行更强的控制，从而可增强栅电极的控制能力，即跨导增加。
以下将通过具体实施例进一步地描述本公开。
制备实施例1
本实施例提供了一种石墨烯场效应晶体管的制备方法，具体如下所示。
获取衬底1：
在硅基底上通过热氧化在硅表面形成厚度为300nm的氧化硅层，形成硅-氧化硅复合衬底。
在所述衬底1上形成由两个以上的凹陷部101和一个以上的凸起部102构成的支撑件：
在衬底1的氧化硅层上涂覆正性光刻胶(如CN101256358A所示的化学式5所示的感光性物质，合成方法如CN101256358A中的制备实施例所示)，利用夹角为35°且波长为193nm的两束相干光对光刻胶进行选择性曝光，使用碱性显影液将上述两相干光的干涉光线中的亮部所对应的光刻胶部分(该光刻胶部分将要用于形成凹陷部101)去除，保留上述两相干光的干涉光线中的暗部所对应的光刻胶部分(该光刻胶部分将要用于形成凸起部102)；
然后将衬底1浸泡在缓冲氧化物刻蚀液(Buffered Oxide Etch，BOE)中15秒的时间，以形成凹陷部101，其中缓冲氧化物刻蚀液通过将质量分数为49％的氟化氢溶液和质量分数为40％的NH4F氟化铵溶液按体积比为1：6进行混合得到；
最后将衬底1上保留的光刻胶用丙酮去除，形成凸起部102。由此得到100个左右的凹陷部101，其中凹陷部101的宽度为50nm且深度为50nm。
在所述支撑件上形成石墨烯沟道层2：
首先，采用化学气相沉积法在铜上生长石墨烯，得到在铜上具有石墨烯层的薄膜。具体的生长条件是，在化学气相沉积管式炉中，在氩气保护下，升温到1000℃，然后分别以1000sccm(Standard Cubic Centimeter per Minute，每分钟标准毫升)、40sccm和1sccm的流速通入氩气、氢气和甲烷，生长时间为30min。
然后在上述在铜上具有石墨烯层的薄膜的石墨烯层上旋涂一层聚甲基丙烯酸甲酯(PMMA)树脂，将该薄膜放入氯化铁溶液中4小时，以将铜完全溶解，接着用去离子水将该薄膜的石墨烯层的相对侧清洗，然后将该薄膜转移到衬底1上，使该薄膜的石墨烯层抵靠在衬底1上，然后用丙酮去除聚甲基丙烯酸甲酯(PMMA)。得到沟道长度为50μm的石墨烯沟道层2和衬底1的复合结构，并且在转移时使石墨烯沟道层2的长度方向与凹陷部101的长度方向相同。
在所述石墨烯沟道层2的两端上形成源电极3和漏电极4；
首先在所述石墨烯沟道层2和衬底1的复合结构的石墨烯沟道层2上涂覆上述正性光刻胶，通过掩模对正性光刻胶进行选择性曝光，其中所述石墨烯沟道层2的两端对应于已发生 光化学反应的光刻胶，使用碱性显影液去除上述已发生光化学反应的光刻胶，保留位于石墨烯沟道层2上方的长度为30微米的光刻胶；
然后采用电子束蒸发镀膜仪在上述步骤中得到的样品的整个表面上依次蒸镀厚度为1nm的钛层、厚度为50nm的钯层、以及厚度为100nm的金层，从而形成了三层复合金属层；
最后采用丙酮对剩余光刻胶进行去除，从而将位于石墨烯沟道层2上方的光刻胶腐蚀以及该部分光刻胶的上方的三层复合金属层去除，从而在石墨烯沟道层2两端分别形成源电极3和漏电极4。
在所述源电极3和所述漏电极4之间的所述石墨烯沟道层2上形成栅介质层5；
首先采用电子束蒸发镀膜仪在石墨烯沟道层2、源电极3和漏电极4上蒸镀厚度为2nm的钇层；
然后在空气气氛、温度为120℃的条件下将所述厚度为2nm的钇层氧化5分钟，得到厚度为4nm的氧化钇层；
最后通过原子层沉积系统在氧化钇层、源电极3和漏电极4上沉积厚度为10nm二氧化铪层，形成栅介质层5。需要说明的是，由于在本步骤中，沉积厚度较大(是上述蒸镀厚度的5倍左右)，因此在源电极3和漏电极4的两个侧面的整体上也形成了二氧化铪层。从图13上可以看出，二氧化铪层已经包覆了该衬底的整个上部表面。
在所述栅介质层5上形成栅电极6。
采用电子束蒸发法镀膜仪在栅介质层5上、且在源电极3和漏电极4之间蒸镀厚度为1nm的钛层，再在钛层上蒸镀厚度为20nm的金层形成两层复合金属层，该两层复合金属层即为栅电极6。
制备实施例2
本实施例与实施例1提供的石墨烯场效应晶体管的区别是：将石墨烯薄膜转移到支撑件上时使石墨烯沟道层2的长度方向与凹陷部101的长度方向垂直。
制备实施例3
本实施例提供了一种石墨烯场效应晶体管的制备方法，具体如下所示：
获取衬底1：
取石英衬底作为衬底1。
在所述衬底1上形成由两个以上的凹陷部101和一个以上的凸起部102构成的支撑件：
在衬底1的氧化硅层上涂覆正性光刻胶(如CN101256358A所示的化学式5所示的感光性物质，合成方法如CN101256358A中的制备实施例所示)，利用夹角为31°，波长为154nm的两束相干光对光刻胶进行选择性曝光，使用碱性将上述两相干光的干涉光线中的亮部所对应的光刻胶部分(该光刻胶部分将要用于形成凹陷部101)去除，保留上述两相干光的干涉光线中的暗部所对应的光刻胶部分(该光刻胶部分将要用于形成凸起部102)；
然后将衬底1浸泡在缓冲氧化物刻蚀液(Buffered Oxide Etch，BOE)中18秒的时间，以形成凹陷部101，其中缓冲氧化物刻蚀液通过将质量分数为49％的氟化氢溶液和质量分数为40％的NH4F氟化铵溶液按体积比为1：6进行混合得到；
最后将衬底1上保留的光刻胶用丙酮去除，形成凸起部102。由此得到200个左右的凹陷部101，其中凹陷部101的宽度为40nm且深度为60nm。
在所述支撑件上形成石墨烯沟道层2：
采用微机械剥离法剥离出薄层状的石墨烯，将该薄层状的石墨烯直接转移到衬底1上。得到沟道长度为20μm的石墨烯沟道层2和衬底1的复合结构。
在所述石墨烯沟道层2的两端上形成源电极3和漏电极4；
首先在所述石墨烯沟道层2和衬底1的复合结构的石墨烯沟道层2上涂覆上述正性光刻胶，通过掩模对正性光刻胶进行选择性曝光，其中所述石墨烯沟道层2的两端对应于已发生 光化学反应的光刻胶，使用碱性显影液去除上述已发生光化学反应的光刻胶，保留位于石墨烯沟道层2上方的长度为10微米的光刻胶；
然后采用电子束蒸发镀膜仪在上述步骤中得到的样品的整个表面上依次蒸镀厚度为15nm的钛层、和厚度为100nm的金层，从而形成了两层复合金属层；
最后采用丙酮对剩余光刻胶进行去除，从而将位于石墨烯沟道层2上方的光刻胶腐蚀以及该部分光刻胶的上方的两层复合金属层去除，从而在石墨烯沟道层2两端分别形成源电极3和漏电极4。
在所述源电极3和所述漏电极4之间的所述石墨烯沟道层2上形成栅介质层5；
通过原子层沉积系统在石墨烯沟道层2、源电极3和漏电极4上沉积厚度为20nm氧化铝层，形成栅介质层5。本步骤中的氧化铝层在源电极3和漏电极4的顶部和两个侧面的整体上均形成了氧化铝层，氧化铝层包覆石墨烯沟道层2、源电极3和漏电极4的整个上表面。
在所述栅介质层5上形成栅电极6。
采用金属溅射镀膜仪在栅介质层5上，且在源电极3和漏电极4之间蒸镀厚度为15nm的 钛层，再在钛层上蒸镀厚度为100nm的金层形成两层复合金属，该两层复合金属层即为栅电极6。
效果实施例4
本实施例对通过实施例1的制备方法得到的石墨烯场效应晶体管以及对比例1的石墨烯场效应晶体管采用Comsol器件仿真工具进行电学特性仿真。
其中对比例1的具体结构如图1所示，其包括硅-氧化硅复合衬底1、形成在所述氧化硅衬底1上的石墨烯沟道层2、分别形成在石墨烯沟道层2的两端的源电极3和漏电极4、形成于石墨烯沟道层2上的栅介质层5以及栅电极层6。其具体参数为：石墨烯沟道层2的沟道长度为10μm，源电极3为厚度分别为15nm和100nm的钛层、金层的复合金属层，漏电极4的材料组成以及金属厚度与源电极3的材料组成以及金属厚度相同，栅介质层5为厚度为30nm的氧化铝层，栅电极层6的材料组成与源电极3的材料组成相同。
将通过电学特性仿真得到的实施例1和对比例1的转移特性曲线进行对比，结果如图15和图16中所示。具体地，图15是本公开实施例4提供的栅电极电压-工作电流对比图，从图15中可以看出，通过实施例1制备得到的石墨烯场效应晶体管的工作电流比对比例1大。此处，工作电流指源电极和漏电极之间导通之后的电流。另外，图16是本公开实施例4提供的栅电极电压-跨导对比图，从图16可以看出，通过实施例1制备得到的石墨烯场效应晶体管的跨导比对比例1大，这表明栅电极电压对工作电流的控制性能增强。
效果实施例5
本实施例对通过实施例2中的制备方法得到的石墨烯场效应晶体管，以及效果实施例4中的对比例1分别采用Comsol器件仿真工具进行电学特性仿真。
通过实施例2制备得到的石墨烯场效应晶体管的器件的电学性能，相对于对比例1而言更好，即通过实施例2制备得到的石墨烯场效应晶体管的器件工作电流比对比例1中的石墨烯场效应晶体管的器件工作电流大，通过实施例2制备得到的石墨烯场效应晶体管的跨导比对比例1中的石墨烯场效应晶体管的跨导大。
效果实施例6
本实施例对通过实施例1和通过实施例2中的制备方法得到的石墨烯场效应晶体管分别采用Comsol器件仿真工具进行电学特性仿真。
通过实施例1制备得到的石墨烯场效应晶体管的器件的电学性能，相对于实施例2而言更好，即通过实施例1制备得到的石墨烯场效应晶体管的器件工作电流比通过实施例2制备得到的石墨烯场效应晶体管的器件工作电流大，通过实施例1制备得到的石墨烯场效应晶体管的跨导比通过实施例2制备得到的石墨烯场效应晶体管的跨导大。
上述所有可选技术方案，可以采用任意结合形成本公开的可选实施例，在此不再一一赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (22)

  1. 一种石墨烯场效应晶体管，包括：衬底(1)、形成于所述衬底(1)上的石墨烯沟道层(2)、分别位于所述石墨烯沟道层(2)的两端上的源电极(3)和漏电极(4)、位于所述源电极(3)和所述漏电极(4)之间的所述石墨烯沟道层(2)上的栅介质层(5)和栅电极(6)；
    其特征在于，所述衬底(1)具有由两个以上的凹陷部(101)和一个以上的凸起部(102)构成的支撑件，所述支撑件的至少一个所述凸起部(102)与所述石墨烯沟道层(2)接触。
  2. 根据权利要求1所述的晶体管，其特征在于，两个以上的所述凹陷部(101)为长条形。
  3. 根据权利要求2所述的晶体管，其特征在于，两个以上的所述凹陷部(101)为长方形。
  4. 根据权利要求3所述的晶体管，其特征在于，两个以上的所述凹陷部(101)的长度(L)方向互相平行。
  5. 根据权利要求3所述的晶体管，其特征在于，两个以上的所述凹陷部(101)的宽度(W)相等。
  6. 根据权利要求5所述的晶体管，其特征在于，两个以上的所述凹陷部(101)的宽度(W)与所述凹陷部(101)的深度(D)的比值为1:1-2。
  7. 根据权利要求6所述的晶体管，其特征在于，所述凹陷部(101)的宽度(W)为30-60nm，所述凹陷部(101)的深度(D)为30-120nm。
  8. 根据权利要求3所述的晶体管，其特征在于，所述石墨烯沟道层(2)的方向与所述凹陷部(101)的长度(L)方向垂直。
  9. 根据权利要求3所述的晶体管，其特征在于，所述石墨烯沟道层(2)的方向与所述凹陷部(101)的长度(L)方向相同。
  10. 根据权利要求1所述的晶体管，其特征在于，所述栅介质层(5)为位于所述石墨烯沟道层(2)上的氧化钇层与位于所述氧化钇层上的二氧化铪层的复合栅介质层，或者为位于所述石墨烯沟道层(2)上的氧化铝层。
  11. 根据权利要求10所述的晶体管，其特征在于，所述栅介质层(5)还覆盖于所述源电极(3)和所述漏电极(4)的顶部和侧面。
  12. 根据权利要求10所述的晶体管，其特征在于，所述复合栅介质层包括厚度为1-10nm的氧化钇层与厚度为5-15nm的二氧化铪层。
  13. 根据权利要求1所述的晶体管，其特征在于，所述栅电极(6)为包含钛层和金层的复合金属层，所述复合金属层中的钛层和金层的厚度比为1:5-20。
  14. 根据权利要求1所述的晶体管，其特征在于，所述源电极(3)和所述漏电极(4)均为包含钛层、钯层、金层的复合金属层，或者均为包含钛层和金层的复合金属层。
  15. 一种制备权利要求1-14中任一项所述的石墨烯场效应晶体管的方法，其特征在于，所述方法包括：
    获取衬底(1)；
    在所述衬底(1)上形成由两个以上的凹陷部(101)和一个以上的凸起部(102)构成的支撑件；
    在所述支撑件上形成石墨烯沟道层(2)；
    在所述石墨烯沟道层(2)的两端上形成源电极(3)和漏电极(4)；
    在所述源电极(3)和所述漏电极(4)之间的所述石墨烯沟道层(2)上形成栅介质层(5)；
    在所述栅介质层(5)上形成栅电极(6)。
  16. 根据权利要求15所述的制备方法，其特征在于，通过相干衍射光刻法和干法刻蚀法相结合、或者相干衍射光刻法和湿法腐蚀法相结合的方法获取所述支撑件。
  17. 根据权利要求16所述的制备方法，其特征在于，所述相干衍射光刻法包括：通过夹角范围为10-60°，波长范围为140-200nm的两束相干光形成明暗光线，利用所述明暗光线对所述衬底(1)进行光刻获取所述支撑件的所述凹陷部(101)。
  18. 根据权利要求15所述的制备方法，其特征在于，所述在所述支撑件上形成石墨烯沟道层(2)，包括：
    通过化学气相沉积法、微机械剥离法、或外延法获取石墨烯，将所述石墨烯通过转移的方法转移到所述支撑件上形成石墨烯沟道层(2)。
  19. 根据权利要求15所述的制备方法，其特征在于，所述在所述石墨烯沟道层(2)的两端上形成源电极(3)和漏电极(4)，包括：通过电子束蒸发法和剥离法相结合的方法,或者金属溅射法和剥离法相结合的方法在所述石墨烯沟道层(2)的两端上形成所述源电极(3)和所述漏电极(4)。
  20. 根据权利要求15所述的制备方法，其特征在于，所述在所述源电极(3)和所述漏电极(4)之间的所述石墨烯沟道层(2)上形成栅介质层(5)，包括：
    首先在所述石墨烯沟道层(2)、所述源电极(3)和所述漏电极(4)上通过电子束蒸发的方法获取钇层；
    然后通过热氧化的方法将所述钇层氧化成为氧化钇层；
    最后通过原子层沉积的方法在所述氧化钇层、所述源电极(3)和所述漏电极(4)上沉积二氧化铪层，形成所述栅介质层(5)。
  21. 根据权利要求15所述的制备方法，其特征在于，所述在所述源极(3)和所述漏极(4)之间的所述石墨烯沟道层(2)上形成栅介质层(5)，包括：通过原子层沉积的方法在所述石墨烯沟道层(2)上所述源电极(3)和所述漏电极(4)上沉积氧化铝层，形成所述栅介质层(5)。
  22. 根据权利要求15所述的制备方法，其特征在于，所述在所述栅介质层(5)上形成栅电极(6)，包括：通过电子束蒸发法、或金属溅射法在所述栅介质层(5)上、且在所述源电极(3)和所述漏电极(4)之间形成所述栅电极(6)。
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