WO2022135595A1 - 功率模组 - Google Patents

功率模组 Download PDF

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Publication number
WO2022135595A1
WO2022135595A1 PCT/CN2021/141373 CN2021141373W WO2022135595A1 WO 2022135595 A1 WO2022135595 A1 WO 2022135595A1 CN 2021141373 W CN2021141373 W CN 2021141373W WO 2022135595 A1 WO2022135595 A1 WO 2022135595A1
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WO
WIPO (PCT)
Prior art keywords
upper bridge
bridge
power module
heat dissipation
chip
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Application number
PCT/CN2021/141373
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English (en)
French (fr)
Inventor
石守操
曾秋莲
骆传名
吴海平
Original Assignee
比亚迪半导体股份有限公司
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Publication date
Application filed by 比亚迪半导体股份有限公司 filed Critical 比亚迪半导体股份有限公司
Priority to EP21909590.8A priority Critical patent/EP4254485A4/en
Priority to JP2023538108A priority patent/JP2024500176A/ja
Publication of WO2022135595A1 publication Critical patent/WO2022135595A1/zh
Priority to US18/337,975 priority patent/US20230335457A1/en

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Definitions

  • the present disclosure relates to the field of electronic technology, and in particular, to a power module.
  • the existing half-bridge structure package mainly has the following three forms: a single-tube series connection to form a half-bridge structure, a single-sided heat dissipation half-bridge structure module, and a double-sided heat dissipation half-bridge structure module.
  • the chip junction temperature of these structures is high, which will affect the reliability of the chip.
  • the purpose of the present disclosure is to provide a power module, which can effectively reduce the package volume and reduce the chip temperature at the same time. Since the power module provided by the present disclosure reduces the package volume, more packages can be installed in the same system, thereby increasing the system power; and due to the reduction of the chip temperature, the power module and the system can be effectively improved reliability.
  • a power module including an input positive electrode, an input negative electrode, an upper bridge substrate, a lower bridge substrate, an upper bridge chip, a lower bridge chip, an output electrode and a signal transmission terminal, wherein the upper bridge substrate, the upper bridge chip, the lower bridge chip and the lower bridge substrate are sequentially stacked and arranged, and wherein: the collector of the upper bridge chip is connected to the upper bridge substrate, and the emitter of the upper bridge chip is connected to the upper bridge substrate.
  • the collectors of the lower bridge chip are respectively connected to the output electrodes, the emitter sampling, collector sampling and control terminals of the upper bridge chip and the emitter sampling, collector sampling and control terminals of the lower bridge chip are respectively connected to the signal transmission terminal, the input positive electrode is connected to the upper bridge substrate, and the input negative electrode is connected to the lower bridge substrate.
  • the power module further includes an upper bridge buffer block and a third connection layer, the upper bridge chip, the upper bridge buffer block and the lower bridge chip are stacked and arranged, and the upper bridge chip passes through the third connection layer.
  • the three connection layers are connected to the upper bridge buffer block, and the emitter of the upper bridge chip is connected to the output electrode through the upper bridge buffer block.
  • the power module further includes a lower bridge buffer block, a fourth connection layer and a fifth connection layer, wherein the upper bridge chip, the upper bridge buffer block, the lower bridge buffer block and the lower bridge
  • the chips are stacked and arranged, the collector of the lower bridge chip is connected to the output electrode, the emitter of the lower bridge chip is connected to the lower bridge buffer block through the fourth connection layer, and the lower bridge buffer block is connected to the lower bridge buffer block through the fourth connection layer.
  • the fifth connection layer is connected to the lower bridge substrate.
  • the power module further includes a second connection layer and an upper bridge heat dissipation base plate, wherein the upper bridge heat dissipation base plate, the upper bridge substrate, the upper bridge chip, the upper bridge buffer block, the upper bridge The lower bridge chip, the lower bridge buffer block and the lower bridge substrate are stacked in sequence, wherein: the upper bridge substrate is connected to the upper bridge heat dissipation base plate through the second connection layer.
  • the power module further includes a sixth connection layer and a lower bridge heat dissipation base plate, wherein the upper bridge heat dissipation base plate, the upper bridge substrate, the upper bridge chip, the upper bridge buffer block, the upper bridge The lower bridge chip, the lower bridge buffer block, the lower bridge substrate and the lower bridge heat dissipation base plate are sequentially stacked and arranged, wherein: the lower bridge base plate is connected to the lower bridge heat dissipation base plate through the sixth connection layer .
  • the upper bridge heat dissipation base plate and the lower bridge heat dissipation base plate are pinfin heat dissipation base plates.
  • the upper bridge substrate and the lower bridge substrate are ceramic substrates.
  • the collector of the upper bridge chip is welded or sintered to the upper bridge substrate; the thermistor, the thermistor terminal, the signal transmission terminal and the input of the power module
  • the positive electrode is welded or sintered to the upper bridge substrate; the input negative electrode of the power module is welded or sintered to the lower bridge substrate; the upper bridge buffer block is welded or sintered to the upper bridge on the emitter of the chip.
  • the output electrode is welded or sintered to the upper bridge buffer block; the collector electrode of the lower bridge chip is welded or sintered to the output electrode; the lower bridge buffer block is welded or sintered to the emitter of the lower bridge chip; the lower bridge substrate is soldered or sintered to the lower bridge buffer block.
  • the back surface of the upper bridge substrate and the back surface of the lower bridge substrate are respectively welded or sintered to the upper bridge heat dissipation base plate and the lower bridge heat dissipation base plate.
  • the upper bridge chip, the output electrode and the lower bridge chip are sequentially stacked.
  • the power module further includes a first connection layer, and the collector of the upper bridge chip is connected to the upper bridge substrate through the first connection layer.
  • the power module further includes a thermistor and a thermistor terminal, and the thermistor is connected to the thermistor terminal through its bonding wire.
  • the thermistor terminal and the signal transmission terminal are bent structures.
  • the upper bridge chip and the lower bridge chip are placed horizontally or vertically.
  • the installation plane of the input positive electrode of the power module and the installation plane of the input negative electrode of the power module are located on different horizontal planes.
  • the installation plane of the input positive electrode of the power module and the installation plane of the input negative electrode of the power module are located on different planes and both are at 90° to the horizontal plane.
  • the power module further includes an upper bridge heat dissipation water channel and a lower bridge heat dissipation water channel, wherein: the upper bridge heat dissipation bottom plate and the upper bridge heat dissipation water channel are installed together, and the lower bridge heat dissipation bottom plate and the lower bridge heat dissipation water channel are installed together.
  • Bridge cooling ducts are installed together.
  • the upper bridge heat dissipation bottom plate is installed together with the upper bridge heat dissipation water channel through an upper bridge sealing ring
  • the lower bridge heat dissipation bottom plate is installed together with the lower bridge heat dissipation water channel through a lower bridge sealing ring
  • the upper bridge heat dissipation water channel and the lower bridge heat dissipation water channel are fastened by fasteners.
  • the lower part of the power module located below is below the power module.
  • the bridge heat dissipation water channel and the upper bridge heat dissipation water channel of the power module located above form a two-in-one water channel, and the two-in-one water channel is an independent water channel that is internally divided into two independent water channel spaces.
  • the power module further includes a drive board, which is arranged on the side of the upper bridge cooling water channel and the lower bridge cooling water channel and is close to the control terminal of the signal transmission terminals.
  • the emitter sampling, collector sampling and control terminals of the upper bridge chip and the emitter sampling, collector sampling and control terminals of the lower bridge chip are connected to the signal transmission terminals through respective bonding wires.
  • the package volume of the power module can be reduced, the system power can be improved, and the parasitic inductance of the power module can be reduced (for example, in the same In the case of high power output, the parasitic inductance of the vertical stacked package structure according to the embodiment of the present disclosure can be within 5nH, while the inductance of the existing package structure exceeds 10nH), which improves the overcurrent capability of the power module and increases the power module Therefore, the temperature of the chip can be effectively reduced, and the reliability of the power module and the system can be effectively improved.
  • FIG. 1 is a schematic diagram of a half-bridge structure package according to the prior art.
  • FIG. 2 is a schematic diagram of a power module according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of the upper bridge substrate.
  • FIG. 4 shows a schematic diagram of the connection between the collector of the upper bridge chip and the upper bridge substrate.
  • FIG. 5 shows a schematic diagram of the connection between the thermistor, the thermistor terminal, the signal transmission terminal and the input positive electrode of the power module and the upper bridge substrate.
  • Figure 6 shows a schematic diagram of a bond wire.
  • FIG. 7 shows a schematic diagram of the connection between the upper bridge buffer block and the emitter of the upper bridge chip.
  • FIG. 8 shows a schematic diagram of the connection between the output electrode and the upper bridge buffer block.
  • FIG. 9 shows a schematic diagram of the connection between the collector electrode and the output electrode of the lower bridge chip.
  • FIG. 10 shows a schematic diagram of the connection mode of the control line, the sampling line and the signal transmission terminal of the lower bridge chip.
  • FIG. 11 shows a schematic diagram of the connection between the lower bridge buffer block and the emitter of the lower bridge chip.
  • FIG. 12 shows a schematic diagram of the connection between the input negative electrode of the power module and the lower bridge substrate.
  • FIG. 13 shows a schematic diagram of the connection between the lower bridge substrate and the lower bridge buffer block.
  • FIG. 14 shows a schematic diagram of the connection between the upper bridge heat dissipation base plate and the lower bridge heat dissipation base plate and the upper bridge base plate and the lower bridge base plate.
  • FIG. 15 shows a schematic diagram of the power module after plastic packaging.
  • FIG. 16 shows another schematic diagram of the power module after plastic packaging.
  • FIG 17 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • FIG. 18 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • FIG. 19 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • FIG. 20 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • 21 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • FIG. 22 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • the existing half-bridge structure packaging mainly has the following three forms:
  • the single tube is connected in series to form a half-bridge structure: the single tube adopts the lower surface of the chip, that is, the collector C to be welded to the substrate, the upper surface of the chip, that is, the emitter E, the bond wire to the substrate, and the chip gate G by bonding (bonding) ) is connected to the electrode to complete the structural package, and the final packaged module is then electrically connected in series to form a single-sided heat dissipation half-bridge structure.
  • Single-sided heat dissipation half-bridge structure module use the substrate groove to form the electrical isolation between the upper and lower bridge arms, and use the lower surface of the chip, that is, the collector C to be welded to the substrate, and the upper surface of the chip, that is, the emitter E.
  • the substrate and the chip gate G are connected to the electrodes by bonding to complete the structural packaging, and at the same time, the connection between the upper bridge arm E and the lower bridge arm C is completed by bonding, forming a single-sided heat dissipation half-bridge structure.
  • Double-sided heat dissipation half-bridge structure module the lower surface of the chip, that is, the collector C is welded to the substrate 1, the upper surface of the chip, that is, the emitter E, is welded to the copper block, the copper block is then welded to the substrate 2, and the gate electrode G of the chip passes through The structure is packaged by bonding and connecting to the electrodes, forming a double-sided heat dissipation half-bridge structure.
  • the main electrodes of these package structures are all planar design structures, that is, the input electrodes and the output electrodes are on the same plane as the substrate, and the upper bridge chip and the lower bridge chip are also arranged in the same plane, as shown in FIG. 1 .
  • the defect of this structure is mainly that the parasitic inductance is high, which will lead to a high junction temperature of the chip, thereby affecting the reliability of the module.
  • the existing module heat dissipation structure mainly includes the following three types: 1) single-sided flat plate, that is, the substrate and the bottom plate are connected to the radiator, and the heat is dissipated through the plane bottom plate; 2) single-sided pinfin (pinfin), that is, the substrate is The base plate with pinfin is connected and installed to the radiator, and the heat is dissipated through the pinfin base plate; 3) The double-sided heat dissipation without the base plate, that is, the base plate is directly mounted to the radiator, and the heat is dissipated through the double-sided base plate.
  • the above three packages are all in the form of upper and lower bridge connection half-bridge packages using a planar horizontal connection structure. Since the single-tube module is connected in series and parallel with multiple single tubes to form the required half-bridge or other circuit structure, the integrated module is connected by Multiple chips are placed on the substrate to form the required circuit structure in series and parallel. Therefore, whether it is the connection between single tubes or the bond wire connection between chips, the parasitic inductance will increase and the overcurrent capability will be reduced.
  • the existing module package volume is large, and the heat dissipation surface is relatively single, and the reliability performance is poor; and the existing main electrode layout is too close in the module miniaturization design, there is a hidden safety distance, and it cannot meet the needs of high-voltage applications; the existing module heat dissipation The structure is relatively low and cannot meet the requirements of higher power density and efficient heat dissipation for high temperature work.
  • FIG. 2 is a schematic diagram of a power module according to an embodiment of the present disclosure.
  • the power module includes an upper bridge chip 8, an upper bridge buffer block 7, a lower bridge chip 5, an output electrode 6, a thermistor 15, a bonding wire 14, a signal transmission terminal 16 and a thermistor terminal 13, wherein the upper bridge chip 8, the upper bridge buffer block 7 and the lower bridge chip 5 are stacked and arranged, wherein: the emitter of the upper bridge chip 8 is connected to the output electrode 6 through the upper bridge buffer block 7, and the collector of the lower bridge chip 5 is connected To the output electrode 6, the emitter sampling, collector sampling and control terminals of the upper bridge chip 8 and the emitter sampling, collector sampling and control terminals of the lower bridge chip 5 are respectively connected to the signal transmission terminals 16 through their respective bonding wires 14.
  • the thermistor 15 is connected to the thermistor terminal 13 by its bond wire 14 .
  • the upper and lower mentioned here are opposite, but in the embodiment of the present disclosure, the front side (emitter E/source S) of the upper bridge chip 8 must be the same as the back side (collector C/drain electrode) of the lower bridge chip 5 D) Connect to the same output electrode 6, and the upper bridge chip 8 and the lower bridge chip 5 are not in the same plane, for example, the output electrodes 6 are arranged on both sides.
  • the signal transmission terminal 16 is used for signal transmission and reception, and its purposes include, but are not limited to, control, sampling, and the like.
  • the signal terminal 16 is equivalent to a set of control terminals and sampling terminals.
  • both the upper bridge chip 8 and the lower bridge chip 5 have control terminals, so the signal transmission terminal 16 includes two control terminals. , and so on for others.
  • the bonding wire 14 here is also a set of all bonding wires, for example, it includes the bonding wire from which the emitter sampling of the upper bridge chip 8 is connected to the signal transmission terminal 16 and the signal transmission terminal 16 from which the emitter sampling of the lower bridge chip 5 leads. bond wires, etc.
  • the upper bridge buffer block 7 here plays the role of electrical connection, increasing the heat capacity of the heat dissipation path to improve the heat dissipation efficiency, and providing a lead-out space for the bonding wire.
  • the upper bridge buffer block 7 may be a copper block, a molybdenum block, or the like.
  • the functions of the other buffer blocks described below are similar to those of the upper bridge buffer block 7 .
  • the buffer block and the chip are not completely attached, but only contact at necessary places such as electrodes, etc., and leave space for the uncontacted position between the buffer block and the chip according to the circuit layout. (clearance).
  • the three terminals of the upper bridge chip 8 and the lower bridge chip 5 are described as emitter, collector and control terminal.
  • the upper bridge chip 8 and the lower bridge chip 5 may be IGBT type devices, MOS type devices or other types of devices.
  • the package volume of the power module can be reduced, the system power can be improved, and the parasitic inductance of the power module (for example, , under the condition of the same power output, the parasitic inductance of the vertical stacked packaging structure according to the embodiment of the present disclosure can be within 5nH, while the inductance of the existing packaging structure exceeds 10nH), which improves the overcurrent capability of the power module, Increasing the heat dissipation area of the power module can effectively reduce the chip temperature and effectively improve the reliability of the power module and the system.
  • the power module further includes an input positive electrode 11 , an input negative electrode 12 , a first connection layer 201 , an upper bridge substrate 9 , a second connection layer 202 , an upper bridge heat dissipation base plate 10 , and a first connection layer 201 .
  • the collector of the upper bridge chip 8 is connected to the upper bridge substrate 9, the upper bridge substrate 9 is connected to the upper bridge heat dissipation base plate 10 through the second connection layer 202, the upper bridge chip 8 is connected to the upper bridge buffer block 7 through the third connection layer 203, The emitter of the lower bridge chip 5 is connected to the lower bridge buffer block 4 through the fourth connection layer 204 , the lower bridge buffer block 4 is connected to the lower bridge substrate 3 through the fifth connection layer 205 , and the lower bridge substrate 3 is connected to the lower bridge substrate 3 through the sixth connection layer 206 .
  • the lower bridge heat dissipation base plate 1 is connected.
  • the collector of the upper bridge chip 8 is connected to the upper bridge substrate 9 through the first connection layer 201 .
  • connection layers are, for example, the connection layers between the heat dissipation base plate and the substrate, the substrate and the chip, the chip and the buffer block, the buffer block and the electrode, and the welding or sintering between the buffer block and the substrate, respectively, and are used for the above-mentioned components. connection between and help dissipate heat.
  • the upper bridge heat dissipation base plate 10 and the lower bridge heat dissipation base plate 1 may be pinfin heat dissipation base plates or other types of heat dissipation base plates.
  • the upper bridge substrate 9 and the lower bridge substrate 3 can be ceramic substrates, such as copper clad ceramic substrates (such as aluminum nitride copper clad ceramic substrates, alumina copper clad ceramic substrates, etc.), active metal brazing ceramic substrates, etc., and the ceramic upper and lower
  • the thickness of the copper cladding is adjustable.
  • FIG. 3 shows a schematic diagram of the upper bridge substrate 9 .
  • the collector of the upper bridge chip 8 is welded or sintered to the upper bridge substrate 9, as shown in FIG. 4 .
  • the thermistor 15 , the thermistor terminal 13 , the signal transmission terminal 16 and the input positive electrode 11 of the power module are welded or sintered to the upper bridge substrate 9 , as shown in FIG. 5 .
  • FIG. 6 shows a schematic diagram of the bond wire 14 .
  • the emitter sampling, collector sampling and control terminals of the upper bridge chip 8 are respectively connected to the signal transmission terminal 16 through their respective bonding wires 14 ;
  • the thermistor 15 is connected to the thermistor through its bonding wires 14 Resistor terminal 13.
  • the upper bridge buffer block 7 is soldered or sintered to the emitter of the upper bridge chip 8 , as shown in FIG. 7 . This increases the heat dissipation area, which is more conducive to the heat dissipation of the chip.
  • the output electrode 6 is welded or sintered to the upper bridge buffer block 7 as shown in FIG. 8 .
  • the collector electrode of the lower bridge chip 5 is welded or sintered to the output electrode 6 to form a vertical path of the upper and lower bridges, which significantly reduces the loop inductance, as shown in FIG. 9 .
  • 10 shows a schematic diagram of the connection mode of the control terminal, the sampling terminal and the signal transmission terminal 16 of the lower bridge chip 5, that is, the control terminal and the sampling terminal of the lower bridge chip 5 (ie collector sampling, emitter sampling) It is connected to the signal transmission terminal 16 through the bonding wire 14 .
  • the lower bridge buffer block 4 is welded or sintered to the emitter of the lower bridge chip 5, as shown in FIG. 11, which increases the heat dissipation area and is more conducive to the heat dissipation of the chip.
  • the input negative electrode 12 of the power module is welded or sintered to the lower bridge substrate 3 , as shown in FIG. 12 .
  • the lower bridge substrate 3 is welded or sintered to the lower bridge buffer block 4, as shown in FIG. 13 .
  • the backside of the upper bridge substrate 9 and the backside of the lower bridge substrate 3 are respectively welded or sintered to the upper bridge heat dissipation base plate 10 and the lower bridge heat dissipation base plate 1 , as shown in FIG. 14 .
  • This double-sided heat dissipation base plate significantly increases the heat dissipation area and improves the heat dissipation efficiency.
  • the "back side” as used herein refers to the side of the substrate that is not characterized with circuit components, or is referred to as the non-device side.
  • the side of the substrate characterized by circuit components is called the front side of the substrate, or the component side.
  • FIG. 15 shows a schematic diagram of the power module after plastic packaging.
  • the plastic casing 17 is used to realize module protection and mechanical support.
  • the high temperature working effect of plastic packaging has significantly improved the application environment of the module.
  • the existing structures are arranged in horizontal series of chips, and the current flows horizontally through the connecting part after vertical transmission through the chips;
  • Stacking reduces the current flow path, the current flows vertically up and down, greatly reducing the parasitic inductance of the loop, and the chip and the substrate, the buffer block and the substrate form a laminated structure, the chip can be dissipated through multiple substrates and buffer blocks, and the heat dissipation efficiency is greatly improved.
  • the working temperature of the chip is lower, the reliability is significantly improved, and the service life is increased.
  • both sides of the power module are heat dissipation baseplates, which can be used for efficient heat dissipation during application, which significantly reduces the temperature of the chip during operation, and improves the working reliability and working life of the chip.
  • the heat dissipation base plate structure is to connect the base plate and the heat dissipation base plate by welding or sintering. The thermal resistance between the base plate and the heat dissipation base plate is significantly reduced, and heat dissipation structures are introduced on both sides of the power module to further improve the heat dissipation efficiency.
  • Group miniaturization provides a cooling base.
  • FIG. 16 shows another schematic diagram of the power module after plastic packaging.
  • the thermistor terminal 13 and the signal transmission terminal 16 are bent structures, for example, they can be bent at 90 degrees but the bending direction is not limited, so that they can be adjusted according to the cooling water channel and the application environment. Make practical matching.
  • the thermistor terminal 13 and the signal transmission terminal 16 may be bent into a shape that matches, for example, the outer shape of the heat dissipation water channel, so that, when assembling, the bending structure of the thermistor terminal 13 and the signal transmission terminal 16
  • the shape of the area of the heat dissipation water channel that is in contact with the bending structure of the thermistor terminal 13 and the signal transmission terminal 16 can be adapted to save installation space.
  • FIG. 17 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • the upper bridge chip 8 and the lower bridge chip 5 are placed vertically, while in the previous embodiment, the upper bridge chip 8 and the lower bridge chip 5 are placed horizontally.
  • the lateral direction refers to the left-right direction of the power module in FIG. 17
  • the longitudinal direction refers to its front-to-rear direction.
  • the vertical placement enables more upper bridge chips 8 and lower bridge chips 5 to be placed in the left-right direction without changing the package volume, thus providing a possibility to increase the output capability.
  • FIG. 18 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • the installation plane of the input positive electrode 11 of the power module and the installation plane of the input negative electrode 12 of the power module are located on different horizontal planes. If the installation plane of the input positive electrode 11 and the installation plane of the input negative electrode 12 are located on the same horizontal plane, the interval between the input positive electrode 11 and the input negative electrode 12 will be smaller, and by placing the installation plane of the input positive electrode 11 The installation plane of the input negative electrode 12 is placed on a different level, so that the distance between the input positive electrode 11 and the input negative electrode 12 is greatly increased, and the safety distance is also increased, thereby greatly improving the voltage safety of the power module.
  • the safety distance refers to the air distance between the input positive electrode 11 and the input negative electrode 12 .
  • FIG. 19 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • FIG. 19 is similar to FIG. 18 , the difference is that the installation plane of the input positive electrode 11 and the installation plane of the input negative electrode 12 are located on different planes and both are at 90° to the horizontal plane, that is, as shown in FIG. 19 , the input positive electrode
  • the installation plane of 11 and the installation plane of the input negative electrode 12 extend along the longitudinal direction, which increases the safety distance between the input positive electrode 11 and the input negative electrode, and improves the voltage safety level of the power module and the application voltage platform scope.
  • FIG. 20 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • the power module according to the embodiment of the present disclosure further includes an upper bridge heat dissipation water channel 19 and a lower bridge heat dissipation water channel 21 , wherein: the upper bridge heat dissipation base plate 10 and the upper bridge heat dissipation water channel 19 are installed together, and the lower bridge heat dissipation base plate 1 is installed together with the cooling water channel 21 of the lower bridge.
  • the upper bridge heat dissipation base plate 10 can be installed with the upper bridge heat dissipation water channel 19 through the upper bridge sealing ring 18, the lower bridge heat dissipation base plate 1 can be installed with the lower bridge heat dissipation water channel 21 through the lower bridge sealing ring 20, and the upper bridge
  • the cooling water channel 19 and the lower bridge cooling water channel 21 are fastened by fasteners (eg, screws). Through the cooling water channel, heat dissipation can be performed, and through such a configuration, the pinfin on the cooling bottom plate can directly contact the cooling medium in the cooling water channel, and the cooling efficiency is relatively high.
  • FIG. 21 is yet another schematic diagram of a power module according to an embodiment of the present disclosure.
  • the difference between FIG. 21 and FIG. 20 is that a plurality of power modules are arranged in layers.
  • a plurality of power modules are stacked in a direction perpendicular to the chip.
  • the lower bridge heat dissipation water channel 21 of the power module located below and the upper bridge heat dissipation water channel 19 of the upper power module form a two-in-one water channel 23,
  • the two-in-one water channel 23 is an independent water channel which is divided into two upper and lower independent water channel spaces.
  • the two independent water channel spaces can be used to dissipate heat from the heat dissipation bottom plates on both sides respectively, and the two independent water channel spaces are independent of each other. affect their heat dissipation.
  • the installation volume of the power module and the cooling water channel is significantly reduced, the power density is improved, and the system volume density is increased.
  • each heat dissipation water channel mentioned in the present disclosure may share the same water inlet and share the same water outlet, but the inner space of each heat dissipation water channel is independent of each other. Of course, it is also feasible that the water inlet and outlet are not shared.
  • the power module according to the embodiment of the present disclosure further includes a driving board 24 .
  • the drive board 24 is used to drive the power module three-phase bridge arm chip to be turned on and off.
  • the driver board 24 is arranged on the side of the control terminal in the signal transmission terminal 16, and the driver board 24 reserves an interface at the position of the control terminal, so that the control terminal can be connected to the driver board 24, and also needs to avoid the position of the output electrode 6, so that the for output wiring.
  • the drive board 24 can be arranged on the side of the upper bridge heat dissipation water channel 19 and the lower bridge heat dissipation water channel 21 described above, so that the drive board 24 can be integrated with the entire power module system without increasing the volume of the power module. .

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Abstract

功率模组，包括输入正电极(11)、输入负电极(12)、上桥基板(9)、下桥基板(3)、上桥芯片(8)、下桥芯片(5)、输出电极(6)和信号传输端子(16)，其中上桥基板(9)、上桥芯片(8)、下桥芯片(5)和下桥基板(3)依次层叠布置。上桥芯片(8)的集电极与上桥基板(9)连接，上桥芯片(8)的发射极与下桥芯片(5)的集电极分别连接到输出电极(6)，上桥芯片(8)的发射极采样、集电极采样和控制端以及下桥芯片(5)的发射极采样、集电极采样和控制端分别连接到信号传输端子(16)，输入正电极(11)连接到上桥基板(9)上，输入负电极(12)连接到下桥基板(3)上。

Description

功率模组
本公开要求于2020年12月25日提交中国专利局，申请号为202011565454.5，申请名称为“功率模组”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及电子技术领域，具体地，涉及一种功率模组。
背景技术
现有的半桥结构封装主要有以下三种形式：单管串联组成半桥结构、单面散热半桥结构模组、双面散热半桥结构模组。然而，这些结构的芯片结温都较高，会影响芯片的可靠性。
发明内容
本公开的目的是提供一种功率模组，能够有效地减小封装体积并且同时降低芯片温度。由于本公开提供的功率模组减小了封装体积，从而能够将更多的封装安装在同一个系统中并由此提升系统功率；并且由于芯片温度的降低，能够有效地提高功率模组及系统可靠性。
根据本公开的第一实施例，提供一种功率模组，该功率模组包括输入正电极、输入负电极、上桥基板、下桥基板、上桥芯片、下桥芯片、输出电极和信号传输端子，其中上桥基板、上桥芯片、下桥芯片和下桥基板依次层叠布置，且其中：所述上桥芯片的集电极与所述上桥基板连接，所述上桥芯片的发射极与所述下桥芯片的集电极分别连接到所述输出电极，所述上桥芯片的发射极采样、集电极采样和控制端以及所述下桥芯片的发射极采样、集电极采样和控制端分别连接到所述信号传输端子，所述输入正电极连接到所述上桥基板上，所述输入负电极连接到所述下桥基板上。
可选地，该功率模组还包括上桥缓冲块和第三连接层，所述上桥芯片、所述上桥缓冲块和所述下桥芯片层叠布置，所述上桥芯片通过所述第三连接层与所述上桥缓冲块连接，所述上桥芯片的发射极通过所述上桥缓冲块连接到所述输出电极。
可选地，该功率模组还包括下桥缓冲块、第四连接层以及第五连接层，其中所述上桥芯片、所述上桥缓冲块、所述下桥缓冲块和所述下桥芯片层叠布置，所述下桥芯片的集电极连接到所述输出电极，所述下桥芯片的发射极通过所述第四连接层与所述下桥缓冲块连接，所述下桥缓冲块通过所述第五连接层与所述下桥基板连接。
可选地，所述功率模组还包括第二连接层和上桥散热底板，其中，所述上桥散热底板所述上桥基板、所述上桥芯片、所述上桥缓冲块、所述下桥芯片、所述下桥缓冲块和所述下桥基板依次层叠布置，其中：所述上桥基板通过所述第二连接层与所述上桥散热底板连接。
可选地，所述功率模组还包括第六连接层和下桥散热底板，其中，所述上桥散热底板、所述上桥基板、所述上桥芯片、所述上桥缓冲块、所述下桥芯片、所述下桥缓冲块、所述下桥基板和所述下桥散热底板依次层叠布置，其中：所述下桥基板通过所述第六连接层与所述下桥散热底板连接。
可选地，所述上桥散热底板和所述下桥散热底板为pinfin散热底板。
可选地，所述上桥基板和所述下桥基板为陶瓷基板。
可选地，所述上桥芯片的集电极被焊接或烧结到所述上桥基板上；所述热敏电阻、所述热敏电阻端子、所述信号传输端子和所述功率模组的输入正电极被焊接或烧结到所述上桥基板上；所述功率模组的输入负电极被焊接或烧结到所述下桥基板上；所述上桥缓冲块被焊接或烧结到所述上桥芯片的发射极上。
可选地，所述输出电极被焊接或烧结到所述上桥缓冲块上；所述下桥芯片的集电极被焊接或烧结到所述输出电极上；所述下桥缓冲块被焊接或烧结到所述下桥芯片的发射极上；所述下桥基板被焊接或烧结到所述下桥缓冲块上。
可选地，所述上桥基板的背面以及所述下桥基板的背面分别被焊接或烧结到所述上桥散热底板和所述下桥散热底板。
可选地，上桥芯片、输出电极和下桥芯片依次层叠布置。
可选地，功率模组还包括第一连接层，上桥芯片的集电极通过第一连接层与上桥基板连接。
可选地，该功率模组还包括热敏电阻和热敏电阻端子，所述热敏电阻通过其键合线连接到所述热敏电阻端子。
可选地，所述热敏电阻端子和所述信号传输端子为弯折结构。
可选地，所述上桥芯片和所述下桥芯片为横向放置或纵向放置。
可选地，所述功率模组的输入正电极的安装平面和所述功率模组的输入负电极的安装平面位于不同的水平面上。
可选地，所述功率模组的输入正电极的安装平面和所述功率模组的输入负电极的安装平面位于不同的平面上且均与水平面成90°。
可选地，所述功率模组还包括上桥散热水道和下桥散热水道，其中：所述上桥散热底板与所述上桥散热水道安装在一起，所述下桥散热底板与所述下桥散热水道安装在一起。
可选地，所述上桥散热底板通过上桥密封圈与所述上桥散热水道安装在一起，所述下桥散热底板通过下桥密封圈与所述下桥散热水道安装在一起，而且，所述上桥散热水道和所述下桥散热水道通过紧固件进行紧固。
可选地，在多个所述功率模组在垂直于所述芯片方向上层叠布置的情况下，对于相邻的两个所述功率模组而言，位于下方的所述功率模组的下桥散热水道和位于上方的所述功率模组的上桥散热水道形成二合一水道，所述二合一水道为内部被分隔成上下2个独立水道空间的独立水道。
可选地，所述功率模组还包括驱动板，该驱动板布置在所述上桥散热水道和所述下桥散热水道的侧边上且靠近所述信号传输端子中的控制端子一侧。
可选地，所述上桥芯片的发射极采样、集电极采样和控制端以及所述下桥芯片的发射极采样、集电极采样和控制端通过各自的键合线连接到所述信号传输端子。通过采用上述技术方案，由于上桥芯片、上桥缓冲块和下桥芯片层叠布置，因此，能够减小功率模组的封装体积，提升系统功率，降低功率模组的寄生电感(例如，在相同的功率输出情况下，根据本公开实施例的垂直叠层封装结构的寄生电感可以做到5nH以内，而现有封装结构的电感则超出10nH)，提升功率模组的过流能力，增加功率模组的散热面积，从而能够有效地降低芯 片温度，有效地提高功率模组及系统的可靠性。
本公开的其他特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是根据现有技术的半桥结构封装的示意图。
图2是根据本公开一种实施例的功率模组的示意图。
图3示出了上桥基板的示意图。
图4示出了上桥芯片的集电极与上桥基板的连接方式示意图。
图5示出了热敏电阻、热敏电阻端子、信号传输端子和功率模组的输入正电极与上桥基板的连接方式示意图。
图6示出了键合线的示意图。
图7示出了上桥缓冲块与上桥芯片的发射极的连接方式示意图。
图8示出了输出电极与上桥缓冲块的连接方式示意图。
图9示出了下桥芯片的集电极与输出电极的连接方式示意图。
图10示出了下桥芯片的控制线、采样线与信号传输端子的连接方式示意图。
图11示出了下桥缓冲块与下桥芯片的发射极的连接方式示意图。
图12示出了功率模组的输入负电极与下桥基板的连接方式示意图。
图13示出了下桥基板与下桥缓冲块的连接方式示意图。
图14示出了上桥散热底板和下桥散热底板与上桥基板和下桥基板的连接方式示意图。
图15示出了塑封后的功率模组示意图。
图16示出了塑封后的功率模组的又一示意图。
图17是根据本公开一种实施例的功率模组的又一示意图。
图18是根据本公开一种实施例的功率模组的又一示意图。
图19是根据本公开一种实施例的功率模组的又一示意图。
图20是根据本公开一种实施例的功率模组的又一示意图。
图21是根据本公开一种实施例的功率模组的又一示意图。
图22是根据本公开一种实施例的功率模组的又一示意图。
附图标记说明
1：下桥散热底板；2：散热底板与基板、基板与芯片、芯片与缓冲块、缓冲块与电极、缓冲块与基板之间的焊接或烧结等连接层；3：下桥基板；4：下桥缓冲块；5：下桥芯片；6：输出电极；7：上桥缓冲块；8：上桥芯片；9：上桥基板；10：上桥散热底板；11：输入正电极；12：输入负电极；13：热敏电阻端子；14：键合线；15：热敏电阻；16：信号传输端子；17：塑封外壳；18：上桥密封圈；19：上桥散热水道；20：下桥密封圈；21：下桥散热水道；23：二合一水道；24：驱动板。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
现有的半桥结构封装主要有以下三种形式：
1)单管串联组成半桥结构：单管采用芯片下表面也即集电极C焊接到基板(Substrate)、芯片上表面也即发射极E邦线到基板、芯片门极G通过键合(bonding)连接到电极的方式完成结构封装，最终完成封装的模组再通过串联方式完成电气连接形成单面散热半桥结构。
2)单面散热半桥结构模组：利用基板沟槽形成上下桥臂各极间的电气隔绝，采用芯片下表面也即集电极C焊接到基板、芯片上表面也即发射极E邦线到基板、芯片门极G通过键合连接到电极的方式完成结构封装，同时通过键合完成上桥臂E与下桥臂C的连接，形成单面散热半桥结构。
3)双面散热半桥结构模组：采用芯片下表面也即集电极C焊接到基板1、芯片上表面也即发射极E焊接铜块、铜块再焊接到基板2、芯片门极G通过键合连接到电极的方式完成结构封装，形成双面散热半桥结构。
然而，这些封装结构的主电极均为平面设计结构也即输入电极和输出电极与基板面在同一平面上，上桥芯片和下桥芯片也是被布局在同一平面内，如图1所示。该结构的缺陷主要是寄生电感较高，从而会导致芯片结温较高，进而影响模块的可靠性。
现有的模块散热结构主要有以下三种：1)单面平板，也即基板与底板形成连接安装到散热器，通过平面底板进行散热；2)单面针翅(pinfin)，也即基板与带pinfin底板形成连接安装到散热器，通过pinfin底板散热；3)无底板双面散热，也即基板直接安装到散热器，通过双面基板进行散热。
上述三种封装均是采用平面横向连接结构形成上下桥连接半桥封装形式，由于单管模组是通过多个单管进行串并联形成所需半桥或其它电路结构，而集成模组是通过基板上放置多颗芯片进行串并联形成所需电路结构，因此无论是单管间的连接还是芯片间的邦线连接均会增加寄生电感，降低过流能力，同时由于上下桥芯片封装在同一平面，模组封装体积较大，而且散热面相对单一，可靠性能较差；且现有主电极布局在模块小型化设计中距离过近，存在安全距离隐患，无法满足高压应用需求；现有模块散热结构相对较低，无法满足更高功率密度及高温工作高效散热的需求。
图2是根据本公开一种实施例的功率模组的示意图。如图2所示，该功率模组包括上桥芯片8、上桥缓冲块7、下桥芯片5、输出电极6、热敏电阻15、键合线14、信号传输端子16和热敏电阻端子13，其中上桥芯片8、上桥缓冲块7和下桥芯片5层叠布置，其中：上桥芯片8的发射极通过上桥缓冲块7连接到输出电极6，下桥芯片5的集电极连接到输出电极6，上桥芯片8的发射极采样、集电极采样和控制端以及下桥芯片5的发射极采样、集电极采样和控制端分别通过各自的键合线14连接到信号传输端子16，以及热敏电阻15通过其键合线14连接到热敏电阻端子13。这里所说的上和下是相对的，但在本公开的实施例中，上桥芯片8的正面(发射极E/源极S)必须与下桥芯片5的背面(集电极C/漏极D)连接到同一输出电极6，且上桥芯片8和下桥芯片5不处于同一平面，例如分列输出电极6两面。
这里，信号传输端子16是用于信号的发送和接收，其用途包括但不限于控制、采样等。在图2的实施例中，信号端子16相当于是控制端子和采样端子的集合，例如，上桥芯片8和下桥芯片5都具有控制端，所以信号传输端子16中就会包括2个控制端子，其他的以此类推。
这里的键合线14也是所有键合线的集合，例如其包括上桥芯片8的发射极采样连接到信号传输端子16的键合线、下桥芯片5的发射极采样引出的信号传输端子16的键合线等等。
这里的上桥缓冲块7起到电气连接、增加散热路径热容以提升散热效率、为键合线提供引出空间等作用。例如，上桥缓冲块7可以是铜块、钼块等等。下文中描述的其他缓冲块的功能与上桥缓冲块7的功能类似。本领域技术人员能够理解，缓冲块与芯片之间并非完全贴合，仅在必要的地方例如电极等位置相接触，在缓冲块和芯片之间未接触的位置按照电路的布局需要留出避空(clearance)。
另外，在本公开中，为了描述的方便，将上桥芯片8和下桥芯片5的三个端子都是描述为发射极、集电极和控制端。但是本领域技术人员应当理解的是，上桥芯片8和下桥芯片5可以是IGBT类型的器件、MOS型器件或者其他类型的器件。
通过采用上述技术方案，由于上桥芯片8、上桥缓冲块7和下桥芯片5层叠布置，因此，能够减小功率模组的封装体积，提升系统功率，降低功率模组的寄生电感(例如，在相同的功率输出情况下，根据本公开实施例的垂直叠层封装结构的寄生电感可以做到5nH以内，而现有封装结构的电感则超出10nH)，提升功率模组的过流能力，增加功率模组的散热面积，从而能够有效地降低芯片温度，有效地提高功率模组及系统的可靠性。
继续参考图2，根据本公开实施例的功率模组还包括输入正电极11、输入负电极12、第一连接层201、上桥基板9、第二连接层202、上桥散热底板10、第三连接层203、第四连接层204、下桥缓冲块4、第五连接层205、下桥基板3、第六连接层206和下桥散热底板1，其中，上桥散热底板10、上桥基板9、上桥芯片8、上桥缓冲块7、下桥芯片5、下桥缓冲块4、下桥基板3和下桥散热底板1在与芯片相垂直的方向上层叠布置，其中：
上桥芯片8的集电极与上桥基板9连接，上桥基板9通过第二连接层202与上桥散热底板10连接，上桥芯片8通过第三连接层203与上桥缓冲块7连接，下桥芯片5的发射极通过第四连接层204与下桥缓冲块4连接，下桥缓冲块4通过第五连接层205与下桥基板3连接，下桥基板3通过第六连接层206与下桥散热底板1连接。优选地，上桥芯片8的集电极通过第一连接层201与上桥基板9连接。上述第一至第六各个连接层例如分别是散热底板与基板、基板与芯片、芯片与缓冲块、缓冲块与电极、缓冲块与基板之间的焊接或烧结等连接层，用于上述各个部件之间的连接，并且有助于散热。
上桥散热底板10和下桥散热底板1可以为带pinfin散热底板或其他类型的散热底板。
上桥基板9和下桥基板3可以为陶瓷基板，例如覆铜陶瓷基板(例如氮化铝覆铜陶瓷基板、氧化铝覆铜陶瓷基板等)、活性金属钎焊陶瓷基板等等，而且陶瓷上下覆铜的厚度是可调整的。图3示出了上桥基板9的示意图。
上桥芯片8的集电极被焊接或烧结到上桥基板9上，如图4所示。
热敏电阻15、热敏电阻端子13、信号传输端子16和功率模组的输入正电极11被焊接或烧结到上桥基板9上，如图5所示。
图6示出了键合线14的示意图。如图6所示，上桥芯片8的发射极采样、集电极采样和控制端分别通过各自的键合线14连接到信号传输端子16；热敏电阻15通过其键合线14连接到热敏电阻端子13。
上桥缓冲块7被焊接或烧结到上桥芯片8的发射极上，如图7所示。这增加了散热面积，更利于芯片的散热。
输出电极6被焊接或烧结到上桥缓冲块7上，如图8所示。
下桥芯片5的集电极被焊接或烧结到输出电极6上，形成上下桥垂直通路，显著降低回路电感，如图9所示。图10则示出了下桥芯片5的控制端、采样端与信号传输端子16的连接方式示意图，也即，下桥芯片5的控制端、采样端(也即集电极采样、发射极采样)通过键合线14连接到信号传输端子16上。
下桥缓冲块4被焊接或烧结到下桥芯片5的发射极上，如图11所示，这增加了散热面积，更有利于芯片的散热。
功率模组的输入负电极12被焊接或烧结到下桥基板3上，如图12所示。
下桥基板3被焊接或烧结到下桥缓冲块4上，如图13所示。
上桥基板9的背面以及下桥基板3的背面分别被焊接或烧结到上桥散热底板10和下桥散热底板1，如图14所示。这种双面散热底板显著增加了散热面积，提升了散热效率。此处所述的“背面”指的是基板的未表征有电路元器件的一面，或称非器件面。相应地，基板的表征有电路元器件的一面称为基板的正面，或称元器件面。
图15示出了塑封后的功率模组示意图。其中，塑封外壳17用于实现模块保护和机械支撑。塑封的高温工作特效为模块的应用环境得到显著提升。
通过上面的描述可以看出，现有结构均是芯片横向串联排布，电流通过芯片垂直传递后通过连接部进行横向流动；根据本公开实施例的功率模组的结构为垂直传递结构，芯片层叠堆栈，减小电流流动路径，电流垂直上下流动，大大降低回路寄生电感，同时芯片与基板、缓冲块、基板形成叠层结构，芯片可以通过多个基板与缓冲块进行散热，散热效率极大提高，同一工况下芯片的工作温度较低，可靠性明显提升，使用寿命增加。同时，功率模组两面均为散热底板，应用时可通过两面进行高效散热，显著降低了芯片工作时的温度，提升了芯片工作可靠性及工作寿命。另外，散热底板结构是将基板与散热底板通过焊接或烧结方式进行连接，基板与散热底板之间热阻显著降低，且在功率模组的两面均引入散热结构，进一步提升散热效率，为封装模组小型化提供了散热基础。
图16示出了塑封后的功率模组的又一示意图。如图16所示，在该结构中，热敏电阻端子13和信号传输端子16为弯折结构，例如，可以进行90度弯折但弯折方向不限制，使得其可根据散热水道及应用环境进行实用性匹配。也即，热敏电阻端子13和信号传输端子16可以被弯折成与例如散热水道的外形相匹配的形状，这样，在进行组装时，热敏电阻端子13和 信号传输端子16的弯折结构就可以与散热水道的、与热敏电阻端子13和信号传输端子16的弯折结构相接触的区域进行形状适配，节省安装空间。
图17是根据本公开一种实施例的功率模组的又一示意图。如图17所示，上桥芯片8和下桥芯片5为纵向放置，而在前面的实施例中，上桥芯片8和下桥芯片5为横向放置。在本公开中，横向指的是图17中的功率模组的左右方向，纵向指的是其前后方向。通过纵向放置，使得能够在不改变封装体积的情况下在左右方向上放置更多的上桥芯片8和下桥芯片5，因此为增加输出能力提供了可能性。
图18是根据本公开一种实施例的功率模组的又一示意图。如图18所示，功率模组的输入正电极11的安装平面和功率模组的输入负电极12的安装平面位于不同的水平面上。如果输入正电极11的安装平面和输入负电极12的安装平面位于同一水平面上，则输入正电极11和输入负电极12之间的间隔就会较小，而通过将输入正电极11的安装平面和输入负电极12的安装平面放置在不同的水平面上，使得输入正电极11和输入负电极12之间的距离大大增加，进而安全距离也就增加了，从而大大提升了功率模组的电压安全等级，而电压安全等级越高，则应用电压平台范围就越大，使得根据本公开实施例的功率模组能够适用于更多的应用场景。在本公开中，安全距离指的是输入正电极11和输入负电极12之间的空中距离。
图19是根据本公开一种实施例的功率模组的又一示意图。图19与图18类似，区别在于，输入正电极11的安装平面和输入负电极12的安装平面位于不同的平面上且均与水平面成90°，也即，如图19所示，输入正电极11的安装平面和输入负电极12的安装平面是沿着纵向方向延伸的，这增加了输入正电极11和输入负电极之间的安全距离，提升了功率模组的电压安全等级及应用电压平台范围。
图20是根据本公开一种实施例的功率模组的又一示意图。如图20所示，根据本公开实施例的功率模组还包括上桥散热水道19和下桥散热水道21，其中：上桥散热底板10与上桥散热水道19安装在一起，下桥散热底板1与下桥散热水道21安装在一起。在一个实施例中，上桥散热底板10可以通过上桥密封圈18与上桥散热水道19安装，下桥散热底板1可以通 过下桥密封圈20与下桥散热水道21安装，而且，上桥散热水道19和下桥散热水道21通过紧固件(例如螺钉)进行紧固。通过散热水道，能够进行散热，而且，通过如此配置，使得散热底板上的pinfin能够直接接触散热水道中的冷却介质，散热效率相对较高。
图21是根据本公开一种实施例的功率模组的又一示意图。图21与图20的区别在于，多个功率模组层叠布置。在图21中，多个功率模组在与芯片垂直的方向上层叠布置。在这种情况下，对于相邻的两个功率模组而言，位于下方的功率模组的下桥散热水道21和位于上方的功率模组的上桥散热水道19形成二合一水道23，该二合一水道23为内部被分隔成上下2个独立水道空间的独立水道，这两个独立水道空间能够分别用于对各自两侧的散热底板进行散热，而且这两个独立水道空间互不影响各自的散热。通过如此布置，显著减小了功率模组和散热水道的安装体积，提升了功率密度，增加了系统体积密度。另外，本公开中提及的各个散热水道可以共用同一个入水口以及共用同一个出水口，但是各个散热水道的内部空间是各自独立的。当然，入水口、出水口不共用也是可行的。
图22是根据本公开一种实施例的功率模组的又一示意图。如图22所示，根据本公开实施例的功率模组还包括驱动板24。该驱动板24用于驱动功率模组三相桥臂芯片的开通和关断。驱动板24布置在信号传输端子16中的控制端子一侧，而且驱动板24在控制端子位置预留接口，以便控制端子能够接入驱动板24，同时还需要避开输出电极6的位置，以便于输出接线。驱动板24可以布置在上面描述的上桥散热水道19和下桥散热水道21的侧边上，这样就能够使得驱动板24与整个功率模组系统融合为一体，不增大功率模组的体积。
以上结合附图详细描述了本公开的优选实施方式，但是，本公开并不限于上述实施方式中的具体细节，在本公开的技术构思范围内，可以对本公开的技术方案进行多种简单变型，这些简单变型均属于本公开的保护范围。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特 征，在不矛盾的情况下，可以通过任何合适的方式进行组合。为了避免不必要的重复，本公开对各种可能的组合方式不再另行说明。
此外，本公开的各种不同的实施方式之间也可以进行任意组合，只要其不违背本公开的思想，其同样应当视为本公开所公开的内容。

Claims (19)

  1. 一种功率模组，其特征在于，该功率模组包括输入正电极(11)、输入负电极(12)、上桥基板(9)、下桥基板(3)、上桥芯片(8)、下桥芯片(5)、输出电极(6)和信号传输端子(16)，其中所述上桥基板(9)、所述上桥芯片(8)、所述下桥芯片(5)和所述下桥基板(3)依次层叠布置，且其中：
    所述上桥芯片(8)的集电极与所述上桥基板(9)连接，所述上桥芯片(8)的发射极与所述下桥芯片(5)的集电极分别连接到所述输出电极(6)，所述上桥芯片(8)的发射极采样、集电极采样和控制端以及所述下桥芯片(5)的发射极采样、集电极采样和控制端分别连接到所述信号传输端子(16)，所述输入正电极(11)连接到所述上桥基板(9)上，所述输入负电极(12)连接到所述下桥基板(3)上。
  2. 根据权利要求1所述的功率模组，其特征在于，该功率模组还包括上桥缓冲块(7)和第三连接层(203)，所述上桥芯片(8)、所述上桥缓冲块(7)和所述下桥芯片(5)层叠布置，所述上桥芯片(8)通过所述第三连接层(203)与所述上桥缓冲块(7)连接，所述上桥芯片(8)的发射极通过所述上桥缓冲块(7)连接到所述输出电极(6)。
  3. 根据权利要求2所述的功率模组，其特征在于，该功率模组还包括下桥缓冲块(4)、第四连接层(204)以及第五连接层(205)，其中所述上桥芯片(8)、所述上桥缓冲块(7)、所述下桥缓冲块(4)和所述下桥芯片(5)层叠布置，所述下桥芯片(5)的集电极连接到所述输出电极(6)，所述下桥芯片(5)的发射极通过所述第四连接层(204)与所述下桥缓冲块(4)连接，所述下桥缓冲块(4)通过所述第五连接层(205)与所述下桥基板(3)连接。
  4. 根据权利要求3所述的功率模组，其特征在于，所述功率模组还包括第二连接层(202)和上桥散热底板(10)，其中，所述上桥散热底板(10)、所述上桥基板(9)、所述上桥芯片(8)、所述上桥缓冲块(7)、所述下桥芯片 (5)、所述下桥缓冲块(4)和所述下桥基板(3)依次层叠布置，其中：
    所述上桥基板(9)通过所述第二连接层(202)与所述上桥散热底板(10)连接。
  5. 根据权利要求4所述的功率模组，其特征在于，所述功率模组还包括第六连接层(206)和下桥散热底板(1)，其中，所述上桥散热底板(10)、所述上桥基板(9)、所述上桥芯片(8)、所述上桥缓冲块(7)、所述下桥芯片(5)、所述下桥缓冲块(4)、所述下桥基板(3)和所述下桥散热底板(1)依次层叠布置，其中：
    所述下桥基板(3)通过所述第六连接层(206)与所述下桥散热底板(1)连接。
  6. 根据权利要求5所述的功率模组，其特征在于，
    所述上桥基板(9)的背面以及所述下桥基板(3)的背面分别被焊接或烧结到所述上桥散热底板(10)和所述下桥散热底板(1)。
  7. 根据权利要求1至6中任一项所述的功率模组，其特征在于，所述上桥芯片(8)、所述输出电极(6)和所述下桥芯片(5)依次层叠布置。
  8. 根据权利要求1至6中任一项所述的功率模组，其特征在于，所述功率模组还包括第一连接层(201)，所述上桥芯片(8)的集电极通过所述第一连接层(201)与所述上桥基板(9)连接。
  9. 根据权利要求1至6中任一项所述的功率模组，其特征在于，该功率模组还包括热敏电阻(15)、和热敏电阻端子(13)，所述热敏电阻(15)通过其键合线(14)连接到所述热敏电阻端子(13)。
  10. 根据权利要求9所述的功率模组，其特征在于，所述热敏电阻端子(13)和所述信号传输端子(16)为弯折结构。
  11. 根据权利要求1至10中任一项所述的功率模组，其特征在于，所述上桥芯片(8)和所述下桥芯片(5)为横向放置。
  12. 根据权利要求1至10中任一项所述的功率模组，其特征在于，所述上桥芯片(8)和所述下桥芯片(5)为纵向放置。
  13. 根据权利要求5至12中任一项所述的功率模组，其特征在于，所述输入正电极(11)的安装平面和所述输入负电极(12)的安装平面位于不同的水平面上。
  14. 根据权利要求5至13中任一项所述的功率模组，其特征在于，所述输入正电极(11)的安装平面和所述输入负电极(12)的安装平面位于不同的平面上且均与水平面成90°。
  15. 根据权利要求5至14中任一项所述的功率模组，其特征在于，所述功率模组还包括上桥散热水道(19)和下桥散热水道(21)，其中：
    所述上桥散热底板(10)与所述上桥散热水道(19)安装在一起，所述下桥散热底板(1)与所述下桥散热水道(21)安装在一起。
  16. 根据权利要求15所述的功率模组，其特征在于，所述上桥散热底板(10)通过上桥密封圈(18)与所述上桥散热水道(19)安装在一起，所述下桥散热底板(1)通过下桥密封圈(20)与所述下桥散热水道(21)安装在一起，而且，所述上桥散热水道(19)和所述下桥散热水道(21)通过紧固件进行紧固。
  17. 根据权利要求16所述的功率模组，其特征在于，在多个所述功率模组在与所述芯片相垂直的方向上层叠布置的情况下，对于相邻的两个功率模组而言，位于下方的功率模组的下桥散热水道(21)和位于上方的功率模组的上桥散热水道(19)形成二合一水道(23)，所述二合一水道(23)为内部被分 隔成上下2个独立水道空间的独立水道。
  18. 根据权利要求16或17所述的功率模组，所述功率模组还包括驱动板(24)，其特征在于，所述驱动板(24)布置在所述上桥散热水道(19)和所述下桥散热水道(21)的侧边上且靠近所述信号传输端子(16)中的控制端子一侧。
  19. 根据权利要求1至6中任一项所述的功率模组，其特征在于，所述上桥芯片(8)的发射极采样、集电极采样和控制端以及所述下桥芯片(5)的发射极采样、集电极采样和控制端通过各自的键合线(14)连接到所述信号传输端子(16)。
PCT/CN2021/141373 2020-12-25 2021-12-24 功率模组 WO2022135595A1 (zh)

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