WO2022128817A3 - Verfahren zur herstellung eines vorbehandelten verbundsubstrats und vorbehandeltes verbundsubstrat - Google Patents

Verfahren zur herstellung eines vorbehandelten verbundsubstrats und vorbehandeltes verbundsubstrat Download PDF

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Publication number
WO2022128817A3
WO2022128817A3 PCT/EP2021/085294 EP2021085294W WO2022128817A3 WO 2022128817 A3 WO2022128817 A3 WO 2022128817A3 EP 2021085294 W EP2021085294 W EP 2021085294W WO 2022128817 A3 WO2022128817 A3 WO 2022128817A3
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WIPO (PCT)
Prior art keywords
substrate
composite substrate
pretreated composite
producing
layer
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PCT/EP2021/085294
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English (en)
French (fr)
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WO2022128817A2 (de
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Constantin Csato
Florian Krippendorf
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mi2-factory GmbH
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Priority to JP2023535861A priority Critical patent/JP2023553476A/ja
Priority to EP21836127.7A priority patent/EP4264658A2/de
Priority to US18/267,564 priority patent/US20240055251A1/en
Publication of WO2022128817A2 publication Critical patent/WO2022128817A2/de
Publication of WO2022128817A3 publication Critical patent/WO2022128817A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Physical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Das Verfahren zur Herstellung eines vorbehandelten Verbundsubstrats (18), das als Basis für die Weiterverarbeitung zu elektronischen Halbleiterbauelementen dient, umfasst das Dotieren einer ersten Schicht (21) aus SiC in einem Spendersubstrat (12) mittels Ionenimplantation unter Verwendung eines Energiefilters (20), das Erzeugen einer Sollbruchstelle (26) im Spendersubstrat (12) und das Herstellen einer Bondverbindung zwischen Spendersubstrat (12) und Akzeptorsubstrat (28), die erste Schicht (21) in einem Bereich zwischen dem Akzeptorsubstrat (28) und einem restlichen Teil (22) des Spendersubstrats (12) angeordnet ist. Schließlich wird das Spendersubstrat (12) im Bereich der Sollbruchstelle (26) zur Erzeugung des vorbehandelten Verbundsubstrats (18) gespalten, wobei das vorbehandelte Verbundsubstrat (18) das Akzeptorsubstrat (28) und eine damit verbundene dotierte Schicht (32), die zumindest einen Abschnitt der ersten Schicht (21) des Spendersubstrats (12) umfasst, aufweist.
PCT/EP2021/085294 2020-12-18 2021-12-10 Verfahren zur herstellung eines vorbehandelten verbundsubstrats und vorbehandeltes verbundsubstrat WO2022128817A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2023535861A JP2023553476A (ja) 2020-12-18 2021-12-10 前処理された複合基板の製造方法、および前処理された複合基板
EP21836127.7A EP4264658A2 (de) 2020-12-18 2021-12-10 Verfahren zur herstellung eines vorbehandelten verbundsubstrats und vorbehandeltes verbundsubstrat
US18/267,564 US20240055251A1 (en) 2020-12-18 2021-12-10 Method for producing a pretreated composite substrate, and pretreated composite substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102020134222.5A DE102020134222A1 (de) 2020-12-18 2020-12-18 Verfahren zur Herstellung eines vorbehandelten Verbundsubstrats und vorbehandeltes Verbundsubstrat
DE102020134222.5 2020-12-18

Publications (2)

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WO2022128817A2 WO2022128817A2 (de) 2022-06-23
WO2022128817A3 true WO2022128817A3 (de) 2022-08-18

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PCT/EP2021/085294 WO2022128817A2 (de) 2020-12-18 2021-12-10 Verfahren zur herstellung eines vorbehandelten verbundsubstrats und vorbehandeltes verbundsubstrat

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US (1) US20240055251A1 (de)
EP (1) EP4264658A2 (de)
JP (1) JP2023553476A (de)
DE (1) DE102020134222A1 (de)
WO (1) WO2022128817A2 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014103518A1 (de) * 2013-03-14 2014-09-18 Infineon Technologies Ag Ein verfahren zum herstellen eines siliziumkarbidsubstrats für eine elektrische siliziumkarbidvorrichtung, ein siliziumkarbidsubstrat und eine elektrische siliziumkarbidvorrichtung
US20190122850A1 (en) * 2016-04-04 2019-04-25 mi2-factory GmbH Energy filter element for ion implantation systems for the use in the production of wafers
DE102019112985A1 (de) * 2019-05-16 2020-11-19 mi2-factory GmbH Verfahren zur Herstellung von Halbleiterbauelementen

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015112649B4 (de) 2015-07-31 2021-02-04 Infineon Technologies Ag Verfahren zum bilden eines halbleiterbauelements und halbleiterbauelement
DE102017127169B4 (de) 2017-11-17 2022-01-27 Infineon Technologies Ag Verfahren zur herstellung eines halbleiterbauelements
DE102018102415B4 (de) 2018-02-02 2022-09-01 Infineon Technologies Ag Waferverbund und verfahren zur herstellung eines halbleiterbauteils

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014103518A1 (de) * 2013-03-14 2014-09-18 Infineon Technologies Ag Ein verfahren zum herstellen eines siliziumkarbidsubstrats für eine elektrische siliziumkarbidvorrichtung, ein siliziumkarbidsubstrat und eine elektrische siliziumkarbidvorrichtung
US20190122850A1 (en) * 2016-04-04 2019-04-25 mi2-factory GmbH Energy filter element for ion implantation systems for the use in the production of wafers
DE102019112985A1 (de) * 2019-05-16 2020-11-19 mi2-factory GmbH Verfahren zur Herstellung von Halbleiterbauelementen

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KRIPPENDORF ET AL: "Dotierung von SiC mittels Energiefilter fuer Ionenimplantation", 6 October 2015, MIKROSYSTEMTECHNIK 2015; 4 (CONFERENCE INFO: MIKROSYSTEMTECHNIK 2015 - MIKROSYSTEMTECHNIK KONGRESS 2015; 2015; KARLSRUHE, DEUTSCHLAND),, PAGE(S) 334 - 337, XP009194563 *

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WO2022128817A2 (de) 2022-06-23
EP4264658A2 (de) 2023-10-25
JP2023553476A (ja) 2023-12-21
DE102020134222A1 (de) 2022-06-23
US20240055251A1 (en) 2024-02-15

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