WO2022121408A1 - 一种多层半导体材料结构及制备方法 - Google Patents

一种多层半导体材料结构及制备方法 Download PDF

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WO2022121408A1
WO2022121408A1 PCT/CN2021/117424 CN2021117424W WO2022121408A1 WO 2022121408 A1 WO2022121408 A1 WO 2022121408A1 CN 2021117424 W CN2021117424 W CN 2021117424W WO 2022121408 A1 WO2022121408 A1 WO 2022121408A1
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layer
thin film
device functional
semiconductor material
functional layer
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French (fr)
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母凤文
王鑫华
黄森
魏珂
刘新宇
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中国科学院微电子研究所
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds

Definitions

  • the present application belongs to the technical field of semiconductors, and particularly relates to a multilayer semiconductor material structure and a preparation method.
  • Gallium oxide (Ga 2 O 3 ) crystal is a new type of ultra-wide band gap semiconductor material. Compared with common third-generation semiconductors, it has a larger band gap and higher electric field breakdown strength. The figure of merit is 4 times that of GaN and more than 10 times that of SiC. Therefore, under the condition of reaching the same withstand voltage, the theoretical on-resistance of the unipolar device using Ga 2 O 3 is only 1/10 of that of SiC and 1/3 of that of GaN, which is beneficial to reduce the conduction of the power supply circuit. power loss, maximizing the power density of the device.
  • the Ga 2 O 3 single crystal substrate can be grown by the solution method, which has obvious advantages compared with SiC and GaN in terms of preparation cost.
  • Ga 2 O 3 material has low preparation cost and excellent device performance, the extremely low thermal conductivity (10-25W/mK) of Ga 2 O 3 material itself will cause severe local self-heating during device operation, resulting in faster device Deterioration and shorter working life will greatly limit its application under high power conditions, especially the thermal conductivity of Ga2O3 - based materials will be further reduced due to size effects, doping and alloying. Therefore, how to realize the effective heat dissipation of Ga2O3 devices is one of the main challenges to make it widely used.
  • the current research on Ga 2 O 3 devices is mainly focused on the improvement of electrical performance, and only a few studies on thermal performance and thermal management have been reported. A very promising solution is the heterointegration of Ga2O3 with highly thermally conductive substrates.
  • MJTadjer et al. transferred the (100) plane Ga 2 O 3 nanoribbons to a single crystal diamond substrate by mechanical exfoliation, and fabricated a Ga 2 O 3 nanofilm field effect transistor; although the Ga 2 O 3 nanofilm Weak van der Waals bonding with the diamond substrate results in a very low interfacial thermal conductance (17MW/m 2 K), but benefiting from the ultra-high thermal conductivity of diamond, the DC power density of Ga 2 O 3 devices reaches 60W/mm.
  • the method of mechanically exfoliating transferred nanoribbons is only suitable for stand-alone devices, and cannot meet the requirements for mass production and large - scale application of Ga2O3 devices.
  • Z. Cheng et al. tried to directly grow Ga 2 O 3 on single crystal diamond by atomic layer deposition method, and realized a high thermal conductivity interface between Ga 2 O 3 and diamond.
  • the atomic layer deposition method can directly grow Ga 2 O 3 and achieve a high thermal conductivity interface, the crystalline quality of the Ga 2 O 3 film is very poor, it is a nano-polycrystalline structure, and its thermal conductivity is close to that of amorphous Ga 2 O 3 , which is difficult to achieve. for device fabrication.
  • F. Mu et al. realized the surface-activated room temperature hetero-bonding integration of 2-inch Ga 2 O 3 single crystal substrate and SiC substrate, and combined with ion implantation and lift-off technology to realize the transfer of single crystal gallium oxide film.
  • the surface-activated room temperature bonding process can achieve very heterogeneous integration of gallium oxide, but the bonding process is complicated, the cost is high, and it is easy to introduce interface defects.
  • materials such as silicon, silicon carbide, GaN, alumina, germanium, carbon, AlN, ZnO, GaAs, and AlGaN also have similar problems of poor heat dissipation.
  • the present application aims to provide a multi-layer semiconductor material structure and a preparation method to solve the problems of poor heat dissipation, high cost, and inability to mass-produce semiconductor materials in the prior art.
  • the present application provides a multi-layer semiconductor material structure, comprising a high thermal conductivity supporting substrate and a crystallized device functional layer; the device functional layer is disposed on the high thermal conductivity supporting substrate, and the device functional layer
  • the surface layer has a single crystal structure.
  • the crystal structure of the functional layer of the device has a microstructural gradient from single crystal to polycrystalline from the surface to the interface;
  • the crystal structure of the device functional layer is that the part of the device functional layer near the surface and the interface is single crystal, and the part of the surface and the interface tending to the middle is a microstructure gradient from single crystal to polycrystalline.
  • the device functional layer is a single-layer structure composed of one of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN materials, with a thickness of At 100nm-50um.
  • the device functional layer includes a first thin film layer and a second thin film layer; the first thin film layer is disposed on the high thermal conductivity supporting substrate, and the second thin film layer is disposed on the first thin film layer. on a thin film layer;
  • the first thin film layer is one of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, SiN, SiO 2 , HfO 2 , SiNO, SiCO, and AlON materials
  • the single-layer structure formed or the composite layer structure formed by a variety of structures has a thickness of 100nm-50um;
  • the second thin film layer is a single-layer structure or a composite layer structure composed of multiple materials, such as gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN materials,
  • the thickness is 100nm-50um.
  • the high thermal conductivity supporting substrate material is one or more composites of diamond, SiC, AlN, BN, BeO, AlSiC, CuW, and CuMo.
  • the present application provides a method for preparing a multilayer semiconductor material structure, comprising the following steps:
  • a single crystal substrate is attached to the surface of the device functional layer
  • the single crystal substrate is peeled off to obtain the multi-layer semiconductor material structure.
  • the method of forming the device functional layer on the high thermal conductivity support substrate is one or more of chemical vapor deposition, atomic layer deposition, molecular beam deposition, HVPE, physical sputtering, plasma enhanced CVD kind.
  • the device functional layer includes a first thin film layer and a second thin film layer
  • Forming the device functional layer on the high thermal conductivity supporting substrate is as follows: depositing a first thin film layer with a thickness of 100nm-50um on the high thermal conductivity supporting substrate; then flattening and smoothing it, and then depositing a second thin film layer, The thickness is 100nm-50um.
  • the functional layer of the device is a single-layer thin film layer with a thickness of 100-50um. After the thin film layer is formed on the high thermal conductivity supporting substrate, it is planarized and smoothed, and then the thin film layer is smoothed. A single crystal substrate is attached to the surface of the back film layer.
  • the device functional layer is planarized and smoothed, and the surface roughness is between 0.1 nm and 10 nm.
  • the device functional layer of the multi-layer semiconductor material structure of the present application is arranged on a high thermal conductivity supporting substrate, and the device functional layer is an at least partially crystallized thin film layer, and the near-surface layer of the device functional layer is a single crystal structure, and the structure of the present application not only forms The high thermal conductivity interface is improved, the heat dissipation efficiency of the device functional film layer is improved, and the practicability of the device functional layer is guaranteed at the same time.
  • the device functional layer includes a first thin film layer and a second thin film layer; the first thin film layer has a thermal expansion coefficient closer to the high thermal conductivity substrate and a higher chemical Affinity ability.
  • FIG. 1 is a schematic diagram of a high thermal conductivity supporting substrate
  • FIG. 2 is a schematic diagram of a preparation process of a multilayer semiconductor material structure according to an embodiment
  • FIG. 3 is a schematic diagram of a manufacturing process of a multilayer semiconductor material structure according to another embodiment
  • FIG. 4 is a schematic diagram of a manufacturing process of a multilayer semiconductor material structure according to another embodiment
  • FIG. 6 is a schematic cross-sectional view of the multilayer semiconductor material structure after patterning and etching
  • FIG. 7 is a schematic cross-sectional view of another multilayer semiconductor material structure after patterning and etching
  • FIG. 8 is a schematic cross-sectional view of another multilayer semiconductor material structure after patterning and etching
  • FIG. 9 is a schematic plan view of the multi-layer semiconductor material structure after patterning and etching.
  • 1-high thermal conductivity supporting substrate 101-first surface; 102-second surface; 2-device function layer; 201-first thin film layer; 202-second thin film layer; 3-single crystal substrate.
  • a layer/element when referred to as being "on" another layer/element, it can be directly on the other layer/element, or intervening layers may be present therebetween /element.
  • a layer/element when a layer/element is “on” another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under” the other layer/element.
  • a multi-layer semiconductor material structure includes a high thermal conductivity supporting substrate 1 and a crystallized device functional layer 2; the device functional layer 2 is arranged on the high thermal conductivity supporting substrate 1, and the near-surface layer of the device functional layer 2 is a single crystal structure.
  • the crystal structure of the crystallized device functional layer 2 has a microstructure gradient from single crystal to polycrystalline from the surface to the interface, and the surface layer near the surface has a high-quality single crystal structure with a fixed orientation, such as [0001], [ 001], [111], [110], etc.
  • the device functional layer 2 of the multi-layer semiconductor material structure of the present application is arranged on the high thermal conductivity supporting substrate 1, and the device functional layer 2 is an at least partially crystallized thin film layer, and the near-surface layer of the device functional layer 2 is a single layer.
  • the structure of the present application not only forms a high thermal conductivity interface, improves the heat dissipation efficiency of the device functional layer 2, but also ensures the practicability of the device functional layer 2, which can be used for device fabrication.
  • the material of the high thermal conductivity supporting substrate 1 is one or more composites of diamond, SiC, AlN, BN, BeO, AlSiC, CuW, and CuMo.
  • the crystal form and orientation are not limited, and can be single crystal, polycrystalline and amorphous.
  • the crystal structure of the crystallized device functional layer 2 is that the part of the device functional layer 2 near the surface and the interface is single crystal, and the part of the surface and the interface toward the middle is from single crystal to polycrystalline microstructural gradient.
  • the highly thermally conductive support substrate 1 includes a first surface 101 and a second surface 102 .
  • the roughness of the first surface 101 is less than 1000 nm. If the surface is too rough, the subsequent process cost will be high.
  • the roughness of the second surface 102 of the substrate is 1nm-20um.
  • the device functional layer 2 is one layer, and the material is one of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN and other materials. single-layer structure.
  • the device functional layer 2 in order to enhance the interface adsorption force, release the stress and enhance the interface thermal conductivity, includes a first thin film layer 201 and a second thin film layer 202;
  • the supporting substrate 1 has a closer thermal expansion coefficient and higher chemical affinity, and is arranged on the high thermal conductivity supporting substrate 1, with a thickness of 100nm-50um, and the second thin film layer 202 is arranged on the first thin film layer 201, with a thickness of 100nm-50um.
  • the first thin film layer 201 is one of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN, SiN, SiO 2 , HfO 2 , SiNO, SiCO, AlON and other materials
  • the second thin film layer 202 is gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, AlGaN
  • the present application also provides a method for preparing a multilayer semiconductor material structure, comprising the following steps:
  • a single crystal substrate 3 is attached to the surface of the device functional layer 2;
  • the single crystal substrate 3 is peeled off to obtain a multi-layer semiconductor material structure.
  • a single crystal substrate 3 with low defect density is attached to the surface of the device functional layer 2 as an initial substrate for nucleation, and then heat annealing is performed, and the surface layer of the device functional layer 2 will follow the nucleation.
  • the surface of the initial substrate undergoes solid-phase epitaxial crystallization, and the orientation is consistent with that of the initial nucleation substrate; after cooling, the initial nucleation substrate (ie, the single crystal substrate 3) is peeled off and removed, and the crystallized device functional layer 2 crystal structure is removed from the surface.
  • the initial nucleation substrate ie, the single crystal substrate 3
  • the crystallized device functional layer 2 crystal structure is removed from the surface.
  • There is a microstructural gradient from single crystal to polycrystalline at the interface and the surface layer near the surface has a high-quality single crystal structure.
  • the preparation method of the present application is simple, and a single crystal structure is formed on the surface layer of the device functional layer 2, which ensures the practicability of the device functional layer 2 and can be used
  • the crystal structure of the crystallized device functional layer 2 at this time is: The parts of the device functional layer 2 near the surface and the interface are all single crystals, and the parts of the surface and the interface tending to the middle are the microstructure gradient from single crystal to polycrystalline.
  • the material of the single crystal substrate 3 may be sapphire, the thickness of the single crystal substrate 3 is in the range of 50um-1000um, and the surface roughness is between 0.1nm-10nm, ensuring sufficient contact with the surface of the device functional layer 2 .
  • the method for forming the device functional layer 2 on the high thermal conductivity supporting substrate 1 is one or more of chemical vapor deposition, atomic layer deposition, molecular beam deposition, HVPE, physical sputtering, and plasma enhanced CVD.
  • the device functional layer 2 is planarized and smoothed so that the surface roughness of the device functional layer 2 is between 0.1 nm and 10 nm.
  • the specific operations of planarization and smoothing are: chemical mechanical polishing and plasma treatment.
  • the annealing temperature is 300-1800°C.
  • the heating and annealing rate is not higher than 50°C/min, and the holding time is 5-100min.
  • a high thermal conductivity support substrate 1 is first provided, and a device functional layer 2 is deposited on the first surface 101 of the high thermal conductivity support substrate 1, which is gallium oxide, silicon, carbide, etc.
  • a single-layer structure composed of one of silicon, GaN, alumina, germanium, carbon, AlN, ZnO, GaAs, AlGaN and other materials. The thickness is between 100nm-50um, the crystal structure is amorphous, and then it is flattened and smoothed to make its surface roughness between 0.1nm-10nm, the thickness after flattening and smoothing is 50nm-45um, and then Annealing is performed to crystallize it.
  • the device functional layer 2 includes a first thin film layer 201 and a second thin film layer 202 .
  • a high thermal conductivity support substrate 1 is provided, and a first thin film layer 201 is deposited on the first surface 101 of the high thermal conductivity support substrate 1.
  • the first thin film layer 201 is made of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, A single-layer structure or a multi-layer composite layer structure composed of one of germanium, carbon, AlN, ZnO, GaAs, AlGaN, SiN, SiO 2 , HfO 2 , SiNO, SiCO, AlON and other materials; the first The thickness of the thin film layer 201 is 100nm-50um, and the crystal structure is amorphous; then it is flattened and smoothed to make its surface roughness between 0.1nm-50nm; then a second thin film layer 202 is deposited and processed The surface is smoothed, and the second thin film layer 202 is a single-layer structure composed of one of gallium oxide, silicon, silicon carbide, GaN, aluminum oxide, germanium, carbon, AlN, ZnO, GaAs, and AlGaN materials or a multi-layer structure composed of multiple materials.
  • the composite layer structure of the layer is between 100nm-50um, the surface roughness is between 0.1nm-10nm; then annealing to make it crystallized, the crystallized thin layer crystal structure has a range from single crystal to interface from the surface to the interface.
  • the microstructure gradient of polycrystalline, the crystal near the surface layer is a high-quality single crystal structure, and has a fixed orientation, such as [0001], [001], [111], [110] and so on.
  • the same device function includes a first thin film layer 201 and a second thin film layer 202 ; after the first thin film layer 201 is deposited, the planarization and smoothing are omitted, and the direct deposition The second thin film layer 202 is then planarized and smoothed.
  • the multi-layer semiconductor material structure obtained by fabrication may also have the structure described above and then perform patterning and etching. Possible sections are shown in Figure 6-8. Possible floor plans are shown in Figure 9, but are not limited to circular substrates and square patches.
  • a high thermal conductivity supporting substrate 1 which is made of diamond and has a thickness of 100-200um.
  • the roughness of the first surface 101 is 1 nm, and the roughness of the second surface 102 is 20 nm.
  • a gallium oxide layer is deposited on the high thermal conductivity supporting substrate 1 by chemical vapor deposition, and the thickness of the gallium oxide layer is 200 nm.
  • the gallium oxide layer is planarized and smoothed to a roughness of 0.5 nm.
  • a sapphire single crystal substrate 3 is attached on the flattened and smoothed gallium oxide layer.
  • the thickness of the single crystal substrate 3 is 500um and the roughness is 0.3nm.
  • heat annealing treatment is performed, specifically, the temperature is raised to 600° C. at a rate of 1° C./min, the temperature is maintained for 30 minutes, and the cooling is performed at a rate of 1° C./min. After cooling, the single crystal substrate 3 is removed to produce a multi-layer semiconductor material structure.
  • a high thermal conductivity supporting substrate 1 which is made of silicon carbide and has a thickness of 400 um.
  • the roughness of the first surface 101 is 0.3 nm, and the roughness of the second surface 102 is 10 nm.
  • An Al 2 O 3 layer was deposited on the high thermal conductivity supporting substrate 1 by the atomic layer substrate method with a thickness of 100 nm.
  • a gallium oxide layer was deposited on the Al 2 O 3 layer by chemical vapor deposition with a thickness of 200 nm.
  • the gallium oxide layer is planarized and smoothed to a roughness of 0.5 nm.
  • a single crystal aluminum oxide substrate is attached on the gallium oxide layer.
  • the thickness of the single crystal substrate 3 is 50 microns and the roughness is 0.3 nm.
  • heat annealing treatment is performed, specifically, the temperature is raised to 600° C. at a rate of 1° C./min, the temperature is maintained for 30 minutes, and the cooling is performed at a rate of 1° C./min. After cooling, the single crystal substrate 3 is removed to produce a multi-layer semiconductor material structure.

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Abstract

本申请公开了一种多层半导体材料结构及制备方法，属于半导体技术领域，解决了现有技术中半导体材料散热性差、成本高、不能批量生产等问题。一种多层半导体材料结构，包括高导热支撑衬底和结晶化的器件功能层；所述器件功能层设置在所述高导热支撑衬底上，所述器件功能层表面层为单晶结构。

Description

一种多层半导体材料结构及制备方法 技术领域
本申请属于半导体技术领域，特别涉及一种多层半导体材料结构及制备方法。
背景技术
氧化镓(Ga 2O 3)晶体是一种新型的超宽禁带半导体材料，相比常见第三代半导体，它具有更大的禁带宽度、更高的电场击穿场强，其巴利加优值是GaN的4倍，SiC的10倍以上。因此，在达到相同耐压的条件下，采用Ga 2O 3的单极器件在理论上的导通电阻仅为SiC的1/10、GaN的1/3，这有利于减少电源电路的导通电力损耗，最大程度上提高器件的功率密度。此外，Ga 2O 3单晶衬底可采用溶体法生长，在制备成本方面相比于SiC和GaN有着非常明显的优势。
尽管Ga 2O 3材料制备成本低，器件性能优异，但Ga 2O 3材料本身极低的热导率(10-25W/mK)会造成器件工作时的严重局部自加热，导致更快的器件劣化和更短的工作寿命，将大大限制其在大功率条件下的应用，特别是Ga 2O 3基材料的热导率会由于尺寸效应、掺杂和合金化等进一步降低。因此，如何实现Ga 2O 3器件的有效散热是使其得以广泛应用的主要挑战之一。目前Ga 2O 3器件的研究主要是集中在电性能提升方面，只有少数关于热性能和热管理的研究被报道。一种非常有潜力的解决方案是将Ga 2O 3与高导热衬底进行异质集成。
M.J.Tadjer等人将(100)晶面的Ga 2O 3纳米带通过机械剥离的方法转移至单晶金刚石衬底上，并制作了Ga 2O 3纳米膜场效应晶体管；尽管Ga 2O 3纳米膜与金刚石衬底之间的弱范德华力键合导致了非常低的界面 热导(17MW/m 2K)，但受益于金刚石超高的热导率，Ga 2O 3器件的直流功率密度达到了60W/mm。机械剥离转移纳米带的方法仅适用于独立器件，并不能满足Ga 2O 3器件批量生产和大规模应用的要求。
Z.Cheng等人尝试了通过原子层沉积方法在单晶金刚石上直接生长Ga 2O 3，实现了Ga 2O 3与金刚石的高导热界面。原子层沉积方法虽然可以直接生长Ga 2O 3，并实现高导热界面，但是Ga 2O 3薄膜的结晶质量非常差，为纳米多晶结构，其热导率接近非晶Ga 2O 3，难以用于器件制作。
F.Mu等人实现了2寸Ga 2O 3单晶衬底与SiC衬底的表面活化室温异质键合集成，并结合离子注入剥离技术，实现了单晶氧化镓薄膜的转移。表面活化室温键合过程可以实现非常的氧化镓异质集成，但键合过程工艺复杂，成本较高，而且容易引入界面缺陷。
因此，亟需开发可大规模应用的Ga 2O 3与高导热衬底的异质集成技术。
此外，硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN等材料也存在类似的散热性差的问题。
发明内容
鉴于以上分析，本申请旨在提供一种多层半导体材料结构及制备方法，用以解决现有技术中半导体材料散热性差、成本高、不能批量生产等问题。
本申请的目的主要是通过以下技术方案实现的：
一方面，本申请提供了一种多层半导体材料结构，包括高导热支撑衬底和结晶化的器件功能层；所述器件功能层设置在所述高导热支撑衬底上，所述器件功能层表面层为单晶结构。
在一种可能的设计中，所述器件功能层晶体结构从表面至界面处有 一从单晶到多晶的微结构梯度；
或所述器件功能层晶体结构为器件功能层靠近表面和界面的部分均为单晶，表面和界面趋向中间的部分为从单晶到多晶的微结构梯度。
在一种可能的设计中，所述器件功能层为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN材料中的一种构成的单层结构，厚度在100nm-50um。
在一种可能的设计中，所述器件功能层包括第一薄膜层和第二薄膜层；所述第一薄膜层设置在所述高导热支撑衬底上，所述第二薄膜层设置在第一薄膜层上；
所述第一薄膜层为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN、SiN、SiO 2、HfO 2、SiNO、SiCO、AlON材料中的一种构成的单层结构或多种构成的复合层结构，厚度在100nm-50um；
所述第二薄膜层为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN材料中的一种构成的单层结构或多种构成的复合层结构，厚度在100nm-50um。
在一种可能的设计中，所述高导热支撑衬底材料为金刚石、SiC、AlN、BN、BeO、AlSiC、CuW、CuMo中的一种或多种复合。
另一方面，本申请提供了一种多层半导体材料结构的制备方法，包括以下步骤：
在高导热支撑衬底上形成器件功能层；
在器件功能层表面贴附一单晶衬底；
在300℃-1800℃退火；
冷却后将单晶衬底剥离去除，得到所述多层半导体材料结构。
在一种可能的设计中，在高导热支撑衬底上形成器件功能层的方法为化学气相沉积、原子层沉积、分子束沉积、HVPE、物理溅射、等离子体增强CVD中的一种或多种。
在一种可能的设计中，所述器件功能层包括第一薄膜层和第二薄膜层；
在高导热支撑衬底上形成器件功能层为：在高导热支撑衬底上沉积第一薄膜层，厚度为100nm～50um；然后对其进行平坦化和光滑化，然后再沉积第二薄膜层，厚度在100nm-50um。
在一种可能的设计中，所述器件功能层为单层薄膜层，厚度在100-50um，在高导热支撑衬底上形成薄膜层后，对其进行平坦化和光滑化，再在光滑化后的薄膜层表面贴附一单晶衬底。
在一种可能的设计中，对器件功能层进行平坦化和光滑化，表面粗糙度在0.1nm～10nm之间。
与现有技术相比，本申请至少能实现以下技术效果之一：
1)本申请多层半导体材料结构器件功能层设置在高导热支撑衬底上，且器件功能层为至少部分结晶化的薄膜层，器件功能层近表面层为单晶结构，本申请结构不仅形成了高导热界面，提高了器件功能膜层的散热效率，同时保证了器件功能层的实用性，制作过程工艺简单，可大尺寸，批量制作，成本低。
2)可用于制作具有高散热能力的高性能MOSFET或HEMT又或肖托基二极管等器件，不局限于横型器件或纵型器件。
3)为了增强界面吸附力、释放应力以及增强界面热导，器件功能层 包括第一薄膜层和第二薄膜层；第一薄膜层具有与高导热衬底更接近的热膨胀系数和更高的化学亲和能力。
本申请的其他特征和优点将在随后的说明书中阐述，并且，部分可从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在所写的说明书以及附图中所特别指出的结构来实现和获得。
附图说明
附图仅用于示出具体实施例的目的，而并不认为是对本申请的限制，在整个附图中，相同的附图标记表示相同的部件。
图1为高导热支撑衬底示意图；
图2为一个实施例的多层半导体材料结构的制备流程示意图；
图3为另一实施例的多层半导体材料结构的制备流程示意图；
图4为另一实施例的多层半导体材料结构的制备流程示意图；
图5为薄膜层结晶化流程示意图；
图6为多层半导体材料结构图形化刻蚀后的截面示意图；
图7为另一多层半导体材料结构图形化刻蚀后的截面示意图；
图8为另一多层半导体材料结构图形化刻蚀后的截面示意图；
图9为多层半导体材料结构图形化刻蚀后的平面示意图。
附图标记：
1-高导热支撑衬底；101-第一表面；102-第二表面；2-器件功能层；201-第一薄膜层；202-第二薄膜层；3-单晶衬底。
具体实施方式
以下，将参照附图来描述本申请公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本申请公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本申请公开的概念。
在附图中示出了根据本申请公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本申请公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
一种多层半导体材料结构，包括高导热支撑衬底1和结晶化的器件功能层2；器件功能层2设置在高导热支撑衬底1上，器件功能层2近表面层为单晶结构。
结晶化的器件功能层2晶体结构从表面至界面处有一从单晶到多晶的微结构梯度，靠近表面的表层部位晶体为高质量单晶结构，且有固定取向，如[0001]，[001]，[111]，[110]等。
与现有技术相比，本申请多层半导体材料结构器件功能层2设置在高导热支撑衬底1上，且器件功能层2为至少部分结晶化薄膜层，器件功能层2近表面层为单晶结构，本申请结构不仅形成了高导热界面，提 高了器件功能层2的散热效率，同时保证了器件功能层2的实用性，可用于器件的制作。
具体的，高导热支撑衬底1(热导率大于100W/m·K)材料为金刚石、SiC、AlN、BN、BeO、AlSiC、CuW、CuMo中的一种或多种复合。晶型与晶向不限，可为单晶，多晶和非晶。
高导热支撑衬底1为单晶时，结晶化的器件功能层2晶体结构为器件功能层2靠近表面和界面的部分均为单晶，表面和界面趋向中间的部分为从单晶到多晶的微结构梯度。
如图1所示，高导热支撑衬底1包括第一表面101和第二表面102，第一表面101的粗糙度小于1000nm，若表面太粗糙，会造成后续工艺成本高。优选的，该衬底第二表面102的粗糙度为1nm-20um。
在本申请的一个实施例中，器件功能层2为一层，材料为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN等材料中的一种构成的单层结构。
在本申请的另一个实施例中，为了增强界面吸附力、释放应力以及增强界面热导，器件功能层2包括第一薄膜层201和第二薄膜层202；第一薄膜层201具有与高导热支撑衬底1更接近的热膨胀系数和更高的化学亲和能力，设置在高导热支撑衬底1上，厚度在100nm-50um，第二薄膜层202设置在第一薄膜层201上，厚度在100nm-50um。第一薄膜层201为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN、SiN、SiO 2、HfO 2、SiNO、SiCO、AlON等材料中的一种构成的单层结构或多种材料分别沉积得到的多层的复合层结构；第二薄膜层202为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN材料中的一种构成的单层结构或多种材料分别沉积得到的多层的 复合层结构。
本申请还提供了一种多层半导体材料结构的制备方法，包括以下步骤：
在高导热支撑衬底1上形成器件功能层2；
在器件功能层2表面贴附一单晶衬底3；
退火；
冷却后将单晶衬底3剥离去除，得到多层半导体材料结构。
如图5所示，本申请通过在器件功能层2表面贴附一低缺陷密度的单晶衬底3，作为形核初始衬底，然后进行加热退火，器件功能层2表层会沿着形核初始衬底表面进行固相外延结晶，取向与形核初始衬底取向一致；冷却后将形核初始衬底(即单晶衬底3)剥离去除，结晶化的器件功能层2晶体结构从表面至界面处有一从单晶到多晶的微结构梯度，靠近表面的表层部位晶体为高质量单晶结构。本申请制备方法简单，且在器件功能层2表层形成单晶结构，保证了器件功能层2的实用性，可用于器件的制作。
当高导热支撑衬底1为单晶时，退火时会产生与器件功能层2表面贴附的单晶衬底3相同的形核作用，此时的结晶化的器件功能层2晶体结构为：器件功能层2靠近表面和界面的部分均为单晶，表面和界面趋向中间的部分为从单晶到多晶的微结构梯度。
示例性的，单晶衬底3的材质可以是蓝宝石，单晶衬底3的厚度范围在50um-1000um，表面粗糙度在0.1nm-10nm之间，保证与器件功能层2表面充分接触。
在高导热支撑衬底1上形成器件功能层2的方法为化学气相沉积、 原子层沉积、分子束沉积、HVPE、物理溅射、等离子体增强CVD中的一种或多种。
在贴附单晶衬底3前，对器件功能层2进行平坦化和光滑化，使器件功能层2表面粗糙度在0.1nm-10nm之间。平坦化和光滑化的具体操作为：化学机械抛光和等离子体处理。
退火温度为300-1800℃，为防止退火时产生高的热应力，升温和退火速率不高于50℃/min，保持时间为5-100min。
在本申请的一个实施例中，如图2所示，首先提供一高导热支撑衬底1，在高导热支撑衬底1第一表面101上沉积器件功能层2，为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN等材料中的一种构成的单层结构。厚度在100nm-50um之间，晶体结构为非晶，然后对其进行平坦化和光滑化，使其表面粗糙度在0.1nm-10nm之间，平坦化和光滑化后厚度为50nm-45um，然后进行退火使其结晶化。
在本申请的另一实施例中，如图3所示，为增强界面吸附力、释放应力以及增强界面热导，结构变为另一多层结构。器件功能层2包括第一薄膜层201和第二薄膜层202。首先提供一高导热支撑衬底1，在高导热支撑衬底1第一表面101上沉积一层第一薄膜层201，第一薄膜层201为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN、SiN、SiO 2、HfO 2、SiNO、SiCO、AlON等材料中的一种构成的单层结构或多种构成的多层的复合层结构；第一薄膜层201厚度为100nm～50um，晶体结构为非晶；然后对其进行平坦化和光滑化，使其表面粗糙度在0.1nm-50nm之间；然后再沉积一层第二薄膜层202并进行表面光滑化，第二薄膜层202为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN材料中的一种构成的单层结构或多种构成的多层的 复合层结构，厚度在100nm-50um之间，表面粗糙度在0.1nm-10nm之间；然后进行退火使其结晶化，结晶化的薄层晶体结构从表面至界面处有一从单晶到多晶的微结构梯度，靠近表层的部位晶体为高质量单晶结构，且有固定取向，如[0001]，[001]，[111]，[110]等。
在本申请的另一实施例中，如图4所示，同样器件功能包括第一薄膜层201和第二薄膜层202；在沉积第一薄膜层201后，省略平坦化和光滑化，直接沉积第二薄膜层202，然后对第二薄膜层202进行平坦化和光滑化。
对于制作获得的多层半导体材料结构，也可以具备上述结构再进行图形化刻蚀后的结构。可能的截面如图6-8所示。可能的平面图如图9所示，但是不仅局限于圆形衬底和方形小块。
实施例1
首先提供一高导热支撑衬底1，材质为金刚石，厚度为100-200um，第一表面101的粗糙度为1nm，第二表面102的粗糙度为20nm。
在高导热支撑衬底1上采用化学气相沉积法沉积氧化镓层，氧化镓层的厚度为200nm。
对氧化镓层进行平坦化和光滑化，粗糙度为0.5nm。
在进行平坦化和光滑化后的氧化镓层上贴附一蓝宝石单晶衬底3，单晶衬底3的厚度为500um，粗糙度为0.3nm。然后进行加热退火处理，具体的，采用1℃/min速率升温至600℃，保温30min时间，采用1℃/min速率进行冷却。冷却后去除单晶衬底3，制得多层半导体材料结构。
实施例2
首先提供一高导热支撑衬底1，材质为碳化硅，厚度400um，第一表面101的粗糙度为0.3nm，第二表面102的粗糙度为10nm。
在高导热支撑衬底1上采用原子层衬底法沉积Al 2O 3层，厚度为100nm。
在Al 2O 3层上采用化学气相沉积法再沉积一层氧化镓层，厚度为200nm。对氧化镓层进行平坦化和光滑化，粗糙度为0.5nm。
在氧化镓层上贴附一单晶氧化铝衬底，单晶衬底3的厚度为50微米，粗糙度为0.3nm。然后进行加热退火处理，具体的，采用1℃/min速率升温至600℃，保温30min时间，采用1℃/min速率进行冷却。冷却后去除单晶衬底3，制得多层半导体材料结构。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本申请公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本申请公开的范围。本申请公开的范围由所附权利要求及其等价物限定。不脱离本申请公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本申请公开的范围之内。

Claims (10)

  1. 一种多层半导体材料结构，其特征在于，包括高导热支撑衬底和结晶化的器件功能层；所述器件功能层设置在所述高导热支撑衬底上，所述器件功能层表面层为单晶结构。
  2. 根据权利要求1所述的多层半导体材料结构，其特征在于，所述器件功能层晶体结构从表面至界面处有一从单晶到多晶的微结构梯度；
    或所述器件功能层晶体结构为器件功能层靠近表面和界面的部分均为单晶，表面和界面趋向中间的部分为从单晶到多晶的微结构梯度。
  3. 根据权利要求1所述的多层半导体材料结构，其特征在于，所述器件功能层为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN材料中的一种构成的单层结构，厚度在100nm-50um。
  4. 根据权利要求1所述的多层半导体材料结构，其特征在于，所述器件功能层包括第一薄膜层和第二薄膜层；所述第一薄膜层设置在所述高导热支撑衬底上，所述第二薄膜层设置在第一薄膜层上；
    所述第一薄膜层为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN、SiN、SiO 2、HfO 2、SiNO、SiCO、AlON材料中的一种构成的单层结构或多种构成的复合层结构，厚度在100nm-50um；
    所述第二薄膜层为氧化镓、硅、碳化硅、GaN、氧化铝、锗、碳、AlN、ZnO、GaAs、AlGaN材料中的一种构成的单层结构或多种构成的复合层结构，厚度在100nm-50um。
  5. 根据权利要求1所述的多层半导体材料结构，其特征在于，所述高导热支撑衬底材料为金刚石、SiC、AlN、BN、BeO、AlSiC、CuW、CuMo中的一种或多种复合。
  6. 一种多层半导体材料结构的制备方法，其特征在于，包括以下步骤：
    在高导热支撑衬底上形成器件功能层；
    在器件功能层表面贴附单晶衬底；
    在300℃-1800℃退火；
    冷却后将单晶衬底剥离去除，得到所述多层半导体材料结构。
  7. 根据权利要求6所述的多层半导体材料结构的制备方法，其特征在于，在高导热支撑衬底上形成器件功能层的方法为化学气相沉积、原子层沉积、分子束沉积、HVPE、物理溅射、等离子体增强CVD中的一种或多种。
  8. 根据权利要求6所述的多层半导体材料结构的制备方法，其特征在于，所述器件功能层包括第一薄膜层和第二薄膜层；
    在高导热支撑衬底上形成器件功能层为：在高导热支撑衬底上沉积第一薄膜层，厚度为100nm～50um；然后对其进行平坦化和光滑化，然后再沉积第二薄膜层，厚度在100nm-50um。
  9. 根据权利要求6所述的多层半导体材料结构的制备方法，其特征在于，所述器件功能层为单层薄膜层，厚度在100-50um，在高导热支撑衬底上形成薄膜层后，对其进行平坦化和光滑化，再在光滑化后的薄膜层表面贴附单晶衬底。
  10. 根据权利要求6-9所述的多层半导体材料结构的制备方法，其特征在于，对器件功能层进行平坦化和光滑化，表面粗糙度在0.1nm～10nm之间。
PCT/CN2021/117424 2020-12-11 2021-09-09 一种多层半导体材料结构及制备方法 WO2022121408A1 (zh)

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US20020038892A1 (en) * 2000-07-28 2002-04-04 National Institute For Materials Science And Kyocera Corporation Boride-based substrate for growing semiconducting layers thereon and a semiconductor devise using the same
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CN109671612A (zh) * 2018-11-15 2019-04-23 中国科学院上海微系统与信息技术研究所 一种氧化镓半导体结构及其制备方法

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US5373171A (en) * 1987-03-12 1994-12-13 Sumitomo Electric Industries, Ltd. Thin film single crystal substrate
US20020038892A1 (en) * 2000-07-28 2002-04-04 National Institute For Materials Science And Kyocera Corporation Boride-based substrate for growing semiconducting layers thereon and a semiconductor devise using the same
CN1564308A (zh) * 2004-03-19 2005-01-12 中国科学院上海微系统与信息技术研究所 一种绝缘层上硅结构及制备方法
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