WO2022117930A3 - Substrat donneur pour le transfert d'une couche mince et procede de transfert associe - Google Patents

Substrat donneur pour le transfert d'une couche mince et procede de transfert associe Download PDF

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Publication number
WO2022117930A3
WO2022117930A3 PCT/FR2021/052047 FR2021052047W WO2022117930A3 WO 2022117930 A3 WO2022117930 A3 WO 2022117930A3 FR 2021052047 W FR2021052047 W FR 2021052047W WO 2022117930 A3 WO2022117930 A3 WO 2022117930A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
donor substrate
transfer
upper portion
thin layer
Prior art date
Application number
PCT/FR2021/052047
Other languages
English (en)
Other versions
WO2022117930A2 (fr
Inventor
Vincent Larrey
Shay Reboh
Lucie Le Van-Jodin
Frédéric Milesi
Ludovic Ecarnot
Gweltaz Gaudin
Didier Landru
Original Assignee
Commissariat A L'energie Atomique Et Aux Energies Alternatives
Soitec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat A L'energie Atomique Et Aux Energies Alternatives, Soitec filed Critical Commissariat A L'energie Atomique Et Aux Energies Alternatives
Priority to JP2023533212A priority Critical patent/JP2024501139A/ja
Priority to EP21824618.9A priority patent/EP4256606A2/fr
Priority to US18/255,574 priority patent/US20240030061A1/en
Priority to KR1020237019431A priority patent/KR20240065035A/ko
Priority to CN202180081095.2A priority patent/CN116583931A/zh
Publication of WO2022117930A2 publication Critical patent/WO2022117930A2/fr
Publication of WO2022117930A3 publication Critical patent/WO2022117930A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un substrat donneur (100) pour le transfert d'une couche mince monocristalline (1) en un premier matériau, sur un substrat receveur (2), le substrat donneur (100) présentant une face avant (100a) et une face arrière (100b), et comprenant : - un plan fragile enterré (30) qui délimite une portion supérieure (101) et une portion inférieure (102) du substrat donneur (100), - dans la portion supérieure (101), une première couche (10) du côté de la face avant (100a), une deuxième couche (20) adjacente au plan fragile enterré (30), et une couche d'arrêt (15) intercalée entre la première couche (10) et la deuxième couche (20), la première couche (10) étant composée du premier matériau, la couche d'arrêt (15) étant formée en un deuxième matériau apte à procurer une gravure sélective par rapport au premier matériau, - une sous-portion amorphisée (101',101'',101'''), rendue amorphe par implantation ionique, présentant une épaisseur strictement inférieure à celle de la portion supérieure (101), et incluant au moins la première couche (10); la deuxième couche (20) comprenant au moins une sous-couche (22) monocristalline, adjacente au plan fragile enterré (30). L'invention concerne également deux modes de mise en œuvre d'un procédé de transfert d'une couche mince monocristalline (1) à partir du substrat donneur (100).
PCT/FR2021/052047 2020-12-01 2021-11-19 Substrat donneur pour le transfert d'une couche mince et procede de transfert associe WO2022117930A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2023533212A JP2024501139A (ja) 2020-12-01 2021-11-19 薄層を転写するためのドナー基板及び関連する転写方法
EP21824618.9A EP4256606A2 (fr) 2020-12-01 2021-11-19 Substrat donneur pour le transfert d'une couche mince et procede de transfert associe
US18/255,574 US20240030061A1 (en) 2020-12-01 2021-11-19 Donor substrate for the transfer of a thin layer and associated transfer method
KR1020237019431A KR20240065035A (ko) 2020-12-01 2021-11-19 얇은 층의 전사를 위한 도너 기판 및 연관된 전사 방법
CN202180081095.2A CN116583931A (zh) 2020-12-01 2021-11-19 用于薄层转移的供体衬底及相关转移方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2012496A FR3116943B1 (fr) 2020-12-01 2020-12-01 Substrat donneur pour le transfert d’une couche mince et procede de transfert associe
FRFR2012496 2020-12-01

Publications (2)

Publication Number Publication Date
WO2022117930A2 WO2022117930A2 (fr) 2022-06-09
WO2022117930A3 true WO2022117930A3 (fr) 2022-09-01

Family

ID=74045978

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2021/052047 WO2022117930A2 (fr) 2020-12-01 2021-11-19 Substrat donneur pour le transfert d'une couche mince et procede de transfert associe

Country Status (8)

Country Link
US (1) US20240030061A1 (fr)
EP (1) EP4256606A2 (fr)
JP (1) JP2024501139A (fr)
KR (1) KR20240065035A (fr)
CN (1) CN116583931A (fr)
FR (1) FR3116943B1 (fr)
TW (1) TW202240652A (fr)
WO (1) WO2022117930A2 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US20170178950A1 (en) * 2015-12-22 2017-06-22 Commissariat à l'Energie Atomique et aux Energies Alternatives Fabrication method of a stack of electronic devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2978603B1 (fr) 2011-07-28 2013-08-23 Soitec Silicon On Insulator Procede de transfert d'une couche semi-conductrice monocristalline sur un substrat support

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US20170178950A1 (en) * 2015-12-22 2017-06-22 Commissariat à l'Energie Atomique et aux Energies Alternatives Fabrication method of a stack of electronic devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BAUMGART H ET AL: "Evaluation of wafer bonding and etch back for SOI technology", PHILIPS JOURNAL OF RESEARCH, ELSEVIER, AMSTERDAM, NL, vol. 49, no. 1, 1 January 1995 (1995-01-01), pages 91 - 124, XP004011508, ISSN: 0165-5817, DOI: 10.1016/0165-5817(95)82005-1 *

Also Published As

Publication number Publication date
TW202240652A (zh) 2022-10-16
FR3116943B1 (fr) 2023-01-13
JP2024501139A (ja) 2024-01-11
US20240030061A1 (en) 2024-01-25
CN116583931A (zh) 2023-08-11
EP4256606A2 (fr) 2023-10-11
FR3116943A1 (fr) 2022-06-03
KR20240065035A (ko) 2024-05-14
WO2022117930A2 (fr) 2022-06-09

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