FR3116943B1 - Substrat donneur pour le transfert d’une couche mince et procede de transfert associe - Google Patents
Substrat donneur pour le transfert d’une couche mince et procede de transfert associe Download PDFInfo
- Publication number
- FR3116943B1 FR3116943B1 FR2012496A FR2012496A FR3116943B1 FR 3116943 B1 FR3116943 B1 FR 3116943B1 FR 2012496 A FR2012496 A FR 2012496A FR 2012496 A FR2012496 A FR 2012496A FR 3116943 B1 FR3116943 B1 FR 3116943B1
- Authority
- FR
- France
- Prior art keywords
- layer
- donor substrate
- transfer
- thin layer
- transferring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title abstract 6
- 238000000034 method Methods 0.000 title abstract 2
- 239000000463 material Substances 0.000 abstract 4
- 239000013078 crystal Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Recrystallisation Techniques (AREA)
Abstract
L’invention concerne un substrat donneur (100) pour le transfert d’une couche mince monocristalline (1) en un premier matériau, sur un substrat receveur (2), le substrat donneur (100) présentant une face avant (100a) et une face arrière (100b), et comprenant :- un plan fragile enterré (30) qui délimite une portion supérieure (101) et une portion inférieure (102) du substrat donneur (100), - dans la portion supérieure (101), une première couche (10) du côté de la face avant (100a), une deuxième couche (20) adjacente au plan fragile enterré (30), et une couche d’arrêt (15) intercalée entre la première couche (10) et la deuxième couche (20), la première couche (10) étant composée du premier matériau, la couche d’arrêt (15) étant formée en un deuxième matériau apte à procurer une gravure sélective par rapport au premier matériau,- une sous-portion amorphisée (101’,101’’,101’’’), rendue amorphe par implantation ionique, présentant une épaisseur strictement inférieure à celle de la portion supérieure (101), et incluant au moins la première couche (10) ; la deuxième couche (20) comprenant au moins une sous-couche (22) monocristalline, adjacente au plan fragile enterré (30). L’invention concerne également deux modes de mise en œuvre d’un procédé de transfert d’une couche mince monocristalline (1) à partir du substrat donneur (100). Pas de Figur e
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2012496A FR3116943B1 (fr) | 2020-12-01 | 2020-12-01 | Substrat donneur pour le transfert d’une couche mince et procede de transfert associe |
JP2023533212A JP2024501139A (ja) | 2020-12-01 | 2021-11-19 | 薄層を転写するためのドナー基板及び関連する転写方法 |
KR1020237019431A KR20240065035A (ko) | 2020-12-01 | 2021-11-19 | 얇은 층의 전사를 위한 도너 기판 및 연관된 전사 방법 |
US18/255,574 US20240030061A1 (en) | 2020-12-01 | 2021-11-19 | Donor substrate for the transfer of a thin layer and associated transfer method |
PCT/FR2021/052047 WO2022117930A2 (fr) | 2020-12-01 | 2021-11-19 | Substrat donneur pour le transfert d'une couche mince et procede de transfert associe |
CN202180081095.2A CN116583931A (zh) | 2020-12-01 | 2021-11-19 | 用于薄层转移的供体衬底及相关转移方法 |
EP21824618.9A EP4256606A2 (fr) | 2020-12-01 | 2021-11-19 | Substrat donneur pour le transfert d'une couche mince et procede de transfert associe |
TW110143356A TW202240652A (zh) | 2020-12-01 | 2021-11-22 | 薄層移轉用供體底材及相關移轉方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2012496A FR3116943B1 (fr) | 2020-12-01 | 2020-12-01 | Substrat donneur pour le transfert d’une couche mince et procede de transfert associe |
FR2012496 | 2020-12-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3116943A1 FR3116943A1 (fr) | 2022-06-03 |
FR3116943B1 true FR3116943B1 (fr) | 2023-01-13 |
Family
ID=74045978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR2012496A Active FR3116943B1 (fr) | 2020-12-01 | 2020-12-01 | Substrat donneur pour le transfert d’une couche mince et procede de transfert associe |
Country Status (8)
Country | Link |
---|---|
US (1) | US20240030061A1 (fr) |
EP (1) | EP4256606A2 (fr) |
JP (1) | JP2024501139A (fr) |
KR (1) | KR20240065035A (fr) |
CN (1) | CN116583931A (fr) |
FR (1) | FR3116943B1 (fr) |
TW (1) | TW202240652A (fr) |
WO (1) | WO2022117930A2 (fr) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
FR2978603B1 (fr) | 2011-07-28 | 2013-08-23 | Soitec Silicon On Insulator | Procede de transfert d'une couche semi-conductrice monocristalline sur un substrat support |
FR3045934B1 (fr) * | 2015-12-22 | 2018-02-16 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d’un empilement de dispositifs electroniques |
-
2020
- 2020-12-01 FR FR2012496A patent/FR3116943B1/fr active Active
-
2021
- 2021-11-19 CN CN202180081095.2A patent/CN116583931A/zh active Pending
- 2021-11-19 WO PCT/FR2021/052047 patent/WO2022117930A2/fr active Application Filing
- 2021-11-19 JP JP2023533212A patent/JP2024501139A/ja active Pending
- 2021-11-19 KR KR1020237019431A patent/KR20240065035A/ko unknown
- 2021-11-19 EP EP21824618.9A patent/EP4256606A2/fr active Pending
- 2021-11-19 US US18/255,574 patent/US20240030061A1/en active Pending
- 2021-11-22 TW TW110143356A patent/TW202240652A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
CN116583931A (zh) | 2023-08-11 |
KR20240065035A (ko) | 2024-05-14 |
JP2024501139A (ja) | 2024-01-11 |
WO2022117930A3 (fr) | 2022-09-01 |
EP4256606A2 (fr) | 2023-10-11 |
TW202240652A (zh) | 2022-10-16 |
FR3116943A1 (fr) | 2022-06-03 |
US20240030061A1 (en) | 2024-01-25 |
WO2022117930A2 (fr) | 2022-06-09 |
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Legal Events
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PLFP | Fee payment |
Year of fee payment: 2 |
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PLSC | Publication of the preliminary search report |
Effective date: 20220603 |
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PLFP | Fee payment |
Year of fee payment: 3 |
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PLFP | Fee payment |
Year of fee payment: 4 |