WO2022116301A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2022116301A1
WO2022116301A1 PCT/CN2020/137962 CN2020137962W WO2022116301A1 WO 2022116301 A1 WO2022116301 A1 WO 2022116301A1 CN 2020137962 W CN2020137962 W CN 2020137962W WO 2022116301 A1 WO2022116301 A1 WO 2022116301A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixel
data line
display area
branch
Prior art date
Application number
PCT/CN2020/137962
Other languages
English (en)
French (fr)
Inventor
许森
肖邦清
傅华
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/260,243 priority Critical patent/US11942486B2/en
Publication of WO2022116301A1 publication Critical patent/WO2022116301A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel.
  • GCOF Gate driver in source COF
  • LCD for short bezel is a new type of panel design, in which the drive signals of scan lines and data lines are output from the same side of the chip-on-film (COF), and there is no GOA on the left and right sides of the panel. stage transmission circuit. Therefore, the use of such a design method can reduce the borders on the left and right sides, and realize the narrow border visual experience of "three narrow and one wide".
  • the sub-pixel design of the ultra-narrow bezel liquid crystal display due to the parasitic capacitance between the data line and the sub-pixel, the change of the data line signal will interfere with the sub-pixel signal, which will cause poor vertical crosstalk display.
  • One object of the present invention is to provide a display panel, which solves the problem of vertical crosstalk while realizing the narrow frame of the display panel, and reduces the number of COFs of the chip-on-film by reducing the number of wirings.
  • the present invention provides a display panel, including a sub-pixel group arranged in an array; the sub-pixel group includes a first sub-pixel: wherein, the first sub-pixel includes: a common electrode wiring, and the square area enclosed by the sub-pixel group is the the display area of the first sub-pixel; the first data line is arranged above the common electrode wiring, and the first data line extends from the non-display area of the first sub-pixel and passes through the display area ; and a second data line, arranged above the common electrode wiring, the second data line is arranged in the display area of the first sub-pixel and is opposite to the first data line; wherein, the The first data line and the second data line are insulated from each other and do not cross each other, and the electrical signals of the first data line and the second data line are opposite.
  • first data line and the second data line in the display area are left-right symmetrical with respect to the center line of the first sub-pixel.
  • the first data line includes: a trunk, disposed in the non-display area; a first branch, disposed in the display area, and the first branch is connected to the trunk.
  • the second data line includes: a second branch, which is arranged in the display area, and the second branch and the first branch are left-right symmetrical with respect to the center line of the first sub-pixel.
  • both the first branch and the second branch include: a vertical part; an upper horizontal part, which is connected to one end of the vertical part; and a lower horizontal part, which is connected to the other end of the vertical part.
  • the sub-pixel group further includes a second sub-pixel, and the second sub-pixel is an adjacent pixel of the first sub-pixel; the second sub-pixel has the same structure as the first sub-pixel.
  • first data line of the second sub-pixel and the second data line of the first sub-pixel share a trunk.
  • the lateral portion of the first data line of the second sub-pixel and the lateral portion of the second data line of the first sub-pixel are respectively connected to the trunk of the first data line of the second sub-pixel.
  • the first sub-pixel further includes: a horizontal scan line disposed in the non-display area; a vertical scan line disposed between the first sub-pixel and the second sub-pixel, the vertical scan line The line is connected to the horizontal scanning line; the pixel electrode is arranged above the display area.
  • the horizontal scan lines are formed in a first metal layer; the vertical scan lines are formed in a second metal layer, and the second metal layer is insulated from the first metal layer; the horizontal scan lines pass through A via hole is connected to the vertical scan line. .
  • the first sub-pixel further includes: a thin film transistor disposed in the non-display area; wherein, the thin film transistor includes: a gate; a source and drain, disposed above the gate. .
  • the present invention provides a display panel.
  • the non-display area of the first sub-pixel has a data line, and the data line is provided with branches in the display area.
  • the first sub-pixel display area has a data line.
  • a second data line is also provided.
  • the second data line branch of the present invention and the first data line branch of the second sub-pixel share the backbone of the non-display area of the second sub-pixel, while realizing the function of the pixel structure in FIG. There is only one, and the number of COFs used in the chip-on-chip film can be reduced, thereby reducing the production cost.
  • FIG. 1 is a schematic diagram of a first pixel structure in the prior art.
  • FIG. 2 is a schematic diagram of a second pixel structure in the prior art.
  • FIG. 3 is a schematic diagram of a third pixel structure in the prior art.
  • FIG. 4 is a schematic diagram of a fourth pixel structure in the prior art.
  • FIG. 5 is a schematic diagram of a pixel structure according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a pixel structure according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of the via hole in FIG. 6 .
  • FIG. 8 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • passivation 206 color resist layer 207; second insulating layer 208;
  • Source-drain metal layer 308 Source-drain metal layer 308 .
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, “plurality” means two or more. Additionally, the term “comprising” and any variations thereof are intended to cover non-exclusive inclusion.
  • the present invention provides a display panel 100 including sub-pixel groups 100 arranged in an array.
  • the sub-pixel group 100 includes a first sub-pixel 110 and a second sub-pixel 120 .
  • the second sub-pixel 120 is disposed on the left side of the first sub-pixel 110 .
  • the first sub-pixel 110 includes: a common electrode line 111 , a first data line 112 , a second data line 1124 , a horizontal scan line 117 , a vertical scan line 118 and a pixel electrode 119 .
  • the square area surrounded by the common electrode traces 111 is the display area 101 of the first sub-pixel 110 .
  • the common electrode traces 111 and the horizontal scan lines 117 are formed on the first metal layer 202 together.
  • the first data line 112 and the second data line 1124 are formed in the second metal layer 204 together.
  • the common electrode traces 111 and the horizontal scan lines 117 are obtained by first depositing a metal material and then patterning.
  • Materials of the common electrode traces 111 and the horizontal scan lines 117 include copper and its alloys.
  • the first data line 112 and the second data line 1124 are obtained by first depositing a metal material and then patterning.
  • Materials of the first data lines 112 and the second data lines 1124 include copper and its alloys.
  • the second metal layer 204 is disposed above the first metal layer 202 , and the second metal layer 204 is disposed on the first metal layer 202 to be insulated from each other .
  • the first data line 112 is disposed above the common electrode trace 111 , and in terms of plan structure, the first data line 112 extends from and passes through the non-display area 102 of the sub-pixel The display area 101 .
  • the second data line 1124 is disposed above the common electrode trace 111 , and in terms of plan structure, the second data line 1124 extends from the non-display area 102 of the first sub-pixel 110 and pass through the display area 101 .
  • the first data lines 112 and the second data lines 1124 are insulated from each other and do not cross each other, and the first data lines 112 and the second data lines 1124 are disposed opposite to each other in the display area 101 .
  • first data line 112 is arranged on the left side of the center line of the first sub-pixel 110
  • second data line 1124 is arranged on the right side of the center line of the first sub-pixel 110 .
  • the structure is such that the first data line 112 and the second data line 1124 are disposed opposite to each other in the display area 101 .
  • the electrical signals of the first data line 112 and the second data line 1124 are set to be opposite. Further, the voltages generated by the coupling of the first data line 112 and the second data line 1124 to the sub-pixels can cancel each other, and finally the problem of vertical crosstalk of the ultra-narrow frame can be improved.
  • the routing portion of the first data line 112 and the second data line 1124 in the display area 101 are left-right symmetrical with respect to the center line of the first sub-pixel 110 .
  • the first data line 112 includes a trunk (not marked in the figure, since the mark 112 of the first data line has been marked, it can also be used as a trunk mark) and the first branch 200 .
  • the trunk is disposed in the non-display area 102 .
  • the first branch 200 is disposed in the display area 101, and the first branch 200 is connected to the trunk.
  • the first branch 200 includes: a vertical part 1121 and two transverse parts (upper transverse part 1122 and lower transverse part 1123 ) parallel to each other.
  • the upper transverse portion 1122 is connected to the upper end of the vertical portion 1121
  • the lower transverse portion 1123 is connected to the lower end of the vertical portion 1121 .
  • the upper lateral portion 1122 corresponds to the upper boundary of the display area 101
  • the lower lateral portion 1123 corresponds to the lower boundary of the display area 101; in other words, the upper lateral portion 1122 corresponds to the common electrode
  • the lower lateral portion 1123 is correspondingly disposed on the lower short side of the square area of the common electrode trace 111 .
  • the second data line 1124 only includes the second branch 210, the second branch 210 has the same structure as the first branch 200, and the second branch 210 also includes a vertical portion and two lateral portions parallel to each other (It is not marked in the figure, for details, please refer to the structural description of the second branch).
  • the upper transverse portion of the second branch 210 is connected to the upper end of the vertical portion of the second branch 210
  • the lower transverse portion of the second branch 210 is connected to the lower end of the vertical portion 1121 .
  • the upper lateral portion of the second branch 210 corresponds to the upper boundary of the display area 101
  • the lower lateral portion of the second branch 210 corresponds to the lower boundary of the display area 101; in other words, the second branch
  • the upper lateral portion of the second branch 210 corresponds to the upper short side of the square area of the common electrode trace 111
  • the lower lateral portion of the second branch 210 corresponds to the lower side of the square area of the common electrode trace 111 . on the short side.
  • the second branch 210 and the first branch 200 are left-right symmetrical with respect to the center line of the display area 101 of the first sub-pixel 110 .
  • the lateral portion of the first branch 200 and the lateral portion of the second branch 210 are correspondingly disposed on the same straight line.
  • the vertical portion of the first branch 200 and the vertical portion of the second branch 210 are parallel to each other and disposed on the left and right sides of the center line of the display area 101 .
  • the opening direction of the pattern formed by the first branch 200 and the upper and lower lateral portions is opposite to the opening direction of the pattern formed by the second branch 210 and the upper and lower lateral portions.
  • the second sub-pixel 120 is an adjacent pixel of the first sub-pixel 110 .
  • the second sub-pixel 120 has the same structure as the first sub-pixel 110 .
  • the present invention does not specifically limit adjacent pixels, and the second sub-pixel 120 is disposed on the right side of the first sub-pixel 110 in this embodiment.
  • the first data line branch 121 of the second sub-pixel 120 and the second data line 1124 of the first sub-pixel 110 share a trunk (marked 113 ).
  • the upper lateral portion of the first data line branch 121 of the second sub-pixel 120 merges with the upper lateral portion of the second branch 210 of the second data line 1124 at the stem (mark 113 ).
  • the trunk (mark 113 ) is divided into the first data line branch 121 and the second data line 1124 of the second sub-pixel 120
  • the second branch 210 of the two branches respectively joins a data line (trunk) when the display areas 101 of different sub-pixels extend to the lower boundary of the display area.
  • the present invention makes the non-display area 102 of the first sub-pixel 110 have one data line (the backbone of the first data line 112 ) by changing the wiring mode of the sub-pixel data lines, and the first data line 112 is arranged in the display area 101
  • the first branch 200 in addition, the display area 101 of the first sub-pixel 110 is further provided with a second data line 1124, the second branch of the second data line 1124 and the first data line branch 121 of the second sub-pixel 120
  • the backbone of the non-display area 102 is shared, since there is only one data line in the non-display area 102, the problem of narrow metal spacing between the same layers of the structure can be avoided, the number of COFs can be reduced, and the production cost can be reduced.
  • the present invention realizes the functions of the pixel structure in FIG. 3 at the same time.
  • the common electrode wiring of the second sub-pixel 120 is connected to the common electrode wiring 111 of the first sub-pixel 110, and the connection is arranged on the long side of the square area, thereby realizing the connection between the first sub-pixel 110 and the common electrode wiring.
  • the common electrode traces of the second sub-pixels 120 are connected to each other.
  • the data line pattern of the present invention is a "mouth-shaped" design.
  • the present invention sets a data line trunk between the non-display areas 102 of adjacent sub-pixels (the first sub-pixel 110 and the second sub-pixel 120 ), and the data line (trunk) extends to the display area 101 , it is divided into two branch structures, which respectively enter different sub-pixels, one of which enters the first sub-pixel 110 and extends in the right area of the first sub-pixel 110, and the other enters the second sub-pixel 110.
  • the pixel 120 extends in the area on the left side of the second sub-pixel 120, and finally the data line branches pass through the display area 101 and merge together at the lower boundary of the display area 101, thereby performing data signal control on the downstream sub-pixels.
  • the horizontal scan lines 117 are disposed in the non-display area 102 , and the horizontal scan lines 117 and the trunks of the first data lines 112 are perpendicular to each other.
  • the vertical scan line 118 is disposed between the first sub-pixel 110 and the second sub-pixel 120 , and the vertical scan line 118 is connected to the horizontal scan line 117 .
  • the material of the vertical scan lines 118 includes copper and its alloys.
  • the vertical scan lines 118 and the horizontal scan lines 117 are arranged in different layers.
  • the pixel electrode 119 is disposed above the display area 101, and the material of the pixel electrode 119 includes indium tin oxide.
  • the pixel electrode 119 includes an electrode trunk and a plurality of electrode branches arranged in parallel.
  • the electrode branch pattern is fishbone-shaped, and the angle between the electrode branches and the electrode trunk is generally set to 45 degrees.
  • the horizontal scan line 117 and the vertical scan line 118 are respectively formed in different metal layers, and the horizontal scan line 117 is connected to the vertical scan line 118 through a via hole 112 . In this way, the problem of narrow metal spacing in the same layer can be avoided.
  • the horizontal scan line 117 and the common electrode wiring 111 are prepared in the same layer.
  • the common electrode traces 111 and the horizontal scan lines 117 are obtained by first depositing a metal material and then patterning.
  • the vertical scan lines 118 and the data lines can be disposed on the same layer, and can be obtained by depositing and patterning together during preparation. Therefore, the vertical scan lines 118 are made of the same material as the data lines.
  • the cross-sectional structure of the sub-pixel includes: a substrate 201 , a first metal layer 202 , a first insulating layer 203 , a second metal layer 204 , a second insulating layer 208 , a third Metal layer 205 , passivation layer 206 and color resist layer 207 .
  • the substrate 201 is a flexible substrate, and its material is polyimide.
  • the first metal layer 202 is disposed on the substrate 201 .
  • the material of the first metal layer 202 includes copper and its alloys.
  • the gate of the thin film transistor is formed in the first metal layer 202 .
  • the first insulating layer 203 is disposed on the substrate 201 and covers the first metal layer 202 , and the first insulating layer 203 includes the via hole 112 .
  • the material of the first insulating layer 203 includes silicon nitride or silicon oxide.
  • the second metal layer 204 is disposed on the first insulating layer 203 , and the second metal layer 204 is connected to the first metal layer 202 through the via hole 112 .
  • the material of the second metal layer 204 includes copper and its alloys.
  • the second insulating layer 208 is disposed on the second metal layer 204 and the first insulating layer 203 .
  • the material of the second insulating layer 208 includes silicon nitride or silicon oxide.
  • the third metal layer 205 is disposed on the second insulating layer 208 .
  • the material of the third metal layer 205 includes copper and its alloys.
  • the first data line 112 and the second data line 1124 are prepared in the third metal layer 205 by vapor deposition.
  • the passivation layer 206 is disposed on the second insulating layer 205 and covers the third metal layer 205 .
  • the material of the passivation layer 206 includes silicon nitride or silicon oxide.
  • the color resist layer 207 is disposed on the passivation layer 206 , and the color resist layer 207 includes a red color resist (R), a blue color resist (B), and a green color resist (G).
  • R red color resist
  • B blue color resist
  • G green color resist
  • the common electrode traces 111 and the horizontal scan lines 117 are disposed in the first metal layer 202 ; the vertical scan lines 118 are disposed in the second metal layer 204 .
  • the common electrode traces 111 and the horizontal scan lines 117 may be disposed in the second metal layer 204 ; the vertical scan lines 118 may be disposed in the first metal layer 202 .
  • the present invention can avoid the problem of narrow metal spacing in the same layer through the arrangement of metal wirings in different layers.
  • the first sub-pixel 110 further includes: a thin film transistor.
  • the thin film transistors are disposed in the non-display area 102 .
  • the layered structure at the thin film transistor specifically includes: a substrate 201 , an active layer 302 , a gate insulating layer 303 , a gate 304 , a first insulating layer 203 , a second metal layer 204 , and a second insulating layer 208 , a source-drain metal layer 308 , a passivation layer 206 and a first electrode layer 310 .
  • Some of the layers in FIG. 8 are the same as those in FIG. 7 .
  • the substrate 201 includes a glass substrate 2011 , a barrier layer 2012 and a buffer layer 2013 .
  • the blocking layer 2012 is disposed on the glass substrate 2011 ; the buffer layer 2013 is disposed on the side of the blocking layer 2012 away from the glass substrate 2011 .
  • Materials of the blocking layer 2012 include silicon nitride and silicon oxide.
  • the active layer 302 is disposed on the substrate 201; the active layer 302 is made of polysilicon material.
  • the gate insulating layer 303 is disposed on the active layer 302 and the substrate 201 .
  • the gate 304 is disposed on the gate insulating layer 303; the material of the gate 304 includes aluminum, copper, and copper-aluminum alloy. That is, the material of the gate electrode 304 can be selected from aluminum, copper or copper-aluminum alloy.
  • aluminum has the best electrical conductivity, and aluminum and copper have better flexibility, which are suitable for preparing the flexible display panel 100 .
  • the grid 304 of the display panel 100 of the present invention is made of copper-aluminum alloy, and its conductivity and bending resistance are far superior to the existing grid material molybdenum, which can be well applied to a folded display panel or a curled display panel.
  • the gate electrode 304 is fabricated in the first metal layer 202 and can be fabricated together with the common electrode wiring 111 and the horizontal scan line 117 by vapor deposition.
  • the first insulating layer 203 is disposed on the gate electrode 304 and the gate insulating layer 303 .
  • the second metal layer 204 is disposed on the first insulating layer 203 .
  • the second insulating layer 208 is disposed on the second metal layer 204 and the first insulating layer 203 .
  • the source-drain metal layer 308 is disposed on the second insulating layer 208 and connected to the active layer 302; the source-drain metal layer 308 has a source wire 3081 and a drain wire 3082, the The source wiring 3081 and the drain wiring 3082 are respectively connected to the active layer 302 .
  • the source-drain metal layer 308 is prepared in the third metal layer 205 by vapor deposition.
  • the passivation layer 206 is disposed on the source-drain metal layer 308 and the second insulating layer 208 ; the first electrode layer 310 is disposed on the passivation layer 206 .
  • the pixel electrode 119 can be obtained by patterning the first electrode layer 310
  • the present invention provides a display panel.
  • a trunk with only one first data line 122 is arranged in the non-display area 102 of the first sub-pixel 110, and the first data line 122 is in the display area 101.
  • the first branch 200 is provided, and the display area 101 of the first sub-pixel 110 is further provided with a second data line 1124 .
  • the coupling voltages of the two data line branch line signals to the sub-pixels cancel each other, which can improve the vertical crosstalk problem of the ultra-narrow frame.
  • the second branch 210 of the second data line 1124 and the first data line branch 121 of the second sub-pixel 120 share the backbone of the non-display area 102, and the present invention realizes the function of the pixel structure in FIG. 3 At the same time, since there is only one data line in the non-display area 102, the number of COFs can be reduced and the production cost can be reduced.
  • the horizontal scanning lines 117 and the vertical scanning lines 118 are arranged in different film layers, which can avoid the problem of narrow metal spacing in the same layer of the structure.
  • the present invention also provides a display device including the display panel 100 of the present invention.

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Abstract

一种显示面板（100），通过改变子像素数据线走线方式，使第一子像素（110）的非显示区（102）具有第一数据线（112），第一数据线（112）在显示区（101）设置分支，另外，第一子像素（110）的显示区（101）还设有第二数据线（1124），通过将第一数据线（112）与第二数据线（1124）设置相反的信号，使两个数据线信号对子像素的耦合电压可以相互抵消，改善超窄边框垂直串扰的问题。

Description

显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
超窄边框简称GCOF（Gate driver in source COF）液晶显示器，是一种新型的面板设计，其中扫描线和数据线驱动信号都从同一侧覆晶薄膜（COF）输出，面板的左右两侧无GOA级传电路。因此采用这样的设计方式可以减小左右两侧的边框，实现“三窄一宽”的窄边框视觉体验。而在超窄边框液晶显示器的子像素设计中，由于数据线和子像素之间存在寄生电容，因此数据线信号的变化会干扰子像素信号，这会造成垂直串扰的显示不良。
 技术问题
在普通的子像素设计中，也会存在垂直串扰的显示不良。如图1所示，任何一个子像素左右两侧的数据线与子像素显示区的距离是相同的（D1=D2）；如果两条数据线信号相反，子像素的耦合电压一正一反，其可以相互抵消。如图2所示，现有产品设计另一设计架构，子像素的显示区内使用两条数据线，一个子像素内有两条数据线（标记11以及12）走线，两条数据线信号相反，可以抵消数据线对像素的耦合电压。
如图3，在超窄边框设计中，由于扫描线垂直走线会经过子像素内，如果使用图1的架构，会造成子像素左右两侧数据线与子像素显示区距离不同（D3<D4），造成数据线和子像素的寄生耦合电容大小不同，即使数据线的信号相反，产生的耦合电压也不能完全抵消，因此超窄边框液晶显示器中也仍会有垂直串扰的风险存在；如果使图2用的架构，即如图4所示，这会使得数据线（标记13以及标记14）数量加倍，增加覆晶薄膜COF数量，增加生产成本。
因此，有必要提供显示面板，以改善现有技术中边框宽度较大的问题。
 技术解决方案
本发明一目的提供一种显示面板，在实现显示面板窄边框化的同时解决垂直串扰的问题，并且通过减小布线数量，减小覆晶薄膜COF数量。
本发明提供一种显示面板，包括阵列设置的子像素组；所述子像素组包括第一子像素：其中，所述第一子像素包括：公共电极走线，其围成的方形区域为所述第一子像素的显示区；第一数据线，设于所述公共电极走线的上方，所述第一数据线从所述第一子像素的非显示区延伸并穿过所述显示区；以及第二数据线，设于所述公共电极走线的上方，所述第二数据线设于所述第一子像素的显示区且与所述第一数据线相对设置；其中，所述第一数据线以及所述第二数据线相互绝缘且互不交叉，所述第一数据线以及所述第二数据线的电性信号相反。
进一步地，在所述显示区内的第一数据线与所述第二数据线关于所述第一子像素的中心线左右对称。
进一步地，所述第一数据线包括：主干，设于所述非显示区；第一分支，设于所述显示区，所述第一分支连接所述主干。所述第二数据线包括：第二分支，设于所述显示区，所述第二分支与所述第一分支关于所述第一子像素的中心线左右对称。
进一步地，所述第一分支与所述第二分支皆包括：竖直部；上横向部，连接所述竖直部的一端；以及下横向部，连接所述竖直部的另一端。
进一步地，所述子像素组还包括第二子像素，所述第二子像素为所述第一子像素的相邻像素；所述第二子像素与所述第一子像素的结构相同。
进一步地，所述第二子像素的第一数据线与所述第一子像素的第二数据线共用一主干。
进一步地，所述第二子像素的第一数据线的横向部与所述第一子像素的第二数据线的横向部分别连接所述第二子像素的第一数据线的主干。
进一步地，所述第一子像素还包括：水平扫描线，设置于所述非显示区；垂直扫描线，设于所述第一子像素与所述第二子像素之间，所述垂直扫描线连接所述水平扫描线；像素电极，设于所述显示区上方。
进一步地，所述水平扫描线形成于第一金属层中；所述垂直扫描线形成于第二金属层中，所述第二金属层与所述第一金属层绝缘；所述水平扫描线通过一过孔与所述垂直扫描线连接。。
进一步地，所述第一子像素还包括：薄膜晶体管，设于所述非显示区；其中，所述薄膜晶体管包括：栅极；源漏极，设于所述栅极的上方。。
 有益效果
本发明提供一种显示面板，通过改变子像素数据线走线方式，使第一子像素的非显示区具有一条数据线，该数据线在显示区设置分支，另外所述第一子像素显示区还设有第二数据线，通过将第一数据线与第二数据线设置相反的信号，使两个数据线信号对子像素的耦合电压可以相互抵消，改善超窄边框垂直串扰的问题。
并且本发明所述第二数据线分支与第二子像素的第一数据线分支共用第二子像素的非显示区的主干，在实现图3像素结构的功能同时，由于非显示区的数据线只有一条，并且可以减小覆晶薄膜COF的使用数量，进而降低生产成本。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术第一像素结构的示意图。
图2为现有技术第二像素结构的示意图。
图3为现有技术第三像素结构的示意图。
图4为现有技术第四像素结构的示意图。
图5为本发明一实施例提供的像素结构的示意图。
图6为本发明一实施例提供的像素结构的示意图。
图7为图6中过孔处的剖面图。
图8为本发明一实施例提供的薄膜晶体管的结构示意图。
本发明附图标记：
第一子像素110；第二子像素120；公共电极走线111；
第一数据线112；第二数据线1124；水平扫描线117；
垂直扫描线118；像素电极119；非显示区102；
显示区101；竖直部1121；第一电极分支的上横向部1122；
过孔112；基板201；第一金属层202；
第一绝缘层203；第二金属层204；第三金属层205；
钝化206；色阻层207；第二绝缘层208；
第一分支200；第一电极分支的横向部1123；
有源层302；栅极绝缘层303；栅极304；
第一绝缘层203；第二金属层204；第二绝缘层208；
源漏极金属层308。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
如图5以及图6所示，本发明提供一种显示面板100，包括阵列设置的子像素组100。
所述子像素组100包括第一子像素110以及第二子像素120。所述第二子像素120设于所述第一子像素110的左侧。
其中，所述第一子像素110包括：公共电极走线111、第一数据线112、第二数据线1124、水平扫描线117、垂直扫描线118以及像素电极119。
所述公共电极走线111围成的方形区域为所述第一子像素110的显示区101。所述公共电极走线111与所述水平扫描线117一同形成于第一金属层202。所述第一数据线112与所述第二数据线1124一同形成于第二金属层204中。
具体地，在制备所述公共电极走线111与所述水平扫描线117时，首先通过沉积金属材料后，再图案化得到所述公共电极走线111与所述水平扫描线117。所述公共电极走线111与所述水平扫描线117的材料包括铜及其合金。
在制备所述第一数据线112与所述第二数据线1124时，首先通过沉积金属材料后，再图案化得到所述第一数据线112与所述第二数据线1124。所述第一数据线112与所述第二数据线1124的材料包括铜及其合金。
从剖面结构讲，可以参照图7所示，所述第二金属层204设于所述第一金属层202的上方，且所述第二金属层204设于所述第一金属层202相互绝缘。
从剖面结构讲，所述第一数据线112设于所述公共电极走线111的上方，从平面结构讲，所述第一数据线112从所述子像素的非显示区102延伸并穿过所述显示区101。
从剖面结构讲，所述第二数据线1124设于所述公共电极走线111的上方，从平面结构讲，所述第二数据线1124从所述第一子像素110的非显示区102延伸并穿过所述显示区101。
所述第一数据线112以及所述第二数据线1124相互绝缘且互不交叉，所述第一数据线112以及所述第二数据线1124在所述显示区101相对设置。
更具体的说，所述第一数据线112设于第一子像素110中心线的左侧，所述第二数据线1124设于第一子像素110中心线的右侧，进而这种平面布局结构使得所述第一数据线112以及所述第二数据线1124在显示区101相对设置。
本发明将所述第一数据线112以及所述第二数据线1124的电信号设置相反。进而可以使所述第一数据线112以及所述第二数据线1124对子像素的耦合时所产生的电压可以相互抵消，最终改善超窄边框垂直串扰的问题。
所述第一数据线112在所述显示区101的走线部分与所述第二数据线1124关于所述第一子像素110的中心线左右对称。
具体地将，所述第一数据线112包括主干（图中并未标记出，由于已经标出第一数据线的112标记，其同样可以用作主干标记）以及第一分支200。
所述主干设于所述非显示区102。
所述第一分支200设于所述显示区101，所述第一分支200连接所述主干。
所述第一分支200包括：竖直部1121以及两个互相平行的横向部（上横向部1122、下横向部1123）。
所述上横向部1122连接所述竖直部1121的上端，所述下横向部1123连接所述竖直部1121的下端。所述上横向部1122对应所述显示区101的上边界，所述下横向部1123对应所述显示区101的下边界；换种方式讲，所述上横向部1122对应设于所述公共电极走线111的方形区域的上侧短边上，所述下横向部1123对应设于所述公共电极走线111的方形区域的下侧短边上。
所述第二数据线1124仅仅包括第二分支210，所述第二分支210与所述第一分支200的结构相同，所述第二分支210同样包括竖直部以及两个互相平行的横向部（图中并未标出，具体可以参考第二分支的结构描述）。
具体的讲，所述第二分支210的上横向部连接所述第二分支210竖直部的上端，所述第二分支210的下横向部连接所述竖直部1121的下端。所述第二分支210的上横向部对应所述显示区101的上边界，所述第二分支210的下横向部对应所述显示区101的下边界；换种方式讲，所述第二分支210的上横向部对应设于所述公共电极走线111的方形区域的上侧短边上，所述第二分支210的下横向部对应设于所述公共电极走线111的方形区域的下侧短边上。
所述第二分支210与所述第一分支200关于所述第一子像素110的显示区101的中心线左右对称。
在所述显示区101，第一分支200的横向部与第二分支210的横向部对应地设在同一直线上。第一分支200的竖直部与第二分支210的竖直部相互平行且设于所述显示区101中心线的左右两侧。
第一分支200与上下横向部形成的图案的开口方向与第二分支210与上下横向部形成的图案的开口方向相反。
所述第二子像素120为所述第一子像素110的相邻像素。所述第二子像素120与所述第一子像素110的结构相同。本发明并未对相邻像素具体作出限定，所述第二子像素120在本实施例中设于所述第一子像素110的右侧。
所述第二子像素120的第一数据线分支121与所述第一子像素110的第二数据线1124共用一主干（标记113）。
换种方式讲，所述第二子像素120的第一数据线分支121的上横向部与第二数据线1124的第二分支210的上横向部在主干（标记113）处汇合。
也可以说，数据线主干穿过非显示区102时，到达显示区101的上边界，主干（标记113）分为所述第二子像素120的第一数据线分支121、第二数据线1124的第二分支210，这两路分支分别在不同子像素的显示区101延伸至显示区下边界的时候再汇合会一根数据线（主干）。
综上，本发明通过改变子像素数据线走线方式，使第一子像素110的非显示区102具有一条数据线（第一数据线112的主干），第一数据线112在显示区101设置第一分支200，另外所述第一子像素110的显示区101还设有第二数据线1124，所述第二数据线1124的第二分支与第二子像素120的第一数据线分支121共用非显示区102的主干，由于非显示区102的数据线只有一条，能够规避该结构同层金属间距窄的问题，并且可以减小COF的数量，降低生产成本。
并且通过将第一数据线112与第二数据线1124设置相反的信号，这样使两个数据线支线信号对子像素的耦合电压相互抵消，改善超窄边框垂直串扰的问题。本发明在实现图3像素结构的功能同时。
所述第二子像素120的公共电极走线与所述第一子像素110的公共电极走线111相连接，连接处设置在方形区域的长边，进而实现所述第一子像素110与所述第二子像素120的公共电极走线之间相连接。
所述第二子像素120的第一数据线112的横向部分别连接所述第一子像素110的第二数据线1124的横向部。因此本发明的所述数据线图案为“口字形”设计。
也可以这样说，本发明在相邻子像素（所述第一子像素110与所述第二子像素120）非显示区102之间设置数据线主干，数据线（主干）延伸至显示区101的时候，分为两路分支结构，分别进入不同的子像素，其中一路进入所述第一子像素110中并在所述第一子像素110右侧区域延伸，另一路进入所述第二子像素120中并在所述第二子像素120左侧区域延伸，最后数据线分支穿过所述显示区101在所述显示区101的下边界汇合在一起，进而对下行子像素进行数据信号控制。
所述水平扫描线117设置于所述非显示区102，所述水平扫描线117与第一数据线112的主干相互垂直。
从图6的平面角度看，所述垂直扫描线118设于所述第一子像素110与所述第二子像素120之间，所述垂直扫描线118连接所述水平扫描线117。所述垂直扫描线118的材料包括铜及其合金。
从层状结构讲，所述垂直扫描线118与所述水平扫描线117设置在不同层中。
所述像素电极119设于所述显示区101上方，其制备的材料包括氧化铟锡。
所述像素电极119包括电极主干以及多根平行设置的电极分支，所述电极分支图案形状为鱼骨形，电极分支与电极主干的角度一般设置为45度。
所述水平扫描线117与所述垂直扫描线118分别形成于不同的金属层中，所述水平扫描线117通过一过孔112与所述垂直扫描线118连接。进而可以规避同层金属间距窄的问题。
在本发明中，所述水平扫描线117与所述公共电极走线111制备于同一层中。在制备所述公共电极走线111与所述水平扫描线117时，首先通过沉积金属材料后，再图案化得到所述公共电极走线111与所述水平扫描线117。
而垂直扫描线118可与数据线设置在同一层，在制备的时候，只需一同沉积图案化即可得到。因此，垂直扫描线118与数据线的材料相同。
如图7所示，在所述过孔112处，子像素的剖面结构包括：基板201、第一金属层202、第一绝缘层203、第二金属层204、第二绝缘层208、第三金属层205、钝化层206以及色阻层207。
所述基板201为柔性基板，其材料为聚酰亚胺。
所述第一金属层202设于所述基板201上。所述第一金属层202的材料包括铜及其合金。所述第一金属层202中形成薄膜晶体管的栅极。
所述第一绝缘层203设于所述基板201上且覆盖所述第一金属层202，所述第一绝缘层203上包括所述过孔112。所述第一绝缘层203材料包括氮化硅或氧化硅。
所述第二金属层204设于所述第一绝缘层203上，所述第二金属层204通过所述过孔112连接所述第一金属层202。所述第二金属层204的材料包括铜及其合金。
所述第二绝缘层208设于所述第二金属层204以及所述第一绝缘层203上。所述第二绝缘层208材料包括氮化硅或氧化硅。
所述第三金属层205设于所述第二绝缘层208上。所述第三金属层205的材料包括铜及其合金。
所述第一数据线112与所述第二数据线1124制备于所述第三金属层205中，通过气相沉积的方法制备形成。
所述钝化层206设于所述第二绝缘层205上且覆盖所述第三金属层205。所述钝化层206的材料包括氮化硅或氧化硅。
所述色阻层207设于所述钝化层206上，所述色阻层207包括红色色阻（R）、蓝色色阻（B）以及绿色色阻（G）。
在一实施例中，所述公共电极走线111与所述水平扫描线117设于所述第一金属层202中；所述垂直扫描线118设于所述第二金属层204中。
在一实施例中，所述公共电极走线111与所述水平扫描线117可以设于所述第二金属层204中；所述垂直扫描线118设于所述第一金属层202中。
本发明通过不同层对金属走线的设置，进而可以规避同层金属间距窄的问题。
在一实施例中，所述第一子像素110还包括：一薄膜晶体管。
如图8所示，所述薄膜晶体管设于所述非显示区102。其中，所述薄膜晶体管处的层状结构：具体包括：基板201、有源层302、栅极绝缘层303、栅极304、第一绝缘层203、第二金属层204、第二绝缘层208、源漏极金属层308、钝化层206以及第一电极层310。图8中有部分膜层是与图7中的膜层相同。
所述基板201包括：玻璃基板2011、阻隔层2012以及缓冲层2013。
所述阻隔层2012设于所述玻璃基板2011上；所述缓冲层2013设于所述阻隔层2012远离所述玻璃基板2011的一侧。所述阻隔层2012的材料包括氮化硅及氧化硅。
所述有源层302设于所述基板201上；所述有源层302为多晶硅材料。
所述栅极绝缘层303设于所述有源层302以及所述基板201上。
所述栅极304设于所述栅极绝缘层303上；所述栅极304的材料包括铝、铜以及铜铝合金。亦即，所述栅极304的材料可选自铝、铜或铜铝合金。
其中，铝的导电性能最好，铝和铜的柔性更好，适合制备柔性显示面板100。
本发明显示面板100的栅极304采用铜铝合金，其导电性和耐弯折特性都远优于现有的栅极材料钼，可以很好的适用于折叠显示面板或卷曲显示面板。
所述栅极304制备于第一金属层202中，可与所述公共电极走线111与所述水平扫描线117通过气相沉积的方法一同制备形成。
所述第一绝缘层203设于所述栅极304以及所述栅极绝缘层303上。
所述第二金属层204设于所述第一绝缘层203上。
所述第二绝缘层208设于所述第二金属层204以及所述第一绝缘层203上。
所述源漏极金属层308设于所述第二绝缘层208上且连接所述有源层302；所述源漏极金属层308具有源极走线3081以及漏极走线3082，所述源极走线3081以及所述漏极走线3082分别连接所述有源层302。所述源漏极金属层308制备于第三金属层205中，通过气相沉积的方法制备形成。
所述钝化层206设于所述源漏极金属层308以及所述第二绝缘层208上；所述第一电极层310设于所述钝化层206上。所述第一电极层310图案化可得到所述像素电极119
本发明提供一种显示面板，通过改变子像素数据线走线方式，在第一子像素110的非显示区102设置只有一条第一数据线122的主干，该第一数据线122在显示区101设置第一分支200，另外所述第一子像素110的显示区101还设有第二数据线1124。本发明通过将第一数据线112与第二数据线1124设置相反的信号使两个数据线支线信号对子像素的耦合电压相互抵消，这可以改善超窄边框垂直串扰的问题。
在一个子像素组中，所述第二数据线1124的第二分支210与第二子像素120的第一数据线分支121共用非显示区102的主干，本发明在实现图3像素结构的功能同时，由于非显示区102的数据线只有一条，可以减小COF的数量，降低生产成本。
本发明将水平扫描线117与垂直扫描线118设在不同膜层中，能够规避该结构同层金属间距窄的问题。
本发明还提供一种显示装置，其包括本发明所述的显示面板100。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，包括阵列设置的子像素组；
    所述子像素组包括第一子像素：
    其中，所述第一子像素包括：
    公共电极走线，其围成的方形区域为所述第一子像素的显示区；
    第一数据线，设于所述公共电极走线的上方，所述第一数据线从所述第一子像素的非显示区延伸并穿过所述显示区；以及
    第二数据线，设于所述公共电极走线的上方，所述第二数据线设于所述第一子像素的显示区且与所述第一数据线相对设置；
    其中，所述第一数据线以及所述第二数据线相互绝缘且互不交叉，所述第一数据线以及所述第二数据线的电性信号相反。
  2. 如权利要求1所述的显示面板，其中，
    在所述显示区内的第一数据线与所述第二数据线关于所述第一子像素的中心线左右对称。
  3. 如权利要求1所述的显示面板，其中，
    所述第一数据线包括：
    主干，设于所述非显示区；
    第一分支，设于所述显示区，所述第一分支连接所述主干；
    所述第二数据线包括：
    第二分支，设于所述显示区，所述第二分支与所述第一分支关于所述第一子像素的中心线左右对称。
  4. 如权利要求3所述的显示面板，其中，
    所述第一分支与所述第二分支皆包括：
    竖直部；
    上横向部，连接所述竖直部的一端；以及
    下横向部，连接所述竖直部的另一端。
  5. 如权利要求4所述的显示面板，其中，
    所述子像素组还包括第二子像素，所述第二子像素为所述第一子像素的相邻的行子像素；
    所述第二子像素与所述第一子像素的结构相同。
  6. 如权利要求5所述的显示面板，其中，
    所述第二子像素的第一数据线与所述第一子像素的第二数据线共用一主干。
  7. 如权利要求5所述的显示面板，其中，
    所述第二子像素的第一数据线的横向部与所述第一子像素的第二数据线的横向部分别连接所述第二子像素的第一数据线的主干。
  8. 如权利要求5所述的显示面板，其中，还包括：
    水平扫描线，设置于所述非显示区；
    垂直扫描线，设于所述第一子像素与所述第二子像素之间，所述垂直扫描线连接所述水平扫描线；
    像素电极，设于所述显示区上方。
  9. 如权利要求8所述的显示面板，其中，
    所述水平扫描线形成于第一金属层中；
    所述垂直扫描线形成于第二金属层中，所述第二金属层与所述第一金属层绝缘；
    所述水平扫描线通过一过孔与所述垂直扫描线连接。
  10. 如权利要求1所述的显示面板，其中，还包括：
    薄膜晶体管，设于所述非显示区；
    其中，所述薄膜晶体管包括：
    栅极；
    源漏极，设于所述栅极的上方。
  11. 一种显示装置，其中，包括一显示面板，所述显示面板包括阵列设置的子像素组；
    所述子像素组包括第一子像素：
    其中，所述第一子像素包括：
    公共电极走线，其围成的方形区域为所述第一子像素的显示区；
    第一数据线，设于所述公共电极走线的上方，所述第一数据线从所述第一子像素的非显示区延伸并穿过所述显示区；以及
    第二数据线，设于所述公共电极走线的上方，所述第二数据线设于所述第一子像素的显示区且与所述第一数据线相对设置；
    其中，所述第一数据线以及所述第二数据线相互绝缘且互不交叉，所述第一数据线以及所述第二数据线的电性信号相反。
  12. 如权利要求11所述的显示装置，其中，
    在所述显示区内的第一数据线与所述第二数据线关于所述第一子像素的中心线左右对称。
  13. 如权利要求11所述的显示装置，其中，
    所述第一数据线包括：
    主干，设于所述非显示区；
    第一分支，设于所述显示区，所述第一分支连接所述主干；
    所述第二数据线包括：
    第二分支，设于所述显示区，所述第二分支与所述第一分支关于所述第一子像素的中心线左右对称。
  14. 如权利要求13所述的显示装置，其中，
    所述第一分支与所述第二分支皆包括：
    竖直部；
    上横向部，连接所述竖直部的一端；以及
    下横向部，连接所述竖直部的另一端。
  15. 如权利要求14所述的显示装置，其中，
    所述子像素组还包括第二子像素，所述第二子像素为所述第一子像素的相邻的行子像素；
    所述第二子像素与所述第一子像素的结构相同。
  16. 如权利要求15所述的显示装置，其中，
    所述第二子像素的第一数据线与所述第一子像素的第二数据线共用一主干。
  17. 如权利要求15所述的显示装置，其中，
    所述第二子像素的第一数据线的横向部与所述第一子像素的第二数据线的横向部分别连接所述第二子像素的第一数据线的主干。
  18. 如权利要求15所述的显示装置，其中，还包括：
    水平扫描线，设置于所述非显示区；
    垂直扫描线，设于所述第一子像素与所述第二子像素之间，所述垂直扫描线连接所述水平扫描线；
    像素电极，设于所述显示区上方。
  19. 如权利要求18所述的显示装置，其中，
    所述水平扫描线形成于第一金属层中；
    所述垂直扫描线形成于第二金属层中，所述第二金属层与所述第一金属层绝缘；
    所述水平扫描线通过一过孔与所述垂直扫描线连接。
  20. 如权利要求11所述的显示装置，其中，还包括：
    薄膜晶体管，设于所述非显示区；
    其中，所述薄膜晶体管包括：
    栅极；
    源漏极，设于所述栅极的上方。
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