WO2022111240A1 - Circuit de commande pour commutateur de puissance intelligent côté bas, et puce - Google Patents

Circuit de commande pour commutateur de puissance intelligent côté bas, et puce Download PDF

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Publication number
WO2022111240A1
WO2022111240A1 PCT/CN2021/128277 CN2021128277W WO2022111240A1 WO 2022111240 A1 WO2022111240 A1 WO 2022111240A1 CN 2021128277 W CN2021128277 W CN 2021128277W WO 2022111240 A1 WO2022111240 A1 WO 2022111240A1
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Prior art keywords
nmos transistor
drain
source
transistor
node
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PCT/CN2021/128277
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English (en)
Chinese (zh)
Inventor
闫兆文
汪西虎
姚和平
唐威
苏海伟
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上海维安半导体有限公司
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Publication of WO2022111240A1 publication Critical patent/WO2022111240A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature

Definitions

  • the invention relates to the technical field of circuits, in particular to a control circuit and a chip of an intelligent low-side power switch.
  • intelligent power switch integrated circuit aims to integrate all high-voltage power devices and low-voltage circuits on the same chip, which can not only improve the overall performance of the chip, but also reduce production costs.
  • the present invention provides a control circuit for an intelligent low-side power switch, which includes:
  • a second NMOS transistor the source of the second NMOS transistor is connected to a first resistor and then grounded in parallel with the source of the first NMOS transistor, the drain of the second NMOS transistor and the first NMOS transistor connected in parallel to a first node and then connected to a load external terminal, the gate of the control terminal is connected to a sixth resistor and a seventh resistor and finally connected to a second node in parallel and then connected to a voltage input terminal through a second resistor;
  • a protection module connected in parallel between the voltage input terminal and the ground, for electrostatic protection
  • an over-temperature protection module connected in parallel between the second node and the ground, for turning off the working current of the control terminal of the first NMOS transistor when the working temperature reaches a preset temperature
  • a current limiting module is connected in parallel between the second node and the ground, and is provided with a sixth NMOS transistor and the second NMOS transistor, the gate of the sixth NMOS transistor and the source of the second NMOS transistor
  • the drain of the sixth NMOS transistor is connected to the gate of the first NMOS transistor, so that when the current collected by the current sampling second NMOS transistor exceeds a preset electrical current, the sixth NMOS transistor is connected
  • the NMOS is turned on to discharge the gate of the first NMOS tube, thereby limiting the output current of the first NMOS tube;
  • An overvoltage protection module is connected in parallel between the first node and the ground, and a fourth zener diode is arranged for pulling down when the drain voltage of the first NMOS transistor exceeds a preset voltage The gate voltage of the first NMOS transistor turns off the first NMOS transistor;
  • a clamping module connected in parallel between the first node and the ground, for when the voltage applied between the drain of the first NMOS transistor and the ground is higher than a preset voltage of the clamping module , the clamping module is turned on, and the voltage applied to both ends of the drain and source of the first NMOS transistor is clamped at a preset voltage value, so that the drain-source breakdown of the first NMOS transistor is avoided.
  • the protection module includes:
  • a first PNP tube the emitter of the first PNP tube is connected to the voltage input terminal, the base of the first PNP tube is short-circuited to the emitter of the first PNP tube, the first PNP tube The collector of the tube is grounded.
  • the over-temperature protection module includes:
  • a current mirror unit connected in parallel between the second node and the ground, and providing a bias current output terminal
  • a start-up unit connected in parallel between the bias current output terminal and the ground, and provides a start-up current output terminal
  • a PATA current source is connected in parallel between the bias current output terminal and ground, and a start-up terminal is connected to the start-up current output terminal for generating a voltage proportional to the operating temperature according to the bias current PATA current;
  • An over-temperature control unit is connected in parallel between the bias current output terminal and the ground, and is used to control the current input to the control terminal of the first NMOS transistor when the operating temperature increases.
  • the current mirror unit includes:
  • the source is connected to the second node, and the control terminal is short-circuited with the drain;
  • a second PMOS transistor the source is connected to the second node, the drain is grounded through a first Zener diode, the control terminal is connected to the control terminal of the first PMOS transistor, and is connected to the ground through a second Zener diode the second node;
  • a third NMOS transistor the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the control terminal is short-circuited with the source;
  • the drain of the second PMOS transistor forms the bias current output terminal.
  • the starting unit includes:
  • the source is connected to the bias current output terminal, the drain is grounded through a capacitor, and the control terminal and the drain are short-circuited;
  • a fourth PMOS transistor the source is connected to the bias current output terminal, the drain is grounded, and the control terminal is connected to the control terminal of the third PMOS transistor;
  • the drain of the fourth PMOS transistor forms the start-up current output terminal.
  • the PTAT current source includes:
  • the source is connected to the bias current output terminal, and the drain is connected to the startup current output terminal;
  • the source is connected to the bias current output terminal, the control terminal is short-circuited with the drain, and is connected to the control terminal of the fifth PMOS tube;
  • the collector is connected to the drain of the fifth PMOS tube, the emitter is grounded, and the base and the collector are short-circuited;
  • a second NPN transistor the collector is connected to the drain of the sixth PMOS transistor, the emitter is grounded through a third resistor, and the base is connected to the base of the first NPN transistor.
  • the over-temperature control unit includes:
  • a seventh PMOS transistor the source is connected to the bias current output terminal, and the drain is grounded through a first series resistance voltage divider circuit;
  • an eighth PMOS transistor the source is connected to the bias current output terminal, and the control terminal is connected to the control terminal of the seventh PMOS transistor and the control terminal of the sixth PMOS transistor;
  • a third NPN transistor the collector is connected to the drain of the eighth PMOS transistor, the base is connected to the drain of the seventh PMOS transistor, and the emitter is grounded;
  • a fourth NMOS transistor the source is grounded, and the drain is connected to the control terminal of the second NMOS transistor;
  • first inverter In series with each other, a first inverter, a second inverter and a third inverter, the input end of the first inverter is connected to the drain of the eighth PMOS transistor, the first inverter The output end of the three-inverter is connected to the control end of the fourth NMOS transistor;
  • a fifth NMOS transistor the source is grounded, the drain is connected to the voltage dividing node of the first series resistance voltage divider circuit, and the control terminal is connected between the second inverter and the third inverter.
  • the current limiting module includes:
  • a sixth NMOS transistor the drain is connected to the control terminal of the second NMOS transistor, the source is grounded, and the control terminal is connected to the source of the second NMOS transistor;
  • a second series resistance voltage divider circuit connected in series between the second node and the control terminal of the second NMOS transistor
  • a seventh NMOS transistor the drain is connected to the second node, the source is connected to the voltage dividing node of the second series resistance voltage divider circuit, and the control terminal is shorted to the source;
  • a third Zener diode is connected between the control terminal of the second NMOS transistor and the control terminal of the sixth NMOS transistor.
  • the overvoltage protection module includes:
  • an eighth NMOS transistor the drain of which is connected to the control terminal of the first NMOS transistor
  • a ninth NMOS transistor the drain is connected to the source of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;
  • the drain is connected to the control terminal of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;
  • the anode is connected to the control terminal of the eighth NMOS transistor, and the cathode is connected to the first node;
  • the positive electrode is connected to the source electrode of the eighth NMOS transistor, and the negative electrode is connected to the control terminal of the eighth NMOS transistor;
  • a sixth Zener diode the anode is connected to the source of the eighth NMOS transistor, and the cathode is grounded.
  • the clamping module includes:
  • a second PNP tube, the emitter of the second PNP tube is connected to the first node, the collector of the second PNP tube is grounded, and the base of the second PNP tube and the emitter are short-circuited.
  • control circuit is formed in a chip.
  • the present invention also provides a chip, which includes the control circuit as described above.
  • the above technical solution has the following advantages or beneficial effects: by embedding a protection module, an over-temperature protection module, a current limiting module, an over-voltage protection module and a clamping voltage module, the energy generated by the first NMOS tube due to high inductive load at the moment of turning off can be solved.
  • the problem of single-pulse avalanche energy breakdown and damage occurs to protect the first NMOS transistor and has high reliability.
  • FIG. 1 is a schematic diagram of a circuit structure of an embodiment of the present invention.
  • the present invention provides a control circuit for an intelligent low-side power switch, which includes:
  • a second NMOS transistor the source of the second NMOS transistor is connected to a first resistor and then grounded in parallel with the source of the first NMOS transistor, the drain of the second NMOS transistor and the first NMOS transistor It is connected in parallel to a first node and then connected to a load external terminal LOAD.
  • the gate of the control terminal is connected to a sixth resistor R6 and a seventh resistor R7 and finally connected to a second node 2 in parallel and then connected to a voltage through a second resistor R2 input terminal VIN;
  • a protection module 3 connected in parallel between the voltage input terminal VIN and the ground GND, for electrostatic protection
  • an over-temperature protection module connected in parallel between the second node 2 and the ground GND, for cutting off the working current of the control terminal of the first NMOS transistor Q1 when the working temperature reaches a preset temperature
  • a current limiting module 5 is connected in parallel between the second node 2 and the ground GND, and is provided with a sixth NMOS transistor Q13 and the above-mentioned second NMOS transistor Q2, the gate of the sixth NMOS transistor Q13 and the source of the second NMOS transistor Q2 connected, the drain of the sixth NMS transistor Q13 is connected to the gate of the first NMOS transistor Q1, for when the current collected by the current sampling second NMOS transistor Q2 exceeds a preset current The gate of an NMOS transistor Q1 is discharged, thereby limiting the output current of the first NMOS transistor Q1;
  • An overvoltage protection module 6 is connected in parallel between the first node 1 and the ground GND, and a fourth qi diode D4 is arranged to pull down the first NMOS transistor when the drain voltage of the first NMOS transistor Q1 exceeds a preset voltage The gate voltage of Q1 turns off the first NMOS transistor Q1;
  • a clamping module 7 is connected in parallel between the first node 1 and the ground GND, for when the voltage applied between the drain of the first NMOS transistor Q1 and the ground GND is higher than the preset voltage of the clamping module 7,
  • the clamping module 7 is turned on to clamp the voltage applied across the drain and source of the first NMOS transistor Q1 to a preset voltage value, and the first NMOS transistor Q1 avoids drain-source breakdown.
  • the protection module 3 is connected in parallel with the first NMOS transistor Q1 between the voltage input terminal VIN and the ground GND, so as to protect the first NMOS transistor from static electricity.
  • an over-temperature protection module is connected between the second node 2 and the ground GND.
  • the over-temperature protection module can pull down the first NMOS transistor Q1. control the terminal voltage, so that the first NMOS transistor Q1 is turned off. Further, if the operating temperature decreases, the over-temperature protection module generates a temperature hysteresis. When the operating temperature drops below a certain temperature, the first NMOS transistor Q1 is in an on state.
  • the current limiting module 5 is connected between the second node 2 and the ground GND.
  • the voltages of the control terminals of the first NMOS transistor Q1 and the second NMOS transistor Q2 are equal.
  • the second NMOS transistor Q2 and the first resistor R1 can monitor the current of the first NMOS transistor Q1 in real time; when the voltage provided by the voltage input terminal VIN is high, the current of the first NMOS transistor Q1 increases, and the first resistor R1
  • the voltage at both ends increases, so that the control terminal voltage of the first NMOS transistor Q1 decreases, and the current flowing through the first NMOS transistor Q1 decreases accordingly, so as to protect the first NMOS transistor Q1.
  • an overvoltage protection module 6 is connected between the first node 1 and the second node 2.
  • the overvoltage protection module 6 is used to make the first NMOS transistor Q1 larger.
  • the voltage of the control terminal of the transistor Q1 is reduced, so that the first NMOS transistor Q1 is turned off.
  • a clamping module 7 is connected in parallel between the first node 1 and the ground GND.
  • the first NMOS transistor Q1 When the first NMOS transistor Q1 is turned off, the energy of the breakdown voltage generated by the high inductive load is released, and the first NMOS transistor Q1 is turned off.
  • the drain voltage of Q1 When the drain voltage of Q1 is clamped to a predetermined value lower than its breakdown voltage, the first NMOS transistor Q1 is effectively prevented from being broken down, so as to protect the first NMOS transistor Q1.
  • over-temperature protection module Through the built-in protection module 3, over-temperature protection module, current limiting module 5, over-voltage protection module 6 and voltage clamping module 7, the single-pulse avalanche energy generated by the energy generated by the high inductive load at the moment of turn-off of the first NMOS transistor Q1 is solved.
  • the problem of breakdown and damage is to protect the first NMOS transistor Q1, which has high reliability.
  • the protection module 3 includes:
  • a first PNP transistor VT1 the emitter of the first PNP transistor VT1 is connected to the voltage input terminal VIN, the base of the first PNP transistor VT1 is short-circuited to the emitter of the first PNP transistor VT1, and the collector of the first PNP transistor VT1 Ground GND.
  • the protection module 3 in the above technical solution is the first PNP tube VT1, and the first PNP tube VT1 plays the role of electrostatic protection.
  • the over-temperature protection module includes:
  • a current mirror unit 40 connected in parallel between the second node 2 and the ground GND, and providing a bias current output terminal;
  • a start-up unit 41 is connected in parallel between the bias current output terminal and the ground GND, and provides a start-up current output terminal;
  • a PATA current source 42 is connected in parallel between the bias current output terminal and the ground GND, and a start-up terminal is connected to the start-up current output terminal for generating a PATA current proportional to the operating temperature according to the bias current;
  • An over-temperature control unit 43 is connected in parallel between the bias current output terminal and the ground GND to control the current input to the control terminal of the first NMOS transistor Q1 when the operating temperature increases.
  • the over-temperature protection module in the above technical solution includes a current mirror unit 40 , a start-up unit 41 , a PATA current source 42 and an over-temperature control unit 43 .
  • the bias current output terminal is provided through the current mirror unit 40 and the bias current is output.
  • the working state of each module is 0. After the voltage input terminal VIN provides a voltage, the starting unit 41 is turned on to start the working state of other modules.
  • the PATA current that is proportional to the operating temperature can be generated according to the bias current provided by the current mirror unit 40 .
  • the over-temperature control unit 43 can pull down the first NMOS transistor Q1.
  • the control terminal voltage of the NMOS transistor Q1 turns off the first NMOS transistor Q1.
  • the over-temperature control unit 43 generates a temperature hysteresis.
  • the first NMOS transistor Q1 turns off. is on.
  • the current mirror unit 40 includes:
  • a first PMOS transistor Q3, the source is connected to the second node 2, and the control terminal is short-circuited with the drain;
  • a second PMOS transistor Q4 the source is connected to the second node 2, the drain is grounded to GND through a first Zener diode D1, the control terminal is connected to the control terminal of the first PMOS transistor Q3, and is connected through a second Zener diode D2 connected to the second node 2;
  • a third NMOS transistor Q5 the source is grounded to GND, the drain is connected to the drain of the first PMOS transistor Q3, and the control terminal is shorted to the source;
  • the drain of the second PMOS transistor Q4 forms a bias current output terminal.
  • the above-mentioned current mirror unit 40 includes a first PMOS transistor Q3, a second PMOS transistor Q4, a third NMOS transistor Q5, and a first Zener diode D1 and a second Zener diode D2 for providing bias current, wherein , the second PMOS transistor Q4 mirrors the current of the first PMOS transistor Q3, the drain of the second PMOS transistor Q4 is connected to the cathode of the first Zener diode D1, and provides a bias current for the PATA current source 42 that generates the above-mentioned PATA current, And the first Zener diode D1 serves as a voltage regulator of the PATA current source 42 that generates the PATA current.
  • the third NMOS transistor Q5 is used as a constant current source.
  • the anode of the second Zener diode D2 is connected to the control terminal of the second PMOS transistor Q4, and the cathode is connected to the source of the second PMOS transistor Q4 to protect the control terminal of the second PMOS transistor Q4 from being broken down.
  • the starting unit 41 includes:
  • a third PMOS transistor Q5 the source is connected to the bias current output terminal, the drain is grounded through a capacitor C, and the control terminal is short-circuited with the drain;
  • a fourth PMOS transistor Q6 the source is connected to the bias current output terminal, the drain is grounded to GND, and the control terminal is connected to the control terminal of the third PMOS transistor Q5;
  • the drain of the fourth PMOS transistor Q6 forms a start-up current output terminal.
  • the start-up unit 41 in the above technical solution includes a third PMOS transistor Q5, a fourth PMOS transistor Q6 and a capacitor C.
  • the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are turned on, and then the third PMOS transistor Q5 charges both ends of the capacitor C, and the fourth PMOS transistor Q6 is input to the PATA current source 42
  • the voltage across the capacitor C is equal to the source voltages of the third PMOS transistor Q5 and the fourth PMOS transistor Q6
  • the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are turned off, and the startup unit 41 is completed.
  • the PTAT current source 42 includes:
  • a fifth PMOS transistor Q7 the source is connected to the bias current output terminal, and the drain is connected to the startup current output terminal;
  • a sixth PMOS transistor Q8, the source is connected to the bias current output terminal, the control terminal is short-circuited with the drain, and is connected to the control terminal of the fifth PMOS transistor Q7;
  • a first NPN transistor VT2 the collector is connected to the drain of the fifth PMOS transistor Q7, the emitter is grounded to GND, and the base and the collector are short-circuited;
  • a second NPN transistor VT3 the collector is connected to the drain of the sixth PMOS transistor Q8, the emitter is grounded to GND through a third resistor R3, and the base is connected to the base of the first NPN transistor VT2.
  • the above-mentioned PTAT current source 42 is formed by connecting the fifth PMOS transistor Q7 , the sixth PMOS transistor Q8 , the first NPN transistor VT2 , the second NPN transistor VT3 and the third resistor R3 .
  • the number ratio of the first NPN transistor VT2 and the second NPN transistor VT3 is set to be 1:4, and a plurality of second NPN transistors VT3 are connected in parallel with each other.
  • the over-temperature control unit 43 includes:
  • a seventh PMOS transistor Q9 the source is connected to the bias current output terminal, and the drain is grounded to GND through a first series resistance voltage divider circuit 8;
  • an eighth PMOS transistor Q10 the source is connected to the bias current output terminal, and the control terminal is connected to the control terminal of the seventh PMOS transistor Q9 and the control terminal of the sixth PMOS transistor Q8;
  • a third NPN transistor VT4 the collector is connected to the drain of the eighth PMOS transistor Q10, the base is connected to the drain of the seventh PMOS transistor Q9, and the emitter is grounded to GND;
  • a fourth NMOS transistor Q11 the source is grounded to GND, and the drain is connected to the control terminal of the second NMOS transistor Q2;
  • first inverter INV1 In series with each other, a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the drain of the eighth PMOS transistor Q10, the third inverter INV1 The output end of the inverter INV3 is connected to the control end of the fourth NMOS transistor Q11;
  • a fifth NMOS transistor Q12 the source is grounded GND, the drain is connected to the voltage dividing node of the first series resistance voltage dividing circuit 8, and the control terminal is connected between the second inverter INV2 and the third inverter INV3.
  • the third NPN transistor VT4 when the operating temperature of the circuit is at a normal temperature, the third NPN transistor VT4 is turned off, and the potential of its collector is relatively high, passing through the first inverter INV1 and the second inverter INV2 connected in series. And the third inverter INV3 outputs a low potential, and inputs the low potential to the control terminal of the fourth NMOS transistor Q11, so that the fourth NMOS transistor Q11 is turned off and the first NMOS transistor Q1 works normally.
  • the first series resistance voltage divider circuit 8 includes a fourth resistor R4 and a fifth resistor R5, and the control terminal of the fifth NMOS transistor Q12 is connected between the second inverter INV2 and the third inverter INV3 , the second inverter INV2 outputs a high potential, so that the fifth NMOS transistor Q12 is turned on, and the fourth resistor R4 is short-circuited.
  • the third NPN transistor VT4 When the operating temperature reaches the preset temperature for over-temperature protection, the third NPN transistor VT4 is turned on, its collector outputs a low potential, and then passes through the first inverter INV1, the second inverter INV2 and the third inverter INV3 A high potential is output, thereby pulling down the voltage of the control terminal of the first NMOS transistor Q1, so that the first NMOS transistor Q1 is turned off.
  • the second NMOS transistor Q2 is turned off.
  • the fourth resistor R4 in the first series resistor divider circuit 8 is turned on, so that the third NPN transistor VT4 is turned on.
  • the potential of the base electrode is raised to generate a temperature hysteresis amount.
  • the third NPN transistor VT4 is turned off again, so that the first NMOS transistor Q1 is turned on.
  • the current limiting module 5 includes:
  • a sixth NMOS transistor Q13 the drain is connected to the control terminal of the second NMOS transistor Q2, the source is grounded to GND, and the control terminal is connected to the source of the second NMOS transistor Q2;
  • a second series resistance voltage divider circuit 9 is connected in series between the second node 2 and the control terminal of the second NMOS transistor Q2;
  • a seventh NMOS transistor Q14 the drain is connected to the second node 2, the source is connected to the voltage dividing node of the second series resistance voltage dividing circuit 9, and the control terminal is short-circuited with the source;
  • a third Zener diode D3 is connected between the control terminal of the second NMOS transistor Q2 and the control terminal of the sixth NMOS transistor Q13.
  • the second series resistance voltage divider circuit 9 includes a sixth resistor R6 and a seventh resistor R7, both of which are current-limiting resistors, the first resistor R1 is used as a sampling resistor, and the second NMOS transistor Q2 is used for current sampling
  • the sixth NMOS transistor Q13 is a pull-down transistor.
  • the magnitude of the current limiting value can be determined by adjusting the number ratio of the second NMOS transistors Q2 and the first NMOS transistors Q1 or adjusting the resistance value of the first resistor R1.
  • the overvoltage protection module 6 includes:
  • an eighth NMOS transistor Q15 the drain of which is connected to the control terminal of the first NMOS transistor Q1;
  • a ninth NMOS transistor Q16 the drain is connected to the source of the eighth NMOS transistor Q15, the source is grounded to GND, and the control terminal is short-circuited with the source;
  • a tenth NMOS transistor Q17 the drain is connected to the control terminal of the eighth NMOS transistor Q15, the source is grounded to GND, and the control terminal is short-circuited with the source;
  • a fourth Zener diode D4 the anode is connected to the control terminal of the eighth NMOS transistor Q15, and the cathode is connected to the first node 1;
  • a sixth Zener diode D6 the anode is connected to the source of the eighth NMOS transistor Q15, and the cathode is grounded to GND.
  • the eighth NMOS transistor Q15 is a pull-down transistor.
  • the eighth NMOS transistor Q15 is turned on to turn on the first NMOS transistor Q15.
  • the voltage of the control terminal of the NMOS transistor Q1 is pulled down, so that the first NMOS transistor Q1 is turned off.
  • the clamping module 7 includes:
  • a second PNP transistor VT5 the emitter of the second PNP transistor VT5 is connected to the first node 1, the collector of the second PNP transistor VT5 is grounded to GND, and the base and the emitter of the second PNP transistor VT5 are short-circuited.
  • the clamping module 7 includes a second PNP transistor VT5.
  • the fifth Schottky diode D5 is used to protect the control terminal of the eighth NMOS transistor Q15
  • the sixth Zener diode D6 generates overvoltage protection.
  • the energy of the breakdown voltage generated by the high inductive load is released, and when the drain voltage of the first NMOS transistor Q1 is clamped to a preset value lower than its breakdown voltage, At the same time, the energy of the breakdown voltage is discharged to the ground, thereby effectively preventing the first NMOS transistor Q1 from being broken down, so as to protect the first NMOS transistor Q1.
  • control circuit is formed in a chip.
  • the present invention provides a chip, which includes the above-mentioned control circuit.

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Abstract

La présente invention se rapporte au domaine technique des circuits, et concerne en particulier un circuit de commande pour un commutateur de puissance intelligent côté bas, et une puce. Le circuit de commande comprend : un premier transistor NMOS ; un second transistor NMOS, l'électrode de source du second transistor NMOS étant connectée à une première résistance, puis étant connectée en parallèle à l'électrode de source du premier transistor NMOS et étant mise à la terre, les électrodes de drain du second transistor NMOS et du premier transistor NMOS étant connectées en parallèle à un premier nœud puis connectées à une charge, et une extrémité de commande étant connectée en parallèle à un second nœud puis étant connectée à une extrémité d'entrée de tension au moyen d'une seconde résistance ; un module de protection connecté en parallèle entre l'extrémité d'entrée de tension et la terre ; un module de protection contre la surchauffe connecté en parallèle entre le second nœud et la terre ; un module de limitation de courant connecté en parallèle entre le second nœud et la terre, une extrémité de détection étant prévue pour être connectée à l'électrode de source du second transistor NMOS ; un module de protection contre les surtensions connecté en parallèle entre le premier nœud et le second nœud ; et un module de tension de blocage connecté en parallèle entre le premier nœud et la terre. La présente invention présente les effets bénéfiques de : résolution du problème selon lequel le premier transistor NMOS est endommagé en raison d'une rupture d'énergie d'avalanche à impulsion unique provoquée par l'énergie produite par une charge à inductance élevée au moment de l'arrêt, et présentation d'une fiabilité élevée.
PCT/CN2021/128277 2020-11-30 2021-11-02 Circuit de commande pour commutateur de puissance intelligent côté bas, et puce WO2022111240A1 (fr)

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Application Number Priority Date Filing Date Title
CN202011375011.XA CN112383293A (zh) 2020-11-30 2020-11-30 一种智能低边功率开关的控制电路及芯片
CN202011375011.X 2020-11-30

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WO2022111240A1 true WO2022111240A1 (fr) 2022-06-02

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