WO2022111240A1 - Control circuit for intelligent low-side power switch, and chip - Google Patents

Abstract

The present invention relates to the technical field of circuits, and particularly relates to a control circuit for an intelligent low-side power switch, and a chip. The control circuit comprises: a first NMOS transistor; a second NMOS transistor, wherein the source electrode of the second NMOS transistor is connected to a first resistor, and then is connected in parallel to the source electrode of the first NMOS transistor and is grounded, the drain electrodes of the second NMOS transistor and the first NMOS transistor are connected in parallel to a first node and then connected to a load, and a control end is connected in parallel to a second node and then is connected to a voltage input end by means of a second resistor; a protection module connected in parallel between the voltage input end and the ground; an over-temperature protection module connected in parallel between the second node and the ground; a current limiting module connected in parallel between the second node and the ground, wherein a detection end is provided to be connected to the source electrode of the second NMOS transistor; an overvoltage protection module connected in parallel between the first node and the second node; and a clamping voltage module connected in parallel between the first node and the ground. The present invention has the beneficial effects of: solving the problem that the first NMOS transistor is damaged due to single-pulse avalanche energy breakdown caused by energy generated by a high inductance load at the moment of turn-off, and having high reliability.

Description

A control circuit and chip of an intelligent low-side power switch technical field

The invention relates to the technical field of circuits, in particular to a control circuit and a chip of an intelligent low-side power switch.

Background technique

As a new generation of power electronic technology, intelligent power switch integrated circuit aims to integrate all high-voltage power devices and low-voltage circuits on the same chip, which can not only improve the overall performance of the chip, but also reduce production costs.

At present, most of the smart power switches on the market are power switches integrating overcurrent protection, overvoltage protection, and overtemperature protection, which are widely used in the fields of household appliances, automotive electronics and industrial control electronics. However, the protection function of these smart power switches is not enough to meet the needs of automotive electronics and industrial control electronics, and their overall volume is large and the production cost is also high. In particular, automotive electronics are often used in harsh conditions such as voltage transients, high-energy and high-inductive loads, as well as many external links and human interference, which put forward new requirements for intelligent power switches with high withstand voltage, high performance and high reliability. For example, with the increase of people's requirements for the response speed of automotive electronics, when intelligent power switches are applied to high inductive loads, excessively fast switching speed will generate high pulse voltages, causing avalanche breakdown of power devices, and power devices in a short period of time. The concentration of current in the area can easily lead to the problem that the temperature of the area rises rapidly and the device is burned. Therefore, in view of the above problems, it is a difficult problem to be solved urgently by those skilled in the text field.

SUMMARY OF THE INVENTION

Aiming at the above problems existing in the prior art, a control circuit and a chip of an intelligent low-side power switch are provided.

The specific technical solutions are as follows:

The present invention provides a control circuit for an intelligent low-side power switch, which includes:

a first NMOS tube;

A second NMOS transistor, the source of the second NMOS transistor is connected to a first resistor and then grounded in parallel with the source of the first NMOS transistor, the drain of the second NMOS transistor and the first NMOS transistor connected in parallel to a first node and then connected to a load external terminal, the gate of the control terminal is connected to a sixth resistor and a seventh resistor and finally connected to a second node in parallel and then connected to a voltage input terminal through a second resistor;

a protection module, connected in parallel between the voltage input terminal and the ground, for electrostatic protection;

an over-temperature protection module, connected in parallel between the second node and the ground, for turning off the working current of the control terminal of the first NMOS transistor when the working temperature reaches a preset temperature;

A current limiting module is connected in parallel between the second node and the ground, and is provided with a sixth NMOS transistor and the second NMOS transistor, the gate of the sixth NMOS transistor and the source of the second NMOS transistor The drain of the sixth NMOS transistor is connected to the gate of the first NMOS transistor, so that when the current collected by the current sampling second NMOS transistor exceeds a preset electrical current, the sixth NMOS transistor is connected The NMOS is turned on to discharge the gate of the first NMOS tube, thereby limiting the output current of the first NMOS tube;

An overvoltage protection module is connected in parallel between the first node and the ground, and a fourth zener diode is arranged for pulling down when the drain voltage of the first NMOS transistor exceeds a preset voltage The gate voltage of the first NMOS transistor turns off the first NMOS transistor;

A clamping module, connected in parallel between the first node and the ground, for when the voltage applied between the drain of the first NMOS transistor and the ground is higher than a preset voltage of the clamping module , the clamping module is turned on, and the voltage applied to both ends of the drain and source of the first NMOS transistor is clamped at a preset voltage value, so that the drain-source breakdown of the first NMOS transistor is avoided.

Preferably, the protection module includes:

A first PNP tube, the emitter of the first PNP tube is connected to the voltage input terminal, the base of the first PNP tube is short-circuited to the emitter of the first PNP tube, the first PNP tube The collector of the tube is grounded.

Preferably, the over-temperature protection module includes:

a current mirror unit, connected in parallel between the second node and the ground, and providing a bias current output terminal;

a start-up unit, connected in parallel between the bias current output terminal and the ground, and provides a start-up current output terminal;

A PATA current source is connected in parallel between the bias current output terminal and ground, and a start-up terminal is connected to the start-up current output terminal for generating a voltage proportional to the operating temperature according to the bias current PATA current;

An over-temperature control unit is connected in parallel between the bias current output terminal and the ground, and is used to control the current input to the control terminal of the first NMOS transistor when the operating temperature increases.

Preferably, the current mirror unit includes:

a first PMOS transistor, the source is connected to the second node, and the control terminal is short-circuited with the drain;

A second PMOS transistor, the source is connected to the second node, the drain is grounded through a first Zener diode, the control terminal is connected to the control terminal of the first PMOS transistor, and is connected to the ground through a second Zener diode the second node;

a third NMOS transistor, the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the control terminal is short-circuited with the source;

The drain of the second PMOS transistor forms the bias current output terminal.

Preferably, the starting unit includes:

a third PMOS transistor, the source is connected to the bias current output terminal, the drain is grounded through a capacitor, and the control terminal and the drain are short-circuited;

a fourth PMOS transistor, the source is connected to the bias current output terminal, the drain is grounded, and the control terminal is connected to the control terminal of the third PMOS transistor;

The drain of the fourth PMOS transistor forms the start-up current output terminal.

Preferably, the PTAT current source includes:

a fifth PMOS transistor, the source is connected to the bias current output terminal, and the drain is connected to the startup current output terminal;

a sixth PMOS tube, the source is connected to the bias current output terminal, the control terminal is short-circuited with the drain, and is connected to the control terminal of the fifth PMOS tube;

a first NPN tube, the collector is connected to the drain of the fifth PMOS tube, the emitter is grounded, and the base and the collector are short-circuited;

A second NPN transistor, the collector is connected to the drain of the sixth PMOS transistor, the emitter is grounded through a third resistor, and the base is connected to the base of the first NPN transistor.

Preferably, the over-temperature control unit includes:

a seventh PMOS transistor, the source is connected to the bias current output terminal, and the drain is grounded through a first series resistance voltage divider circuit;

an eighth PMOS transistor, the source is connected to the bias current output terminal, and the control terminal is connected to the control terminal of the seventh PMOS transistor and the control terminal of the sixth PMOS transistor;

a third NPN transistor, the collector is connected to the drain of the eighth PMOS transistor, the base is connected to the drain of the seventh PMOS transistor, and the emitter is grounded;

a fourth NMOS transistor, the source is grounded, and the drain is connected to the control terminal of the second NMOS transistor;

In series with each other, a first inverter, a second inverter and a third inverter, the input end of the first inverter is connected to the drain of the eighth PMOS transistor, the first inverter The output end of the three-inverter is connected to the control end of the fourth NMOS transistor;

A fifth NMOS transistor, the source is grounded, the drain is connected to the voltage dividing node of the first series resistance voltage divider circuit, and the control terminal is connected between the second inverter and the third inverter.

Preferably, the current limiting module includes:

a sixth NMOS transistor, the drain is connected to the control terminal of the second NMOS transistor, the source is grounded, and the control terminal is connected to the source of the second NMOS transistor;

a second series resistance voltage divider circuit, connected in series between the second node and the control terminal of the second NMOS transistor;

a seventh NMOS transistor, the drain is connected to the second node, the source is connected to the voltage dividing node of the second series resistance voltage divider circuit, and the control terminal is shorted to the source;

A third Zener diode is connected between the control terminal of the second NMOS transistor and the control terminal of the sixth NMOS transistor.

Preferably, the overvoltage protection module includes:

an eighth NMOS transistor, the drain of which is connected to the control terminal of the first NMOS transistor;

a ninth NMOS transistor, the drain is connected to the source of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;

a tenth NMOS transistor, the drain is connected to the control terminal of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;

a fourth Zener diode, the anode is connected to the control terminal of the eighth NMOS transistor, and the cathode is connected to the first node;

a fifth Schottky diode, the positive electrode is connected to the source electrode of the eighth NMOS transistor, and the negative electrode is connected to the control terminal of the eighth NMOS transistor;

A sixth Zener diode, the anode is connected to the source of the eighth NMOS transistor, and the cathode is grounded.

Preferably, the clamping module includes:

A second PNP tube, the emitter of the second PNP tube is connected to the first node, the collector of the second PNP tube is grounded, and the base of the second PNP tube and the emitter are short-circuited.

Preferably, the control circuit is formed in a chip.

The present invention also provides a chip, which includes the control circuit as described above.

The above technical solution has the following advantages or beneficial effects: by embedding a protection module, an over-temperature protection module, a current limiting module, an over-voltage protection module and a clamping voltage module, the energy generated by the first NMOS tube due to high inductive load at the moment of turning off can be solved. The problem of single-pulse avalanche energy breakdown and damage occurs to protect the first NMOS transistor and has high reliability.

Description of drawings

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the accompanying drawings are for illustration and illustration only, and are not intended to limit the scope of the present invention.

FIG. 1 is a schematic diagram of a circuit structure of an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict.

The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention.

The present invention provides a control circuit for an intelligent low-side power switch, which includes:

A first NMOS transistor Q1;

A second NMOS transistor, the source of the second NMOS transistor is connected to a first resistor and then grounded in parallel with the source of the first NMOS transistor, the drain of the second NMOS transistor and the first NMOS transistor It is connected in parallel to a first node and then connected to a load external terminal LOAD. The gate of the control terminal is connected to a sixth resistor R6 and a seventh resistor R7 and finally connected to a second node 2 in parallel and then connected to a voltage through a second resistor R2 input terminal VIN;

A protection module 3, connected in parallel between the voltage input terminal VIN and the ground GND, for electrostatic protection;

an over-temperature protection module, connected in parallel between the second node 2 and the ground GND, for cutting off the working current of the control terminal of the first NMOS transistor Q1 when the working temperature reaches a preset temperature;

A current limiting module 5 is connected in parallel between the second node 2 and the ground GND, and is provided with a sixth NMOS transistor Q13 and the above-mentioned second NMOS transistor Q2, the gate of the sixth NMOS transistor Q13 and the source of the second NMOS transistor Q2 connected, the drain of the sixth NMS transistor Q13 is connected to the gate of the first NMOS transistor Q1, for when the current collected by the current sampling second NMOS transistor Q2 exceeds a preset current The gate of an NMOS transistor Q1 is discharged, thereby limiting the output current of the first NMOS transistor Q1;

An overvoltage protection module 6 is connected in parallel between the first node 1 and the ground GND, and a fourth qi diode D4 is arranged to pull down the first NMOS transistor when the drain voltage of the first NMOS transistor Q1 exceeds a preset voltage The gate voltage of Q1 turns off the first NMOS transistor Q1;

A clamping module 7 is connected in parallel between the first node 1 and the ground GND, for when the voltage applied between the drain of the first NMOS transistor Q1 and the ground GND is higher than the preset voltage of the clamping module 7, The clamping module 7 is turned on to clamp the voltage applied across the drain and source of the first NMOS transistor Q1 to a preset voltage value, and the first NMOS transistor Q1 avoids drain-source breakdown.

Specifically, in this embodiment, the protection module 3 is connected in parallel with the first NMOS transistor Q1 between the voltage input terminal VIN and the ground GND, so as to protect the first NMOS transistor from static electricity.

In this embodiment, an over-temperature protection module is connected between the second node 2 and the ground GND. When the operating temperature reaches the preset temperature for over-temperature protection, the over-temperature protection module can pull down the first NMOS transistor Q1. control the terminal voltage, so that the first NMOS transistor Q1 is turned off. Further, if the operating temperature decreases, the over-temperature protection module generates a temperature hysteresis. When the operating temperature drops below a certain temperature, the first NMOS transistor Q1 is in an on state.

In this embodiment, the current limiting module 5 is connected between the second node 2 and the ground GND. When the voltage provided by the voltage input terminal VIN is low, the voltages of the control terminals of the first NMOS transistor Q1 and the second NMOS transistor Q2 are equal. , and the second NMOS transistor Q2 and the first resistor R1 can monitor the current of the first NMOS transistor Q1 in real time; when the voltage provided by the voltage input terminal VIN is high, the current of the first NMOS transistor Q1 increases, and the first resistor R1 The voltage at both ends increases, so that the control terminal voltage of the first NMOS transistor Q1 decreases, and the current flowing through the first NMOS transistor Q1 decreases accordingly, so as to protect the first NMOS transistor Q1.

In this embodiment, an overvoltage protection module 6 is connected between the first node 1 and the second node 2. When the drain voltage of the first NMOS transistor Q1 is large, the overvoltage protection module 6 is used to make the first NMOS transistor Q1 larger. The voltage of the control terminal of the transistor Q1 is reduced, so that the first NMOS transistor Q1 is turned off.

In this example, a clamping module 7 is connected in parallel between the first node 1 and the ground GND. When the first NMOS transistor Q1 is turned off, the energy of the breakdown voltage generated by the high inductive load is released, and the first NMOS transistor Q1 is turned off. When the drain voltage of Q1 is clamped to a predetermined value lower than its breakdown voltage, the first NMOS transistor Q1 is effectively prevented from being broken down, so as to protect the first NMOS transistor Q1.

Through the built-in protection module 3, over-temperature protection module, current limiting module 5, over-voltage protection module 6 and voltage clamping module 7, the single-pulse avalanche energy generated by the energy generated by the high inductive load at the moment of turn-off of the first NMOS transistor Q1 is solved. The problem of breakdown and damage is to protect the first NMOS transistor Q1, which has high reliability.

In a preferred embodiment, the protection module 3 includes:

A first PNP transistor VT1, the emitter of the first PNP transistor VT1 is connected to the voltage input terminal VIN, the base of the first PNP transistor VT1 is short-circuited to the emitter of the first PNP transistor VT1, and the collector of the first PNP transistor VT1 Ground GND.

Specifically, the protection module 3 in the above technical solution is the first PNP tube VT1, and the first PNP tube VT1 plays the role of electrostatic protection.

In a preferred embodiment, the over-temperature protection module includes:

a current mirror unit 40, connected in parallel between the second node 2 and the ground GND, and providing a bias current output terminal;

A start-up unit 41 is connected in parallel between the bias current output terminal and the ground GND, and provides a start-up current output terminal;

A PATA current source 42 is connected in parallel between the bias current output terminal and the ground GND, and a start-up terminal is connected to the start-up current output terminal for generating a PATA current proportional to the operating temperature according to the bias current;

An over-temperature control unit 43 is connected in parallel between the bias current output terminal and the ground GND to control the current input to the control terminal of the first NMOS transistor Q1 when the operating temperature increases.

Specifically, the over-temperature protection module in the above technical solution includes a current mirror unit 40 , a start-up unit 41 , a PATA current source 42 and an over-temperature control unit 43 .

In this embodiment, the bias current output terminal is provided through the current mirror unit 40 and the bias current is output.

In this embodiment, before the entire circuit system is powered on, the working state of each module is 0. After the voltage input terminal VIN provides a voltage, the starting unit 41 is turned on to start the working state of other modules.

In this embodiment, after the startup of the startup unit 41 is completed, the PATA current that is proportional to the operating temperature can be generated according to the bias current provided by the current mirror unit 40 .

In this embodiment, when the operating temperature of the circuit is at a normal temperature, the first NMOS transistor Q1 also works normally, but when the operating temperature reaches the preset temperature for over-temperature protection, the over-temperature control unit 43 can pull down the first NMOS transistor Q1. The control terminal voltage of the NMOS transistor Q1 turns off the first NMOS transistor Q1. Further, if the operating temperature drops, the over-temperature control unit 43 generates a temperature hysteresis. When the operating temperature drops below a certain temperature, the first NMOS transistor Q1 turns off. is on.

In a preferred embodiment, the current mirror unit 40 includes:

A first PMOS transistor Q3, the source is connected to the second node 2, and the control terminal is short-circuited with the drain;

A second PMOS transistor Q4, the source is connected to the second node 2, the drain is grounded to GND through a first Zener diode D1, the control terminal is connected to the control terminal of the first PMOS transistor Q3, and is connected through a second Zener diode D2 connected to the second node 2;

A third NMOS transistor Q5, the source is grounded to GND, the drain is connected to the drain of the first PMOS transistor Q3, and the control terminal is shorted to the source;

The drain of the second PMOS transistor Q4 forms a bias current output terminal.

Specifically, the above-mentioned current mirror unit 40 includes a first PMOS transistor Q3, a second PMOS transistor Q4, a third NMOS transistor Q5, and a first Zener diode D1 and a second Zener diode D2 for providing bias current, wherein , the second PMOS transistor Q4 mirrors the current of the first PMOS transistor Q3, the drain of the second PMOS transistor Q4 is connected to the cathode of the first Zener diode D1, and provides a bias current for the PATA current source 42 that generates the above-mentioned PATA current, And the first Zener diode D1 serves as a voltage regulator of the PATA current source 42 that generates the PATA current.

In this embodiment, the third NMOS transistor Q5 is used as a constant current source. The anode of the second Zener diode D2 is connected to the control terminal of the second PMOS transistor Q4, and the cathode is connected to the source of the second PMOS transistor Q4 to protect the control terminal of the second PMOS transistor Q4 from being broken down.

In a preferred embodiment, the starting unit 41 includes:

A third PMOS transistor Q5, the source is connected to the bias current output terminal, the drain is grounded through a capacitor C, and the control terminal is short-circuited with the drain;

a fourth PMOS transistor Q6, the source is connected to the bias current output terminal, the drain is grounded to GND, and the control terminal is connected to the control terminal of the third PMOS transistor Q5;

The drain of the fourth PMOS transistor Q6 forms a start-up current output terminal.

Specifically, the start-up unit 41 in the above technical solution includes a third PMOS transistor Q5, a fourth PMOS transistor Q6 and a capacitor C. When the voltage input terminal VIN provides the voltage, the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are turned on, and then the third PMOS transistor Q5 charges both ends of the capacitor C, and the fourth PMOS transistor Q6 is input to the PATA current source 42 When the voltage across the capacitor C is equal to the source voltages of the third PMOS transistor Q5 and the fourth PMOS transistor Q6, the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are turned off, and the startup unit 41 is completed.

In a preferred embodiment, the PTAT current source 42 includes:

A fifth PMOS transistor Q7, the source is connected to the bias current output terminal, and the drain is connected to the startup current output terminal;

A sixth PMOS transistor Q8, the source is connected to the bias current output terminal, the control terminal is short-circuited with the drain, and is connected to the control terminal of the fifth PMOS transistor Q7;

A first NPN transistor VT2, the collector is connected to the drain of the fifth PMOS transistor Q7, the emitter is grounded to GND, and the base and the collector are short-circuited;

A second NPN transistor VT3, the collector is connected to the drain of the sixth PMOS transistor Q8, the emitter is grounded to GND through a third resistor R3, and the base is connected to the base of the first NPN transistor VT2.

Specifically, the above-mentioned PTAT current source 42 is formed by connecting the fifth PMOS transistor Q7 , the sixth PMOS transistor Q8 , the first NPN transistor VT2 , the second NPN transistor VT3 and the third resistor R3 . In this embodiment, the number ratio of the first NPN transistor VT2 and the second NPN transistor VT3 is set to be 1:4, and a plurality of second NPN transistors VT3 are connected in parallel with each other.

In a preferred embodiment, the over-temperature control unit 43 includes:

A seventh PMOS transistor Q9, the source is connected to the bias current output terminal, and the drain is grounded to GND through a first series resistance voltage divider circuit 8;

an eighth PMOS transistor Q10, the source is connected to the bias current output terminal, and the control terminal is connected to the control terminal of the seventh PMOS transistor Q9 and the control terminal of the sixth PMOS transistor Q8;

A third NPN transistor VT4, the collector is connected to the drain of the eighth PMOS transistor Q10, the base is connected to the drain of the seventh PMOS transistor Q9, and the emitter is grounded to GND;

A fourth NMOS transistor Q11, the source is grounded to GND, and the drain is connected to the control terminal of the second NMOS transistor Q2;

In series with each other, a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the drain of the eighth PMOS transistor Q10, the third inverter INV1 The output end of the inverter INV3 is connected to the control end of the fourth NMOS transistor Q11;

A fifth NMOS transistor Q12, the source is grounded GND, the drain is connected to the voltage dividing node of the first series resistance voltage dividing circuit 8, and the control terminal is connected between the second inverter INV2 and the third inverter INV3.

Specifically, in this embodiment, when the operating temperature of the circuit is at a normal temperature, the third NPN transistor VT4 is turned off, and the potential of its collector is relatively high, passing through the first inverter INV1 and the second inverter INV2 connected in series. And the third inverter INV3 outputs a low potential, and inputs the low potential to the control terminal of the fourth NMOS transistor Q11, so that the fourth NMOS transistor Q11 is turned off and the first NMOS transistor Q1 works normally.

In this embodiment, the first series resistance voltage divider circuit 8 includes a fourth resistor R4 and a fifth resistor R5, and the control terminal of the fifth NMOS transistor Q12 is connected between the second inverter INV2 and the third inverter INV3 , the second inverter INV2 outputs a high potential, so that the fifth NMOS transistor Q12 is turned on, and the fourth resistor R4 is short-circuited. When the operating temperature reaches the preset temperature for over-temperature protection, the third NPN transistor VT4 is turned on, its collector outputs a low potential, and then passes through the first inverter INV1, the second inverter INV2 and the third inverter INV3 A high potential is output, thereby pulling down the voltage of the control terminal of the first NMOS transistor Q1, so that the first NMOS transistor Q1 is turned off.

Further, at this time, the second NMOS transistor Q2 is turned off. When the above-mentioned operating temperature is lowered, since the second NMOS transistor Q2 is turned off, the fourth resistor R4 in the first series resistor divider circuit 8 is turned on, so that the third NPN transistor VT4 is turned on. The potential of the base electrode is raised to generate a temperature hysteresis amount. When the operating temperature drops below a certain temperature, the third NPN transistor VT4 is turned off again, so that the first NMOS transistor Q1 is turned on.

In a preferred embodiment, the current limiting module 5 includes:

A sixth NMOS transistor Q13, the drain is connected to the control terminal of the second NMOS transistor Q2, the source is grounded to GND, and the control terminal is connected to the source of the second NMOS transistor Q2;

A second series resistance voltage divider circuit 9 is connected in series between the second node 2 and the control terminal of the second NMOS transistor Q2;

A seventh NMOS transistor Q14, the drain is connected to the second node 2, the source is connected to the voltage dividing node of the second series resistance voltage dividing circuit 9, and the control terminal is short-circuited with the source;

A third Zener diode D3 is connected between the control terminal of the second NMOS transistor Q2 and the control terminal of the sixth NMOS transistor Q13.

Specifically, in this embodiment, the second series resistance voltage divider circuit 9 includes a sixth resistor R6 and a seventh resistor R7, both of which are current-limiting resistors, the first resistor R1 is used as a sampling resistor, and the second NMOS transistor Q2 is used for current sampling The sixth NMOS transistor Q13 is a pull-down transistor. When the voltage provided by the above-mentioned voltage input terminal VIN is low, the voltages of the second NMOS transistor Q2 and the control terminal of the above-mentioned first NMOS transistor Q1 are equal, and the second NMOS transistor Q2 and the first The resistor R1 monitors the current flowing through the first NMOS transistor Q1 in real time.

In this embodiment, when the voltage provided by the above-mentioned voltage input terminal VIN is relatively high, the current flowing through the first NMOS transistor Q1 increases, and the voltage across the first resistor R1 increases, so that the voltage at the control terminal of the sixth NMOS transistor Q13 increases It is turned on and starts to discharge, the voltage of the control terminal of the first NMOS transistor Q1 decreases, so that the current flowing through the first NMOS transistor Q1 decreases, which in turn acts as a current limiter to protect the first NMOS transistor. Q1.

In addition, it should be noted that, in this embodiment, the magnitude of the current limiting value can be determined by adjusting the number ratio of the second NMOS transistors Q2 and the first NMOS transistors Q1 or adjusting the resistance value of the first resistor R1.

In a preferred embodiment, the overvoltage protection module 6 includes:

an eighth NMOS transistor Q15, the drain of which is connected to the control terminal of the first NMOS transistor Q1;

A ninth NMOS transistor Q16, the drain is connected to the source of the eighth NMOS transistor Q15, the source is grounded to GND, and the control terminal is short-circuited with the source;

A tenth NMOS transistor Q17, the drain is connected to the control terminal of the eighth NMOS transistor Q15, the source is grounded to GND, and the control terminal is short-circuited with the source;

A fourth Zener diode D4, the anode is connected to the control terminal of the eighth NMOS transistor Q15, and the cathode is connected to the first node 1;

A fifth Schottky diode D5, the anode is connected to the source of the eighth NMOS transistor Q15, and the cathode is connected to the control terminal of the eighth NMOS transistor Q15;

A sixth Zener diode D6, the anode is connected to the source of the eighth NMOS transistor Q15, and the cathode is grounded to GND.

Specifically, in this embodiment, the eighth NMOS transistor Q15 is a pull-down transistor. When the voltage of the drain of the first NMOS transistor Q1 is greater than the breakdown voltage of the fourth Zener diode D4, the eighth NMOS transistor Q15 is turned on to turn on the first NMOS transistor Q15. The voltage of the control terminal of the NMOS transistor Q1 is pulled down, so that the first NMOS transistor Q1 is turned off.

In a preferred embodiment, the clamping module 7 includes:

A second PNP transistor VT5, the emitter of the second PNP transistor VT5 is connected to the first node 1, the collector of the second PNP transistor VT5 is grounded to GND, and the base and the emitter of the second PNP transistor VT5 are short-circuited.

Specifically, in this embodiment, the clamping module 7 includes a second PNP transistor VT5. When the fifth Schottky diode D5 is used to protect the control terminal of the eighth NMOS transistor Q15, the sixth Zener diode D6 generates overvoltage protection. At the moment when the first NMOS transistor Q1 is turned off, the energy of the breakdown voltage generated by the high inductive load is released, and when the drain voltage of the first NMOS transistor Q1 is clamped to a preset value lower than its breakdown voltage, At the same time, the energy of the breakdown voltage is discharged to the ground, thereby effectively preventing the first NMOS transistor Q1 from being broken down, so as to protect the first NMOS transistor Q1.

In a preferred embodiment, the control circuit is formed in a chip.

The present invention provides a chip, which includes the above-mentioned control circuit.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the embodiments and protection scope of the present invention. Those skilled in the art should be aware of the equivalents made by using the description and illustrations of the present invention. The solutions obtained by substitution and obvious changes shall all be included in the protection scope of the present invention.

Claims (12)

1. A control circuit for an intelligent low-side power switch, characterized in that it includes:

   a first NMOS tube;

   A second NMOS transistor, the source of the second NMOS transistor is connected to a first resistor and then grounded in parallel with the source of the first NMOS transistor, the drain of the second NMOS transistor and the first NMOS transistor connected in parallel to a first node and then connected to a load external terminal, the gate of the control terminal is connected to a sixth resistor and a seventh resistor and finally connected to a second node in parallel and then connected to a voltage input terminal through a second resistor;

   a protection module, connected in parallel between the voltage input terminal and the ground, for electrostatic protection;

   an over-temperature protection module, connected in parallel between the second node and the ground, for cutting off the working current of the control terminal of the first NMOS transistor when the working temperature reaches a preset temperature;

   A current limiting module is connected in parallel between the second node and the ground, and is provided with a sixth NMOS transistor and the second NMOS transistor, the gate of the sixth NMOS transistor and the source of the second NMOS transistor The drain of the sixth NMOS transistor is connected to the gate of the first NMOS transistor, so that when the current collected by the current sampling second NMOS transistor exceeds a preset electrical current, the sixth NMOS transistor is connected The NMOS is turned on to discharge the gate of the first NMOS tube, thereby limiting the output current of the first NMOS tube;

   An overvoltage protection module is connected in parallel between the first node and the ground, and a fourth zener diode is arranged for pulling down when the drain voltage of the first NMOS transistor exceeds a preset voltage The gate voltage of the first NMOS transistor turns off the first NMOS transistor;

   A clamping module, connected in parallel between the first node and the ground, for when the voltage applied between the drain of the first NMOS transistor and the ground is higher than a preset voltage of the clamping module , the clamping module is turned on, and the voltage applied to both ends of the drain and source of the first NMOS transistor is clamped at a preset voltage value, so that the drain-source breakdown of the first NMOS transistor is avoided.
2. The control circuit of claim 1, wherein the protection module comprises:

   A first PNP tube, the emitter of the first PNP tube is connected to the voltage input terminal, the base of the first PNP tube is short-circuited to the emitter of the first PNP tube, the first PNP tube The collector of the tube is grounded.
3. The control circuit of claim 1, wherein the over-temperature protection module comprises:

   a current mirror unit, connected in parallel between the second node and the ground, and providing a bias current output terminal;

   a start-up unit, connected in parallel between the bias current output terminal and the ground, and provides a start-up current output terminal;

   A PATA current source is connected in parallel between the bias current output terminal and the ground, and a start-up terminal is connected to the start-up current output terminal for generating a voltage proportional to the operating temperature according to the bias current PATA current;

   An over-temperature control unit is connected in parallel between the bias current output terminal and the ground, and is used to control the current input to the control terminal of the first NMOS transistor when the operating temperature increases.
4. The control circuit of claim 3, wherein the current mirror unit comprises:

   a first PMOS transistor, the source is connected to the second node, and the control terminal is short-circuited with the drain;

   A second PMOS transistor, the source is connected to the second node, the drain is grounded through a first Zener diode, the control terminal is connected to the control terminal of the first PMOS transistor, and is connected to the ground through a second Zener diode the second node;

   a third NMOS transistor, the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the control terminal is short-circuited with the source;

   The drain of the second PMOS transistor forms the bias current output terminal.
5. The control circuit of claim 3, wherein the starting unit comprises:

   a third PMOS transistor, the source is connected to the bias current output terminal, the drain is grounded through a capacitor, and the control terminal and the drain are short-circuited;

   a fourth PMOS transistor, the source is connected to the bias current output terminal, the drain is grounded, and the control terminal is connected to the control terminal of the third PMOS transistor;

   The drain of the fourth PMOS transistor forms the start-up current output terminal.
6. The control circuit of claim 3, wherein the PTAT current source comprises:

   a fifth PMOS transistor, the source is connected to the bias current output terminal, and the drain is connected to the startup current output terminal;

   a sixth PMOS tube, the source is connected to the bias current output terminal, the control terminal is short-circuited with the drain, and is connected to the control terminal of the fifth PMOS tube;

   a first NPN tube, the collector is connected to the drain of the fifth PMOS tube, the emitter is grounded, and the base and the collector are short-circuited;

   A second NPN transistor, the collector is connected to the drain of the sixth PMOS transistor, the emitter is grounded through a third resistor, and the base is connected to the base of the first NPN transistor.
7. The control circuit of claim 6, wherein the over-temperature control unit comprises:

   a seventh PMOS transistor, the source is connected to the bias current output terminal, and the drain is grounded through a first series resistance voltage divider circuit;

   an eighth PMOS transistor, the source is connected to the bias current output terminal, and the control terminal is connected to the control terminal of the seventh PMOS transistor and the control terminal of the sixth PMOS transistor;

   a third NPN transistor, the collector is connected to the drain of the eighth PMOS transistor, the base is connected to the drain of the seventh PMOS transistor, and the emitter is grounded;

   a fourth NMOS transistor, the source is grounded, and the drain is connected to the control terminal of the second NMOS transistor;

   In series with each other, a first inverter, a second inverter and a third inverter, the input end of the first inverter is connected to the drain of the eighth PMOS transistor, the first inverter The output end of the three-inverter is connected to the control end of the fourth NMOS transistor;

   A fifth NMOS transistor, the source is grounded, the drain is connected to the voltage dividing node of the first series resistance voltage divider circuit, and the control terminal is connected between the second inverter and the third inverter.
8. The control circuit of claim 3, wherein the current limiting module comprises:

   a second series resistance voltage divider circuit, connected in series between the second node and the control terminal of the second NMOS transistor;

   a seventh NMOS transistor, the drain is connected to the second node, the source is connected to the voltage dividing node of the second series resistance voltage divider circuit, and the control terminal is shorted to the source;

   A third Zener diode is connected between the control terminal of the second NMOS transistor and the control terminal of the sixth NMOS transistor.
9. The control circuit of claim 3, wherein the overvoltage protection module comprises:

   an eighth NMOS transistor, the drain of which is connected to the control terminal of the first NMOS transistor;

   a ninth NMOS transistor, the drain is connected to the source of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;

   a tenth NMOS transistor, the drain is connected to the control terminal of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;

   a fourth Zener diode, the anode is connected to the control terminal of the eighth NMOS transistor, and the cathode is connected to the first node;

   a fifth Schottky diode, the positive electrode is connected to the source electrode of the eighth NMOS transistor, and the negative electrode is connected to the control terminal of the eighth NMOS transistor;

   A sixth Zener diode, the anode is connected to the source of the eighth NMOS transistor, and the cathode is grounded.
10. The control circuit of claim 3, wherein the clamping module comprises:

    A second PNP tube, the emitter of the second PNP tube is connected to the first node, the collector of the second PNP tube is grounded, and the base of the second PNP tube and the emitter are short-circuited.
11. The control circuit according to any one of claims 1-10, wherein the control circuit is formed in a chip.
12. A chip, characterized by comprising the control circuit according to any one of claims 1-10.

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