WO2022110889A1 - 半导体器件的制备方法及屏蔽栅沟槽器件 - Google Patents

半导体器件的制备方法及屏蔽栅沟槽器件 Download PDF

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WO2022110889A1
WO2022110889A1 PCT/CN2021/110551 CN2021110551W WO2022110889A1 WO 2022110889 A1 WO2022110889 A1 WO 2022110889A1 CN 2021110551 W CN2021110551 W CN 2021110551W WO 2022110889 A1 WO2022110889 A1 WO 2022110889A1
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trench
layer
polysilicon
dielectric layer
polysilicon structure
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French (fr)
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冯冰
张建栋
贺腾飞
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

Definitions

  • the present application relates to the technical field of semiconductors, and in particular, to a preparation method of a semiconductor device and a shielded gate trench device.
  • Shielded gate trench (SGT, Shield Gate trench) products are easy to form small holes on both sides of the top of the shielded gate polysilicon.
  • SGT Shield Gate trench
  • the polysilicon gate is subsequently formed in the deep trench, the polysilicon gate is likely to enter the small hole, resulting in a gate-source short circuit.
  • the protruding structure on the top of the shielding gate is easy to form a sharp charge concentration, it may cause the breakdown and leakage of the shielding gate and the gate during operation.
  • the present invention provides a preparation method of a semiconductor device, comprising:
  • a substrate with trenches Obtaining a substrate with trenches, a first dielectric layer is formed on the inner wall of the trench, a polysilicon structure is formed in the space where the first dielectric layer is not formed in the trench, and the top of the polysilicon structure is lower than the lining the surface of the bottom;
  • a second dielectric layer is filled into the trench, and the second dielectric layer fills the trench.
  • the present invention also provides a shielded gate trench device, comprising:
  • the substrate is provided with grooves
  • a shielding gate dielectric layer located at the bottom and inner wall of the trench
  • the shielding gate polysilicon layer is disposed in the trench, and two sides of the top of the shielding gate polysilicon layer are slope structures extending downward.
  • 1 is a scanning electron microscope photograph of cracks under the silicon nitride mask layer and small holes on both sides of the top of the polysilicon of the shielded gate after the silicon dioxide is filled in the trench of an exemplary shielded gate trench device;
  • FIG. 2 is a schematic flowchart of a method for fabricating a semiconductor device in an embodiment
  • step S102 is a schematic flowchart of step S102 in an embodiment
  • FIG. 4 is a schematic cross-sectional structural diagram of a substrate on which a mask layer is formed in a method for fabricating a semiconductor device provided in an embodiment
  • FIG. 5 is a schematic cross-sectional structure diagram of the semiconductor device corresponding to FIG. 4 after the trench is formed;
  • FIG. 6 is a schematic cross-sectional structure diagram of the semiconductor device corresponding to FIG. 5 after forming the polysilicon structure in one embodiment
  • FIG. 7 is a schematic cross-sectional structure diagram of the semiconductor device corresponding to FIG. 6 after removing the part of the first dielectric layer higher than the polysilicon structure;
  • FIG. 8 is a schematic cross-sectional structure diagram of the semiconductor device after plasma bombardment corresponding to FIG. 7;
  • FIG. 9 is a schematic cross-sectional structure diagram of a semiconductor device after forming a second dielectric layer in an embodiment, and is also a cross-sectional structure schematic diagram of a shielded gate trench device;
  • FIG. 10 is a schematic diagram of a partial fabrication process of an exemplary shielded gate trench device
  • FIG. 11 is a topographical comparison diagram of a scanning electron microscope photograph of a cross-sectional structure of a semiconductor device prepared by the preparation method of the present application and a conventional manufacturing method, and is also a topography of a scanning electron microscope photograph of the cross-sectional structure of the shielded gate trench device. Appearance comparison chart.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the invention.
  • a shielded gate oxide layer is formed on the inner wall of the deep trench, and a shielded gate polysilicon structure is formed in the deep trench.
  • the top of the gate polysilicon structure is lower than the surface of the substrate, that is, the top of the shielding gate oxide layer, and then the part of the shielding gate oxide layer higher than the shielding gate polysilicon structure is removed by a wet etching process.
  • the shield gate polysilicon structure Due to the isotropic characteristics of wet etching, in the process of completely removing the part of the shield gate oxide layer formed on the inner wall of the deep trench which is higher than the shield gate polysilicon structure through the etching process, the shield gate polysilicon structure will be etched away.
  • the shielding gate oxide layers on both sides of the top make the edge of the top of the shielding gate polysilicon structure exposed, and two small trenches between the sidewalls of the shielding gate polysilicon structure and the sidewalls of the deep trench are formed inside the deep trench, and the small trenches The depth of the trench deepens as the thickness of the shield gate oxide increases.
  • the rate of oxidizing polysilicon to form a sacrificial oxide layer Differently, after the Sacrificial Oxide growth is completed, the small trenches on both sides of the top of the shielded gate polysilicon structure will become a concave structure with a narrow upper and a lower width (that is, a convex structure is formed on both sides of the top of the shielded polysilicon structure).
  • the surface of the substrate is covered with a silicon nitride mask layer for forming the trench.
  • a shielding gate oxide layer is grown in the trench with dry oxygen, the silicon nitride mask layer below the silicon nitride mask layer will be consumed.
  • the silicon on the sidewall of the trench after the subsequent wet etching process removes the part of the shielding gate oxide layer higher than the polysilicon structure of the shielding gate, the silicon nitride mask layer will protrude relative to the trench, that is, the silicon nitride mask layer is close to the trench Portions of the grooves are suspended above the grooves.
  • the etching rate in the trench is different during the subsequent wet etching of the polysilicon gate oxide layer, resulting in a difference in the thickness of the polysilicon gate oxide layer between the gate and the source, which is prone to breakdown and leakage. .
  • the present application provides a new fabrication method of a semiconductor device and a new shielded gate trench device.
  • FIG. 2 it is a schematic flowchart of a method for fabricating a semiconductor device in an embodiment.
  • a preparation method of a semiconductor device includes the following steps:
  • a substrate with a trench is obtained, a first dielectric layer is formed on the inner wall of the trench, a polysilicon structure is formed in the space where the first dielectric layer is not formed, and the top of the polysilicon structure is lower than the surface of the substrate.
  • the substrate can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, etc., and the trench can be opened in a single crystal silicon epitaxial layer on the surface of the substrate.
  • the portion of the trench where the first dielectric layer is higher than the polysilicon structure is removed to obtain a shielding gate dielectric layer composed of the remaining first dielectric layer.
  • Both sides of the top of the polysilicon structure formed in the trench are removed by plasma bombardment, so that the top of the polysilicon structure is partially removed, the width of the top of the polysilicon structure is narrowed, and the top shape of the polysilicon structure becomes smooth. It can be avoided that when the first oxide layer (ie, the sacrificial oxide layer) is thermally grown in the trench in step S108, due to the different crystal orientations of the polysilicon at the top of the polysilicon structure and other positions, the growth rate of the first oxide layer at the top edge of the polysilicon structure is faster, and the polysilicon The first oxide layer is thicker at the top of the structure and at its top edge, resulting in a structure that is convex on both sides of the top.
  • the first oxide layer ie, the sacrificial oxide layer
  • a furnace tube is used to grow a thin sacrificial oxide layer.
  • the first dielectric layer is an insulating oxide layer
  • step S102 includes:
  • step S102 the substrate on which the mask layer is formed is etched, and a trench is formed at the position where the substrate is not covered by the mask layer.
  • step S102 includes:
  • FIG. 4 to FIG. 9 introduce the fabrication method of the semiconductor device of the present application by taking the fabrication of a shielded gate trench device as an example.
  • a silicon oxide film 103 is formed on the substrate 102 , and the mask layer is located on the silicon oxide film 103 .
  • step S202 may specifically include: the first step, forming a mask layer 104 on the substrate 102 , and the mask layer 104 exposes part of the silicon oxide film 103 (and part of the substrate 102 ).
  • an etching process is performed to remove the silicon oxide film 103 on the substrate 102 that is not covered by the mask layer 104 and a part of the substrate 102 below it, and a trench 106 is formed in the substrate 102, and the residual oxide film 106 is formed in the substrate 102.
  • the oxide layer 202 constituted by the silicon thin film 103 .
  • the mask layer 104 includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbide layer, a silicon carbonitride layer, and a silicon oxycarbonitride layer.
  • the mask layer 104 is exemplified as a silicon nitride layer.
  • silicon on the inner wall of the trench 106 is oxidized by a thermal oxidation process, and an insulating oxide layer 108 is formed on the inner wall of the trench 106 .
  • the substrate 102 is put into a furnace tube and oxygen is introduced to conduct dry oxygen oxidation to form an insulating oxide layer 108; layer 108; or the substrate 102 is put into the furnace tube, and oxygen and hydrogen are introduced to conduct hydrogen-oxygen synthesis and oxidation to form an insulating oxide layer 108; or the substrate 102 is put into the furnace tube, and oxygen and chlorine-containing gas are introduced to do the Chlorine is oxidized to form an insulating oxide layer 108 and the like.
  • a polysilicon structure 110 is formed in the trench 106 , and the top of the polysilicon structure 110 is lower than the surface of the substrate 102 .
  • the polysilicon structure 110 may be formed by a conventional process of forming a structure whose top is lower than the surface of the substrate, for example, polysilicon is deposited and then etched back, which will not be repeated here.
  • the portion of the insulating oxide layer 108 higher than the polysilicon structure 110 is removed by wet etching to obtain a shielding gate dielectric layer 204 composed of the remaining insulating oxide layer 108 .
  • a wet etching process is performed to remove the insulating oxide layer 108 located between the top of the opening of the trench 106 and the top of the polysilicon structure 110, and at the same time, the part of the oxide layer 202 located above the insulating oxide layer 108 is removed, so that the remaining insulating oxide layer 108 is removed.
  • the gate dielectric layer 204 formed by the oxide layer 108 is shielded.
  • the wet etching process is isotropic, and the ratio of the depth and width of the insulating oxide layer 108 to be removed on the sidewall of the trench 106 is greater than 1, after the wet etching process, it is located on the top of the polysilicon structure 110 The insulating oxide layers 108 on both sides are removed so that the top of the polysilicon structure 110 is higher than the top of the shielding gate dielectric layer 204 .
  • the shielding gate dielectric layer 204 After the shielding gate dielectric layer 204 is obtained, plasma bombardment is performed to partially remove the top of the polysilicon structure 110 . It can be avoided that when the first oxide layer (that is, the sacrificial oxide layer) is thermally grown in the trench, due to the different crystal orientations of the polysilicon on the top of the polysilicon structure 110 and other positions, the growth rate of the first oxide layer on the top edge of the polysilicon structure 110 is faster, and the polysilicon The first oxide layer on the top of the structure 110 and its top edge is thicker, resulting in the formation of a convex structure on both sides of the top.
  • the first oxide layer that is, the sacrificial oxide layer
  • the included angle at the top of the s is an obtuse angle, and a shielded gate polysilicon layer 210 composed of the remaining polysilicon structures 110 is obtained.
  • both sides of the polysilicon structure 110 can be filled to avoid small holes, so as to prevent the polysilicon gate from entering the small holes when the polysilicon gate is formed in the trench 106 , causing the gate source short-circuit problem.
  • step S106 simultaneously bombards the edge of the mask layer 104 located at the top of the trench 106, so that the edge of the mask layer 104 is partially removed.
  • the width of the top of the mask layer 104 is narrowed to avoid the subsequent formation of the polysilicon gate oxide layer filling the trench 106 by plasma chemical vapor deposition, due to the directionality of the plasma at the edge of the wafer. Cracks are formed below where the layer 104 protrudes. The crack will cause different etching rates in the trench 106 during subsequent wet etching of the polysilicon gate oxide layer, resulting in a difference in the thickness of the polysilicon gate oxide layer between the gate and source electrodes, which is prone to breakdown leakage problems. In the actual production process, when the edge of the mask layer 104 is removed by plasma bombardment, the oxide layer 202 located under the mask layer 104 may not be damaged.
  • the step of bombarding the edge of the mask layer 104 at the top of the trench 106 to partially remove the edge of the mask layer 104 includes: removing the part of the mask layer 104 protruding from the top of the inner wall of the trench 106 , so that the bottom edge of mask layer 104 is aligned with the top of trench 102 . That is, the suspended portion of the mask layer 104 above the trench 106 is removed.
  • the step of bombarding the edge of the polysilicon structure 110 with plasma includes: using a high density plasma chemical vapor deposition (HDPCVD) tool to form plasma and bombard the edge of the polysilicon structure 110 .
  • HDPCVD high density plasma chemical vapor deposition
  • the process gases for HDPCVD include helium and oxygen.
  • the volume flow ratio of helium to oxygen in the HDPCVD process gas is not less than 1. Further, the flow rate of helium gas is greater than or equal to 90 sccm and less than or equal to 110 sccm, and the flow rate of oxygen gas is greater than or equal to 90 sccm and less than or equal to 110 sccm.
  • the top radio frequency power (RF-TOP) is between 4700W and 5000W, such as 4850W; the bottom radio frequency power (RF-BIAS) is between 2600W and 3100W, such as 2850W; the side radio frequency power (RF-SIDE) is between 800W and 1000W.
  • the reaction pressure is between 3mTorr and 5mTorr, for example, 3mTorr, and the above descriptions include both endpoints.
  • the parameters of the high-density plasma etching process are adjusted according to the thickness of the first dielectric layer and the feature size of the deep groove. Within a certain range, the larger the thickness of the first dielectric layer, the larger the feature size of the deep groove. , the higher the rate of the high-density plasma etching process, the longer the time.
  • step S110 includes: forming a second dielectric layer through a high-density plasma chemical vapor deposition process.
  • the second dielectric layer 112 filling the trenches 106 is formed by a high-density plasma chemical vapor deposition process.
  • the high-density plasma chemical vapor deposition process further includes a chemical mechanical polishing step.
  • the second dielectric layer 112 includes a silicon oxide layer.
  • the method for fabricating the semiconductor device further includes: etching the second dielectric layer 112 to obtain a gate oxide layer located above the shielded gate polysilicon layer 210 .
  • the sharp corners exposed by the isotropic wet etching of the top edge of the polysilicon structure can be improved.
  • the first dielectric layer on both sides of the top of the polysilicon structure will be removed, so that the top of the polysilicon structure is removed.
  • the edge is exposed; when the exposed polysilicon structure thermally grows the first oxide layer, since the crystal orientation of the top of the polysilicon structure is different from that of the polysilicon structure at other positions, the growth rate of the first oxide layer at the top edge of the polysilicon structure will be faster, so The first oxide layer on the top of the polysilicon structure and its top edge is thicker, forming a protruding structure on both sides of the top, which makes it difficult to fill the space under the second dielectric layer when filling the trench with the second dielectric layer.
  • the filling ability of the second dielectric layer during filling can achieve the purpose of avoiding the formation of small holes on both sides of the top of the polysilicon structure, thereby achieving the purpose of eliminating the gate-source short circuit caused by abnormal filling.
  • steps in the flowcharts of FIG. 1 and FIG. 3 are sequentially displayed according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 1 and FIG. 3 may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The order of execution is also not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages within the other steps.
  • the present invention also provides a shielded gate trench device, comprising:
  • the substrate 102 is provided with a trench 106;
  • the shielding gate dielectric layer 204 is located at the bottom and inner wall of the trench 106;
  • the shielding gate polysilicon layer 210 is disposed in the trench 106 . Two sides of the top of the shielding gate polysilicon layer 210 are downwardly extending slope structures 208 . The angle between the slope structure 208 and the top 206 of the shielding gate dielectric layer 204 is an obtuse angle.
  • the shielded gate trench device further includes a gate oxide layer, and the gate oxide layer is located above the shielded gate polysilicon layer 210 .
  • FIG. 11 it is a morphology comparison diagram of SEM photographs of the cross-sectional structure of the semiconductor device prepared by the preparation method of the semiconductor device of the present application and the traditional preparation method. It can be seen from FIG.
  • the semiconductor device made by the preparation method of the semiconductor device in the application has a smooth top shape of the top of the polysilicon layer of the shielded gate (the part circled by the dotted line in the trench in the figure), has no voids on both sides, and has no abnormal filling, and the trench is There is no crack at the opening of the slot (the part circled by the dotted line at the opening of the slot in the figure).
  • the shielded gate polysilicon layer is disposed in the trench and is made of polysilicon, and two sides of the top of the shielded gate polysilicon layer are downwardly extending slope structures, and the slope structures and the The included angle of the top of the shielding gate dielectric layer is an obtuse angle.
  • the width of the top of the polysilicon structure will become smaller, so that the thermally grown first oxide layer will not form the above-mentioned protruding structure, so it can avoid affecting the filling ability of the second dielectric layer when filling, so as to avoid forming on both sides of the top of the polysilicon structure.
  • the purpose of the small hole is that the angle between the slope and the top end of the shielding gate dielectric layer is an obtuse angle.
  • the width of the top of the polysilicon structure is small, and the thermally grown protruding structure will not be formed on the top of the polysilicon structure, which can avoid affecting the filling ability of the polysilicon gate when filling, and achieve the purpose of avoiding the formation of small holes on both sides of the top of the polysilicon structure, thereby achieving The purpose of eliminating the gate-source short circuit caused by filling abnormality.

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Abstract

本发明涉及一种半导体器件的制备方法及屏蔽栅沟槽器件，所述方法包括：获取开设有沟槽的衬底，沟槽内壁形成有第一介质层，所述沟槽内未形成所述第一介质层的空间形成有多晶硅结构，所述多晶硅结构的顶部低于所述衬底的表面；湿法刻蚀去除所述第一介质层高于所述多晶硅结构的部分；等离子体轰击所述多晶硅结构的顶部，使所述多晶硅结构的顶部被部分去除；在所述沟槽内壁和所述多晶硅结构表面热生长第一氧化层；向所述沟槽内填充第二介质层，所述第二介质层将所述沟槽填满。本申请通过等离子体轰击多晶硅结构的边缘，使得多晶硅结构顶部的宽度变小，达到避免在多晶硅结构顶部两侧形成小孔的目的，进而达到消除填充异常造成的栅源短路的目的。

Description

半导体器件的制备方法及屏蔽栅沟槽器件 技术领域
本申请涉及半导体技术领域，特别是涉及一种半导体器件的制备方法，及一种屏蔽栅沟槽器件。
背景技术
屏蔽栅沟槽(SGT，Shield Gate trench)产品在屏蔽栅多晶硅顶部两侧容易形成小孔。后续在深沟槽内形成多晶硅栅时，多晶硅栅容易进入小孔中，造成栅源短路。且由于屏蔽栅顶部的突出结构易形成尖端电荷集中，可能会造成屏蔽栅和栅极在工作时有发生击穿漏电。
发明内容
基于此，有必要提供一种半导体器件的制备方法及一种屏蔽栅沟槽器件。
为了实现上述目的，一方面，本发明提供了一种半导体器件的制备方法，包括：
获取开设有沟槽的衬底，沟槽内壁形成有第一介质层，所述沟槽内未形成所述第一介质层的空间形成有多晶硅结构，所述多晶硅结构的顶部低于所述衬底的表面；
湿法刻蚀去除所述第一介质层高于所述多晶硅结构的部分；
等离子体轰击所述多晶硅结构的顶部，使所述多晶硅结构的顶部被部分去除；
在所述沟槽内壁和所述多晶硅结构表面热生长第一氧化层；
向所述沟槽内填充第二介质层，所述第二介质层将所述沟槽填满。
本发明还提供了一种屏蔽栅沟槽器件，包括：
衬底，开设有沟槽；
屏蔽栅介质层，位于所述沟槽的底部及内壁；
屏蔽栅多晶硅层，设于所述沟槽内，所述屏蔽栅多晶硅层的顶部的两侧为向下延伸的斜坡结构。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、 目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为示例性的屏蔽栅沟槽器件在沟槽内填充二氧化硅后氮化硅掩膜层下的裂缝及屏蔽栅多晶硅顶部两侧小孔的扫描电镜照片；
图2为一实施例中半导体器件的制备方法的流程示意图；
图3为一实施例中步骤S102的流程示意图；
图4为一实施例中提供的半导体器件的制备方法中形成有掩膜层的衬底的截面结构示意图；
图5为图4对应的形成沟槽后半导体器件的截面结构示意图；
图6为一实施例中图5对应的形成多晶硅结构后半导体器件的截面结构示意图；
图7为图6对应的去除第一介质层高于多晶硅结构的部分后半导体器件的截面结构示意图；
图8为图7对应的进行等离子体轰击后半导体器件的截面结构示意图；
图9为一实施例中形成第二介质层后半导体器件的截面结构示意图，亦为屏蔽栅沟槽器件的截面结构示意图；
图10是一示例性的屏蔽栅沟槽器件的部分制备流程示意图；
图11为以本申请的制备方法和以传统的制备方法分别制成的半导体器件的截面结构的扫描电镜照片的形貌对比图，亦为屏蔽栅沟槽器件的截面结构的扫描电镜照片的形貌对比图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术 人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
参照图10，一示例性的屏蔽栅沟槽(SGT，Shield Gate trench)产品的制备过程中，在深沟槽内壁形成有屏蔽栅氧化层，在深沟槽内形成有屏蔽栅多晶硅结构，屏蔽栅多晶硅结构的顶部低于衬底的表面即屏蔽栅氧化层的顶部，然后通过湿法刻蚀工艺去除屏蔽栅氧化层高于屏蔽栅多晶硅结构的部分。由于湿法刻蚀具有各向同性的特点，在通过刻蚀工艺完全去除形成于深沟槽内壁的屏蔽栅氧化层高于屏蔽栅多晶硅结构的部分的过程中，会刻蚀掉屏蔽栅多晶硅结构顶部两侧的屏蔽栅氧化层，使得屏蔽栅多晶硅结构顶部的边缘露出，在深沟槽内部形成两个位于屏蔽栅多晶硅结构侧壁与深沟槽侧壁之间的小沟槽，并且小沟槽的深度随着屏蔽栅氧化层的厚度增加而加深。
后续通过热氧化工艺在深沟槽中生长一层薄的牺牲氧化层(Sacrificial Oxide)时，由于屏蔽栅多晶硅结构的顶部和其他位置的多晶硅结构的晶向不同，氧化多晶硅形成牺牲氧化层的速率不同，Sacrificial Oxide生长完成后，位于屏蔽栅多晶硅结构顶部两侧的小沟槽会变成上窄下宽的内凹结构(即屏蔽栅多晶硅结构顶部两侧形成外凸的结构)，通过高密度等离子体化学气相淀积工艺向深沟槽中填充多晶硅栅氧化层时，难以将屏蔽栅多晶硅结构顶部两侧的小沟槽中内凹结构的位置填满，从而在小沟槽内形成小孔(如图1所示)，并且小沟槽内部填充的多晶硅栅氧化层的质量不佳，容易造成栅源漏电，后续在深沟槽内形成多晶硅栅时，多晶硅栅容易进入小孔中，造成栅源短路。
其次，形成沟槽后，衬底表面覆盖有用于形成沟槽的氮化硅掩膜层，在沟槽内干氧生长了一层屏蔽栅氧化层时，会消耗氮化硅掩膜层下方位于沟槽侧壁的硅，后续通过湿法刻蚀工艺去除屏蔽栅氧化层高于屏蔽栅多晶硅结构的部分后，氮化硅掩膜层相对沟槽会突出，即氮化硅掩膜层靠近沟槽的部分在沟槽上方悬空。在后续通过等离子体化学气相淀积形成填充沟槽的多晶硅栅氧化层时，由于晶圆边缘处的等离子体具有倾斜的方向，会在氮化硅掩膜层突出位置的下方形成小的裂缝(如图1所示)，使得后续湿法腐蚀多晶硅栅氧 化层时沟槽内的腐蚀速率不同，导致栅极和源极之间的多晶硅栅氧化层厚度有高低差异，容易出现击穿漏电的问题。
针对上述问题，本申请提供一种新的半导体器件的制备方法及一种新的屏蔽栅沟槽器件。
参见图2，为一实施例中半导体器件的制备方法的流程示意图。
如图2示，在其中一个实施例中，提供一种半导体器件的制备方法，该制备方法包括以下步骤：
S102，获取开设有沟槽的衬底。
获取开设有沟槽的衬底，沟槽内壁形成有第一介质层，沟槽内未形成第一介质层的空间形成有多晶硅结构，多晶硅结构的顶部低于衬底的表面。
衬底可以是硅衬底、锗衬底、锗硅衬底、碳化硅衬底等，沟槽可以开设于衬底表面的单晶硅外延层中，以下以衬底为硅衬底进行描述。
S104，湿法刻蚀去除所述第一介质层高于所述多晶硅结构的部分。
通过湿法刻蚀工艺，去除沟槽中第一介质层高于多晶硅结构的部分，得到由剩余第一介质层构成的屏蔽栅介质层。
S106，等离子体轰击所述多晶硅结构的顶部，使所述多晶硅结构的顶部被部分去除。
通过等离子体轰击去除形成于沟槽中的多晶硅结构顶部两侧，使得多晶硅结构的顶部被部分去除，多晶硅结构的顶部宽度变窄，多晶硅结构顶部的尖角形貌变得平缓。可以避免步骤S108在沟槽中热生长第一氧化层(即牺牲氧化层)时，因多晶硅结构顶部和其他位置的多晶硅晶向不同，多晶硅结构顶部边缘的第一氧化层生长速度更快，多晶硅结构顶部及其顶部边缘的第一氧化层更厚，而导致形成顶部两侧外凸的结构。
S108，在所述沟槽内壁和所述多晶硅结构表面热生长第一氧化层。
在其中一个实施例中，是使用炉管长一层薄的牺牲氧化层。
S110，向所述沟槽内填充第二介质层，所述第二介质层将所述沟槽填满。
在一个实施例中，第一介质层是绝缘氧化层，步骤S102包括：
第一步，对形成有掩膜层的衬底进行刻蚀，在衬底未覆盖掩膜层的位置形成沟槽。第二步，通过化学气相淀积工艺在沟槽内壁形成第一介质层。第三步，在沟槽内未形成第一介质层的空间形成多晶硅结构，多晶硅结构的顶部低于衬底的表面。其中，第三步可以采用常规的形成顶部低于衬底的表面的结构的工艺方式进行，这里不做赘述。图3为一实施例中步骤S102的流程示意图。在该实施例中，第一介质层是绝缘氧化层，步骤S102包括：
S202，对形成有掩膜层的衬底进行刻蚀，在衬底未覆盖掩膜层的位置形成沟槽。
图4至图9以制备屏蔽栅沟槽器件为例对本申请的半导体器件的制备方法进行介绍。参见图4，在其中一个实施例中，衬底102上形成有氧化硅薄膜103，掩膜层位于氧化硅薄膜103上。
一并参见图5，步骤S202具体可以包括：第一步，在衬底102上形成掩膜层104，掩膜层104露出部分氧化硅薄膜103(和部分衬底102)。第二步，进行刻蚀工艺，去除衬底102上未被掩膜层104覆盖的氧化硅薄膜103及其下方的部分衬底102，在衬底102中形成沟槽106，并得到由剩余氧化硅薄膜103构成的氧化层202。
在其中一个实施例中，掩膜层104至少包括氮化硅层、氮氧化硅层、碳氧化硅层、碳氮化硅层、碳氮氧化硅层中的一种。以下以掩膜层104是氮化硅层进行示例性说明。
S204，在沟槽内壁热生长形成所述绝缘氧化层。
如图6，通过热氧化工艺氧化沟槽106内壁的硅，在沟槽106的内壁形成绝缘氧化层108。例如将衬底102放入炉管中通入氧气，进行干氧氧化，形成绝缘氧化层108；或者将衬底102放入炉管中通入氧气和水蒸气，进行湿氧氧化，形成绝缘氧化层108；或者将衬底102放入炉管中通入氧气和氢气，进行氢氧合成氧化，形成绝缘氧化层108；或者衬底102放入炉管中通入氧气和含氯气体，进行掺氯氧化，形成绝缘氧化层108等。
在沟槽106的内壁形成绝缘氧化层108之后，在沟槽106中形成多晶硅结构110，多晶硅结构110的顶部低于所述衬底102的表面。在实际应用中，可以采用常规的形成顶部低于衬底的表面的结构的工艺方式形成多晶硅结构110，例如淀积多晶硅后回刻，这里不做赘述。
如图7所示，形成多晶硅结构110之后，湿法刻蚀去除绝缘氧化层108高于多晶硅结构110的部分，得到由剩余绝缘氧化层108构成的屏蔽栅介质层204。具体地，进行湿法刻蚀工艺，去除位于沟槽106开口顶部与多晶硅结构110顶部之间的绝缘氧化层108，同时氧化层202位于绝缘氧化层108上方的部分被去除，得到由剩余的绝缘氧化层108构成的屏蔽栅介质层204。因湿法刻蚀具有各向同性的特点，且位于沟槽106侧壁上需要去除的绝缘氧化层108的深度和宽度的比值大于1，因此，湿法刻蚀工艺之后，位于多晶硅结构110顶部两侧的绝缘氧化层108会被去除，使得多晶硅结构110的顶部高于屏蔽栅介质层204的顶部。
得到屏蔽栅介质层204之后，进行等离子体轰击，使多晶硅结构110的顶部被部分去除，即使得多晶硅结构110的顶部变窄，多晶硅结构110顶部的尖角形貌变得平缓。可以避免在沟槽中热生长第一氧化层(即牺牲氧化层)时，因多晶硅结构110顶部和其他位置的多晶硅晶向不同，多晶硅结构110顶部边缘的第一氧化层生长速度更快，多晶硅结构110 顶部及其顶部边缘的第一氧化层更厚，而导致形成顶部两侧外凸的结构。
如图8所示，等离子体轰击多晶硅结构110的边缘，使得多晶硅结构110顶部两侧被去除，形成向屏蔽栅介质层204的顶部206延伸的下降斜坡208，斜坡结构208与屏蔽栅介质层204的顶部的夹角为钝角，得到由剩余的多晶硅结构110构成的屏蔽栅多晶硅层210。这样在后续(步骤S110)填充第二介质层时，可以将多晶硅结构110两侧填满，避免出现小孔，从而避免在沟槽106内形成多晶硅栅时，多晶硅栅进入小孔中，造成栅源短路的问题。
参见图6和图7，在沟槽106内干氧生长绝缘氧化层108会消耗掩膜层104下方位于沟槽106侧壁的硅。因此去除绝缘氧化层108高于多晶硅结构110的部分后，掩膜层104相对106会突出。在其中一个实施例中，步骤S106的等离子体同时会轰击位于沟槽106顶部的掩膜层104的边缘，使掩膜层104的边缘被部分去除。此时，掩膜层104的顶部的宽度变窄，避免后续通过等离子体化学气相淀积形成填充沟槽106的多晶硅栅氧化层时，由于晶圆边缘处的等离子体具有方向性，在掩膜层104突出位置的下方形成裂缝。该裂缝会在后续湿法腐蚀多晶硅栅氧化层时导致沟槽106内的腐蚀速率不同，使得栅源极之间的多晶硅栅氧化层厚度有高低差异，容易出现击穿漏电的问题。实际生产工艺中通过等离子体轰击去除掩膜层104的边缘的时候可以不损伤位于掩膜层104下方的氧化层202。
在其中一个实施例中，轰击沟槽106顶部的掩膜层104的边缘，使掩膜层104的边缘被部分去除的步骤包括：去除掩膜层104外凸于沟槽106内壁的顶部的部分，使得掩膜层104的底部边缘与沟槽102的顶部对齐。即去除掩膜层104在沟槽106上方悬空的部分。
在其中一个实施例中，等离子体轰击多晶硅结构110的边缘的步骤包括：采用高密度等离子体化学气相淀积(HDPCVD)机台形成等离子体并轰击多晶硅结构110的边缘。
在其中一个实施例中，HDPCVD的工艺气体包括氦气和氧气。
在其中一个实施例中，HDPCVD工艺气体中氦气和氧气的体积流量比不小于1。进一步地，氦气的流量大于或等于90sccm且小于或等于110sccm，氧气的流量大于或等于90sccm且小于或等于110sccm。顶部射频功率(RF-TOP)在4700W～5000W之间，例如4850W；底部射频功率(RF-BIAS)在2600W～3100W之间，例如2850W；侧面射频功率(RF-SIDE)在800W～1000W之间，例如900W，反应压力在3mTorr～5mTorr之间，例如3mTorr，上述描述均包括两个端点。在实际应用中，根据第一介质层的厚度、深槽的特征尺寸调整高密度等离子体刻蚀工艺的参数，在一定范围内，第一介质层的厚度越大、深槽的特征尺寸越大，高密度等离子体刻蚀工艺的速率越大，时间越长。
参见图9，在其中一个实施例中，步骤S110包括：通过高密度等离子体化学气相淀积 工艺形成第二介质层。
具体地，通过高密度等离子体化学气相淀积工艺形成填充沟槽106的第二介质层112。典型的，高密度等离子体化学气相淀积工艺之后还包括进行化学机械研磨的步骤。
在其中一个实施例中，第二介质层112包括氧化硅层。
在其中一个实施例中，所述半导体器件的制备方法还包括：对第二介质层112进行刻蚀，得到位于屏蔽栅多晶硅层210上方的栅氧化层的步骤。
上述半导体器件的制备方法，通过等离子体轰击多晶硅结构的边缘，能够改善多晶硅结构顶部边缘因湿法刻蚀各向同性而露出的尖角。具体地，上述方法的湿法刻蚀步骤为了将沟槽内壁高于多晶硅结构顶部的第一介质层去除干净，会使得多晶硅结构顶部两侧的第一介质层被去除，从而使多晶硅结构顶部的边缘露出；露出的多晶硅结构在热生长第一氧化层时，由于多晶硅结构顶部的晶向与其他位置的多晶硅结构的晶向不同，多晶硅结构顶部边缘的第一氧化层生长速度会更快，因此多晶硅结构顶部及其顶部边缘的第一氧化层更厚，形成顶部两侧外凸的结构，该外凸结构使得向沟槽内填充第二介质层时难以将第二介质层下方的空间填满，从而形成小孔；而上述等离子体轰击能够去除部分所述边缘的多晶硅，使得多晶硅结构顶部的宽度变小，从而热生长的第一氧化层不会形成上述外凸结构，因此能够避免影响第二介质层填充时的填充能力，达到避免在多晶硅结构顶部两侧形成小孔的目的，进而达到消除填充异常造成的栅源短路的目的。
应该理解的是，虽然图1、图3的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1、图3中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
如图9所示，本发明还提供了一种屏蔽栅沟槽器件，包括：
衬底102，开设有沟槽106；
屏蔽栅介质层204，位于沟槽106的底部及内壁；
屏蔽栅多晶硅层210，设于沟槽106内，屏蔽栅多晶硅层210的顶部的两侧为向下延伸的斜坡结构208，斜坡结构208与屏蔽栅介质层204的顶部206的夹角为钝角。
在其中一个实施例中，屏蔽栅沟槽器件还包括栅氧化层，栅氧化层位于屏蔽栅多晶硅层210的上方。
如图11所示，为以本申请的半导体器件的制备方法和以传统的制备方法分别制成的半导体器件的截面结构的扫描电镜照片的形貌对比图，由图11可以看出，以本申请中的半导体器件的制备方法制成的半导体器件，屏蔽栅多晶硅层顶部(图中沟槽内虚线圈出的部分)的尖角形貌较平缓，两侧无空洞，填充无异常，并且沟槽开口处(图中沟槽开口位置虚线圈出的部分)无裂纹。
上述屏蔽栅沟槽器件，屏蔽栅多晶硅层，设于所述沟槽内，为多晶硅材质，所述屏蔽栅多晶硅层的顶部的两侧为向下延伸的斜坡结构，所述斜坡结构与所述屏蔽栅介质层的顶部的夹角为钝角。多晶硅结构顶部的宽度会变小，从而热生长的第一氧化层也不会形成上述外凸结构，因此能够避免影响第二介质层填充时的填充能力，达到从而避免在多晶硅结构顶部两侧形成小孔的目的所述斜坡与所述屏蔽栅介质层的顶端部的夹角为钝角。使得多晶硅结构顶部的宽度较小，在多晶硅结构顶部不会形成热生长的外凸结构，能够避免影响多晶硅栅填充时的填充能力，达到避免在多晶硅结构顶部两侧形成小孔的目的，进而达到消除填充异常造成的栅源短路的目的。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件的制备方法，包括：
    获取开设有沟槽的衬底，沟槽内壁形成有第一介质层，所述沟槽内未形成所述第一介质层的空间形成有多晶硅结构，所述多晶硅结构的顶部低于所述衬底的表面；
    湿法刻蚀去除所述第一介质层高于所述多晶硅结构的部分；
    等离子体轰击所述多晶硅结构的边缘，使所述多晶硅结构的边缘被部分去除；
    在所述沟槽内壁和所述多晶硅结构表面热生长第一氧化层；以及
    向所述沟槽内填充第二介质层，所述第二介质层将所述沟槽填满。
  2. 根据权利要求1所述的制备方法，其特征在于，所述第一介质层是绝缘氧化层，所述获取开设有沟槽的衬底，沟槽内壁形成有第一介质层，所述沟槽内未形成所述第一介质层的空间形成有多晶硅结构，所述多晶硅结构的顶部低于所述衬底的表面的步骤包括：
    对形成有掩膜层的衬底进行刻蚀，在衬底未覆盖掩膜层的位置形成沟槽；
    在沟槽内壁热生长形成所述绝缘氧化层；
    所述等离子体轰击所述多晶硅结构的边缘的步骤包括：轰击位于所述沟槽顶部的掩膜层的边缘，使所述掩膜层的边缘被部分去除。
  3. 根据权利要求2所述的制备方法，其特征在于，所述掩膜层是氮化硅层。
  4. 根据权利要求1所述的制备方法，其特征在于，所述向所述沟槽内填充第二介质层的步骤包括：通过高密度等离子体化学气相淀积工艺形成所述第二介质层。
  5. 根据权利要求1所述的制备方法，其特征在于，所述等离子体轰击所述多晶硅结构的边缘的步骤采用高密度等离子体化学气相淀积机台形成等离子体。
  6. 根据权利要求5所述的制备方法，其特征在于，所述高密度等离子体化学气相淀积机台形成等离子体的工艺气体包括氦气和氧气。
  7. 根据权利要求6所述的制备方法，其特征在于，所述工艺气体中氦气和氧气的体积流量比不小于1。
  8. 根据权利要求1所述的制备方法，其特征在于，所述等离子体轰击所述多晶硅结构的边缘，使所述多晶硅结构的边缘被部分去除的步骤使得多晶硅结构顶部的两侧在去除后，形成向第一介质层的顶部延伸的多晶硅下降斜坡结构，所述斜坡结构与所述第一介质层的顶部的夹角为钝角。
  9. 根据权利要求2所述的制备方法，其特征在于，所述轰击所述沟槽顶部的掩膜层的边缘，使所述掩膜层的边缘被部分去除的步骤包括：去除掩膜层外凸于所述沟槽内壁的顶部的部分，使得去除后所述掩膜层不再外凸于所述沟槽内壁的顶部。
  10. 根据权利要求1所述的制备方法，其特征在于，所述半导体器件是屏蔽栅沟槽器件，所述多晶硅结构用于形成屏蔽栅结构。
  11. 一种屏蔽栅沟槽器件，包括：
    衬底，开设有沟槽；
    屏蔽栅介质层，位于所述沟槽的底部及内壁；以及
    屏蔽栅多晶硅层，设于所述沟槽内，所述屏蔽栅多晶硅层的顶部的两侧为向下延伸的斜坡结构。
  12. 根据权利要求11所述的屏蔽栅沟槽器件，其特征在于，所述屏蔽栅多晶硅层的顶部高于屏蔽栅介质层的顶部，且所述屏蔽栅多晶硅层的顶部及所述屏蔽栅介质层的顶部均低于所述衬底的表面。
  13. 根据权利要求12所述的屏蔽栅沟槽器件，其特征在于，所述屏蔽栅多晶硅层的宽度由所述屏蔽栅多晶硅层的顶部位置处至所述屏蔽栅介质层的顶部位置处逐渐增大。
  14. 根据权利要求11所述的屏蔽栅沟槽器件，其特征在于，所述斜坡结构与所述屏蔽栅介质层的顶部的夹角为钝角。
  15. 根据权利要求11所述的屏蔽栅沟槽器件，其特征在于，还包括栅氧化层，所述栅氧化层位于所述屏蔽栅多晶硅层的上方。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114975126A (zh) * 2022-07-29 2022-08-30 威晟半导体科技(广州)有限公司 一种降低栅电荷的屏蔽栅沟槽型mosfet制造方法
CN115985769A (zh) * 2022-11-30 2023-04-18 华虹半导体(无锡)有限公司 一种用于改善udsgt产品igss漏电问题的工艺方法
CN116013776A (zh) * 2023-03-02 2023-04-25 绍兴中芯集成电路制造股份有限公司 屏蔽栅沟槽型晶体管的制备方法及屏蔽栅沟槽型晶体管
CN118016593A (zh) * 2024-04-09 2024-05-10 合肥晶合集成电路股份有限公司 一种半导体结构及其制备方法
CN118248737A (zh) * 2024-05-27 2024-06-25 无锡市查奥微电子科技有限公司 沟槽型碳化硅mosfet器件及其制备方法
CN118800802A (zh) * 2024-07-03 2024-10-18 杭州芯迈半导体技术有限公司 一种具有mgd结构的屏蔽栅沟槽器件及其制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115394854B (zh) * 2022-08-22 2025-12-30 华羿微电子股份有限公司 Split Gate MOSFET器件及制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130248982A1 (en) * 2011-06-13 2013-09-26 Semiconductor Components Industries, Llc Semiconductor device with enhanced mobility and method
CN110890424A (zh) * 2018-09-10 2020-03-17 长鑫存储技术有限公司 晶体管、半导体器件及其形成方法
CN111244166A (zh) * 2020-01-19 2020-06-05 上海华虹宏力半导体制造有限公司 一种屏蔽栅结构及其形成方法
CN111261717A (zh) * 2020-01-19 2020-06-09 上海华虹宏力半导体制造有限公司 一种屏蔽栅功率mosfet结构及制作方法
CN111403291A (zh) * 2019-12-30 2020-07-10 广州粤芯半导体技术有限公司 屏蔽栅沟槽功率器件的制造方法
CN111987039A (zh) * 2019-05-22 2020-11-24 无锡华润上华科技有限公司 半导体器件制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1218956A (en) * 1986-01-28 1987-03-10 Thomas Abraham Process for plasma etching polysilicon to produce rounded profile islands
JP2006032410A (ja) * 2004-07-12 2006-02-02 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7385248B2 (en) * 2005-08-09 2008-06-10 Fairchild Semiconductor Corporation Shielded gate field effect transistor with improved inter-poly dielectric
KR101105433B1 (ko) * 2009-07-03 2012-01-17 주식회사 하이닉스반도체 매립게이트를 구비한 반도체장치 및 그 제조 방법
DE102016116019B4 (de) * 2016-08-29 2023-11-23 Infineon Technologies Ag Verfahren zum Bilden eines Halbleiterbauelements
CN107785273B (zh) * 2016-08-31 2020-03-13 无锡华润上华科技有限公司 半导体器件及其制造方法
CN107507765A (zh) * 2017-08-31 2017-12-22 上海华虹宏力半导体制造有限公司 屏蔽栅沟槽功率器件及其制造方法
CN108010847B (zh) * 2017-11-30 2020-09-25 上海华虹宏力半导体制造有限公司 屏蔽栅沟槽mosfet及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130248982A1 (en) * 2011-06-13 2013-09-26 Semiconductor Components Industries, Llc Semiconductor device with enhanced mobility and method
CN110890424A (zh) * 2018-09-10 2020-03-17 长鑫存储技术有限公司 晶体管、半导体器件及其形成方法
CN111987039A (zh) * 2019-05-22 2020-11-24 无锡华润上华科技有限公司 半导体器件制备方法
CN111403291A (zh) * 2019-12-30 2020-07-10 广州粤芯半导体技术有限公司 屏蔽栅沟槽功率器件的制造方法
CN111244166A (zh) * 2020-01-19 2020-06-05 上海华虹宏力半导体制造有限公司 一种屏蔽栅结构及其形成方法
CN111261717A (zh) * 2020-01-19 2020-06-09 上海华虹宏力半导体制造有限公司 一种屏蔽栅功率mosfet结构及制作方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114975126A (zh) * 2022-07-29 2022-08-30 威晟半导体科技(广州)有限公司 一种降低栅电荷的屏蔽栅沟槽型mosfet制造方法
CN115985769A (zh) * 2022-11-30 2023-04-18 华虹半导体(无锡)有限公司 一种用于改善udsgt产品igss漏电问题的工艺方法
CN116013776A (zh) * 2023-03-02 2023-04-25 绍兴中芯集成电路制造股份有限公司 屏蔽栅沟槽型晶体管的制备方法及屏蔽栅沟槽型晶体管
CN116013776B (zh) * 2023-03-02 2023-09-15 绍兴中芯集成电路制造股份有限公司 屏蔽栅沟槽型晶体管的制备方法及屏蔽栅沟槽型晶体管
CN118016593A (zh) * 2024-04-09 2024-05-10 合肥晶合集成电路股份有限公司 一种半导体结构及其制备方法
CN118248737A (zh) * 2024-05-27 2024-06-25 无锡市查奥微电子科技有限公司 沟槽型碳化硅mosfet器件及其制备方法
CN118800802A (zh) * 2024-07-03 2024-10-18 杭州芯迈半导体技术有限公司 一种具有mgd结构的屏蔽栅沟槽器件及其制作方法

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