WO2022110504A1 - 存储芯片 - Google Patents

存储芯片 Download PDF

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Publication number
WO2022110504A1
WO2022110504A1 PCT/CN2020/142226 CN2020142226W WO2022110504A1 WO 2022110504 A1 WO2022110504 A1 WO 2022110504A1 CN 2020142226 W CN2020142226 W CN 2020142226W WO 2022110504 A1 WO2022110504 A1 WO 2022110504A1
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WIPO (PCT)
Prior art keywords
unit
sot
mtj
layer
spin
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PCT/CN2020/142226
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English (en)
French (fr)
Inventor
何世坤
周亚星
郑泽杰
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浙江驰拓科技有限公司
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Publication of WO2022110504A1 publication Critical patent/WO2022110504A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods

Definitions

  • the present disclosure relates to the field of memory, and in particular, to a memory chip.
  • SOT-MRAM Spin Orbit Torque Magnetic Random Access Memory
  • MRAM magnetic RAM
  • Voltage and read and write paths are separated. It is expected to replace STT-MRAM and utilize the spin-orbit moment to achieve fast and reliable magnetization inversion.
  • Memory chips generally have a one-time programmable module for storing the configuration information of the chip (such as read and write conditions, etc.), and usually volatile chips use eFuse as a one-time programmable module.
  • MRAM can use its memory unit MTJ to store configuration information, but it is often required to withstand reflow soldering in applications.
  • the manufacturing process of the memory chip with the function of storing configuration information in the prior art is complicated, and the manufacturing cost is high.
  • the main purpose of the present disclosure is to provide a memory chip to solve the problems of complicated manufacturing process and high manufacturing cost of a memory chip with a function of storing configuration information in the prior art.
  • a memory chip includes a one-time programmable area and a data storage area, wherein the one-time programmable area includes a first SOT unit, a switch unit and a data reading unit, the first end of the first SOT unit is electrically connected to the bit line, the second end of the first SOT unit is electrically connected to the first end of the switch unit, the second end of the switch unit is electrically connected
  • the terminal is electrically connected to the source line
  • the third terminal of the switch unit is electrically connected to the word line
  • the data read unit is electrically connected to the first terminal of the switch unit or the third terminal of the first SOT unit
  • the terminals are electrically connected
  • the first SOT unit includes a first MTJ and a first spin-orbit moment layer arranged in contact
  • the data storage area includes a second SOT unit, a read unit and a write unit, and the first SOT unit of the read unit The terminal and the first terminal of the write unit
  • the second end of the first MTJ is the first end of the first SOT unit
  • the second end of the first spin-orbit moment layer is the second end of the first SOT unit
  • the The third end of the first spin-orbit moment layer is the third end of the first SOT unit
  • the data reading unit is electrically connected to the third end of the first SOT unit
  • the third end of the first MTJ is electrically connected to the third end of the first SOT unit.
  • the second MTJ has one, the second end of the second MTJ is the first end of the second SOT unit, the second The second end of the spin-orbit moment layer is the second end of the second SOT unit, the third end of the second spin-orbit moment layer is the third end of the second SOT unit, and the second The first end of the MTJ is electrically connected to the first end of the second spin-orbit moment layer.
  • the second end of the first spin-orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, and the The data reading unit is electrically connected to the first end of the switch unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer;
  • the second MTJ has one,
  • the second end of the second spin-orbit moment layer is the first end of the second SOT unit, the second end of the second MTJ is the second end of the second SOT unit, and the second end of the second MTJ
  • the first end is electrically connected to the first end of the second spin-orbit moment layer.
  • the second end of the first MTJ is the first end of the first SOT unit
  • the second end of the first spin-orbit moment layer is the second end of the first SOT unit
  • the The third end of the first spin-orbit moment layer is the third end of the first SOT unit
  • the data reading unit is electrically connected to the third end of the first SOT unit
  • the third end of the first MTJ is electrically connected to the third end of the first SOT unit.
  • One end is electrically connected to the first end of the first spin-orbit moment layer; there are multiple second MTJs, and the second ends of the multiple second MTJs are the first ends of the second SOT unit, so The second end of the second spin-orbit moment layer is the second end of the second SOT unit, the third end of the second spin-orbit moment layer is the third end of the second SOT unit, so The first end of the second MTJ is electrically connected to the first end of the second spin-orbit moment layer.
  • the second end of the first spin-orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, and the The data reading unit is electrically connected to the first end of the switch unit, the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer; the second spin-orbit moment layer
  • the second end of the layer is the first end of the second SOT unit, there are multiple second MTJs, the second ends of the multiple second MTJs are the second end of the second SOT unit, and the second end of the second MTJ is the second end of the second SOT unit.
  • the first ends of the two MTJs are electrically connected to the first ends of the second spin-orbit moment layer.
  • the first SOT unit further includes a through-hole structure and an insulating dielectric layer, the through-hole structure vertically penetrates the insulating dielectric layer, and the insulating dielectric layer is far away from the first spin-orbit moment layer.
  • the surface of the first MTJ is in contact, the first end of the via structure is in contact with the surface of the first spin-orbit moment layer away from the first MTJ, and the second end of the via structure is in contact with the surface of the first MTJ.
  • the second end of the first SOT unit, and the projection of the via structure on a predetermined plane is located in the structure layer of the first MTJ, and the predetermined plane is the plane where the first MTJ is located.
  • the read unit includes at least one read word line and at least one first transistor, the gate of the first transistor is connected to the read word line in a one-to-one correspondence, and the source of the first transistor They are respectively electrically connected to the source lines, the drains of the first transistors are electrically connected to the second MTJs in a one-to-one correspondence, the writing unit includes a second transistor and a writing word line, and the second transistor has a The gate electrode is electrically connected to the write word line, the source electrode of the second transistor is electrically connected to the source electrode line, and the drain electrode of the second transistor is electrically connected to the second spin-orbit matrix layer.
  • the switch unit is a third transistor, the gate of the third transistor is electrically connected to the word line, the source of the third transistor is electrically connected to the source line, and the third transistor is The drain is electrically connected to the through hole structure.
  • the first spin-orbit moment layer and the second spin-orbit moment layer have the same structure, and the material of the first spin-orbit moment layer in contact with the first MTJ is a heavy metal material layer, and the material of the second spin-orbit moment layer in contact with the second MTJ is a heavy metal material layer, and the heavy metal material layer includes platinum, tantalum, tungsten, iridium, hafnium, ruthenium, thallium, bismuth, gold, titanium and Any of the osmium.
  • the first MTJ includes a first free layer, a first barrier layer, and a first pinning layer that are stacked in sequence
  • the second MTJ includes a second free layer, a second barrier layer, and a second barrier layer that are stacked in sequence.
  • a second pinned layer, the first free layer is in contact with the first spin-orbit moment layer
  • the second free layer is in contact with the second spin-orbit moment layer.
  • the first MTJ further includes a first top electrode or a first bottom electrode, and when the second end of the first MTJ is the first end of the first SOT unit, the first The MTJ includes the first top electrode, the first top electrode is electrically connected to the bit line, and in the case where the second end of the first MTJ is the second end of the first SOT unit, the first MTJ Including the first bottom electrode, the first bottom electrode is electrically connected to the switch unit, the second MTJ further includes a second top electrode or a second bottom electrode, at the second end of the second MTJ In the case of the first end of the second SOT unit, the second MTJ includes the second top electrode, and the second top electrode is electrically connected to the read unit at the second end of the second MTJ In the case of being the second terminal of the second SOT unit, the second MTJ includes the second bottom electrode, and the second bottom electrode is electrically connected to the writing unit.
  • the via structure includes a conductive via and a filling material, and the filling material is a low-resistance conductive material.
  • the present disclosure provides a memory chip, the memory chip includes the one-time programmable area and the data storage area, the one-time programmable area includes a first SOT unit, a switch unit and a data reading unit, so The first SOT unit includes a first MTJ and a first spin-orbit moment layer arranged in contact; the data storage area includes a second SOT unit, a read unit and a write unit, and the second SOT unit includes at least one of the contact arrangements The second MTJ and the second spin-orbit moment layer.
  • the storage of chip configuration information can be realized through the one-time programmable area and the data storage area, and the one-time programmable area and the data storage area have the same basic structure SOT unit.
  • the memory chip has the function of storing configuration information, and at the same time does not require an additional mask, the one-time programmable area and the data storage area can be manufactured at the same time, the manufacturing process is relatively simple, and the manufacturing of the chip is effectively controlled. cost, which alleviates the problems of complicated manufacturing process and high manufacturing cost of the existing memory chips with the function of storing configuration information.
  • FIG. 1 shows a schematic structural diagram of a memory chip according to an embodiment of the present disclosure
  • FIG. 5( a ) shows a side view of the structure of a memory chip according to a specific embodiment of the present disclosure
  • FIG. 5( b ) shows a top view of the structure of a memory chip according to a specific embodiment of the present disclosure
  • FIG. 6 shows a schematic structural diagram of a memory chip according to a specific embodiment of the present disclosure.
  • One-time programmable area 20. Data storage area; 100, First SOT unit; 101, Switch unit; 102, Data reading unit; 103, First MTJ; 104, First spin-orbit moment layer; 105, insulating medium layer; 106, conductive via; 107, first pinning layer; 108, first barrier layer; 109, first free layer; 110, first bottom electrode; 111, first top electrode; 200, first Two SOT units; 201, the first transistor; 202, the second transistor; 203, the second MTJ; 204, the second spin-orbit moment layer; 205, the second pinning layer; 206, the second barrier layer; 207, The second free layer; 208, the second bottom electrode; 209, the second top electrode.
  • a memory chip with a function of storing configuration information has a complicated manufacturing process and high manufacturing cost.
  • the present disclosure proposes a memory chip.
  • FIG. 1 shows a schematic structural diagram of a memory chip according to an embodiment of the present disclosure.
  • the second end of the first SOT unit 100 is electrically connected to the first end of the switch unit 101, the second end of the switch unit 101 is electrically connected to the source line, and the third end of the switch unit 101 is electrically connected to the word line
  • the data reading unit 102 is electrically connected to the first terminal of the switching unit 101 or to the third terminal of the first SOT unit 100, that is, the data reading unit 102 can be connected in two ways.
  • the data reading unit 102 is electrically connected to the first terminal of the switching unit 101, as shown in FIG. 1; the second type is that the data reading unit 102 is electrically connected to the third terminal of the first SOT unit 100, Not shown in FIG.
  • the above-mentioned first SOT unit 100 includes a first MTJ 103 and a first spin-orbit moment layer 104 arranged in contact;
  • the above-mentioned data storage area 20 includes a second SOT unit 200, a read unit and a write unit, the above-mentioned read
  • the first end of the unit and the first end of the writing unit are respectively electrically connected to the source line, the second end of the reading unit is electrically connected to the first end of the second SOT unit 200, and the second end of the writing unit is electrically connected to the first end of the second SOT unit 200.
  • the second end of the second SOT unit 200 is electrically connected, the third end of the second SOT unit 200 is electrically connected to the bit line, and the second SOT unit 200 includes at least one second MTJ 203 and a second spin orbital arranged in contact Rectangular layer 204 .
  • the above-mentioned memory chip includes the above-mentioned one-time programmable area and the above-mentioned data storage area, the above-mentioned one-time programmable area includes the first SOT unit, the switch unit and the data reading unit 102, and the above-mentioned first SOT unit includes the first MTJ and The first spin-orbit moment layer; the data storage area includes a second SOT unit, a read unit and a write unit, and the second SOT unit includes at least one second MTJ and a second spin-orbit moment layer arranged in contact.
  • the above-mentioned memory chip can realize the storage of chip configuration information through the above-mentioned one-time programmable area and the above-mentioned data storage area, and the above-mentioned one-time programmable area and the above-mentioned data storage area have the same basic structure SOT unit.
  • the above-mentioned storage While the chip has the function of storing configuration information, the above-mentioned one-time programmable area and the above-mentioned data storage area can be manufactured at the same time without an additional mask.
  • the manufacturing process is relatively simple, the manufacturing cost of the chip is effectively controlled, and the existing problems with The manufacturing process of the memory chip with the function of storing configuration information is complicated and the manufacturing cost is high.
  • the positional relationship between the first MTJ and the first spin-orbit moment layer is not limited to the positional relationship shown in FIG. 1
  • the positional relationship between the second MTJ and the second spin-orbit moment layer is not limited to that shown in FIG. 1 .
  • the second end of the first MTJ is the first end of the first SOT unit
  • the second end of the first spin-orbit moment layer is the second end of the first SOT unit end
  • the third end of the first spin-orbit moment layer is the third end of the first SOT unit
  • the data reading unit 102 is electrically connected to the third end of the first SOT unit
  • the third end of the first MTJ One end is electrically connected to the first end of the first spin-orbit moment layer
  • the second MTJ has one, the second end of the second MTJ is the first end of the second SOT unit, and the second spin-orbit moment
  • the second end of the layer is the second end of the second SOT unit
  • the third end of the second spin-orbit moment layer is the third end of the second SOT unit, the first end of the second MTJ and the first end of the second MTJ.
  • the first ends of the two spin-orbit moment layers are electrically connected.
  • the structures of the above-mentioned first SOT unit and the above-mentioned second SOT unit are the same, which further ensures that the manufacturing process of the above-mentioned memory chip is relatively simple, further guarantees that the manufacturing cost of the above-mentioned memory chip is low, and further alleviates the problem.
  • the existing memory chips with the function of storing configuration information have the problems of complicated manufacturing process and high manufacturing cost.
  • the second end of the first spin-orbit moment layer is the first end of the first SOT unit, and the second end of the first MTJ is the first end of the first SOT unit.
  • the data reading unit 102 is electrically connected to the first terminal of the switching unit, the first terminal of the first MTJ is electrically connected to the first terminal of the first spin-orbit moment layer;
  • the second MTJ has a , the second end of the second spin-orbit moment layer is the first end of the second SOT unit, the second end of the second MTJ is the second end of the second SOT unit, and the first end of the second MTJ is electrically connected to the first end of the second spin-orbit moment layer.
  • the structures of the above-mentioned first SOT unit and the above-mentioned second SOT unit are the same, which further ensures that the manufacturing process of the above-mentioned memory chip is relatively simple, further guarantees that the manufacturing cost of the above-mentioned memory chip is low, and further alleviates the problem.
  • the existing memory chips with the function of storing configuration information have the problems of complicated manufacturing process and high manufacturing cost.
  • the size of the first MTJ and the second MTJ may be the same or different, and the width of the first spin-orbit moment layer and the width of the second spin-orbit moment layer may be the same or different.
  • the second end of the first MTJ is the first end of the first SOT unit
  • the second end of the first spin-orbit moment layer is the first end of the first SOT unit.
  • Two terminals the third terminal of the first spin-orbit moment layer is the third terminal of the first SOT unit
  • the data reading unit 102 is electrically connected to the third terminal of the first SOT unit
  • the first MTJ The first end is electrically connected to the first end of the first spin-orbit moment layer; there are multiple second MTJs, the second ends of the multiple second MTJs are the first ends of the second SOT unit, the second The second end of the spin-orbit moment layer is the second end of the second SOT unit, the third end of the second spin-orbit moment layer is the third end of the second SOT unit, and the first end of the second MTJ
  • the terminal is electrically connected to the first terminal of the second spin-orbit moment layer.
  • the above-mentioned memory chip includes a plurality of the above-mentioned second MTJs. While ensuring that the manufacturing process is relatively simple, through the plurality of the above-mentioned second MTJs, the performance of the storage configuration information of the above-mentioned data storage area is better, and it is ensured that the above-mentioned chip has better performance. The ability to store configuration information.
  • the second end of the first spin-orbit moment layer is the first end of the first SOT unit, and the second end of the first MTJ is the first end of the first SOT unit.
  • the data reading unit is electrically connected to the first terminal of the switching unit, the first terminal of the first MTJ is electrically connected to the first terminal of the first spin orbit moment layer; the second spin orbit moment layer
  • the second end of the layer is the first end of the second SOT unit, there are multiple second MTJs, the second ends of the multiple second MTJs are the second ends of the second SOT unit, and the second end of the second MTJ is the second end of the second SOT unit.
  • the above-mentioned memory chip includes a plurality of the above-mentioned second MTJs. While ensuring that the manufacturing process is relatively simple, through the plurality of the above-mentioned second MTJs, the performance of the storage configuration information of the above-mentioned data storage area is better, and it is ensured that the above-mentioned chip has better performance. The ability to store configuration information.
  • the first SOT unit further includes a through-hole structure and an insulating dielectric layer, the through-hole structure vertically penetrates the insulating dielectric layer, and the distance between the insulating dielectric layer and the first spin-orbit moment layer is far from the first SOT layer.
  • a surface of the MTJ is in contact
  • the first end of the via structure is in contact with the surface of the first spin-orbit moment layer that is far from the first MTJ
  • the second end of the via structure is the second end of the first SOT unit end
  • the projection of the through hole structure on a predetermined plane is located in the structure layer of the first MTJ, and the predetermined plane is the plane where the first MTJ is located.
  • the first SOT unit includes a through-hole structure and an insulating dielectric layer, and the through-hole structure vertically penetrates the insulating dielectric layer, the projection of the through-hole structure on the predetermined plane is located in the structural layer of the first MTJ, and the through-hole structure A conductive path perpendicular to the first spin-orbit moment layer is provided, so that the read-write current of the one-time programmable region is perpendicular to the first spin-orbit moment layer, thereby effectively avoiding the first spin-orbit moment layer.
  • the above-mentioned one-time programmable region can have a better ability to withstand reflow soldering, thereby effectively alleviating the The problem of data loss after reflow soldering in the above-mentioned one-time programmable area.
  • the first end of the through-hole structure can also be in contact with the surface of the first MTJ that is far from the first spin-orbit moment layer, and the second end of the through-hole structure is the second end of the first SOT unit, And the projection of the through hole structure on the predetermined plane is located in the structure layer of the first MTJ, and the predetermined plane is the plane where the first MTJ is located.
  • the projection of the through hole structure on the plane where the first MTJ is located is located at The distance from the center of the structure layer of the first MTJ, the center of the projection to the center of the structure layer of the first MTJ is less than 50 nm.
  • the read unit includes at least one read word line and at least one first transistor, the gate of the first transistor and the read word line are connected in a one-to-one correspondence, and the first transistor is connected to the read word line in one-to-one correspondence.
  • the sources of the transistors are respectively electrically connected to the source lines, the drains of the first transistors are electrically connected to the second MTJs in one-to-one correspondence,
  • the writing unit includes a second transistor and a writing word line, and the gate of the second transistor is The electrode is electrically connected to the write word line, the source electrode of the second transistor is electrically connected to the source electrode line, and the drain electrode of the second transistor is electrically connected to the second spin orbit layer.
  • the above-mentioned read unit may also include a read-out word line and other devices
  • the above-mentioned write unit may also include a write-in word line and other devices.
  • the above-mentioned switch unit may include any device having a switching function, and those skilled in the art can select it according to actual needs.
  • the above-mentioned switch unit is a third transistor, The gate of the third transistor is electrically connected to the word line, the source of the third transistor is electrically connected to the source line, and the drain of the third transistor is electrically connected to the via structure.
  • the memory chip of the present disclosure utilizes the characteristics of high resistance value (generally greater than 5 ⁇ 10 3 ohms) before breakdown of the MTJ device and low resistance value (generally less than 200 ohms) after breakdown to read information of memory cells.
  • the state of the first MTJ must be changed by the current parallel to the interface between the heavy metal layer material and the first MTJ in the one-time programmable region.
  • the resistances of the first SOT cell and the above-mentioned switch cell form a voltage divider, which can cause breakdown of the barrier layer when the voltage across the first SOT cell is large enough.
  • the first SOT cell is short-circuited, and the one-time programmable region is in a programming state with a resistance value of about 100 ohms, while the on-resistance of the switch unit is about 500 ohms, and the output data state is state 1.
  • the pinned layer and the free layer of the first MTJ in the first SOT unit are not short-circuited, the magnetization directions of the two layers are the same or opposite, and the corresponding resistances are Rp or Rap, respectively.
  • the on-resistance of the transistor is about 500 ohms, and the output data state of the data reading unit is state 0.
  • the current passes through the first MTJ vertically and vertically through the first spin-orbit moment layer.
  • the spin-orbit moment and the through-hole structure make the vertical passage make high resistivity.
  • the heavy metal layer material contributes very little series resistance, and the influence on the voltage divider circuit can be basically ignored.
  • the first spin-orbit moment layer and the second spin-orbit moment layer are both multilayer structures in the vertical direction, and the first spin-orbit moment layer and the second spin-orbit moment layer are in the vertical direction.
  • the layer structure is the same, the material of the first spin-orbit moment layer in contact with the first MTJ is a heavy metal material layer, the material of the second spin-orbit moment layer in contact with the second MTJ is a heavy metal material layer, and the heavy metal material layer is The material layer includes any one of platinum, tantalum, tungsten, iridium, hafnium, ruthenium, thallium, bismuth, gold, titanium and osmium.
  • the material of the first spin-orbit moment layer in contact with the first MTJ can also be other heavy metal materials
  • the material of the second spin-orbit moment layer in contact with the second MTJ can also be other heavy metal materials .
  • the second bottom electrode first MTJ includes a first free layer, a first barrier layer and a first pinning layer stacked in sequence
  • the second bottom electrode second MTJ includes a second free layer stacked in sequence.
  • layer, the second barrier layer and the second pinning layer, the second bottom electrode first free layer is in contact with the second bottom electrode first spin orbit moment layer, the second bottom electrode second free layer and the second bottom electrode first Two spin contact orbit moment layer contacts.
  • the first free layer of the first MTJ is in contact with the first spin-orbit moment layer
  • the second free layer of the second MTJ is in contact with the second spin-orbit moment layer, thereby further ensuring the spin-orbit moment.
  • the effect is generated to realize the rapid magnetization reversal of the first MTJ and the second MTJ.
  • the second bottom electrode first MTJ further includes a first top electrode or a first bottom electrode, and the second end of the second bottom electrode first MTJ is the second bottom electrode first
  • the second bottom electrode and the first MTJ include a second bottom electrode and a first top electrode, and the second bottom electrode and the first top electrode are electrically connected to the bit line.
  • the second bottom electrode first MTJ includes the second bottom electrode first bottom electrode, the second bottom electrode first bottom electrode and the second bottom electrode switch
  • the electrical connection of the unit ensures that when the first MTJ is electrically connected to the bit line, the first MTJ is electrically connected to the bit line through the top electrode, and that the first MTJ is electrically connected to the switch unit. , the first MTJ is electrically connected to the switch unit through the bottom electrode.
  • the second bottom electrode The second MTJ further includes a second top electrode or a second bottom electrode. In the case where the second end of the second bottom electrode and the second MTJ is the first end of the second SOT unit, the second bottom electrode is the second bottom electrode.
  • the MTJ includes a second bottom electrode and a second top electrode.
  • the second bottom electrode and the second top electrode are electrically connected to the second bottom electrode reading unit.
  • the second end of the second bottom electrode and the second MTJ is the second bottom electrode and the second SOT unit.
  • the second bottom electrode and the second MTJ include the second bottom electrode and the second bottom electrode, and the second bottom electrode and the second bottom electrode are electrically connected to the writing unit, thus ensuring that the second MTJ and the reading unit are
  • the above-mentioned second MTJ is electrically connected to the above-mentioned read unit through the above-mentioned second top electrode
  • the above-mentioned second MTJ is electrically connected to the above-mentioned write unit
  • the above-mentioned second MTJ is connected to the above-mentioned read unit through the above-mentioned second bottom electrode.
  • the write unit is electrically connected.
  • the first SOT unit when the first SOT unit includes a through-hole structure, and the through-hole structure is in contact with the first MTJ, the first MTJ is electrically connected to the switch unit through the through-hole structure, and the through-hole
  • the structure is equivalent to the bottom electrode of the first MTJ.
  • the first MTJ may not include the first bottom electrode.
  • the through hole structure includes a conductive through hole and a filling material, and the filling material is a low-resistance conductive material.
  • the above-mentioned filling material is a low-resistance conductive material, which ensures that the data reading accuracy of the above-mentioned one-time programmable region is good.
  • the filler includes copper (Cu) and/or tungsten (W).
  • the filler may also include other low-resistance metal materials.
  • the structure diagram of the memory chip as shown in FIG. 2 is generated.
  • the first MTJ includes a first top electrode 111 , a first pinning layer 107 , a first barrier layer 108 and a first free layer 109
  • the second MTJ includes a second top electrode 209 and a second pinning layer 205 , the second barrier layer 206 and the second free layer 207
  • the writing unit includes a second transistor 202 and a writing word line WWL
  • the reading unit includes a reading word line RWL and a first transistor 201
  • the swirl torque layer 104 is electrically connected to the data reading unit 102
  • the switch unit 101 is a third transistor
  • the first SOT unit includes a via structure and an insulating dielectric layer 105
  • the via structure includes a conductive via 106 and a filling substance
  • the second spin-orbit moment layer 204 is electrically connected to the second transistor 202 .
  • the above-mentioned conductive via 106 is formed on the above-mentioned first spin-orbit layer 104 and connected to the above-mentioned data reading unit 102.
  • the programming voltage V BL is applied to the bit line BL to cross the above-mentioned one-time programmable region, the above-mentioned first SOT
  • the divided voltage V SOT across the cell is determined by the following equation:
  • R HM is the resistance of the first spin-orbit moment layer 104 perpendicular to the direction of the first SOT unit
  • Rvia is the resistance of the through-hole structure
  • R MOS is the resistance of the third transistor when it is turned on
  • R SOT is The resistance of the first SOT cell above.
  • the R HM resistance is small (about 10 ohms), and the conductive vias 106 are filled with low-resistance metal materials such as Cu, W, etc. , the resistance is only a few ohms, then:
  • V SOT When the value of V SOT is lower than the breakdown voltage of the first SOT unit, the output data state is 0, and when the V SOT is sufficiently large, the device is broken down and the output data state is 1.
  • the switch unit may also include other devices, and the first transistor and the second transistor may also be other devices.
  • the memory chip structure diagram shown in FIG. 3 is generated.
  • the first MTJ includes a first top electrode 111 , a first pinning layer 107 , a first barrier layer 108 and a first free layer 109
  • the second MTJ includes a second top electrode 209 and a second pinning layer 205 , the second barrier layer 206 and the second free layer 207
  • the writing unit includes a second transistor 202 and a writing word line WWL
  • the reading unit includes a reading word line RWL and a first transistor 201
  • the switching unit 101 is the third transistor
  • the switch unit is electrically connected to the data reading unit 102, that is, data is read from the drain of the third transistor
  • the first SOT unit includes a through hole structure and an insulating dielectric layer 105
  • the second spin-orbit moment layer 204 is electrically connected to the second transistor 202 including the conductive via 106 and the filling material.
  • the conductive vias 106 are filled with low-resistance metal materials such as Cu, W, etc., and the resistance is only a few ohms, which does not affect the accuracy of data reading; at the same time, the conductive vias 106 of the first MTJ and the conductive vias of the data reading unit are 106 can be process integrated in the same step, which can reduce the difficulty and cost of process integration.
  • the switch unit may also include other devices, and the first transistor and the second transistor may also be other devices.
  • the memory chip structure diagram shown in FIG. 4 is generated.
  • the first MTJ includes a first pinning layer 107, a first barrier layer 108, a first free layer 109 and a first bottom electrode 110
  • the second MTJ includes a second pinning layer 205 and a second barrier layer 206, the second free layer 207 and the second bottom electrode 208
  • the writing unit includes a second transistor 202 and a writing word line WWL
  • the reading unit includes a reading word line RWL and a first transistor 201
  • the first self The spin orbit torque layer 104 is electrically connected to the bit line
  • the first spin orbit torque layer 104 is above the first MTJ
  • the switch unit 101 is a third transistor
  • the data read unit 102 is electrically connected to the switch unit 101 , that is, data is read from the drain of the third transistor
  • the second spin-orbit layer 204 is above the second MTJ
  • one end of the second spin-orbit layer 204 is electrically connected to the bit line
  • the other end of the spin orbit moment layer 204 is electrically connected to the first transistor 201 , the first SOT unit includes a via structure and an insulating dielectric layer 105 , the via structure includes a conductive via 106 and a filling material, and the second spin The orbital matrix layer 204 is electrically connected to the above-mentioned second transistor 202 .
  • the data reading and writing of the above-mentioned one-time programmable area is through two independent channels, and the data reading and writing of the above-mentioned data storage area is through a single channel.
  • the first pinning layer 107 is electrically connected to the first bottom electrode 110 , and when the first MTJ does not include the first bottom electrode 110 , the above The first pinned layer 107 is electrically connected to the conductive via 106 , the first free layer 109 is above the first barrier layer 108 , and the first spin-orbit layer 104 is connected to the bit line BL.
  • the data reading unit 102 is connected from the drain terminal of the third transistor or the first bottom electrode 110 of the first MTJ, and judges the state of the first SOT unit through an amplifier.
  • the voltage division expression of the first SOT unit above is:
  • the switch unit may also include other devices, the first transistor and the second transistor may also be other devices, and in the case that the first SOT unit includes the through-hole structure, the first MTJ may not include the first transistor. a bottom electrode.
  • FIG. 5( a ) is a top view of the memory chip
  • FIG. 5( b ) is a side view of the memory chip.
  • the first MTJ 103 includes a first top electrode 111 , a first pinning layer 107 , a first barrier layer 108 and a first free layer 109
  • the second MTJ 203 includes a second top electrode 209 and a second pinning layer 205 , the second barrier layer 206 and the second free layer 207, in the above-mentioned one-time programmable area unit
  • the above-mentioned switch unit 101 is a third transistor
  • the drain of the above-mentioned third transistor is connected to the above-mentioned first spin-orbit torque layer 104
  • the source of the third transistor is connected to the source line SL
  • the gate of the third transistor is connected to the word line WL
  • the data reading unit 102 is connected to one end of the first spin orbit torque layer
  • the resistance per unit length of the second spin-orbit moment layer 204 , and the total resistance of the first spin-orbit moment layer 104 is much smaller than the resistance of the first MTJ 103 .
  • the first spin-orbit moment layer 104 is connected to the first free layer 109 of the first MTJ 103 , and the first MTJ 103 is connected to the bit line BL.
  • the width of the first spin-orbit moment layer 104 in the one-time programmable region is about twice the width of the second spin-orbit moment layer 204 in the data storage region, so that the first spin-orbit moment layer
  • the resistance per unit length of the layer 104 is more than 50% smaller than the resistance per unit length of the second spin-orbit moment layer 204, and the device size of the one-time programmable region and the data storage region is the same.
  • the read unit includes a read word line RWL and a first transistor 201
  • the write unit includes a second transistor 202 and a write word line WWL.
  • R HM is the resistance of the first spin-orbit moment layer 104 between the data reading unit and the first SOT unit
  • R MOS is the resistance of the third transistor when the third transistor is turned on
  • R SOT is the first SOT unit
  • the resistance, V BL is the voltage applied on the bit line.
  • the resistance of R HM is about 500 ohms
  • the resistance of R MOS is about 500 ohms.
  • the memory chip in this embodiment does not include a through-hole structure, and the data reading unit 102 is directly electrically connected to the first spin-orbit moment layer 104 .
  • the resistance per unit length of the layer 104 is much lower than the resistance per unit length of the second spin-orbit moment layer 204, and the total resistance of the first spin-orbit moment layer 104 is much smaller than the resistance of the first MTJ 103, which ensures that the above-mentioned one-time can be achieved.
  • the programming area can work better, thereby ensuring better performance of the memory chip.
  • the switch unit may also include other devices, and the first transistor and the second transistor may also be other devices.
  • FIG. 5( a ) is a top view of the memory chip
  • FIG. 5( b ) is a side view of the memory chip.
  • the switch unit 101 is a third transistor. In the one-time programmable region, the drain of the third transistor is connected to the first spin orbit layer 104, and the source of the third transistor is connected to the source line SL.
  • the gate of the third transistor is connected to the word line WL, the data reading unit 102 is connected to one end of the first spin-orbit layer 104, the first MTJ 103 is above the first spin-orbit layer 104,
  • the width of the first spin-orbit moment layer 104 is larger than the size of the first MTJ 103, so that the resistance per unit length of the first spin-orbit moment layer 104 is much lower than the resistance per unit length of the second spin-orbit moment layer 204, And the total resistance of the first spin-orbit moment layer 104 is much smaller than the resistance of the first MTJ 103 .
  • the first spin-orbit moment layer 104 is connected to the first free layer 109 of the first MTJ 103 , and the first MTJ 103 is connected to the bit line BL.
  • the size of the first MTJ103 in the one-time programmable area is about 20% smaller than the size of the second MTJ203 in the data storage area, so that the device resistance of the one-time programmable area is smaller than that of the data storage area.
  • the device resistance is greater than 40%; the size of the first spin-orbit layer 104 in the one-time programmable region and the second spin-orbit layer 204 in the data storage region are the same.
  • the read unit includes a read word line RWL and the first transistor 201, and the write unit includes the second transistor 202 and a write word line WWL.
  • V SOT of the first SOT cell is expressed as:
  • R HM is the resistance of the first spin orbit moment layer 104 between the data reading unit and the first SOT unit
  • R MOS is the resistance of the third transistor when the third transistor is turned on
  • R SOT is the resistance of the first SOT unit. resistance
  • V BL is the voltage applied on the bit line.
  • the resistance of the R HM in the above-mentioned one-time programmable region is about 1000 ohms
  • the resistance of the above-mentioned first SOT cell is about 7800 or 15,600 ohms
  • the value of the divided voltage V SOT of the above-mentioned first SOT cell increases, and the above-mentioned one-time programmable region is easier to breakdown .
  • the first SOT unit does not break down, it is in a parallel state or an anti-parallel state, the output voltage is low, and the state is "0"; when the first SOT unit breaks down, its resistance is about 100 ohms, and the output The level is high and the state is "1".
  • the memory chip in this embodiment does not include a through-hole structure, and the data reading unit 102 is directly electrically connected to the first spin-orbit moment layer 104 .
  • the resistance per unit length of the layer 104 is much lower than the resistance per unit length of the second spin-orbit moment layer 204, and the total resistance of the first spin-orbit moment layer 104 is much smaller than the resistance of the first MTJ 103, which ensures that the above-mentioned one-time can be achieved.
  • the programming area can work better, thereby ensuring better performance of the memory chip.
  • the switch unit may also include other devices, and the first transistor and the second transistor may also be other devices.
  • the structure diagram of the memory chip shown in FIG. 6 is generated, wherein there are multiple second MTJs, the read unit includes multiple read word lines RWL and multiple first transistors 201, and the switch unit 101 is the first transistor 201.
  • the writing unit includes the second transistor 202 and the writing word line WWL, the second MTJ is connected to the first transistor 201 in one-to-one correspondence, and the data storage area can pass through a NAND-like SOT (a NAND flash memory transistor).
  • the above-mentioned one-time programmable region can be realized by any one of the above embodiments, including adopting the above-mentioned conductive via structure, or increasing the width structure of the above-mentioned first spin-orbit layer, or reducing the above-mentioned one-time programmable region.
  • the above-mentioned first MTJ size method the above-mentioned one-time programmable region is obtained.
  • the above-mentioned data reading unit 102 may be connected to the drain terminal of the above-mentioned third transistor, and may also be connected to the above-mentioned first spin-orbit layer 104 .
  • the switch unit may also include other devices, and the first transistor and the second transistor may also be other devices.
  • the present disclosure provides a memory chip, the above-mentioned memory chip includes the above-mentioned one-time programmable area and the above-mentioned data storage area, the above-mentioned one-time programmable area includes a first SOT unit, a switch unit and a data reading unit, and the above-mentioned first SOT unit
  • the first MTJ and the first spin-orbit moment layer are provided in contact;
  • the above-mentioned data storage area includes the second SOT unit, the read unit and the write unit, and the above-mentioned second SOT unit includes at least one second MTJ and the second self-contained unit. Swirl moment layer.
  • the above-mentioned memory chip can realize the storage of chip configuration information through the above-mentioned one-time programmable area and the above-mentioned data storage area, and the above-mentioned one-time programmable area and the above-mentioned data storage area have the same basic structure SOT unit.
  • the above-mentioned storage While the chip has the function of storing configuration information, the above-mentioned one-time programmable area and the above-mentioned data storage area can be manufactured at the same time without an additional mask.
  • the manufacturing process is relatively simple, the manufacturing cost of the chip is effectively controlled, and the existing problems with The manufacturing process of the memory chip with the function of storing configuration information is complicated and the manufacturing cost is high.

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Abstract

本公开提供了一种存储芯片，包括：一次可编程区域，包括第一SOT单元、开关单元和数据读取单元，第一SOT单元的第一端与位线电连接，第一SOT单元的第二端与开关单元的第一端电连接，开关单元的第二端与源极线电连接，开关单元的第三端与字线电连接，第一SOT单元包括接触设置的第一MTJ和第一自旋轨道矩层；数据存储区域，包括第二SOT单元、读单元和写单元，读单元的第一端和写单元的第一端分别与源极线电连接，读单元的第二端与第二SOT单元的第一端电连接，写单元的第二端与第二SOT单元的第二端电连接，第二SOT单元的第三端与位线电连接，第二SOT单元包括接触设置的至少一个第二MTJ和第二自旋轨道矩层。

Description

存储芯片
本公开以2020年11月27日递交的、申请号为202011360601.5且名称为“存储芯片”的专利文件为优先权文件，该文件的全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储器领域，具体而言，涉及一种存储芯片。
背景技术
相比于传统的STT-MRAM(自旋转移矩磁性随机存储器)，SOT-MRAM(自旋轨道矩磁性随机存储器)即保持了MRAM高速度和低功耗等优异特性，又实现了低写入电压及读写路径分离。有望取代STT-MRAM，利用自旋轨道矩实现快速而可靠的磁化翻转。存储芯片一般都会有一次可编程模块用来存储芯片的配置信息(如读取和写入条件等等)，通常易失性芯片采用eFuse作为一次可编程模块。MRAM作为非易失存储，可以利用其存储单元MTJ来存储配置信息，但应用中往往要求能够承受回流焊。现有技术中具有存储配置信息功能的存储芯片制作过程复杂，制造成本高。
在背景技术部分中公开的以上信息只是用来加强对本文所描述技术的背景技术的理解，因此，背景技术中可能包含某些信息，这些信息对于本领域技术人员来说并未形成在本国已知的现有技术。
发明内容
本公开的主要目的在于提供一种存储芯片，以解决现有技术中具有存储配置信息功能的存储芯片制作过程复杂，制造成本高的问题。
为了实现上述目的，根据本公开的一个方面，提供了一种存储芯片，所述存储芯片包括一次可编程区域和数据存储区域，其中，所述一次可编程区域包括第一SOT单元、开关单元和数据读取单元，所述第一SOT单元的第一端与位线电连接，所述第一SOT单元的第二端与所述开关单元的第一端电连接，所述开关单元的第二端与源极线电连接，所述开关单元的第三端与字线电连接，所述数据读取单元与所述开关单元的第一端电连接或者与所述第一SOT单元的第三端电连接，所述第一SOT单元包括接触设置的第一MTJ和第一自旋轨道矩层；所述数据存储区域包括第二SOT单元、读单元和写单元，所述读单元的第一端和所述写单元的第一端分别与源极线电连接，所述读单元的第二端与所述第二SOT单元的第一端电连接，所述写单元的第二端与所述第二SOT单元的第二端电连接，所述第二SOT单元的第三端与位线电连接，所述第二SOT单元包括接触设置的至少一个第二MTJ和第二自旋轨道矩层。
可选地，所述第一MTJ的第二端为第一SOT单元的第一端，所述第一自旋轨道矩层的第二端为所述第一SOT单元的第二端，所述第一自旋轨道矩层的第三端为所述第一SOT单元的 第三端，所述数据读取单元与所述第一SOT单元的第三端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二MTJ有一个，所述第二MTJ的第二端为第二SOT单元的第一端，所述第二自旋轨道矩层的第二端为所述第二SOT单元的第二端，所述第二自旋轨道矩层的第三端为所述第二SOT单元的第三端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
可选地，所述第一自旋轨道矩层的第二端为第一SOT单元的第一端，所述第一MTJ的第二端为所述第一SOT单元的第二端，所述数据读取单元与所述开关单元的第一端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二MTJ有一个，所述第二自旋轨道矩层的第二端为第二SOT单元的第一端，所述第二MTJ的第二端为所述第二SOT单元的第二端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
可选地，所述第一MTJ的第二端为第一SOT单元的第一端，所述第一自旋轨道矩层的第二端为所述第一SOT单元的第二端，所述第一自旋轨道矩层的第三端为所述第一SOT单元的第三端，所述数据读取单元与所述第一SOT单元的第三端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二MTJ有多个，多个所述第二MTJ的第二端为第二SOT单元的第一端，所述第二自旋轨道矩层的第二端为所述第二SOT单元的第二端，所述第二自旋轨道矩层的第三端为所述第二SOT单元的第三端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
可选地，所述第一自旋轨道矩层的第二端为第一SOT单元的第一端，所述第一MTJ的第二端为所述第一SOT单元的第二端，所述数据读取单元与所述开关单元的第一端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二自旋轨道矩层的第二端为第二SOT单元的第一端，所述第二MTJ有多个，多个所述第二MTJ的第二端为所述第二SOT单元的第二端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
可选地，所述第一SOT单元还包括通孔结构和绝缘介质层，所述通孔结构垂直贯穿所述绝缘介质层，所述绝缘介质层与所述第一自旋轨道矩层的远离所述第一MTJ的表面接触，所述通孔结构的第一端与所述第一自旋轨道矩层的远离所述第一MTJ的表面接触，所述通孔结构的第二端为所述第一SOT单元的第二端，且所述通孔结构在预定平面上的投影位于所述第一MTJ的结构层中，所述预定平面为所述第一MTJ所在的平面。
可选地，所述读单元包括至少一个读出字线和至少一个第一晶体管，所述第一晶体管的栅极和所述读出字线一一对应连接，所述第一晶体管的源极分别与所述源极线电连接，所述第一晶体管的漏极与所述第二MTJ一一对应电连接，所述写单元包括第二晶体管和写入字线，所述第二晶体管的栅极和所述写入字线电连接，所述第二晶体管的源极与所述源极线电连接，所述第二晶体管的漏极与所述第二自旋轨道矩层电连接。
可选地，所述开关单元为第三晶体管，所述第三晶体管的栅极与所述字线电连接，所述第三晶体管的源极与源极线电连接，所述第三晶体管的漏极与所述通孔结构电连接。
可选地，所述第一自旋轨道矩层和所述第二自旋轨道矩层结构相同，所述第一自旋轨道矩层的与所述第一MTJ接触的材料为重金属材料层，所述第二自旋轨道矩层的与所述第二MTJ接触的材料为重金属材料层，所述重金属材料层包括铂、钽、钨、铱、铪、钌、铊、铋、金、钛和锇中的任意一种。
可选地，所述第一MTJ包括依次层叠的第一自由层、第一势垒层和第一钉扎层，所述第二MTJ包括依次层叠的第二自由层、第二势垒层和第二钉扎层，所述第一自由层与所述第一自旋轨道矩层接触，所述第二自由层和所述第二自旋接触轨道矩层接触。
可选地，所述第一MTJ还包括第一顶电极或第一底电极，在所述第一MTJ的第二端为所述第一SOT单元的第一端的情况下，所述第一MTJ包括所述第一顶电极，所述第一顶电极与位线电连接，在所述第一MTJ的第二端为所述第一SOT单元的第二端的情况下，所述第一MTJ包括所述第一底电极，所述第一底电极与所述开关单元的电连接，所述第二MTJ还包括第二顶电极或第二底电极，在所述第二MTJ的第二端为第二SOT单元的第一端的情况下，所述第二MTJ包括所述第二顶电极，所述第二顶电极与所述读单元电连接，在所述第二MTJ的第二端为所述第二SOT单元的第二端的情况下，所述第二MTJ包括所述第二底电极，所述第二底电极与所述写单元电连接。
可选地，所述通孔结构包括导电通孔和填充物质，所述填充物质为低电阻导电材料。
本公开提供了一种存储芯片，所述的存储芯片，包括所述一次可编程区域和所述数据存储区域，所述一次可编程区域包括第一SOT单元、开关单元和数据读取单元，所述第一SOT单元包括接触设置的第一MTJ和第一自旋轨道矩层；所述数据存储区域包括第二SOT单元、读单元和写单元，所述第二SOT单元包括接触设置的至少一个第二MTJ和第二自旋轨道矩层。所述存储芯片，通过所述一次可编程区域和所述数据存储区域可以实现芯片配置信息的存储，且所述一次可编程区域和所述数据存储区域有相同的基本结构SOT单元，相比现有技术，所述存储芯片在具备存储配置信息功能的同时，无需额外光罩，可同时制造得到所述一次可编程区域和所述数据存储区域，制造工艺较为简单，有效地控制了芯片的制造成本，缓解了现有的具有存储配置信息功能的存储芯片制作过程复杂，制造成本高的问题。
附图说明
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1示出了根据本公开的实施例的存储芯片的结构示意图；
图2至图4分别示出了根据本公开的三种具体的实施例的存储芯片的结构示意图；
图5(a)示出了根据本公开的具体的实施例的存储芯片的结构的侧视图；
图5(b)示出了根据本公开的具体的实施例的存储芯片的结构的俯视图；
图6示出了根据本公开的具体的实施例的存储芯片的结构示意图。
其中，上述附图包括以下附图标记：
10、一次可编程区域；20、数据存储区域；100、第一SOT单元；101、开关单元；102、数据读取单元；103、第一MTJ；104、第一自旋轨道矩层；105、绝缘介质层；106、导电通孔；107、第一钉扎层；108、第一势垒层；109、第一自由层；110、第一底电极；111、第一顶电极；200、第二SOT单元；201、第一晶体管；202、第二晶体管；203、第二MTJ；204、第二自旋轨道矩层；205、第二钉扎层；206、第二势垒层；207、第二自由层；208、第二底电极；209、第二顶电极。
具体实施方式
应该指出，以下详细说明都是例示性的，旨在对本公开提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本公开所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本公开的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
正如背景技术所介绍的，现有技术中具有存储配置信息功能的存储芯片制作过程复杂，制造成本高，为了解决如上问题，本公开提出了一种存储芯片。
根据本公开的一种典型的实施例，提供了一种存储芯片，图1示出了根据本公开的实施例的一种存储芯片的结构示意图，如图1所示，上述存储芯片包括一次可编程区域10和数据存储区域20，其中，上述一次可编程区域10包括第一SOT单元100、开关单元101和数据读取单元102，上述第一SOT单元100的第一端与位线电连接，上述第一SOT单元100的第二端与上述开关单元101的第一端电连接，上述开关单元101的第二端与源极线电连接，上述开关单元101的第三端与字线电连接，上述数据读取单元102与上述开关单元101的第一端电连接或者与上述第一SOT单元100的第三端电连接，即，上述数据读取单元102的连接方式有两种，第一种，上述数据读取单元102与上述开关单元101的第一端电连接，如图1所示；第二种，上述数据读取单元102与上述第一SOT单元100的第三端电连接，图1中未示出；上述第一SOT单元100包括接触设置的第一MTJ103和第一自旋轨道矩层104；上述数据存储区域20包括第二SOT单元200、读单元和写单元，上述读单元的第一端和上述写单元的第一端分别与源极线电连接，上述读单元的第二端与上述第二SOT单元200的第一端电连 接，上述写单元的第二端与上述第二SOT单元200的第二端电连接，上述第二SOT单元200的第三端与位线电连接，上述第二SOT单元200包括接触设置的至少一个第二MTJ203和第二自旋轨道矩层204。
上述的存储芯片，包括上述一次可编程区域和上述数据存储区域，上述一次可编程区域包括第一SOT单元、开关单元和数据读取单元102，上述第一SOT单元包括接触设置的第一MTJ和第一自旋轨道矩层；上述数据存储区域包括第二SOT单元、读单元和写单元，上述第二SOT单元包括接触设置的至少一个第二MTJ和第二自旋轨道矩层。上述存储芯片，通过上述一次可编程区域和上述数据存储区域可以实现芯片配置信息的存储，且上述一次可编程区域和上述数据存储区域有相同的基本结构SOT单元，相比现有技术，上述存储芯片在具备存储配置信息功能的同时，无需额外光罩，可同时制造得到上述一次可编程区域和上述数据存储区域，制造工艺较为简单，有效地控制了芯片的制造成本，缓解了现有的具有存储配置信息功能的存储芯片制作过程复杂，制造成本高的问题。
当然，上述第一MTJ和第一自旋轨道矩层的位置关系并不限于图1中所示的位置关系，上述第二MTJ和第二自旋轨道矩层的位置关系也并不限于图1中所示的位置关系。
根据本公开的一种具体的实施例，上述第一MTJ的第二端为第一SOT单元的第一端，上述第一自旋轨道矩层的第二端为上述第一SOT单元的第二端，上述第一自旋轨道矩层的第三端为上述第一SOT单元的第三端，上述数据读取单元102与上述第一SOT单元的第三端电连接，上述第一MTJ的第一端和上述第一自旋轨道矩层的第一端电连接；上述第二MTJ有一个，上述第二MTJ的第二端为第二SOT单元的第一端，上述第二自旋轨道矩层的第二端为上述第二SOT单元的第二端，上述第二自旋轨道矩层的第三端为上述第二SOT单元的第三端，上述第二MTJ的第一端和上述第二自旋轨道矩层的第一端电连接。上述的存储芯片，上述第一SOT单元和上述第二SOT单元结构相同，这样进一步地保证了上述存储芯片的制造工艺较为简单，进一步地保证了上述存储芯片的制造成本较低，进一步地缓解了现有的具有存储配置信息功能的存储芯片制作过程复杂，制造成本高的问题。
根据本公开的另一种具体的实施例，上述第一自旋轨道矩层的第二端为第一SOT单元的第一端，上述第一MTJ的第二端为上述第一SOT单元的第二端，上述数据读取单元102与上述开关单元的第一端电连接，上述第一MTJ的第一端和上述第一自旋轨道矩层的第一端电连接；上述第二MTJ有一个，上述第二自旋轨道矩层的第二端为第二SOT单元的第一端，上述第二MTJ的第二端为上述第二SOT单元的第二端，上述第二MTJ的第一端和上述第二自旋轨道矩层的第一端电连接。上述的存储芯片，上述第一SOT单元和上述第二SOT单元结构相同，这样进一步地保证了上述存储芯片的制造工艺较为简单，进一步地保证了上述存储芯片的制造成本较低，进一步地缓解了现有的具有存储配置信息功能的存储芯片制作过程复杂，制造成本高的问题。
在实际的应用过程中，上述第一MTJ和上述第二MTJ的大小可以相同也可以不同，上述第一自旋轨道矩层的宽度与上述第二自旋轨道矩层的宽度可以相同也可以不同。
本公开的再一种具体的实施例中，上述第一MTJ的第二端为第一SOT单元的第一端，上述第一自旋轨道矩层的第二端为上述第一SOT单元的第二端，上述第一自旋轨道矩层的第三端为上述第一SOT单元的第三端，上述数据读取单元102与上述第一SOT单元的第三端电连接，上述第一MTJ的第一端和上述第一自旋轨道矩层的第一端电连接；上述第二MTJ有多个，多个上述第二MTJ的第二端为第二SOT单元的第一端，上述第二自旋轨道矩层的第二端为上述第二SOT单元的第二端，上述第二自旋轨道矩层的第三端为上述第二SOT单元的第三端，上述第二MTJ的第一端和上述第二自旋轨道矩层的第一端电连接。上述存储芯片，包括多个上述第二MTJ，在保证制造工艺较为简单的同时，通过多个上述第二MTJ，使得上述数据存储区域的存储配置信息的性能较好，保证了上述芯片具有较好的存储配置信息的能力。
根据本公开的又一种具体的实施例，上述第一自旋轨道矩层的第二端为第一SOT单元的第一端，上述第一MTJ的第二端为上述第一SOT单元的第二端，上述数据读取单元与上述开关单元的第一端电连接，上述第一MTJ的第一端和上述第一自旋轨道矩层的第一端电连接；上述第二自旋轨道矩层的第二端为第二SOT单元的第一端，上述第二MTJ有多个，多个上述第二MTJ的第二端为上述第二SOT单元的第二端，上述第二MTJ的第一端和上述第二自旋轨道矩层的第一端电连接。上述存储芯片，包括多个上述第二MTJ，在保证制造工艺较为简单的同时，通过多个上述第二MTJ，使得上述数据存储区域的存储配置信息的性能较好，保证了上述芯片具有较好的存储配置信息的能力。
在实际的应用过程中，上述第一SOT单元还包括通孔结构和绝缘介质层，上述通孔结构垂直贯穿上述绝缘介质层，上述绝缘介质层与上述第一自旋轨道矩层的远离上述第一MTJ的表面接触，上述通孔结构的第一端与上述第一自旋轨道矩层的远离上述第一MTJ的表面接触，上述通孔结构的第二端为上述第一SOT单元的第二端，且上述通孔结构在预定平面上的投影位于上述第一MTJ的结构层中，上述预定平面为上述第一MTJ所在的平面。上述第一SOT单元包括通孔结构和绝缘介质层，且上述通孔结构垂直贯穿上述绝缘介质层，上述通孔结构在预定平面上的投影位于上述第一MTJ的结构层中，上述通孔结构提供了一个垂直于上述第一自旋轨道矩层的导电路径，这样使得上述一次可编程区域的读写电流垂直于上述第一自旋轨道矩层，从而有效地避免了上述第一自旋轨道矩层的横向电阻造成的读窗口扰动影响；同时，通过上述通孔结构和上述第一MTJ的击穿特性，可以使得上述一次可编程区域具备较好的承受回流焊的能力，从而有效地缓解上述一次可编程区域在回流焊后数据丢失的问题。
当然，上述通孔结构的第一端还可以与上述第一MTJ的远离上述第一自旋轨道矩层的表面接触，上述通孔结构的第二端为上述第一SOT单元的第二端，且上述通孔结构在预定平面上的投影位于上述第一MTJ的结构层中，上述预定平面为上述第一MTJ所在的平面。
为了进一步地减小上述存储芯片的读窗口扰动影响，以及进一步地增强上述存储芯片承受回流焊的能力，在实际的应用过程中，上述通孔结构在上述第一MTJ所在的平面上的投影位于上述第一MTJ的结构层的中心，上述投影的中心至上述第一MTJ的结构层的中心的距离小于50nm。
根据本公开的另一种具体的实施例，上述读单元包括至少一个读出字线和至少一个第一晶体管，上述第一晶体管的栅极和上述读出字线一一对应连接，上述第一晶体管的源极分别与上述源极线电连接，上述第一晶体管的漏极与上述第二MTJ一一对应电连接，上述写单元包括第二晶体管和写入字线，上述第二晶体管的栅极和上述写入字线电连接，上述第二晶体管的源极与上述源极线电连接，上述第二晶体管的漏极与上述第二自旋轨道矩层电连接。
当然，上述读单元还可以包括读出字线和其他器件，上述写单元还可以包括写入字线和其他器件。
在实际的应用过程中，上述开关单元可以包括任何具有开关作用的器件，本领域技术人员可以根据实际需要进行选择，本公开的又一种具体的实施例中，上述开关单元为第三晶体管，上述第三晶体管的栅极与上述字线电连接，上述第三晶体管的源极与源极线电连接，上述第三晶体管的漏极与上述通孔结构电连接。
本公开的存储芯片利用MTJ器件击穿前为高电阻值(一般大于5×10 3欧姆)，击穿后为低电阻值(一般小于200欧姆)的特性读取存储单元的信息。在实际的应用过程中，上述一次可编程区域必须通过平行于重金属层材料和上述第一MTJ界面的电流使得上述第一MTJ的状态发生改变。当跨越一次可编程区域施加电压时，第一SOT单元和上述开关单元的电阻会形成分压器，当跨越第一SOT单元的电压足够大时，会导致势垒层的击穿。击穿后，第一SOT单元短路，此时一次可编程区域处于编程状态，其具有大约100欧姆的电阻值，而上述开关单元的导通电阻约为500欧姆，输出数据状态为状态1。在读取过程中，第一SOT单元中第一MTJ的钉扎层和自由层未短路，两层磁化方向相同或者相反，对应的电阻分别为Rp或者Rap。晶体管的导通电阻约为500欧姆，数据读取单元输出数据状态为状态0。一次可编程区域在读取过程中，电流通过第一MTJ后纵向垂直通过第一自旋轨道矩层，在有通孔结构的情况下自旋轨道矩和通孔结构，垂直通过使得高电阻率的重金属层材料贡献很小的串联电阻，对分压电路影响基本可以忽略。
在实际的应用过程中，上述第一自旋轨道矩层和上述第二自旋轨道矩层在垂直方向上均为多层结构，上述第一自旋轨道矩层和上述第二自旋轨道矩层结构相同，上述第一自旋轨道矩层的与上述第一MTJ接触的材料为重金属材料层，上述第二自旋轨道矩层的与上述第二MTJ接触的材料为重金属材料层，上述重金属材料层包括铂、钽、钨、铱、铪、钌、铊、铋、金、钛和锇中的任意一种。这样保证了上述第一自旋轨道矩层的与上述第一MTJ接触的表面电阻率较大，上述第二自旋轨道矩层的与上述第二MTJ接触的表面电阻率较大，便于产生自旋轨道距效应，使得上述第一MTJ和上述第二MTJ能实现较为快速和可靠的磁化翻转。
当然，上述第一自旋轨道矩层的与上述第一MTJ接触的材料还可以为其他重金属材料，上述第二自旋轨道矩层的与上述第二MTJ接触的材料也还可以为其他重金属材料。
一种具体的实施例中，第二底电极第一MTJ包括依次层叠的第一自由层、第一势垒层和第一钉扎层，第二底电极第二MTJ包括依次层叠的第二自由层、第二势垒层和第二钉扎层，第二底电极第一自由层与第二底电极第一自旋轨道矩层接触，第二底电极第二自由层和第二 底电极第二自旋接触轨道矩层接触。通过上述第一MTJ的第一自由层与上述第一自旋轨道矩层接触，以及上述第二MTJ的第二自由层与上述第二自旋轨道矩层接触，进一步地保证了自旋轨道矩效应的产生，来实现上述第一MTJ和上述第二MTJ的快速磁化翻转。
本公开的另一种具体的实施例中，第二底电极第一MTJ还包括第一顶电极或第一底电极，在第二底电极第一MTJ的第二端为第二底电极第一SOT单元的第一端的情况下，第二底电极第一MTJ包括第二底电极第一顶电极，第二底电极第一顶电极与位线电连接，在第二底电极第一MTJ的第二端为第二底电极第一SOT单元的第二端的情况下，第二底电极第一MTJ包括第二底电极第一底电极，第二底电极第一底电极与第二底电极开关单元的电连接，这样保证了在上述第一MTJ与位线电连接的情况下，上述第一MTJ通过上述顶电极与位线电连接，在上述第一MTJ与上述开关单元电连接的情况下，上述第一MTJ通过上述底电极与上述开关单元电连接。第二底电极第二MTJ还包括第二顶电极或第二底电极，在第二底电极第二MTJ的第二端为第二SOT单元的第一端的情况下，第二底电极第二MTJ包括第二底电极第二顶电极，第二底电极第二顶电极与第二底电极读单元电连接，在第二底电极第二MTJ的第二端为第二底电极第二SOT单元的第二端的情况下，第二底电极第二MTJ包括第二底电极第二底电极，第二底电极第二底电极与所写单元电连接，这样保证了上述第二MTJ与上述读单元电连接的情况下，上述第二MTJ通过上述第二顶电极与上述读单元电连接，在上述第二MTJ与上述写单元电连接的情况下，上述第二MTJ通过上述第二底电极与上述写单元电连接。
在实际的应用过程中，当上述第一SOT单元包括通孔结构，且上述通孔结构与上述第一MTJ接触时，上述第一MTJ通过上述通孔结构与上述开关单元电连接，上述通孔结构相当于上述第一MTJ的底电极，此时，上述第一MTJ可以不包括上述第一底电极。
根据本公开的再一种具体的实施例，上述通孔结构包括导电通孔和填充物质，上述填充物质为低电阻导电材料。上述填充物质为低电阻导电材料，保证了上述一次可编程区域的数据读取的准确性较好。
具体的一种实施例中，上述填充物包括铜(Cu)和/或钨(W)，当然，上述填充物还可以包括其他低电阻金属材料。
为了使得本领域的技术人员更加清楚地了解本公开的技术方案，下面将通过具体的实施例来进行说明。
实施例1
生成了如图2所示的存储芯片结构图。其中，上述第一MTJ包括第一顶电极111、第一钉扎层107、第一势垒层108和第一自由层109，上述第二MTJ包括第二顶电极209、第二钉扎层205、第二势垒层206和第二自由层207，上述写单元包括第二晶体管202和写入字线WWL，上述读单元包括一个读出字线RWL和一个第一晶体管201，上述第一自旋轨道矩层104与上述数据读取单元102电连接，上述开关单元101为第三晶体管，上述第一SOT单元包括通孔结构和绝缘介质层105，上述通孔结构包括导电通孔106和填充物质，上述第二自旋 轨道矩层204与上述第二晶体管202电连接。上述一次可编程区域的数据读取和写入通过两个独立通道，上述数据存储区域的数据读取和写入通过单一通道。
通过在上述第一自旋轨道矩层104上做上述导电通孔106，连接到上述数据读取单元102，当在位线BL施加编程电压V BL跨越上述一次可编程区域时，上述第一SOT单元两端的分压V SOT由下列方程来决定：
Figure PCTCN2020142226-appb-000001
其中，R HM为上述第一自旋轨道矩层104垂直于上述第一SOT单元方向的电阻，Rvia为上述通孔结构的电阻，R MOS为上述第三晶体管导通时的电阻，R SOT为上述第一SOT单元的电阻。
由于在垂直于第一SOT单元的方向上，第一自旋轨道矩层104很薄，R HM电阻较小(约10欧姆)，导电通孔106填充物为低电阻金属材料如Cu、W等，电阻只有几欧姆，则：
Figure PCTCN2020142226-appb-000002
当V SOT数值低于第一SOT单元击穿电压时，输出数据状态为0，当V SOT足够大时，器件被击穿，输出数据状态为1。
当然，上述开关单元还可以包括其他器件，上述第一晶体管和上述第二晶体管还可以为其他器件。
实施例2
生成了如图3所示的存储芯片结构图。其中，上述第一MTJ包括第一顶电极111、第一钉扎层107、第一势垒层108和第一自由层109，上述第二MTJ包括第二顶电极209、第二钉扎层205、第二势垒层206和第二自由层207，上述写单元包括第二晶体管202和写入字线WWL，上述读单元包括一个读出字线RWL和一个第一晶体管201，上述开关单元101为第三晶体管，上述开关单元与上述数据读取单元102电连接，即数据从上述第三晶体管的漏极读取，上述第一SOT单元包括通孔结构和绝缘介质层105，上述通孔结构包括导电通孔106和填充物质，上述第二自旋轨道矩层204与上述第二晶体管202电连接。上述一次可编程区域的数据读取和写入通过两个独立通道，上述数据存储区域的数据读取和写入通过单一通道。
导电通孔106填充物为低电阻金属材料如Cu、W等，电阻只有几欧姆，不影响数据读取的准确性；同时，第一MTJ的导电通孔106与数据读取单元的导电通孔106可以工艺集成在同一步骤，这样可以降低工艺集成难度和成本。
Figure PCTCN2020142226-appb-000003
当然，上述开关单元还可以包括其他器件，上述第一晶体管和上述第二晶体管还可以为其他器件。
实施例3
生成了如图4所示的存储芯片结构图。其中，上述第一MTJ包括第一钉扎层107、第一势垒层108、第一自由层109和第一底电极110，上述第二MTJ包括第二钉扎层205、第二势垒层206、第二自由层207和第二底电极208，上述写单元包括第二晶体管202和写入字线WWL，上述读单元包括一个读出字线RWL和一个第一晶体管201，上述第一自旋轨道矩层104与位线电连接，上述第一自旋轨道矩层104在上述第一MTJ的上方，上述开关单元101为第三晶体管，上述数据读取单元102与上述开关单元101电连接，即数据从上述第三晶体管的漏极读取，上述第二自旋轨道矩层204在上述第二MTJ的上方，上述第二自旋轨道矩层204的一端与位线电连接，第二自旋轨道矩层204的另一端与第一晶体管201电连接，上述第一SOT单元包括通孔结构和绝缘介质层105，上述通孔结构包括导电通孔106和填充物质，上述第二自旋轨道矩层204与上述第二晶体管202电连接。上述一次可编程区域的数据读取和写入通过两个独立通道，上述数据存储区域的数据读取和写入通过单一通道。
上述第一自旋轨道矩层104在第一MTJ器件上方时，上述第一钉扎层107与上述第一底电极110电连接，在上述第一MTJ不包括上述第一底电极110时，上述第一钉扎层107与导电通孔106电连接，上述第一自由层109在上述第一势垒层108的上方，上述第一自旋轨道矩层104与位线BL相连。数据读取单元102从上述第三晶体管的漏端或者从上述第一MTJ的上述第一底电极110连出，通过放大器判断上述第一SOT单元的状态。上述第一SOT单元的分压表达式为：
Figure PCTCN2020142226-appb-000004
当然，上述开关单元还可以包括其他器件，上述第一晶体管和上述第二晶体管还可以为其他器件，在上述第一SOT单元包括上述通孔结构的情况下，上述第一MTJ可以不包括上述第一底电极。
实施例4
生成如图5所示的存储芯片结构图，图5(a)为存储芯片俯视图，图5(b)为存储芯片侧视图。其中，上述第一MTJ103包括第一顶电极111、第一钉扎层107、第一势垒层108和第一自由层109，上述第二MTJ203包括第二顶电极209、第二钉扎层205、第二势垒层206和第二自由层207，上述一次可编程区域单元中，上述开关单元101为第三晶体管，上述第三 晶体管的漏级与上述第一自旋轨道矩层104连接，上述第三晶体管的源极与源极线SL连接，上述第三晶体管的栅极与字线WL连接，上述数据读取单元102与上述第一自旋轨道矩层104的一端连接，上述第一MTJ103在上述第一自旋轨道矩层104的上方，上述第一自旋轨道矩层104的宽度大于上述第一MTJ103的尺寸，使得上述第一自旋轨道矩层104单位长度的电阻远低于上述第二自旋轨道矩层204单位长度的电阻，并且上述第一自旋轨道矩层104的总电阻远小于上述第一MTJ103的电阻。上述第一自旋轨道矩层104与上述第一MTJ103的上述第一自由层109连接，上述第一MTJ103与位线BL连接。优选地，上述一次可编程区域的上述第一自旋轨道矩层104的宽度约为上述数据存储区域的上述第二自旋轨道矩层204的宽度的2倍，使得上述第一自旋轨道矩层104单位长度的电阻比上述第二自旋轨道矩层204单位长度的电阻小50％以上，上述一次可编程区域与上述数据存储区域的器件尺寸一致。上述读单元包括一个读出字线RWL和一个第一晶体管201，上述写单元包括第二晶体管202和写入字线WWL。
对于上述一次可编程区域单元来说，上述第一SOT单元的电压V SOT表达式为：
Figure PCTCN2020142226-appb-000005
其中，R HM为上述数据读取单元与上述第一SOT单元之间的上述第一自旋轨道矩层104电阻，R MOS为上述第三晶体管打开时的电阻，R SOT为上述第一SOT单元的电阻，V BL为位线上施加的电压。
上述一次可编程区域中，R HM的电阻约为500欧姆，R MOS的电阻约为500欧姆，上述第一SOT单元分压V SOT数值增大，上述一次可编程区域单元更容易击穿。当上述第一SOT单元没有击穿时，处于平行态或者反平行态，电阻为5000或者10000欧姆，输出电压为低电平，状态为“0”；当上述第一SOT单元击穿后，其电阻约为100欧姆，输出电平为高电平，状态为“1”。
与实施例3相比，本实施例中的上述存储芯片不包括通孔结构，上述数据读取单元102与上述第一自旋轨道矩层104直接电连接，通过使上述第一自旋轨道矩层104单位长度的电阻远低于上述第二自旋轨道矩层204单位长度的电阻，并且上述第一自旋轨道矩层104的总电阻远小于上述第一MTJ103的电阻，保证了上述一次可编程区域能较好地工作，进而保证存储芯片的性能较好。
当然，上述开关单元还可以包括其他器件，上述第一晶体管和上述第二晶体管还可以为其他器件。
实施例5
生成了如图5所示的存储芯片结构图，图5(a)为存储芯片俯视图，图5(b)为存储芯片侧视图。其中，上述开关单元101为第三晶体管，一次可编程区域中，上述第三晶体管的 漏级与上述第一自旋轨道矩层104连接，上述第三晶体管的源极与源极线SL连接，上述第三晶体管的栅极与字线WL连接，上述数据读取单元102与上述第一自旋轨道矩层104的一端连接，上述第一MTJ103在上述第一自旋轨道矩层104的上方，上述第一自旋轨道矩层104的宽度大于上述第一MTJ103的尺寸，使得上述第一自旋轨道矩层104单位长度的电阻远低于上述第二自旋轨道矩层204单位长度的电阻，并且上述第一自旋轨道矩层104的总电阻远小于上述第一MTJ103的电阻。上述第一自旋轨道矩层104与上述第一MTJ103的第一自由层109连接，上述第一MTJ103与位线BL连接。优选地，上述一次可编程区域中的上述第一MTJ103的尺寸比上述数据存储区域中的上述第二MTJ203的尺寸要小约20％，使得上述一次可编程区域的器件电阻比上述数据存储区域的器件电阻大40％以上；上述一次可编程区域的上述第一自旋轨道矩层104与上述数据存储区域的上述第二自旋轨道矩层204的大小一致。上述读单元包括一个读出字线RWL和一个上述第一晶体管201，上述写单元包括上述第二晶体管202和写入字线WWL。
对于上述一次可编程区域来说，第一SOT单元的电压V SOT表达式为：
Figure PCTCN2020142226-appb-000006
其中R HM为上述数据读取单元与上述第一SOT单元之间的上述第一自旋轨道矩层104电阻，R MOS为上述第三晶体管打开时的电阻，R SOT为上述第一SOT单元的电阻，V BL为位线上施加的电压。
上述一次可编程区域的R HM的电阻约为1000欧姆，上述第一SOT单元电阻约为7800或者15600欧姆，上述第一SOT单元分压V SOT数值增大，上述一次可编程区域更容易击穿。当上述第一SOT单元没有击穿时，处于平行态或者反平行态，输出电压为低电平，状态为“0”；当上述第一SOT单元击穿后，其电阻约为100欧姆，输出电平为高电平，状态为“1”。
与实施例3相比，本实施例中的上述存储芯片不包括通孔结构，上述数据读取单元102与上述第一自旋轨道矩层104直接电连接，通过使上述第一自旋轨道矩层104单位长度的电阻远低于上述第二自旋轨道矩层204单位长度的电阻，并且上述第一自旋轨道矩层104的总电阻远小于上述第一MTJ103的电阻，保证了上述一次可编程区域能较好地工作，进而保证存储芯片的性能较好。
当然，上述开关单元还可以包括其他器件，上述第一晶体管和上述第二晶体管还可以为其他器件。
实施例6
生成如图6所示的存储芯片结构图，其中，上述第二MTJ有多个，上述读单元包括多个上述读出字线RWL和多个上述第一晶体管201，上述开关单元101为上述第三晶体管，上述写单元包括上述第二晶体管202和上述写入字线WWL，上述第二MTJ与上述第一晶体管201 一一对应连接，上述数据存储区域可以通过NAND-like SOT(类NAND闪存晶体管)阵列实现，上述一次可编程区域可以通过以上任意一种实施例实现，包括采用上述导电通孔结构，或者增大上述第一自旋轨道矩层的宽度结构，或者减小上述一次可编程区域中上述第一MTJ尺寸方法得到上述一次可编程区域。上述数据读取单元102可以与上述第三晶体管的漏端连接，也可以与上述第一自旋轨道矩层104连接。
当然，上述开关单元还可以包括其他器件，上述第一晶体管和上述第二晶体管还可以为其他器件。
从以上的描述中，可以看出，本公开上述的实施例实现了如下技术效果：
本公开提供了一种存储芯片，上述的存储芯片，包括上述一次可编程区域和上述数据存储区域，上述一次可编程区域包括第一SOT单元、开关单元和数据读取单元，上述第一SOT单元包括接触设置的第一MTJ和第一自旋轨道矩层；上述数据存储区域包括第二SOT单元、读单元和写单元，上述第二SOT单元包括接触设置的至少一个第二MTJ和第二自旋轨道矩层。上述存储芯片，通过上述一次可编程区域和上述数据存储区域可以实现芯片配置信息的存储，且上述一次可编程区域和上述数据存储区域有相同的基本结构SOT单元，相比现有技术，上述存储芯片在具备存储配置信息功能的同时，无需额外光罩，可同时制造得到上述一次可编程区域和上述数据存储区域，制造工艺较为简单，有效地控制了芯片的制造成本，缓解了现有的具有存储配置信息功能的存储芯片制作过程复杂，制造成本高的问题。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (12)

  1. 一种存储芯片，其特征在于，包括：
    一次可编程区域，包括第一SOT单元、开关单元和数据读取单元，所述第一SOT单元的第一端与位线电连接，所述第一SOT单元的第二端与所述开关单元的第一端电连接，所述开关单元的第二端与源极线电连接，所述开关单元的第三端与字线电连接，所述数据读取单元与所述开关单元的第一端电连接或者与所述第一SOT单元的第三端电连接，所述第一SOT单元包括接触设置的第一MTJ和第一自旋轨道矩层；
    数据存储区域，包括第二SOT单元、读单元和写单元，所述读单元的第一端和所述写单元的第一端分别与源极线电连接，所述读单元的第二端与所述第二SOT单元的第一端电连接，所述写单元的第二端与所述第二SOT单元的第二端电连接，所述第二SOT单元的第三端与位线电连接，所述第二SOT单元包括接触设置的至少一个第二MTJ和第二自旋轨道矩层。
  2. 根据权利要求1所述的存储芯片，其特征在于，所述第一MTJ的第二端为第一SOT单元的第一端，所述第一自旋轨道矩层的第二端为所述第一SOT单元的第二端，所述第一自旋轨道矩层的第三端为所述第一SOT单元的第三端，所述数据读取单元与所述第一SOT单元的第三端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二MTJ有一个，所述第二MTJ的第二端为第二SOT单元的第一端，所述第二自旋轨道矩层的第二端为所述第二SOT单元的第二端，所述第二自旋轨道矩层的第三端为所述第二SOT单元的第三端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
  3. 根据权利要求1所述的存储芯片，其特征在于，所述第一自旋轨道矩层的第二端为第一SOT单元的第一端，所述第一MTJ的第二端为所述第一SOT单元的第二端，所述数据读取单元与所述开关单元的第一端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二MTJ有一个，所述第二自旋轨道矩层的第二端为第二SOT单元的第一端，所述第二MTJ的第二端为所述第二SOT单元的第二端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
  4. 根据权利要求1所述的存储芯片，其特征在于，所述第一MTJ的第二端为第一SOT单元的第一端，所述第一自旋轨道矩层的第二端为所述第一SOT单元的第二端，所述第一自旋轨道矩层的第三端为所述第一SOT单元的第三端，所述数据读取单元与所述第一SOT单元的第三端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二MTJ有多个，多个所述第二MTJ的第二端为第二SOT单元的第一端，所述第二自旋轨道矩层的第二端为所述第二SOT单元的第二端，所述第二自旋轨道矩层的第三端为所述第二SOT单元的第三端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
  5. 根据权利要求1所述的存储芯片，其特征在于，所述第一自旋轨道矩层的第二端为第一SOT单元的第一端，所述第一MTJ的第二端为所述第一SOT单元的第二端，所述数据读 取单元与所述开关单元的第一端电连接，所述第一MTJ的第一端和所述第一自旋轨道矩层的第一端电连接；所述第二自旋轨道矩层的第二端为第二SOT单元的第一端，所述第二MTJ有多个，多个所述第二MTJ的第二端为所述第二SOT单元的第二端，所述第二MTJ的第一端和所述第二自旋轨道矩层的第一端电连接。
  6. 根据权利要求2所述的存储芯片，其特征在于，所述第一SOT单元还包括通孔结构和绝缘介质层，所述通孔结构垂直贯穿所述绝缘介质层，所述绝缘介质层与所述第一自旋轨道矩层的远离所述第一MTJ的表面接触，所述通孔结构的第一端与所述第一自旋轨道矩层的远离所述第一MTJ的表面接触，所述通孔结构的第二端为所述第一SOT单元的第二端，且所述通孔结构在预定平面上的投影位于所述第一MTJ的结构层中，所述预定平面为所述第一MTJ所在的平面。
  7. 根据权利要求1至6中任意一项所述的存储芯片，其特征在于，所述读单元包括至少一个读出字线和至少一个第一晶体管，所述第一晶体管的栅极和所述读出字线一一对应连接，所述第一晶体管的源极分别与所述源极线电连接，所述第一晶体管的漏极与所述第二MTJ一一对应电连接，所述写单元包括第二晶体管和写入字线，所述第二晶体管的栅极和所述写入字线电连接，所述第二晶体管的源极与所述源极线电连接，所述第二晶体管的漏极与所述第二自旋轨道矩层电连接。
  8. 根据权利要求1至6中任意一项所述的存储芯片，其特征在于，所述开关单元为第三晶体管，所述第三晶体管的栅极与所述字线电连接，所述第三晶体管的源极与源极线电连接，所述第三晶体管的漏极与所述通孔结构电连接。
  9. 根据权利要求1所述的存储芯片，其特征在于，所述第一自旋轨道矩层和所述第二自旋轨道矩层结构相同，所述第一自旋轨道矩层的与所述第一MTJ接触的材料为重金属材料层，所述第二自旋轨道矩层的与所述第二MTJ接触的材料为重金属材料层，所述重金属材料层包括铂、钽、钨、铱、铪、钌、铊、铋、金、钛和锇中的任意一种。
  10. 根据权利要求1所述的存储芯片，其特征在于，所述第一MTJ包括依次层叠的第一自由层、第一势垒层和第一钉扎层，所述第二MTJ包括依次层叠的第二自由层、第二势垒层和第二钉扎层，所述第一自由层与所述第一自旋轨道矩层接触，所述第二自由层和所述第二自旋轨道矩层接触。
  11. 根据权利要求1所述的存储芯片，其特征在于，所述第一MTJ还包括第一顶电极或第一底电极，在所述第一MTJ的第二端为所述第一SOT单元的第一端的情况下，所述第一MTJ包括所述第一顶电极，所述第一顶电极与位线电连接，在所述第一MTJ的第二端为所述第一SOT单元的第二端的情况下，所述第一MTJ包括所述第一底电极，所述第一底电极与所述开关单元的电连接，所述第二MTJ还包括第二顶电极或第二底电极，在所述第二MTJ的第二端为第二SOT单元的第一端的情况下，所述第二MTJ包括所述第二顶电极，所述第二顶电极与所述读单元电连接，在所述第二MTJ的第二端为所述第二SOT 单元的第二端的情况下，所述第二MTJ包括所述第二底电极，所述第二底电极与所述写单元电连接。
  12. 根据权利要求6所述的存储芯片，其特征在于，所述通孔结构包括导电通孔和填充物质，所述填充物质为低电阻导电材料。
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