WO2022110124A1 - 像素电路、驱动方法、显示基板和显示装置 - Google Patents

像素电路、驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2022110124A1
WO2022110124A1 PCT/CN2020/132711 CN2020132711W WO2022110124A1 WO 2022110124 A1 WO2022110124 A1 WO 2022110124A1 CN 2020132711 W CN2020132711 W CN 2020132711W WO 2022110124 A1 WO2022110124 A1 WO 2022110124A1
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Prior art keywords
voltage
line
transistor
electrically connected
circuit
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Application number
PCT/CN2020/132711
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English (en)
French (fr)
Inventor
宋二龙
张锴
蔡兴瑞
高雅瑰
颜海龙
魏昕宇
付强
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/132711 priority Critical patent/WO2022110124A1/zh
Priority to CN202080003117.9A priority patent/CN115104148B/zh
Priority to US17/434,709 priority patent/US11862084B2/en
Publication of WO2022110124A1 publication Critical patent/WO2022110124A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method, a display substrate and a display device.
  • the pixel definition layer (PDL) is gradually increased, making the pixel definition layer between the layers.
  • the PDL gap (PDL Gap) is gradually reduced, and the efficiency of OLED (organic light emitting diode) devices is gradually improved and the turn-on voltage is reduced.
  • an embodiment of the present disclosure provides a pixel circuit, including a driving circuit, a first light-emitting control circuit, a light-emitting element, a first initialization circuit, and a second initialization circuit;
  • the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the control terminal; the cathode of the light-emitting element is electrically connected to the first voltage line;
  • the first light-emitting control circuit is respectively electrically connected to the light-emitting control line, the driving circuit and the anode of the light-emitting element, and is used for controlling the driving circuit and the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line
  • the anodes of the light-emitting elements are connected or disconnected;
  • the first initialization circuit is respectively electrically connected to the first initialization control line, the control terminal of the driving circuit and the initialization voltage line, and is used for controlling the first initialization control signal provided by the first initialization control line under the control of the first initialization control line. writing the initialization voltage provided by the initialization voltage line into the control terminal of the drive circuit;
  • the second initialization circuit is respectively electrically connected with the second initialization control line, the anode of the light-emitting element and the initial data line, and is used for controlling the second initialization control signal provided by the second initialization control line to control the
  • the initial data voltage provided by the initial data line is applied to the anode of the light emitting element.
  • the second initialization circuit includes a first transistor
  • the gate of the first transistor is electrically connected to the second initialization control line, the first electrode of the first transistor is electrically connected to the initial data line, and the second electrode of the first transistor is electrically connected to the light emission
  • the anodes of the components are electrically connected.
  • the first initialization circuit includes a second transistor
  • the gate of the second transistor is electrically connected to the first initialization control line, the first electrode of the second transistor is electrically connected to the initialization voltage line, and the second electrode of the second transistor is electrically connected to the driver The control end of the circuit is electrically connected.
  • the pixel circuit further includes a second light-emitting control circuit, an energy storage circuit, a data writing circuit, and a compensation circuit; the first light-emitting control circuit and the second light-emitting control circuit of the driving circuit terminal electrical connection;
  • the second light-emitting control circuit is respectively electrically connected to the light-emitting control line, the second voltage line and the first end of the driving circuit, and is used for controlling the first end of the driving circuit under the control of the light-emitting control signal. Connecting or disconnecting between one end and the second voltage line;
  • the energy storage circuit is electrically connected to the control terminal of the driving circuit, and is used for maintaining the potential of the control terminal of the driving circuit;
  • the data writing circuit is respectively electrically connected with the gate line, the display data line and the first end of the driving circuit, and is used for writing the display data voltage on the display data line under the control of the gate driving signal write to the first end of the drive circuit;
  • the compensation circuit is respectively electrically connected to the gate line, the control terminal of the driving circuit and the second terminal of the driving circuit, and is used for controlling the control of the driving circuit under the control of the gate driving signal
  • the terminal is connected or disconnected with the second terminal of the driving circuit.
  • the driving circuit includes a driving transistor; the gate of the driving transistor is the control terminal of the driving circuit, the first electrode of the driving transistor is the first terminal of the driving circuit, and the gate of the driving transistor is the control terminal of the driving circuit.
  • the second electrode is the second end of the driving circuit;
  • the first light-emitting control circuit includes a third transistor; the gate of the third transistor is electrically connected to the light-emitting control line, and the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the third transistor is electrically connected to the anode of the light-emitting element;
  • the second light-emitting control circuit includes a fourth transistor; the gate of the fourth transistor is electrically connected to the light-emitting control line, the first electrode of the fourth transistor is electrically connected to the second voltage line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor;
  • the energy storage circuit includes a storage capacitor; the first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the second voltage line;
  • the data writing circuit includes a fifth transistor; the gate of the fifth transistor is electrically connected to the gate line, the first electrode of the fifth transistor is electrically connected to the display data line, and the fifth transistor is electrically connected to the gate line.
  • the second electrode is electrically connected to the first electrode of the driving transistor;
  • the compensation circuit includes a sixth transistor; the gate of the sixth transistor is electrically connected to the gate line, the first electrode of the sixth transistor is electrically connected to the gate of the driving transistor, and the sixth transistor is electrically connected to the gate line.
  • the second electrode of the drive transistor is electrically connected to the second electrode of the drive transistor.
  • an embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned pixel circuit, and the driving method includes:
  • the first initialization circuit controls to write the initialization voltage provided by the initialization voltage line into the control terminal of the drive circuit;
  • the second initialization circuit is under the control of the second initialization control signal , controlling the initial data voltage provided by the initial data line to the anode of the light-emitting element.
  • the pixel circuit further includes a data writing circuit, and the pixel circuit is included in the display panel; the driving method further includes: the data writing circuit is controlled by a gate driving signal on the gate line, Write the display data voltage on the display data line into the drive circuit;
  • the lowest display data voltage connected to all pixel circuits in the display panel is greater than a predetermined gray-scale voltage, and the initial data voltage is the same as the first voltage provided by the first voltage line; or,
  • the lowest display data voltage is less than the predetermined grayscale voltage
  • the initial data voltage is different from the first voltage
  • the absolute value of the difference between the initial data voltage and the first voltage is less than a predetermined voltage value
  • the difference between the initial data voltage and the first voltage is smaller than the turn-on voltage of the light-emitting element
  • the predetermined voltage value is a positive value
  • an embodiment of the present disclosure further provides a display substrate, the display substrate includes a base substrate and the above-mentioned pixel circuit disposed on the base substrate.
  • the pixel circuit includes a driving transistor and a storage capacitor; the display substrate further includes an initial data line disposed on the base substrate;
  • the gate of the driving transistor is multiplexed as the first plate of the storage capacitor
  • the initial data line and the gate electrode of the driving transistor are provided in the same layer and the same material, or the initial data line and the second electrode plate of the storage capacitor are provided in the same layer and the same material.
  • the display substrate further includes grid lines disposed on the base substrate;
  • the extension direction of the initial data line is the same as the extension direction of the gate line.
  • the display substrate further includes a display data line disposed on the base substrate;
  • the initial data line and the display data line are arranged on the same layer and material, or the initial data line is arranged on the side of the display data line facing away from the base substrate.
  • the extension direction of the initial data line is the same as the extension direction of the display data line.
  • the pixel circuit further includes a first transistor; the display substrate further includes a second initialization control line and an initial data line disposed on the base substrate;
  • the gate of the first transistor and the gate of the driving transistor are provided with the same layer and material, and the gate of the first transistor is electrically connected to the second initialization control line;
  • the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the driving transistor and the second electrode of the driving transistor are provided in the same layer and the same material;
  • the first electrode of the first transistor is electrically connected to the initial data line, and the second electrode of the first transistor is electrically connected to the anode of the light-emitting element.
  • the pixel circuit includes a drive transistor and a storage capacitor
  • the gate of the driving transistor is multiplexed as the first plate of the storage capacitor
  • the initialization voltage line and the gate electrode of the driving transistor are provided in the same layer and with the same material, or the initialization voltage line and the second electrode plate of the storage capacitor are provided in the same layer and the same material.
  • the display substrate further includes grid lines disposed on the base substrate;
  • the extension direction of the initialization voltage line is the same as the extension direction of the gate line.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • the display device further includes a driver chip and an initial data line, a first voltage line, and a second voltage line disposed outside the effective display area of the base substrate;
  • the initial data wiring includes a first initial data wiring portion that is directly electrically connected to the driver chip;
  • the first voltage line includes a first voltage line portion that is directly electrically connected with the driving chip, and the second voltage line includes a first voltage line portion that is directly electrically connected to the driving chip;
  • the first initial data wiring portion is disposed between the first voltage wiring portion and the first voltage wiring portion.
  • the first initial data wiring portion, the first voltage wiring portion, and the first voltage wiring portion all extend along the second direction;
  • the second direction is the direction in which the display data lines extend.
  • the display device further includes a driver chip and an initial data line, an initialization voltage line, a first voltage line and a second line disposed outside the effective display area of the base substrate. voltage wiring;
  • the initial data wiring includes a first initial data wiring portion that is directly electrically connected to the driver chip;
  • the initialization voltage wiring includes a first initialization voltage wiring portion that is directly electrically connected to the driving chip;
  • the first voltage line includes a first voltage line portion that is directly electrically connected with the driving chip, and the second voltage line includes a first voltage line portion that is directly electrically connected to the driving chip;
  • the first initialization voltage wiring part, the first initial data wiring part, the first voltage wiring part and the first voltage wiring part are arranged in sequence along a direction close to the effective display area.
  • FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic layout diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 5 is the structure diagram of the active layer in Fig. 4;
  • FIG. 6 is a structural diagram of the first gate metal layer in FIG. 4;
  • FIG. 7 is a structural diagram of the second gate metal layer in FIG. 4;
  • Fig. 8 is the schematic diagram of the via hole in Fig. 4;
  • FIG. 9 is a schematic structural diagram of the first source-drain metal layer in FIG. 4.
  • FIG. 10 is a schematic layout diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 11 is a structural diagram of the second gate metal layer in FIG. 10;
  • FIG. 12 is a schematic diagram of the via hole in FIG. 10;
  • FIG. 13 is a structural diagram of the second source-drain metal layer in FIG. 10;
  • FIG. 14 is a structural diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 15 is a structural diagram of a display device according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode;
  • the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode.
  • the pixel circuit described in at least one embodiment of the present disclosure includes a driving circuit 11 , a first light-emitting control circuit 12 , a light-emitting element EL, a first initialization circuit 13 and a second initialization circuit 14 ;
  • the driving circuit 11 is used to generate a driving current for driving the light-emitting element EL under the control of its control terminal; the cathode of the light-emitting element is electrically connected to the first voltage line V1;
  • the first light-emitting control circuit 12 is electrically connected to the light-emitting control E1, the driving circuit 11 and the anode of the light-emitting element EL respectively, and is used for controlling the driving under the control of the light-emitting control signal provided by the light-emitting control line E1
  • the circuit 11 is connected or disconnected with the anode of the light-emitting element EL;
  • the first initialization circuit 13 is electrically connected to the first initialization control line R1, the control terminal of the driving circuit 11 and the initialization voltage line I1 respectively, and is used for the first initialization control signal provided by the first initialization control line R1 Under the control of , the initialization voltage provided by the initialization voltage line I1 is controlled to be written into the control terminal of the drive circuit 11;
  • the second initialization circuit 14 is electrically connected to the second initialization control line R2, the anode of the light-emitting element EL and the initial data line D02, respectively, and is used for the second initialization control signal provided by the second initialization control line R2. Under the control, the initial data voltage provided by the initial data line D02 is controlled to the anode of the light-emitting element EL.
  • the pixel circuit writes an initialization voltage to the control terminal of the driving circuit 11 through the first initialization circuit 13 to initialize the control terminal of the driving circuit 11 , and sends the initialization voltage to the control terminal of the driving circuit 11 through the second initialization circuit 14 .
  • the initial data voltage is written to the anode of the light-emitting element EL to initialize the anode of the light-emitting element EL, and by adjusting the initial data voltage, it is possible to prevent leakage caused by light emission of the light-emitting element EL when the anode of the light-emitting element EL is initialized. Lateral leakage occurs in bright and low gray scales.
  • first initialization control line and the second initialization control line may be the same initialization control line; or, the first initialization control line and the second initialization control line may be different.
  • the pixel circuit is included in a display substrate, and the display substrate includes a base substrate, and multiple rows of gate lines, multiple columns of display data lines and multiple rows disposed on the base substrate Multi-column pixel circuit;
  • the pixel circuit of the nth row is electrically connected to the first initialization control line of the nth row and the gate line of the nth row respectively; n is a positive integer; the first initialization control line of the nth row and the second initialization control line of the nth row are the same initialization control line Wire;
  • the first initialization control signal of the nth row on the first initialization control line of the nth row is the same as the gate drive signal of the n-1th row on the gate line of the n-1th row;
  • n is a positive integer.
  • the pixel circuit is included in a display substrate, and the display substrate includes a base substrate, and multiple rows of gate lines, multiple columns of display data lines and multiple rows disposed on the base substrate Multi-column pixel circuit;
  • the pixel circuit of the nth row is electrically connected to the first initialization control line of the nth row, the second initialization control line of the nth row and the gate line of the nth row; n is a positive integer; the first initialization control line of the nth row and the nth row The second initialization control line is a different initialization control line;
  • the first initialization control signal of the nth row on the first initialization control line of the nth row is the same as the gate drive signal of the n-1th row on the gate line of the n-1th row;
  • the second initialization control signal of the nth row on the second initialization control line of the nth row is the same as the gate drive signal of the nth row on the gate line of the nth row;
  • n is a positive integer.
  • each row of pixel circuits included in the display substrate may be sequentially arranged along the extending direction of the display data lines.
  • each row of pixel circuits may face the direction of the side of the display substrate where the driver chip is disposed , arranged in order, but not limited to this.
  • the first voltage line may be a ground line or a low voltage signal line, but not limited thereto.
  • the light-emitting element EL may be an OLED (Organic Light-Emitting Diode), but is not limited thereto.
  • the second initialization circuit includes a first transistor
  • the gate of the first transistor is electrically connected to the second initialization control line, the first electrode of the first transistor is electrically connected to the initial data line, and the second electrode of the first transistor is electrically connected to the light emission
  • the anodes of the components are electrically connected.
  • the first initialization circuit includes a second transistor
  • the gate of the second transistor is electrically connected to the first initialization control line, the first electrode of the second transistor is electrically connected to the initialization voltage line, and the second electrode of the second transistor is electrically connected to the driver The control end of the circuit is electrically connected.
  • the pixel circuit further includes a second lighting control circuit 21 , an energy storage circuit 22 , a data writing circuit 23 and a compensation circuit 24; the first lighting control circuit 12 is electrically connected to the second end of the driving circuit 11;
  • the second light-emitting control circuit 21 is electrically connected to the light-emitting control line E1, the second voltage line V2 and the first end of the driving circuit 11 respectively, and is used for controlling the light-emitting control signal under the control of the light-emitting control signal. Connecting or disconnecting between the first end of the driving circuit 11 and the second voltage line V2;
  • the energy storage circuit 22 is electrically connected to the control terminal of the driving circuit 11 for maintaining the potential of the control terminal 11 of the driving circuit;
  • the data writing circuit 23 is electrically connected to the gate line G0, the display data line D01 and the first end of the driving circuit 11, respectively, and is used for connecting the display data line D01 to the display data line D01 under the control of the gate driving signal.
  • the display data voltage above is written into the first end of the drive circuit 11;
  • the compensation circuit 24 is respectively electrically connected to the gate line G0, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11, and is used for controlling the gate driving signal under the control of the gate driving signal.
  • the control terminal of the driving circuit 11 is connected or disconnected with the second terminal of the driving circuit 11 .
  • the second voltage line may be a high-voltage signal line, but not limited thereto.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second lighting control circuit 21 , an energy storage circuit 22 , a data writing circuit 23 and a compensation circuit 24 .
  • the second lighting control circuit 21 controls the first end of the driving circuit 11 .
  • the tank circuit 22 maintains the potential of the control terminal of the driving circuit 11
  • the data writing circuit 23 controls the writing of the display data voltage to the first terminal of the driving circuit 11
  • the compensation circuit 24 controls The threshold voltage of the drive transistor included in the drive circuit 11 is compensated.
  • the driving circuit includes a driving transistor; the gate of the driving transistor is the control terminal of the driving circuit, the first electrode of the driving transistor is the first terminal of the driving circuit, and the gate of the driving transistor is the control terminal of the driving circuit.
  • the second electrode is the second end of the driving circuit;
  • the first light-emitting control circuit includes a third transistor; the gate of the third transistor is electrically connected to the light-emitting control line, and the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the third transistor is electrically connected to the anode of the light-emitting element;
  • the second light-emitting control circuit includes a fourth transistor; the gate of the fourth transistor is electrically connected to the light-emitting control line, the first electrode of the fourth transistor is electrically connected to the second voltage line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor;
  • the energy storage circuit includes a storage capacitor; the first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the second voltage line;
  • the data writing circuit includes a fifth transistor; the gate of the fifth transistor is electrically connected to the gate line, the first electrode of the fifth transistor is electrically connected to the display data line, and the fifth transistor is electrically connected to the gate line.
  • the second electrode is electrically connected to the first electrode of the driving transistor;
  • the compensation circuit includes a sixth transistor; the gate of the sixth transistor is electrically connected to the gate line, the first electrode of the sixth transistor is electrically connected to the gate of the driving transistor, and the sixth transistor is electrically connected to the gate line.
  • the second electrode of the drive transistor is electrically connected to the second electrode of the drive transistor.
  • the light-emitting element is an organic light-emitting diode O1;
  • the driving circuit 11 includes a driving transistor T7;
  • the second initialization circuit includes a first transistor T1;
  • the gate G1 of the first transistor T1 is electrically connected to the second initialization control line R2, the first electrode S1 of the first transistor T1 is electrically connected to the initial data line D02, and the first transistor T1 is electrically connected to the initial data line D02.
  • the second electrode D1 is electrically connected to the anode of O1;
  • the first initialization circuit includes a second transistor T2;
  • the gate G2 of the second transistor T2 is electrically connected to the first initialization control line R1, the first electrode S2 of the second transistor T2 is electrically connected to the initialization voltage line I1, and the The second electrode D2 is electrically connected to the control terminal of the driving circuit;
  • the gate G7 of the driving transistor T7 is the control terminal of the driving circuit 11
  • the first electrode S7 of the driving transistor T7 is the first terminal of the driving circuit 11
  • the second electrode D7 of the driving transistor T7 is the second end of the drive circuit 11;
  • the first lighting control circuit includes a third transistor T3;
  • the gate G3 of the third transistor T3 is electrically connected to the light-emitting control line E1
  • the first electrode S3 of the third transistor T3 is electrically connected to the second electrode D7 of the driving transistor T7
  • the third transistor T3 is electrically connected to the second electrode D7 of the driving transistor T7.
  • the second electrode D3 of T3 is electrically connected to the anode of O1;
  • the second lighting control circuit includes a fourth transistor T4;
  • the gate G4 of the fourth transistor T4 is electrically connected to the light-emitting control line E1, the first electrode S4 of the fourth transistor T4 is electrically connected to the second voltage line V2, and the first electrode S4 of the fourth transistor T4 is electrically connected to the second voltage line V2.
  • the two electrodes D4 are electrically connected to the first electrode S7 of the driving transistor T7;
  • the energy storage circuit includes a storage capacitor C1; the first plate C1a of the storage capacitor C1 is electrically connected to the gate G7 of the driving transistor T7, and the second plate C1b of the storage capacitor C1 is electrically connected to the second plate C1b of the storage capacitor C1.
  • the voltage line V2 is electrically connected;
  • the data writing circuit includes a fifth transistor T5; the gate G5 of the fifth transistor T5 is electrically connected to the gate line G0, and the first electrode of the fifth transistor is electrically connected to the display data line D01, the second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor;
  • the compensation circuit includes a sixth transistor T6; the gate G6 of the sixth transistor T6 is electrically connected to the gate line G0, and the first electrode S6 of the sixth transistor T6 is connected to the gate G7 of the driving transistor T7 Electrically connected, the second electrode D6 of the sixth transistor T6 is electrically connected to the second electrode D7 of the driving transistor T7.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the second initialization control signal on R2 is the same as the gate driving signal on G0 , but not limited thereto.
  • the display period includes an initialization phase, a data writing phase, and a light-emitting phase that are set in sequence;
  • R1 provides a low voltage signal
  • E0, G0 and R2 provide a high voltage signal
  • T2 is turned on
  • T1, T5, T3, T4 and T6 are all turned off
  • I1 provides an initialization voltage signal to the gate of T7, so that T7 turn off;
  • R1 provides a high voltage signal
  • G0 and R2 provide a low voltage signal
  • E0 provides a high voltage signal
  • T1, T5 and T6 are all turned on
  • T2, T3 and T4 are all turned off
  • D02 provides the initial data voltage to O1 The anode of , so that O1 does not emit light
  • D01 provides the display data voltage Vd to S7
  • the connection between G7 and D7 is used to write data voltage and compensate for the threshold voltage of T7;
  • R1, G0 and R2 all provide high voltage signals
  • E0 provides low voltage signals
  • T1, T2, T5 and T6 are all turned off
  • T3 and T4 are turned on
  • T7 drives O1 to emit light.
  • the driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:
  • the first initialization circuit controls to write the initialization voltage provided by the initialization voltage line into the control terminal of the drive circuit under the control of the first initialization control signal;
  • the second initialization circuit controls the initial data voltage provided by the initial data line to the anode of the light-emitting element under the control of a second initialization control signal.
  • an initialization voltage is written to the control terminal of the driving circuit 11 through a first initialization circuit to initialize the control terminal of the driving circuit, and an initialization voltage is applied to the control terminal of the light-emitting element through the second initialization circuit.
  • the anode writes the initial data voltage to initialize the anode of the light-emitting element.
  • the pixel circuit may further include a data writing circuit, and the pixel circuit may be included in a display panel (the display panel may include the display substrate); the driving method may further include:
  • the data writing circuit writes the display data voltage on the display data line into the first end of the driving circuit under the control of the gate driving signal;
  • the lowest display data voltage connected to all pixel circuits in the display panel is greater than a predetermined gray-scale voltage, and the initial data voltage is the same as the first voltage provided by the first voltage line; or,
  • the lowest display data voltage is less than the predetermined grayscale voltage
  • the initial data voltage is different from the first voltage
  • the absolute value of the difference between the initial data voltage and the first voltage is less than a predetermined voltage value
  • the difference between the initial data voltage and the first voltage is smaller than the turn-on voltage of the light-emitting element
  • the predetermined voltage value is a positive value
  • the predetermined grayscale voltage and the predetermined voltage value may be selected according to actual conditions.
  • the predetermined grayscale voltage may be the grayscale voltage corresponding to L32, but not limit.
  • At least one embodiment of the present disclosure sets the initial data voltage according to the lowest display data voltage connected to the pixel circuit of the display panel
  • the initial data voltage is set to be the same as the first voltage, so that when the anode of the light-emitting element is initialized, it can be ensured that the light-emitting element does not emit light, and the leakage caused by the light-emitting element is prevented from emitting light. ;
  • the initial data voltage is set to be slightly larger than the first voltage, or the initial data voltage is set to be slightly smaller than the first voltage, so as to improve the low gray scale In the case of lower side leakage, and the difference between the initial data voltage and the first voltage is smaller than the turn-on voltage of the light-emitting element, so that when the anode of the light-emitting element is initialized, the light-emitting element can be guaranteed. Not glowing.
  • the display period may include an initialization phase, a data writing phase, and a light-emitting phase that are set in sequence;
  • the first initialization circuit controls to write the initialization voltage provided by the initialization voltage line into the control terminal of the drive circuit under the control of the first initialization control signal ;
  • the second initialization circuit under the control of the second initialization control signal, controls the initial data voltage provided by the initial data line to the anode of the light-emitting element, and the data writing circuit is in the Under the control of the gate driving signal, the display data voltage on the display data line is written into the first end of the driving circuit;
  • the first initialization circuit controls to write the initialization voltage provided by the initialization voltage line into the control terminal of the drive circuit under the control of the first initialization control signal ;
  • the second initialization circuit controls the initial data voltage provided by the initial data line to the anode of the light-emitting element;
  • the data writing circuit is in the Under the control of the gate driving signal, the display data voltage on the display data line is written into the first end of the driving circuit.
  • the display substrate includes a base substrate and the above-mentioned pixel circuit disposed on the base substrate.
  • the pixel circuit includes a driving transistor and a storage capacitor; the display substrate further includes an initial data line disposed on the base substrate;
  • the gate of the driving transistor is multiplexed as the first plate of the storage capacitor
  • the initial data line and the gate electrode of the driving transistor are provided in the same layer and the same material, or the initial data line and the second electrode plate of the storage capacitor are provided in the same layer and the same material.
  • the display substrate may include an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer sequentially disposed on the base substrate;
  • a patterning process may be performed on the first gate metal layer to form gate lines and gates of each transistor, and a patterning process may be performed on the second gate metal layer to form the second plate of the storage capacitor;
  • the initial data lines may be The gate electrode of each transistor is provided with the same layer and material, or the initial data line may be provided with the same layer and material as the second electrode plate of the storage capacitor. That is, the initial data line may be formed on the first gate metal layer or the second gate metal layer.
  • the display substrate when the initial data line is formed on the first gate metal layer or the second gate metal layer, the display substrate further includes a gate line disposed on the base substrate;
  • the extension direction of the initial data line is the same as the extension direction of the gate line.
  • the extension direction of the initial data line is the same as the extension direction of the gate line may mean that the extension direction of the initial data line is exactly the same as the extension direction of the gate line, Alternatively, the angle between the extension direction of the initial data line and the extension direction of the gate line is smaller than a predetermined angle, so that the extension direction of the initial data line is substantially the same as the extension direction of the gate line; This is limited.
  • the display substrate further includes a display data line disposed on the base substrate;
  • the initial data line and the display data line are arranged on the same layer and material, or the initial data line is arranged on the side of the display data line facing away from the base substrate.
  • the display substrate may include an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer sequentially disposed on the base substrate, which may
  • the first source-drain metal layer is subjected to a patterning process to form display data lines and initial data lines.
  • the initial data lines can be provided with the same layer and material as the display data lines. the first source-drain metal layer; or,
  • the display substrate may include an active layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially arranged on the base substrate.
  • a patterning process is performed on the first source-drain metal layer to form a display data line
  • a patterning process is performed on the second source-drain metal layer to form an initial data line, that is, the initial data line is arranged on the back of the display data line
  • the initial data lines are formed on the second source-drain metal layer.
  • the extension direction of the initial data line may be the same as the extension direction of the display data line same.
  • the extension direction of the initial data line is the same as the extension direction of the display data line may mean that the extension direction of the initial data line is completely the same as the extension direction of the display data line or, the angle between the extension direction of the initial data line and the extension direction of the display data line is smaller than a predetermined angle, so that the extension direction of the initial data line and the extension direction of the display data line are approximately the same ; but not limited thereto.
  • the pixel circuit further includes a first transistor; the display substrate further includes a second initialization control line and an initial data line disposed on the base substrate;
  • the gate of the first transistor and the gate of the driving transistor are provided with the same layer and material, and the gate of the first transistor is electrically connected to the second initialization control line;
  • the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the driving transistor and the second electrode of the driving transistor are provided in the same layer and the same material;
  • the first electrode of the first transistor is electrically connected to the initial data line, and the second electrode of the first transistor is electrically connected to the anode of the light-emitting element.
  • the second initialization control line may be provided with the same layer and material as the gate line, and the second initialization control signal on the second initialization control line may be the same as the gate on the gate line
  • the driving signals are the same.
  • the pixel circuit may include a drive transistor and a storage capacitor
  • the gate of the driving transistor is multiplexed as the first plate of the storage capacitor
  • the initialization voltage line and the gate electrode of the driving transistor are provided in the same layer and with the same material, or the initialization voltage line and the second electrode plate of the storage capacitor are provided in the same layer and the same material.
  • the initialization voltage line may be formed on the first gate metal layer, or the initialization voltage line may also be formed on the second gate metal layer, but not limited thereto.
  • the display substrate may further include grid lines disposed on the base substrate;
  • the extension direction of the initialization voltage line is the same as the extension direction of the gate line.
  • the extension direction of the initialization voltage line is the same as the extension direction of the gate line may mean that the extension direction of the initialization voltage line is exactly the same as the extension direction of the gate line, Alternatively, the angle between the extension direction of the initialization voltage line and the extension direction of the gate line is smaller than a predetermined angle, so that the extension direction of the initialization voltage line is substantially the same as the extension direction of the gate line; This is limited.
  • FIG. 4 is a schematic layout diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit is arranged in the effective display area of the display substrate.
  • the first initialization voltage line part included in the initialization voltage line is labeled I11
  • the first initial data line part included in the initial data line is labeled D021
  • the first initial data line part included in the initialization voltage line is labeled I12.
  • Two initializing voltage line parts labeled D022 is the second initial data line part included in the initial data line; I11, I12, D021 and D022 can be set in the effective display area; I11 and I12 can be set in the same The initialization voltage traces outside the effective display area are electrically connected, I11 and I12 are electrically connected to each other, D021 and D022 can both be electrically connected to the initial data traces set outside the effective display area, and D021 and D022 are electrically connected to each other, but not This is the limit.
  • the display substrate includes multiple rows and multiple columns of pixel circuits disposed on the base substrate, each row of pixel circuits is electrically connected to the same row of gate lines, and the same column of pixel circuits is electrically connected to the same column of display data lines ;
  • the initialization voltage line includes a plurality of initialization voltage line parts extending along the first direction, each row of pixel circuits is electrically connected with the corresponding initialization voltage line part, and the initial data line including a plurality of initial data line portions extending along the first direction, and each row of pixel circuits is electrically connected to the corresponding initial data line portion;
  • the same row of pixel circuits can be electrically connected to the same initializing voltage line portion, and the same row of pixel circuits can be electrically connected to the same initial data line portion;
  • an initial data line and an initialization voltage line are arranged outside the effective display area of the display substrate, and the initialization voltage line is used to provide initialization voltage to each of the initialization voltage line parts, and the initial data line is used to provide The initial data voltage is applied to each initial data line portion, the initial data line portions are electrically connected to each other, and the initial data line portions are electrically connected to each other.
  • the first initialization control line is labeled R1
  • the gate line is labeled G0
  • the second plate of the storage capacitor in the pixel circuit is labeled C1b
  • the light-emitting control line is labeled E1.
  • the one labeled D01 is the display data line
  • the one labeled R2 is the second initialization control line;
  • the second initialization control signal supplied to the second initialization control line R2 is the same as the gate driving signal supplied to G0.
  • an active layer, a first gate metal layer, a second gate metal layer and a first source-drain metal layer are sequentially arranged along a direction away from the base substrate ;
  • the initial data line and the initializing voltage line are formed in the second gate metal layer, and the extension direction of the initial data line is the same as that of the gate line G0, and the extension direction of the initializing voltage line is the same as that of the gate line G0.
  • the extending directions of the gate lines G0 are the same.
  • the extending direction of G0 may be a first direction, for example, the first direction may be a horizontal direction, and the extending direction of D01 may be a second direction, for example, the second direction may be vertical direction, but not limited to this.
  • the extension direction of the gate lines may be the first direction
  • the extension direction of the display data lines may be the second direction
  • the first direction and the second direction intersect; but not limited thereto.
  • the pattern of the active layer in FIG. 4 includes the first electrode S1 of the first transistor, the second electrode D1 of the first transistor, the first electrode S2 of the second transistor, and the second electrode of the second transistor D2, the first electrode S4 of the fourth transistor, the first electrode S5 of the fifth transistor, the second electrode D5 of the fifth transistor, and the second electrode D6 of the sixth transistor;
  • the second electrode D2 of the second transistor is multiplexed as the first electrode of the sixth transistor
  • the second electrode D5 of the fifth transistor is multiplexed as The second electrode of the fourth transistor and the second electrode D5 of the fifth transistor are multiplexed as the first electrode of the driving transistor; the second electrode D6 of the sixth transistor is multiplexed as the driving transistor. second electrode.
  • T2 is a double-gate transistor, the first gate pattern included in the gate of the second transistor is labeled G21, and the second gate pattern included in the gate of the second transistor is labeled G22;
  • the gate numbered as G5 is the gate of the fifth transistor
  • T6 is a double-gate transistor, the third gate pattern included in the gate of the sixth transistor is labeled G61, and the fourth gate pattern included in the gate of the sixth transistor is labeled G62;
  • the gate marked G3 is the gate of the third transistor, the gate marked G4 is the gate of the fourth transistor, and the gate marked G1 is the gate of the first transistor;
  • the gate numbered G7 is the gate of the driving transistor, and G7 is multiplexed as the first plate of the storage capacitor in the pixel circuit.
  • the label C1b is the second plate of the storage capacitor
  • the label H0 is the connection hole provided on C1b
  • D2 is electrically connected to G2 through the connection hole H0.
  • the first gate metal layer and the second gate metal layer are arranged in sequence, an interlayer dielectric layer can be arranged, and via holes can be formed after the interlayer medium layer is arranged.
  • the first via is marked H1
  • the second via is marked H2
  • the third via is marked H3
  • the fourth via is marked H4
  • the one marked H5 is the fourth via.
  • the fifth via, the sixth via H6, the seventh via H7, the eighth via H8, the ninth via H9, and the H10 It is the tenth via hole, the one marked H11 is the eleventh via hole, the one marked H12 is the twelfth via hole, the one marked H13 is the thirteenth via hole, and the one marked H14 is the fourteenth via hole, The one marked as H15 is the fifteenth via.
  • the pattern of the first source-drain metal layer includes a display data line D01, a second voltage line, a first conductive connection part L1, a second conductive connection part L2, a third conductive connection part L3, a fourth conductive connection part L3, and a fourth conductive connection part L1.
  • the portion of the first voltage line included in the second voltage line is labeled V21 .
  • the second voltage line includes a plurality of voltage line parts extending along the second direction, and each column of pixel circuits is electrically connected to the corresponding voltage line part;
  • a second voltage line is arranged outside the display area, and the second voltage line is used to provide a second voltage signal to each of the voltage line parts included in the second voltage line, and each of the second voltage line includes The voltage line portions are electrically connected to each other.
  • S2 is electrically connected to the first conductive connection part L1 through the fourth via hole H4, and L1 is electrically connected to I11 through the first via hole H1, so that S2 is electrically connected to I11, that is, S2 is electrically connected. electrically connected to the initialization voltage line;
  • S1 is electrically connected to L6 through H14, and L6 is electrically connected to D022 through H11, so that S1 and D022 are electrically connected, that is, S1 is electrically connected to the initial data line;
  • D2 is electrically connected to L3 through H7, and L3 is electrically connected to G7 through H0;
  • S5 is electrically connected to D01 through H3;
  • S4 is electrically connected to V21 through H8;
  • D1 is electrically connected to L4 through H9, and L4 is electrically connected to the anode layer through vias.
  • the display substrate When fabricating the display substrate, after fabricating the first source-drain metal layer, fabricate a first flat layer and an anode layer in sequence, and the anode layer includes a plurality of mutually independent anodes; L4 can pass through the first source-drain metal layer.
  • a via hole of a flat layer is electrically connected to the anode; after the anode layer is fabricated, a PDL layer (pixel definition layer, pixel definition layer), an organic light-emitting functional layer and a cathode layer may be fabricated in sequence.
  • the cathode layer may cover the entire effective display area, and the cathode layer may overlap with the first voltage line through the anode layer in the non-display area of the display substrate, so that the light-emitting element
  • the cathode is electrically connected to the first voltage line, but not limited thereto.
  • the first voltage line may be disposed around the effective display area, but not limited thereto.
  • a first gate insulating layer may be provided between the active layer and the first gate metal layer, and a second gate may be provided between the first gate metal layer and the second gate metal layer
  • an interlayer dielectric layer may be provided between the second gate metal layer and the first source-drain metal layer, but not limited thereto.
  • both the initial data line and the initializing voltage line are formed in the second gate metal layer, but not limited thereto.
  • the initial data line and the initializing voltage line both extend along a first direction, for example, the first direction may be a horizontal direction, then the initial data line includes The initial data line portions of the multiple rows also extend along the first direction, and the initial data line portions of the multiple rows included in the initialization voltage lines also extend along the first direction. Outside the effective display area of the display substrate, there may be provided with an initial data voltage.
  • the initial data wiring and the initializing voltage wiring providing the initializing voltage, the initial data wiring and the initializing voltage wiring may be arranged on the first side and/or the second side (the first side) of the display substrate.
  • the side may be the left side, and the second side may be the right side), and at least part of the traces included in the initial data trace and at least part of the traces included in the initialization voltage trace may extend in the second direction (
  • the second direction may be, for example, a vertical direction)
  • the initial data line portion of each row may extend in the first direction until it is electrically connected to the initial data line
  • the initializing voltage line portion of each row may extend along the first direction until it is electrically connected to the initial data line.
  • the initialization voltage traces are electrically connected.
  • the second voltage line extends along the second direction, and the plurality of voltage line portions included in the second voltage line extend along the second direction, so the second voltage line is used to provide the second voltage signal.
  • the second voltage traces may be disposed on the side of the effective display area of the display substrate close to the driving chip.
  • the second voltage traces may be disposed on the lower side of the display substrate, but this is not the case. limit.
  • the second voltage wiring may include a second voltage wiring portion extending along the first direction and a first voltage wiring portion extending along the second direction, and the second voltage wiring portion is used for electrical Connect a plurality of voltage line parts included in the second voltage line (for example, when the second voltage line is arranged on the lower side of the display substrate, each voltage line part included in the second voltage line can be along the first line. extending downward in two directions to be electrically connected to the second voltage wiring portion), the first end of the first voltage wiring portion is electrically connected to the second voltage wiring portion, and the first end of the first voltage wiring portion is electrically connected to the second voltage wiring portion.
  • the two terminals are directly electrically connected with the driving chip to receive the second voltage signal provided by the driving chip.
  • R1 and R2 are different initialization control lines. In actual operation, R1 and R2 can also be the same initialization control line.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 10 and at least one embodiment of the pixel circuit shown in FIG. 4 is that a second source is further provided on the side of the first source-drain metal layer away from the base substrate. Drain metal layer, the initial data line extends along the second direction, that is, the extension direction of the initial data line is the same as the extension direction of the display data line, and a patterning process is performed on the second source-drain metal layer to form the initial data Each initial data line portion included in the line. In FIG. 10 , the portion of the first initial data line included in the initial data line is labeled D021 .
  • the structure diagram of the active layer in FIG. 10 is shown in FIG. 5 , the structure diagram of the first gate metal layer in FIG. 10 is shown in FIG. 6 , and the structure diagram of the second gate metal layer in FIG. 10 is shown in FIG. 11 .
  • the schematic diagram of the via hole in FIG. 10 is shown in FIG. 12
  • the structure diagram of the first source-drain metal layer in FIG. 10 is shown in FIG. 9, and the structure diagram of the second source-drain metal layer in FIG. 10 is shown in FIG. 13 shown.
  • FIG. 10-FIG. 13 L6 is electrically connected to D021 through H11. As shown in FIG. 10, the extension direction of D021 is the same as that of D01.
  • connection relationship of the other components in FIG. 10 is the same as the connection relationship of the components in FIG. 4 .
  • the same column of pixel circuits can be electrically connected to the same initial data line portion, and the same row of pixel circuits can be connected to the same initializing voltage
  • the wire part is electrically connected.
  • R1 and R2 are different initialization control lines. In actual operation, R1 and R2 can also be the same initialization control line.
  • the display device includes the above-mentioned display substrate.
  • the display device may further include a driver chip and initial data lines, first voltage lines and second voltage lines disposed outside the effective display area of the base substrate ;
  • the initial data wiring includes a first initial data wiring portion that is directly electrically connected to the driver chip;
  • the first voltage line includes a first voltage line portion that is directly electrically connected with the driving chip, and the second voltage line includes a first voltage line portion that is directly electrically connected to the driving chip;
  • the first initial data wiring portion is disposed between the first voltage wiring portion and the first voltage wiring portion.
  • the first initial data wiring portion is disposed between the first voltage wiring portion and the first voltage wiring portion, the first voltage wiring portion is used for providing a first voltage signal, and the first voltage wiring portion is used for providing a first voltage signal.
  • the voltage wiring part is used to provide a second voltage signal, and both the first voltage signal and the second voltage signal are DC voltage signals, so that the initial data voltage on the first initial data wiring part will not be disturbed .
  • the driving chip may be disposed on a COF (chip on film) or directly bound on the base substrate, and the COF may be attached to the side of the display substrate, but not limited thereto.
  • the driving chip may be used for providing a first voltage signal, a second voltage signal, an initialization voltage and an initial data voltage.
  • the base substrate may be a flexible substrate or a rigid substrate
  • the driving chip may use a COP (Chip On Pi, COP is a technology in which a chip is bound on a flexible substrate) technology or COG (Chip On Glass, COG is a technology in which the chip is directly bonded to the glass surface) technology is bonded on the substrate substrate.
  • COP Chip On Pi
  • COG Chip On Glass
  • COG Chip On Glass
  • the first initial data wiring portion, the first voltage wiring portion, and the first voltage wiring portion all extend along the second direction, but not limited thereto;
  • the second direction is the direction in which the display data lines extend.
  • the display device may further include a driver chip and initial data lines, initialization voltage lines, first voltage lines, and second lines disposed outside the effective display area of the base substrate voltage wiring;
  • the initial data wiring includes a first initial data wiring portion that is directly electrically connected to the driver chip;
  • the initialization voltage wiring includes a first initialization voltage wiring portion that is directly electrically connected to the driving chip;
  • the first voltage line includes a first voltage line portion that is directly electrically connected with the driving chip, and the second voltage line includes a first voltage line portion that is directly electrically connected to the driving chip;
  • the first initialization voltage wiring part, the first initial data wiring part, the first voltage wiring part and the first voltage wiring part are arranged in sequence along a direction close to the effective display area.
  • the first initial data wiring portion may also be disposed between the first initializing voltage wiring portion and the first voltage wiring portion.
  • the display substrate further includes an initial data line, an initialization voltage line, a gate driving circuit 140, a first voltage line and a second voltage line arranged outside the effective display area A0;
  • the second voltage wiring includes a second voltage wiring portion L22 extending along the first direction and a first voltage wiring portion L21 extending along the second direction, and the second voltage wiring portion L22 is used to electrically connect all The plurality of voltage line parts included in the second voltage line (when the second voltage wiring is arranged on the lower side of the display substrate, each voltage line part included in the second voltage line may be downward in the second direction extending to be electrically connected to the second voltage wiring portion), the first end of the first voltage wiring portion L21 is electrically connected to the second voltage wiring portion L22, and the second voltage wiring portion L21
  • the terminal is directly electrically connected to the driver chip 141 to receive the second voltage signal provided by the driver chip 141;
  • the initial data wiring includes a first initial data wiring portion L31 extending along the second direction, a second initial data wiring portion L32 disposed on the left side of the effective display area A0, and a second initial data wiring portion L32 for electrical connection
  • the third initial data wiring parts L33; L32 of L31 and L32 may extend along the second direction; each initial data line part included in the initial data line is directly electrically connected to the second initial data wiring part L32; L31 , L32 and L33 are integrated; L31 is directly electrically connected to the driver chip 141 to receive the second voltage signal provided by the driver chip 141;
  • the initialization voltage wiring includes a first initialization voltage wiring portion L41 extending along the second direction, and a second initialization voltage wiring portion L42 disposed on the left side of the effective display area A0.
  • L41 and L42 are directly connected to each other. Electrical connection; L41 and L42 are integrated; L41 is directly electrically connected to the driver chip 141, and the driver chip 141 is used to provide an initialization voltage to L41; L42 also extends in the second direction;
  • the gate driving circuit 140 is disposed on the side of L42 away from the effective display area A0; the gate driving circuit 140 can be electrically connected to multiple rows of gate lines;
  • the first voltage line includes a first voltage line portion L51 that is directly electrically connected to the driving chip 141, a second voltage line portion L52 that is disposed on the left side of the effective display area A0, and is used for electrical connection.
  • the third initial data wiring portion L53 of L51 and L52; L51 and L52 extend along the second direction, and L53 extends along the first direction; the driving chip 141 provides the first voltage signal to L51;
  • the first voltage line may be disposed on each side of the display substrate without the driving chip, and the first voltage line is electrically connected to the driving chip for receiving all the driving chips.
  • the first voltage signal provided by the driver chip but not limited to this;
  • the initial data wiring, the initializing voltage wiring and the second voltage wiring may also be provided on the right side of the effective display area, but not limited thereto.
  • the initialization voltage traces can be set with the same layer and material as the initialization voltage traces
  • the initial data traces can be set with the same layer and the same material as the initial data traces
  • the second voltage traces can be set with the second voltage traces The same layer and the same material are set, but not limited to this.
  • the first voltage line may be fabricated from the first source-drain metal layer or the second source-drain metal layer, but not limited thereto.
  • L42 and L32 can be provided in the same layer and material, and L42 is electrically connected to the initialization voltage line in the effective display area through a jumper to avoid L42 and the initialization voltage line in the effective display area.
  • the connecting line between them is overlapped with L32 to avoid short circuit.
  • the display substrate according to at least one embodiment of the present disclosure further includes an initial data wiring, an initializing voltage wiring, a gate driving circuit 140, a first voltage line and a second voltage line;
  • the initial data wiring is arranged below the effective display area A0 (that is, the initial data wiring is arranged on the lower side of the display substrate);
  • the initial data wiring includes a first initial data wiring portion L31 extending along the second direction, a second initial data wiring portion L32 extending along the first direction, and a third initial data wiring portion for electrically connecting L31 and L32.
  • the data wiring portion L33; L33 extends along the second direction; L31 is directly electrically connected to the driving chip 141 to receive the second voltage signal provided by the driving chip 141;
  • the second voltage traces are arranged below the effective display area A0 (that is, the second voltage traces are disposed on the lower side of the display substrate), and the second voltage traces include a second voltage trace extending along the first direction.
  • a voltage wiring part L22 and a first voltage wiring part L21 extending along the second direction, the second voltage wiring part L22 is used for electrically connecting a plurality of voltage line parts included in the second voltage line, the first voltage
  • the first end of the wiring portion L21 is electrically connected to the second voltage wiring portion L22
  • the second end of the first voltage wiring portion L21 is directly electrically connected to the driving chip 141 to receive the second voltage provided by the driving chip 141 . signal;
  • the second voltage wiring portion L22 can be electrically connected to the voltage line part included in the second voltage line in the effective display area A0 through a jumper, so as to avoid short circuit due to overlapping with L32;
  • the initialization voltage wiring includes a first initialization voltage wiring portion L41 extending along the second direction, a second initialization voltage wiring portion L42 disposed on the left side of the effective display area A0, and for electrical connection
  • the third initialization voltage trace portion L43 extending along the first direction of L41 and L42; L41 is directly electrically connected to the driving chip 141, and the driving chip 141 is used to provide the initialization voltage to L41; L42 also extends along the second direction ;
  • the gate driving circuit 140 is disposed on the side of L41 away from the effective display area A0; the gate driving circuit 140 can be electrically connected to multiple rows of gate lines;
  • the first voltage line includes a first voltage line portion L51 that is directly electrically connected to the driving chip 141, a second voltage line portion L52 that is disposed on the left side of the effective display area A0, and is used for electrical connection.
  • the third initial data wiring portion L53 of L51 and L52; L51 and L52 extend along the second direction, and L53 extends along the first direction; the driving chip 141 provides the first voltage signal to L51;
  • the first voltage line may be disposed on each side of the display substrate without the driving chip, and the first voltage line is electrically connected to the driving chip for receiving all the driving chips.
  • the first voltage signal provided by the driver chip but not limited to this;
  • initialization voltage trace and the second voltage trace may also be set on the right side of the effective display area, but not limited to this.
  • the display device may be any product or component with a display touch function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display touch function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

Abstract

一种像素电路、驱动方法、显示基板和显示装置。像素电路包括驱动电路（11）、第一发光控制电路（12）、发光元件（EL）、第一初始化电路（13）和第二初始化电路（14）；第一初始化电路（13）在第一初始化控制信号的控制下，控制将初始化电压线（I1）提供的初始化电压写入驱动电路（11）的控制端；第二初始化电路（14）在第二初始化控制线（R2）提供的第二初始化控制信号的控制下，控制将初始数据线（D02）提供的初始数据电压至发光元件（EL）的阳极；从而能够防止在对发光元件（EL）的阳极进行初始化时，由于发光元件（EL）发光而产生的漏电起亮以及低灰阶下侧向漏电的情况发生。

Description

像素电路、驱动方法、显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法、显示基板和显示装置。
背景技术
随着AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光而二极管)显示技术的不断发展，为了适应更为复杂的显示环境，像素定义层(PDL)逐渐增加，使得像素定义层之间的间距(PDL Gap)逐渐减小，且OLED(有机发光二极管)器件效率逐渐提升以及开启电压降低，以上因素导致OLED器件阳极节点越来越受到关注。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括驱动电路、第一发光控制电路、发光元件、第一初始化电路和第二初始化电路；
所述驱动电路用于在其控制端的控制下，产生驱动所述发光元件的驱动电流；所述发光元件的阴极与第一电压线电连接；
所述第一发光控制电路分别与发光控制线、所述驱动电路和所述发光元件的阳极电连接，用于在发光控制线提供的发光控制信号的控制下，控制所述驱动电路与所述发光元件的阳极之间连通或断开；
所述第一初始化电路分别与第一初始化控制线、所述驱动电路的控制端和初始化电压线电连接，用于在所述第一初始化控制线提供的第一初始化控制信号的控制下，控制将初始化电压线提供的初始化电压写入所述驱动电路的控制端；
所述第二初始化电路分别与第二初始化控制线、所述发光元件的阳极和初始数据线电连接，用于在所述第二初始化控制线提供的第二初始化控制信号的控制下，控制将所述初始数据线提供的初始数据电压至所述发光元件的阳极。
可选的，所述第二初始化电路包括第一晶体管；
所述第一晶体管的栅极与所述第二初始化控制线电连接，所述第一晶体管的第一电极与所述初始数据线电连接，所述第一晶体管的第二电极与所述发光元件的阳极电连接。
可选的，所述第一初始化电路包括第二晶体管；
所述第二晶体管的栅极与所述第一初始化控制线电连接，所述第二晶体管的第一电极与所述初始化电压线电连接，所述第二晶体管的第二电极与所述驱动电路的控制端电连接。
可选的，本公开至少一实施例所述的像素电路还包括第二发光控制电路、储能电路、数据写入电路和补偿电路；所述第一发光控制电路与所述驱动电路的第二端电连接；
所述第二发光控制电路分别与所述发光控制线、第二电压线和所述驱动电路的第一端电连接，用于在所述发光控制信号的控制下，控制所述驱动电路的第一端与所述第二电压线之间连通或断开；
所述储能电路与所述驱动电路的控制端电连接，用于维持所述驱动电路的控制端的电位；
所述数据写入电路分别与栅线、显示数据线和所述驱动电路的第一端电连接，用于在所述栅极驱动信号的控制下，将所述显示数据线上的显示数据电压写入所述驱动电路的第一端；
所述补偿电路分别与所述栅线、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述栅极驱动信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通或断开。
可选的，所述驱动电路包括驱动晶体管；所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一电极为所述驱动电路的第一端，所述驱动晶体管的第二电极为所述驱动电路的第二端；
所述第一发光控制电路包括第三晶体管；所述第三晶体管的栅极与所述发光控制线电连接，所述第三晶体管的第一电极与所述驱动晶体管的第二电极电连接，所述第三晶体管的第二电极与所述发光元件的阳极电连接；
所述第二发光控制电路包括第四晶体管；所述第四晶体管的栅极与所述 发光控制线电连接，所述第四晶体管的第一电极与所述第二电压线电连接，所述第四晶体管的第二电极与所述驱动晶体管的第一极电连接；
所述储能电路包括存储电容；所述存储电容的第一极板与所述驱动晶体管的栅极电连接，所述存储电容的第二极板与所述第二电压线电连接；
所述数据写入电路包括第五晶体管；所述第五晶体管的栅极与所述栅线电连接，所述第五晶体管的第一电极与所述显示数据线电连接，所述第五晶体管的第二电极与所述驱动晶体管的第一电极电连接；
所述补偿电路包括第六晶体管；所述第六晶体管的栅极与所述栅线电连接，所述第六晶体管的第一电极与所述驱动晶体管的栅极电连接，所述第六晶体管的第二电极与所述驱动晶体管的第二电极电连接。
在第二个方面中，本公开实施例还提供了一种驱动方法，应用于上述的像素电路，所述驱动方法包括：
所述第一初始化电路在第一初始化控制信号的控制下，控制将初始化电压线提供的初始化电压写入所述驱动电路的控制端；所述第二初始化电路在第二初始化控制信号的控制下，控制将所述初始数据线提供的初始数据电压至所述发光元件的阳极。
可选的，所述像素电路还包括数据写入电路，所述像素电路包含于显示面板；所述驱动方法还包括：所述数据写入电路在栅线上的栅极驱动信号的控制下，将显示数据线上的显示数据电压写入驱动电路；
所述显示面板中的所有像素电路接入的最低显示数据电压大于预定灰阶电压，所述初始数据电压与第一电压线提供的第一电压相同；或者，
所述最低显示数据电压小于所述预定灰阶电压，所述初始数据电压与所述第一电压不相同，所述初始数据电压与所述第一电压的差值的绝对值小于预定电压值，所述初始数据电压与所述第一电压之间的差值小于所述发光元件的启亮电压，所述预定电压值为正值。
在第三个方面中，本公开实施例还提供了一种显示基板，所述显示基板包括衬底基板和设置于所述衬底基板上的上述的像素电路。
可选，所述像素电路包括驱动晶体管和存储电容；所述显示基板还包括设置于所述衬底基板上的初始数据线；
所述驱动晶体管的栅极复用为所述存储电容的第一极板；
所述初始数据线与所述驱动晶体管的栅极同层同材料设置，或者，所述初始数据线与所述存储电容的第二极板同层同材料设置。
可选的，所述显示基板还包括设置于所述衬底基板上的栅线；
所述初始数据线的延伸方向与所述栅线的延伸方向相同。
可选的，所述显示基板还包括设置于所述衬底基板上的显示数据线；
初始数据线与所述显示数据线同层同材料设置，或者，所述初始数据线设置于所述显示数据线背向所述衬底基板的一侧。
可选的，所述初始数据线的延伸方向与所述显示数据线的延伸方向相同。
可选的，所述像素电路还包括第一晶体管；所述显示基板还包括设置于所述衬底基板上的第二初始化控制线和初始数据线；
所述第一晶体管的栅极与所述驱动晶体管的栅极同层同材料设置，所述第一晶体管的栅极与第二初始化控制线电连接；
所述第一晶体管的第一电极、所述第一晶体管的第二电极、所述驱动晶体管的第一电极和所述驱动晶体管的第二电极同层同材料设置；
所述第一晶体管的第一电极与所述初始数据线电连接，所述第一晶体管的第二电极与发光元件的阳极电连接。
可选的，所述像素电路包括驱动晶体管和存储电容；
所述驱动晶体管的栅极复用为所述存储电容的第一极板；
初始化电压线与所述驱动晶体管的栅极同层同材料设置，或者，所述初始化电压线与所述存储电容的第二极板同层同材料设置。
可选的，所述显示基板还包括设置于所述衬底基板上的栅线；
所述初始化电压线的延伸方向与所述栅线的延伸方向相同。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的显示基板。
可选的，本公开至少一实施例所述的显示装置还包括驱动芯片和设置于所述衬底基板的有效显示区外的初始数据走线、第一电压线和第二电压走线；
所述初始数据走线包括直接与所述驱动芯片电连接的第一初始数据走线部；
所述第一电压线包括直接与所述驱动芯片电连接的第一电压线部，所述第二电压走线包括直接与所述驱动芯片电连接的第一电压走线部；
所述第一初始数据走线部设置于所述第一电压线部与所述第一电压走线部之间。
可选的，所述第一初始数据走线部、所述第一电压线部和所述第一电压走线部都沿第二方向延伸；
所述第二方向为显示数据线延伸的方向。
可选的，本公开至少一实施例所述的显示装置还包括驱动芯片和设置于所述衬底基板的有效显示区外的初始数据走线、初始化电压走线、第一电压线和第二电压走线；
所述初始数据走线包括直接与所述驱动芯片电连接的第一初始数据走线部；
所述初始化电压走线包括直接与所述驱动芯片电连接的第一初始化电压走线部；
所述第一电压线包括直接与所述驱动芯片电连接的第一电压线部，所述第二电压走线包括直接与所述驱动芯片电连接的第一电压走线部；
所述第一初始化电压走线部、所述第一初始数据走线部、所述第一电压线部和所述第一电压走线部沿着靠近有效显示区的方向依次排列。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的电路图；
图4是本公开至少一实施例所述的像素电路的布局示意图；
图5是图4中的有源层的结构图；
图6是图4中的第一栅金属层的结构图；
图7是图4中的第二栅金属层的结构图；
图8是图4中的过孔示意图；
图9是图4中的第一源漏金属层的结构示意图；
图10是本公开至少一实施例所述的像素电路的布局示意图；
图11是图10中的第二栅金属层的结构图；
图12是图10中的过孔示意图；
图13是图10中的第二源漏金属层的结构图；
图14是本公开至少一实施例所述的显示装置的结构图；
图15是本公开至少一实施例所述的显示装置的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极；或者，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极。
如图1所示，本公开至少一实施例所述的像素电路包括驱动电路11、第一发光控制电路12、发光元件EL、第一初始化电路13和第二初始化电路14；
所述驱动电路11用于在其控制端的控制下，产生驱动所述发光元件EL的驱动电流；所述发光元件的阴极与第一电压线V1电连接；
所述第一发光控制电路12分别与发光控制E1、所述驱动电路11和所述发光元件EL的阳极电连接，用于在发光控制线E1提供的发光控制信号的控制下，控制所述驱动电路11与所述发光元件EL的阳极之间连通或断开；
所述第一初始化电路13分别与第一初始化控制线R1、所述驱动电路11 的控制端和初始化电压线I1电连接，用于在所述第一初始化控制线R1提供的第一初始化控制信号的控制下，控制将初始化电压线I1提供的初始化电压写入所述驱动电路11的控制端；
所述第二初始化电路14分别与第二初始化控制线R2、所述发光元件EL的阳极和初始数据线D02电连接，用于在所述第二初始化控制线R2提供的第二初始化控制信号的控制下，控制将所述初始数据线D02提供的初始数据电压至所述发光元件EL的阳极。
本公开至少一实施例所述的像素电路通过第一初始化电路13向所述驱动电路11的控制端写入初始化电压，以对驱动电路11的控制端进行初始化，并通过第二初始化电路14向发光元件EL的阳极写入初始数据电压，以对发光元件EL的阳极进行初始化，通过调节初始数据电压，能够防止在对发光元件EL的阳极进行初始化时，由于发光元件EL发光而产生的漏电起亮以及低灰阶下侧向漏电的情况发生。
可选的，所述第一初始化控制线与所述第二初始化控制线可以为同一初始化控制线；或者，所述第一初始化控制线与所述第二初始化控制线可以不同。
在本公开至少一实施例中，所述像素电路包含于显示基板，所述显示基板包括衬底基板，以及设置于所述衬底基板上的多行栅线、多列显示数据线和多行多列像素电路；
第n行像素电路分别与第n行第一初始化控制线和第n行栅线电连接；n为正整数；第n行第一初始化控制线与第n行第二初始化控制线为同一初始化控制线；
第n行第一初始化控制线上的第n行第一初始化控制信号，与第n-1行栅线上的第n-1行栅极驱动信号相同；
n为正整数。
在本公开至少一实施例中，所述像素电路包含于显示基板，所述显示基板包括衬底基板，以及设置于所述衬底基板上的多行栅线、多列显示数据线和多行多列像素电路；
第n行像素电路分别与第n行第一初始化控制线、第n行第二初始化控 制线和第n行栅线电连接；n为正整数；第n行第一初始化控制线和第n行第二初始化控制线为不同的初始化控制线；
第n行第一初始化控制线上的第n行第一初始化控制信号，与第n-1行栅线上的第n-1行栅极驱动信号相同；
第n行第二初始化控制线上的第n行第二初始化控制信号，与第n行栅线上的第n行栅极驱动信号相同；
n为正整数。
在具体实施时，所述显示基板包括的各行像素电路可以沿着所述显示数据线的延伸方向依次排列，例如，所述各行像素电路可以朝向所述显示基板设置有驱动芯片的侧边的方向，依次排列，但不以此为限。
可选的，所述第一电压线可以为地线或低电压信号线，但不以此为限。
在本公开至少一实施例中，所述发光元件EL可以为OLED(Organic Light-Emitting Diode,有机发光二极管)，但不以此为限。
可选的，所述第二初始化电路包括第一晶体管；
所述第一晶体管的栅极与所述第二初始化控制线电连接，所述第一晶体管的第一电极与所述初始数据线电连接，所述第一晶体管的第二电极与所述发光元件的阳极电连接。
可选的，所述第一初始化电路包括第二晶体管；
所述第二晶体管的栅极与所述第一初始化控制线电连接，所述第二晶体管的第一电极与所述初始化电压线电连接，所述第二晶体管的第二电极与所述驱动电路的控制端电连接。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，所述的像素电路还包括第二发光控制电路21、储能电路22、数据写入电路23和补偿电路24；所述第一发光控制电路12与所述驱动电路11的第二端电连接；
所述第二发光控制电路21分别与所述发光控制线E1、第二电压线V2和所述驱动电路11的第一端电连接，用于在所述发光控制信号的控制下，控制所述驱动电路11的第一端与所述第二电压线V2之间连通或断开；
所述储能电路22与所述驱动电路11的控制端电连接，用于维持所述驱动电路的11控制端的电位；
所述数据写入电路23分别与栅线G0、显示数据线D01和所述驱动电路11的第一端电连接，用于在所述栅极驱动信号的控制下，将所述显示数据线D01上的显示数据电压写入所述驱动电路11的第一端；
所述补偿电路24分别与所述栅线G0、所述驱动电路11的控制端和所述驱动电路11的第二端电连接，用于在所述栅极驱动信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第二端之间连通或断开。
在本公开至少一实施例中，所述第二电压线可以为高电压信号线，但不以此为限。
本公开至少一实施例所述的像素电路还可以包括第二发光控制电路21、储能电路22、数据写入电路23和补偿电路24，第二发光控制电路21控制驱动电路11的第一端与第二电压线V2之间连通或断开，储能电路22维持驱动电路11的控制端的电位，数据写入电路23控制将显示数据电压写入驱动电路11的第一端，补偿电路24控制对驱动电路11包括的驱动晶体管的阈值电压进行补偿。
可选的，所述驱动电路包括驱动晶体管；所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一电极为所述驱动电路的第一端，所述驱动晶体管的第二电极为所述驱动电路的第二端；
所述第一发光控制电路包括第三晶体管；所述第三晶体管的栅极与所述发光控制线电连接，所述第三晶体管的第一电极与所述驱动晶体管的第二电极电连接，所述第三晶体管的第二电极与所述发光元件的阳极电连接；
所述第二发光控制电路包括第四晶体管；所述第四晶体管的栅极与所述发光控制线电连接，所述第四晶体管的第一电极与所述第二电压线电连接，所述第四晶体管的第二电极与所述驱动晶体管的第一极电连接；
所述储能电路包括存储电容；所述存储电容的第一极板与所述驱动晶体管的栅极电连接，所述存储电容的第二极板与所述第二电压线电连接；
所述数据写入电路包括第五晶体管；所述第五晶体管的栅极与所述栅线电连接，所述第五晶体管的第一电极与所述显示数据线电连接，所述第五晶体管的第二电极与所述驱动晶体管的第一电极电连接；
所述补偿电路包括第六晶体管；所述第六晶体管的栅极与所述栅线电连 接，所述第六晶体管的第一电极与所述驱动晶体管的栅极电连接，所述第六晶体管的第二电极与所述驱动晶体管的第二电极电连接。
如图3所示，在图所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述驱动电路11包括驱动晶体管T7；
所述第二初始化电路包括第一晶体管T1；
所述第一晶体管T1的栅极G1与所述第二初始化控制线R2电连接，所述第一晶体管T1的第一电极S1与所述初始数据线D02电连接，所述第一晶体管T1的第二电极D1与O1的阳极电连接；
所述第一初始化电路包括第二晶体管T2；
所述第二晶体管T2的栅极G2与所述第一初始化控制线R1电连接，所述第二晶体管T2的第一电极S2与所述初始化电压线I1电连接，所述第二晶体管T2的第二电极D2与所述驱动电路的控制端电连接；
所述驱动晶体管T7的栅极G7为所述驱动电路11的控制端，所述驱动晶体管T7的第一电极S7为所述驱动电路11的第一端，所述驱动晶体管T7的第二电极D7为所述驱动电路11的第二端；
所述第一发光控制电路包括第三晶体管T3；
所述第三晶体管T3的栅极G3与所述发光控制线E1电连接，所述第三晶体管T3的第一电极S3与所述驱动晶体管T7的第二电极D7电连接，所述第三晶体管T3的第二电极D3与O1的阳极电连接；
所述第二发光控制电路包括第四晶体管T4；
所述第四晶体管T4的栅极G4与所述发光控制线E1电连接，所述第四晶体管T4的第一电极S4与所述第二电压线V2电连接，所述第四晶体管T4的第二电极D4与所述驱动晶体管T7的第一极S7电连接；
所述储能电路包括存储电容C1；所述存储电容C1的第一极板C1a与所述驱动晶体管T7的栅极G7电连接，所述存储电容C1的第二极板C1b与所述第二电压线V2电连接；
所述数据写入电路包括第五晶体管T5；所述第五晶体管T5的栅极G5与所述栅线G0电连接，所述第五晶体管的第一电极与所述显示数据线D01电连接，所述第五晶体管的第二电极与所述驱动晶体管的第一电极电连接；
所述补偿电路包括第六晶体管T6；所述第六晶体管T6的栅极G6与所述栅线G0电连接，所述第六晶体管T6的第一电极S6与所述驱动晶体管T7的栅极G7电连接，所述第六晶体管T6的第二电极D6与所述驱动晶体管T7的第二电极D7电连接。
在图3所示的像素电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在图3所示的像素电路的至少一实施例中，R2上的第二初始化控制信号与G0上的栅极驱动信号相同，但不以此为限。
本公开如图3所示的像素电路的至少一实施例在工作时，显示周期包括依次设置的初始化阶段、数据写入阶段和发光阶段；
在初始化阶段，R1提供低电压信号，E0、G0和R2提供高电压信号，T2打开，T1、T5、T3、T4和T6都关断，I1提供初始化电压信号至T7的栅极，以使得T7关断；
在数据写入阶段，R1提供高电压信号，G0和R2提供低电压信号，E0提供高电压信号，T1、T5和T6都打开，T2、T3和T4都关断，D02提供初始数据电压至O1的阳极，以使得O1不发光；D01提供显示数据电压Vd至S7，G7与D7之间连通，以进行数据电压写入以及对T7的阈值电压的补偿；
在发光阶段，R1、G0和R2都提供高电压信号，E0提供低电压信号，T1、T2、T5和T6都关断，T3和T4打开，T7驱动O1发光。
本公开至少一实施例所述的驱动方法，应用于上述的像素电路，所述驱动方法包括：
所述第一初始化电路在第一初始化控制信号的控制下，控制将初始化电压线提供的初始化电压写入所述驱动电路的控制端；
所述第二初始化电路在第二初始化控制信号的控制下，控制将所述初始数据线提供的初始数据电压至所述发光元件的阳极。
本公开至少一实施例所述的驱动方法通过第一初始化电路向所述驱动电路11的控制端写入初始化电压，以对驱动电路的控制端进行初始化，并通过第二初始化电路向发光元件的阳极写入初始数据电压，以对发光元件的阳极进行初始化，通过调节初始数据电压，能够防止在对发光元件的阳极进行初 始化时，由于发光元件发光而产生的漏电起亮以及低灰阶下侧向漏电的情况发生。
在具体实施时，所述像素电路还可以包括数据写入电路，所述像素电路包含于显示面板(所述显示面板可以包括所述显示基板)；所述驱动方法还可以包括：
数据写入电路在所述栅极驱动信号的控制下，将显示数据线上的显示数据电压写入所述驱动电路的第一端；
所述显示面板中的所有像素电路接入的最低显示数据电压大于预定灰阶电压，所述初始数据电压与第一电压线提供的第一电压相同；或者，
所述最低显示数据电压小于所述预定灰阶电压，所述初始数据电压与所述第一电压不相同，所述初始数据电压与所述第一电压的差值的绝对值小于预定电压值，所述初始数据电压与所述第一电压之间的差值小于所述发光元件的启亮电压，所述预定电压值为正值。
在本公开至少一实施例中，所述预定灰阶电压和所述预定电压值可以根据实际情况选定，例如，所述预定灰阶电压可以为L32对应的灰阶电压，但不以此为限。
本公开至少一实施例根据所述显示面板的像素电路接入的最低显示数据电压来设定初始数据电压；
当所述最低显示数据电压较大时，将初始数据电压设定为第一电压相同，以在对发光元件的阳极进行初始化时，能够保证发光元件不发光，防止由于发光元件发光而引起的漏电；
当所述最低显示数据电压较小时，根据实际情况，将初始数据电压设定为略大于所述第一电压，或将初始数据电压设定为略小于所述第一电压，以改善低灰阶下侧向漏电的情况，并所述初始数据电压与所述第一电压之间的差值小于所述发光元件的启亮电压，以使得在对发光元件的阳极进行初始化时，能够保证发光元件不发光。
在本公开实施例中，显示周期可以包括依次设置的初始化阶段、数据写入阶段和发光阶段；
当R1和R2为不同的初始化控制线时，在初始化阶段，所述第一初始化 电路在第一初始化控制信号的控制下，控制将初始化电压线提供的初始化电压写入所述驱动电路的控制端；在数据写入阶段，所述第二初始化电路在第二初始化控制信号的控制下，控制将所述初始数据线提供的初始数据电压至所述发光元件的阳极，所述数据写入电路在所述栅极驱动信号的控制下，将显示数据线上的显示数据电压写入所述驱动电路的第一端；
当R1和R2为相同的初始化控制线时，在初始化阶段，所述第一初始化电路在第一初始化控制信号的控制下，控制将初始化电压线提供的初始化电压写入所述驱动电路的控制端；所述第二初始化电路在第二初始化控制信号的控制下，控制将所述初始数据线提供的初始数据电压至所述发光元件的阳极；在数据写入阶段，所述数据写入电路在所述栅极驱动信号的控制下，将显示数据线上的显示数据电压写入所述驱动电路的第一端。
本公开至少一实施例所述的显示基板包括衬底基板和设置于所述衬底基板上的上述的像素电路。
可选的，所述像素电路包括驱动晶体管和存储电容；所述显示基板还包括设置于所述衬底基板上的初始数据线；
所述驱动晶体管的栅极复用为所述存储电容的第一极板；
所述初始数据线与所述驱动晶体管的栅极同层同材料设置，或者，所述初始数据线与所述存储电容的第二极板同层同材料设置。
在本公开至少一实施例中，所述显示基板可以包括依次设置于所述衬底基板上的有源层、第一栅金属层、第二栅金属层和第一源漏金属层；
可以对所述第一栅金属层进行构图工艺，以形成栅线和各晶体管的栅极，对第二栅金属层进行构图工艺，以形成存储电容的第二极板；所述初始数据线可以与所述各晶体管的栅极同层同材料设置，或者，所述初始数据线可以与所述存储电容的第二极板同层同材料设置。也即，所述初始数据线可以形成于所述第一栅金属层或所述第二栅金属层。
在具体实施时，当所述初始数据线形成于所述第一栅金属层或所述第二栅金属层时，所述显示基板还包括设置于所述衬底基板上的栅线；
所述初始数据线的延伸方向与所述栅线的延伸方向相同。
在本公开至少一实施例中，所述初始数据线的延伸方向与所述栅线的延 伸方向相同指的可以是：所述初始数据线的延伸方向与所述栅线的延伸方向完全相同，或者，所述初始数据线的延伸方向与所述栅线的延伸方向之间的角度小于预定角度，以使得所述初始数据线的延伸方向与所述栅线的延伸方向大致相同；但不以此为限。
可选的，所述显示基板还包括设置于所述衬底基板上的显示数据线；
初始数据线与所述显示数据线同层同材料设置，或者，所述初始数据线设置于所述显示数据线背向所述衬底基板的一侧。
在本公开至少一实施例中，所述显示基板可以包括依次设置于所述衬底基板上的有源层、第一栅金属层、第二栅金属层和第一源漏金属层，可以对所述第一源漏金属层进行构图工艺，以形成显示数据线和初始数据线，所述初始数据线可以与所述显示数据线同层同材料设置，也即所述初始数据线形成于所述第一源漏金属层；或者，
所述显示基板可以包括依次设置于所述衬底基板上的有源层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层，可以对所述第一源漏金属层进行构图工艺，以形成显示数据线，对所述第二源漏金属层进行构图工艺，以形成初始数据线，也即所述初始数据线设置于所述显示数据线背向所述衬底基板的一侧，所述初始数据线形成于第二源漏金属层。
在具体实施时，当所述初始数据线形成于所述第一源漏金属层或所述第二源漏金属层时，所述初始数据线的延伸方向可以与所述显示数据线的延伸方向相同。
在本公开至少一实施例中，所述初始数据线的延伸方向与所述显示数据线的延伸方向相同指的可以是：所述初始数据线的延伸方向与所述显示数据线的延伸方向完全相同，或者，所述初始数据线的延伸方向与所述显示数据线的延伸方向之间的角度小于预定角度，以使得所述初始数据线的延伸方向与所述显示数据线的延伸方向大致相同；但不以此为限。
可选的，所述像素电路还包括第一晶体管；所述显示基板还包括设置于所述衬底基板上的第二初始化控制线和初始数据线；
所述第一晶体管的栅极与所述驱动晶体管的栅极同层同材料设置，所述第一晶体管的栅极与第二初始化控制线电连接；
所述第一晶体管的第一电极、所述第一晶体管的第二电极、所述驱动晶体管的第一电极和所述驱动晶体管的第二电极同层同材料设置；
所述第一晶体管的第一电极与所述初始数据线电连接，所述第一晶体管的第二电极与发光元件的阳极电连接。
在本公开至少一实施例中，所述第二初始化控制线可以与栅线同层同材料设置，所述第二初始化控制线上的第二初始化控制信号可以与所述栅线上的栅极驱动信号相同。
可选的，所述像素电路可以包括驱动晶体管和存储电容；
所述驱动晶体管的栅极复用为所述存储电容的第一极板；
初始化电压线与所述驱动晶体管的栅极同层同材料设置，或者，所述初始化电压线与所述存储电容的第二极板同层同材料设置。
在具体实施时，所述初始化电压线可以形成于第一栅金属层，或者，所述初始化电压线也可以形成于第二栅金属层，但不以此为限。
可选的，所述显示基板还可以包括设置于所述衬底基板上的栅线；
所述初始化电压线的延伸方向与所述栅线的延伸方向相同。
在本公开至少一实施例中，所述初始化电压线的延伸方向与所述栅线的延伸方向相同指的可以是：所述初始化电压线的延伸方向与所述栅线的延伸方向完全相同，或者，所述初始化电压线的延伸方向与所述栅线的延伸方向之间的角度小于预定角度，以使得所述初始化电压线的延伸方向与所述栅线的延伸方向大致相同；但不以此为限。
图4是本公开至少一实施例所述的像素电路的布局示意图。所述像素电路设置于显示基板的有效显示区内。
在图4中，标号为I11的是初始化电压线包括的第一初始化电压线部分，标号为D021的是初始数据线包括的第一初始数据线部分，标号为I12的是初始化电压线包括的第二初始化电压线部分，标号为D022的是初始数据线包括的第二初始数据线部分；I11、I12、D021和D022可以设置于所述有效显示区内；I11和I12可以都与设置于所述有效显示区外的初始化电压走线电连接，I11和I12相互电连接，D021和D022可以都与设置于所述有效显示区外的初始数据走线电连接，D021和D022相互电连接，但不以此为限。
在本公开至少一实施例中，显示基板包括设置于衬底基板上的多行多列像素电路，每一行像素电路与同一行栅线电连接，同一列像素电路与同一列显示数据线电连接；当所述像素电路采用如图4所示的结构时，初始化电压线包括多个沿第一方向延伸的初始化电压线部分，每一行像素电路与相应的初始化电压线部分电连接，初始数据线包括多个沿第一方向延伸的初始数据线部分，每一行像素电路与相应的初始数据线部分电连接；
同一行像素电路可以与同一所述初始化电压线部分电连接，同一行像素电路可以与同一所述初始数据线部分电连接；
并且，在显示基板的有效显示区外部设有初始数据走线与初始化电压走线，所述初始化电压走线用于提供初始化电压至各所述初始化电压线部分，所述初始数据线用于提供初始数据电压至各初始数据线部分，各所述初始化电压线部分相互电连接，各所述初始数据线部分相互电连接。
在图4中，标号为R1的是第一初始化控制线，标号为G0的为栅线，标号为C1b的为像素电路中的存储电容的第二极板，标号为E1的为发光控制线，标号为D01的为显示数据线，标示为R2的为第二初始化控制线；
提供至所述第二初始化控制线R2的第二初始化控制信号与提供至G0的栅极驱动信号相同。
在图4对应的至少一实施例中，在衬底基板上，沿着远离衬底基板的方向依次设置了有源层、第一栅金属层、第二栅金属层和第一源漏金属层；
对所述第一栅金属层进行构图工艺，以形成栅线G0、第一初始化控制线R1、第二初始化控制线R2、发光控制线E1和像素电路中的各晶体管的栅极；
对所述第二栅金属层进行构图工艺，以形成初始数据线、初始化电压线和像素电路中的存储电容的第二极板；
在图4所示的至少一实施例中，初始数据线和初始化电压线形成于第二栅金属层，并初始数据线的延伸方向与栅线G0的延伸方向相同，初始化电压线的延伸方向与栅线G0的延伸方向相同。
在图4所示的至少一实施例中，G0的延伸方向可以为第一方向，所述第一方向例如可以为水平方向，D01的延伸方向可以为第二方向，所述第二方向例如可以为竖直方向，但不以此为限。
在本公开至少一实施例中，栅线的延伸方向可以为第一方向，显示数据线的延伸方向可以为第二方向，第一方向和第二方向相交；但不以此为限。
如图5所示，图4中的有源层的图形包括第一晶体管的第一电极S1、第一晶体管的第二电极D1、第二晶体管的第一电极S2、第二晶体管的第二电极D2、第四晶体管的第一电极S4、第五晶体管的第一电极S5、第五晶体管的第二电极D5和第六晶体管的第二电极D6；
在图4、图5对应的至少一实施例中，所述第二晶体管的第二电极D2复用为所述第六晶体管的第一电极，所述第五晶体管的第二电极D5复用为所述第四晶体管的第二电极，所述第五晶体管的第二电极D5复用为所述驱动晶体管的第一极；所述第六晶体管的第二电极D6复用为所述驱动晶体管的第二电极。
如图6所示，T2为双栅晶体管，标号为G21的为第二晶体管的栅极包括的第一栅极图形，标号为G22的为第二晶体管的栅极包括的第二栅极图形；
标号为G5的为第五晶体管的栅极；
T6为双栅晶体管，标号为G61的为第六晶体管的栅极包括的第三栅极图形，标号为G62的为第六晶体管的栅极包括的第四栅极图形；
标号为G3的为第三晶体管的栅极，标号为G4的为第四晶体管的栅极，标号为G1的为第一晶体管的栅极；
标号为G7的为驱动晶体管的栅极，G7复用为像素电路中的存储电容的第一极板。
如图7所示，标号为C1b的为所述存储电容的第二极板，标号H0的为C1b上设置的连接孔，D2通过所述连接孔H0与G2电连接。
在依次设置了有源层、第一栅金属层和第二栅金属层后，可以设置层间介质层，在设置层间介质层后可以制作过孔。如图8所示，标号为H1的为第一过孔，标号为H2的为第二过孔，标号为H3的为第三过孔，标号为H4的为第四过孔，标号为H5的为第五过孔，标号为H6的为第六过孔，标号为H7的为第七过孔，标号为H8的为第八过孔，标号为H9的为第九过孔，标号为H10的为第十过孔，标号为H11的为第十一过孔，标号为H12的为第十二过孔，标号为H13的为第十三过孔，标号为H14的为第十四过孔，标号为 H15的为第十五过孔。
如图9所示，所述第一源漏金属层的图形包括显示数据线D01、第二电压线、第一导电连接部L1、第二导电连接部L2、第三导电连接部L3、第四导电连接部L4、第五导电连接部L5和第六导电连接部L6。在图8中，标号为V21的为所述第二电压线包括的第一电压线部分。
当所述像素电路采用如图4所示的结构时，第二电压线包括多个沿第二方向延伸的电压线部分，每一列像素电路与相应的电压线部分电连接；在显示基板的有效显示区外部设有第二电压走线，所述第二电压走线用于提供第二电压信号至所述第二电压线包括的各所述电压线部分，所述第二电压线包括的各所述电压线部分相互电连接。
如图4-图9所示，S2通过第四过孔H4与第一导电连接部L1电连接，L1通过第一过孔H1与I11电连接，以使得S2与I11电连接，也即使得S2与初始化电压线电连接；
S1通过H14与L6电连接，L6通过H11与D022电连接，以使得S1与D022电连接，也即使得S1与初始数据线电连接；
D2通过H7与L3电连接，L3通过H0与G7电连接；
S5通过H3与D01电连接；
S4通过H8与V21电连接；
D1通过H9与L4电连接，L4通过过孔与阳极层电连接。
在制作所述显示基板时，在制作完所述第一源漏金属层之后，依次制作第一平坦层和阳极层，所述阳极层包括多个相互独立的阳极；L4可以通过贯穿所述第一平坦层的过孔与所述阳极电连接；在制作完所述阳极层之后还可以依次制作PDL层(pixel definition layer，像素定义层)、有机发光功能层和阴极层。
在本公开至少一实施例中，所述阴极层可以覆盖整个有效显示区，并所述阴极层可以在所述显示基板的非显示区通过阳极层与第一电压线搭接，以使得发光元件的阴极与与所述第一电压线电连接，但不以此为限。可选的，所述第一电压线可以围绕着所述有效显示区设置，但不以此为限。
在本公开至少一实施例中，在有源层与第一栅金属层之间可以设有第一 栅绝缘层，在第一栅金属层与第二栅金属层之间可以设有第二栅绝缘层，在第二栅金属层与所述第一源漏金属层之间可以设有层间介质层，但不以此为限。
在图4所示的至少一实施例中，初始数据线和初始化电压线都形成于第二栅金属层，但不以此为限。
当显示基板包括如图4所示的像素电路的至少一实施例时，初始数据线和初始化电压线都沿第一方向延伸，例如所述第一方向可以为水平方向，则初始数据线包括的多行初始数据线部分也沿第一方向延伸，初始化电压线包括的多行初始化电压线部分也沿第一方向延伸，在所述显示基板的有效显示区外，可以设有提供初始数据电压的初始数据走线和提供初始化电压的初始化电压走线，所述初始数据走线和所述初始化电压走线可以设置于所述显示基板的第一侧边和/或第二侧边(第一侧边可以为左侧边，第二侧边可以为右侧边)，所述初始数据走线包括的至少部分走线和所述初始化电压走线包括的至少部分走线可以沿第二方向延伸(所述第二方向例如可以为竖直方向)，各行初始数据线部分可以沿第一方向延伸，直至与所述初始数据走线电连接，各行初始化电压线部分可以沿第一方向延伸，直至与所述初始化电压走线电连接。
并由于在图4所示的至少一实施例中，第二电压线沿第二方向延伸，第二电压线包括的多个电压线部分沿第二方向延伸，因此用于提供第二电压信号的第二电压走线可以设置于所述显示基板的有效显示区的靠近驱动芯片的侧边，例如，所述第二电压走线可以设置于所述显示基板的下侧边，但不以此为限。
可选的，所述第二电压走线可以包括沿第一方向延伸的第二电压走线部和沿第二方向延伸的第一电压走线部，所述第二电压走线部用于电连接所述第二电压线包括的多个电压线部分(例如，当所述第二电压走线设置于所述显示基板的下侧边时，第二电压线包括的各电压线部分可以沿第二方向向下延伸，以与所述第二电压走线部电连接)，第一电压走线部的第一端与所述第二电压走线部电连接，第一电压走线部的第二端直接与驱动芯片电连接，以接收驱动芯片提供的第二电压信号。
在图4所示的至少一实施例中，R1和R2为不同的初始化控制线。在实际操作时，R1和R2也可以为相同的初始化控制线。
如图10所示的像素电路的至少一实施例与图4所示的像素电路的至少一实施例不同的是：在第一源漏金属层远离衬底基板的一侧还设有第二源漏金属层，初始数据线沿第二方向延伸，也即，初始数据线的延伸方向与显示数据线的延伸方向相同，对所述第二源漏金属层进行构图工艺，以形成所述初始数据线包括的各初始数据线部分。在图10中，标号为D021的为初始数据线包括的第一初始数据线部分。
图10中的有源层的结构图如图5所示，图10中的第一栅金属层的结构图如图6所示，图10中的第二栅金属层的结构图如图11所示，图10中的过孔示意图如图12所示，图10中的第一源漏金属层的结构图如图9所示，图10中的第二源漏金属层的结构图如图13所示。
如图9、图10-图13所示，L6通过H11与D021电连接，如图10所示，D021的延伸方向与D01的延伸方向相同。
图10中的其他各部件的连接关系与图4中的各部件的连接关系相同。
当显示基板包括多行多列如图10所示的像素电路的至少一实施例时，同一列像素电路可以与同一所述初始数据线部分电连接，同一行像素电路可以与同一所述初始化电压线部分电连接。
在图10所示的至少一实施例中，R1和R2为不同的初始化控制线。在实际操作时，R1和R2也可以为相同的初始化控制线。
本公开实施例所述的显示装置包括上述的显示基板。
在具体实施时，本公开至少一实施例所述的显示装置还可以包括驱动芯片和设置于所述衬底基板的有效显示区外的初始数据走线、第一电压线和第二电压走线；
所述初始数据走线包括直接与所述驱动芯片电连接的第一初始数据走线部；
所述第一电压线包括直接与所述驱动芯片电连接的第一电压线部，所述第二电压走线包括直接与所述驱动芯片电连接的第一电压走线部；
所述第一初始数据走线部设置于所述第一电压线部与所述第一电压走线 部之间。
在本公开至少一实施例中，所述第一初始数据走线部设置于第一电压线部与第一电压走线部之间，第一电压线部用于提供第一电压信号，第一电压走线部用于提供第二电压信号，所述第一电压信号和所述第二电压信号都为直流电压信号，这样就不会对第一初始数据走线部上的初始数据电压造成干扰。
可选的，所述驱动芯片可以设置于COF(覆晶薄膜)或直接绑定在衬底基板上，COF可以贴设于所述显示基板的侧边，但不以此为限。所述驱动芯片可以用于提供第一电压信号、第二电压信号、初始化电压和初始数据电压。
在本公开至少一实施例中，所述衬底基板可以为柔性基板或刚性基板，所述驱动芯片可以采用COP(Chip On Pi，COP是芯片被绑定在柔性基板上的技术)技术或COG(Chip On Glass，COG是芯片被直接绑定在玻璃表面的技术)技术绑定在所述衬底基板上。
可选的，所述第一初始数据走线部、所述第一电压线部和所述第一电压走线部都沿第二方向延伸，但不以此为限；
所述第二方向为显示数据线延伸的方向。
在本公开至少一实施例中，所述的显示装置还可以包括驱动芯片和设置于所述衬底基板的有效显示区外的初始数据走线、初始化电压走线、第一电压线和第二电压走线；
所述初始数据走线包括直接与所述驱动芯片电连接的第一初始数据走线部；
所述初始化电压走线包括直接与所述驱动芯片电连接的第一初始化电压走线部；
所述第一电压线包括直接与所述驱动芯片电连接的第一电压线部，所述第二电压走线包括直接与所述驱动芯片电连接的第一电压走线部；
所述第一初始化电压走线部、所述第一初始数据走线部、所述第一电压线部和所述第一电压走线部沿着靠近有效显示区的方向依次排列。
在具体实施时，如空间紧张，所述第一初始数据走线部也可以设置于第一初始化电压走线部与所述第一电压线部之间。
如图14所示，当初始化电压线的延伸方向和初始数据线的延伸方向都与栅线的延伸方向相同(所述栅线的延伸方向为第一方向)时，本公开至少一实施例所述的显示基板还包括设置于有效显示区A0外部的初始数据走线、初始化电压走线、栅极驱动电路140、第一电压线和第二电压走线；
所述第二电压走线包括沿第一方向延伸的第二电压走线部L22和沿第二方向延伸的第一电压走线部L21，所述第二电压走线部L22用于电连接所述第二电压线包括的多个电压线部分(当所述第二电压走线设置于所述显示基板的下侧边时，第二电压线包括的各电压线部分可以沿第二方向向下延伸，以与所述第二电压走线部电连接)，第一电压走线部L21的第一端与所述第二电压走线部L22电连接，第一电压走线部L21的第二端直接与驱动芯片141电连接，以接收驱动芯片141提供的第二电压信号；
所述初始数据走线包括沿第二方向延伸的第一初始数据走线部L31、设置于所述有效显示区A0的左侧边的第二初始数据走线部L32，以及，用于电连接L31和L32的第三初始数据走线部L33；L32可以沿第二方向延伸；所述初始数据线包括的各初始数据线部分都直接与所述第二初始数据走线部L32电连接；L31、L32和L33为一体结构；L31直接与驱动芯片141电连接，以接收所述驱动芯片141提供的第二电压信号；
所述初始化电压走线包括沿第二方向延伸的第一初始化电压走线部L41、以及，设置于所述有效显示区A0的左侧边的第二初始化电压走线部L42，L41和L42直接电连接；L41和L42为一体结构；L41与所述驱动芯片141直接电连接，所述驱动芯片141用于向L41提供初始化电压；L42也沿第二方向延伸；
所述栅极驱动电路140设置于L42远离所述有效显示区A0的一侧；所述栅极驱动电路140可以与多行栅线电连接；
所述第一电压线包括直接与所述驱动芯片141电连接的第一电压线部L51、设置于所述有效显示区A0的左侧边的第二电压线部L52，以及，用于电连接L51和L52的第三初始数据走线部L53；L51和L52沿第二方向延伸，L53沿第一方向延伸；驱动芯片141向L51提供第一电压信号；
在实际操作时，所述第一电压线可以设置于所述显示基板的不设有所述 驱动芯片的各个侧边，并所述第一电压线与所述驱动芯片电连接，用于接收所述驱动芯片提供的第一电压信号，但不以此为限；
并且，在有效显示区的右侧边也可以设置有初始数据走线、初始化电压走线和第二电压走线，但不以此为限。
在本公开至少一实施例中，初始化电压走线可以与初始化电压线同层同材料设置，初始数据走线可以与初始数据线同层同材料设置，第二电压走线可以与第二电压线同层同材料设置，但不以此为限。
在本公开至少一实施例中，第一电压线可以由所述第一源漏金属层或所述第二源漏金属层制作，但不以此为限。
在图14所示的至少一实施例中，L42和L32可以同层同材料设置，L42通过跳线与有效显示区中的初始化电压线电连接，以避免L42与有效显示区中的初始化电压线之间的连接线与L32搭接，避免产生短路。
如图15所示，当初始化电压线的延伸方向与栅线的延伸方向相同，初始数据线的延伸方向与显示数据线的延伸方向相同(所述栅线的延伸方向为第一方向，所述显示数据线的延伸方向为第二方向)时，本公开至少一实施例所述的显示基板还包括设置于有效显示区A0外部的初始数据走线、初始化电压走线、栅极驱动电路140、第一电压线和第二电压走线；
所述初始数据走线设置于所述有效显示区A0的下方(也即，初始数据走线设置于显示基板的下侧边)；
所述初始数据走线包括沿第二方向延伸的第一初始数据走线部L31、沿第一方向延伸的第二初始数据走线部L32，以及，用于电连接L31和L32的第三初始数据走线部L33；L33沿第二方向延伸；L31直接与驱动芯片141电连接，以接收所述驱动芯片141提供的第二电压信号；
所述第二电压走线设置于有效显示区A0的下方(也即，第二电压走线设置于显示基板的下侧边)，所述第二电压走线包括沿第一方向延伸的第二电压走线部L22和沿第二方向延伸的第一电压走线部L21，所述第二电压走线部L22用于电连接所述第二电压线包括的多个电压线部分，第一电压走线部L21的第一端与所述第二电压走线部L22电连接，第一电压走线部L21的第二端直接与驱动芯片141电连接，以接收驱动芯片141提供的第二电压信号； 所述第二电压走线部L22可以通过跳线与有效显示区A0中的第二电压线包括的电压线部分电连接，以避免与L32搭接而短路；
所述初始化电压走线包括沿第二方向延伸的第一初始化电压走线部L41、设置于所述有效显示区A0的左侧边的第二初始化电压走线部L42，以及，用于电连接L41和L42的沿第一方向延伸的第三初始化电压走线部L43；L41与所述驱动芯片141直接电连接，所述驱动芯片141用于向L41提供初始化电压；L42也沿第二方向延伸；
所述栅极驱动电路140设置于L41远离所述有效显示区A0的一侧；所述栅极驱动电路140可以与多行栅线电连接；
所述第一电压线包括直接与所述驱动芯片141电连接的第一电压线部L51、设置于所述有效显示区A0的左侧边的第二电压线部L52，以及，用于电连接L51和L52的第三初始数据走线部L53；L51和L52沿第二方向延伸，L53沿第一方向延伸；驱动芯片141向L51提供第一电压信号；
在实际操作时，所述第一电压线可以设置于所述显示基板的不设有所述驱动芯片的各个侧边，并所述第一电压线与所述驱动芯片电连接，用于接收所述驱动芯片提供的第一电压信号，但不以此为限；
并且，在有效显示区的右侧边也可以设置有初始化电压走线和第二电压走线，但不以此为限。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示触控功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (19)

  1. 一种像素电路，包括驱动电路、第一发光控制电路、发光元件、第一初始化电路和第二初始化电路；
    所述驱动电路用于在其控制端的控制下，产生驱动所述发光元件的驱动电流；所述发光元件的阴极与第一电压线电连接；
    所述第一发光控制电路分别与发光控制线、所述驱动电路和所述发光元件的阳极电连接，用于在发光控制线提供的发光控制信号的控制下，控制所述驱动电路与所述发光元件的阳极之间连通或断开；
    所述第一初始化电路分别与第一初始化控制线、所述驱动电路的控制端和初始化电压线电连接，用于在所述第一初始化控制线提供的第一初始化控制信号的控制下，控制将初始化电压线提供的初始化电压写入所述驱动电路的控制端；
    所述第二初始化电路分别与第二初始化控制线、所述发光元件的阳极和初始数据线电连接，用于在所述第二初始化控制线提供的第二初始化控制信号的控制下，控制将所述初始数据线提供的初始数据电压至所述发光元件的阳极。
  2. 如权利要求1所述的像素电路，其中，所述第二初始化电路包括第一晶体管；
    所述第一晶体管的栅极与所述第二初始化控制线电连接，所述第一晶体管的第一电极与所述初始数据线电连接，所述第一晶体管的第二电极与所述发光元件的阳极电连接。
  3. 如权利要求1所述的像素电路，其中，所述第一初始化电路包括第二晶体管；
    所述第二晶体管的栅极与所述第一初始化控制线电连接，所述第二晶体管的第一电极与所述初始化电压线电连接，所述第二晶体管的第二电极与所述驱动电路的控制端电连接。
  4. 如权利要求1至3中任一权利要求所述的像素电路，其中，还包括第二发光控制电路、储能电路、数据写入电路和补偿电路；所述第一发光控制 电路与所述驱动电路的第二端电连接；
    所述第二发光控制电路分别与所述发光控制线、第二电压线和所述驱动电路的第一端电连接，用于在所述发光控制信号的控制下，控制所述驱动电路的第一端与所述第二电压线之间连通或断开；
    所述储能电路与所述驱动电路的控制端电连接，用于维持所述驱动电路的控制端的电位；
    所述数据写入电路分别与栅线、显示数据线和所述驱动电路的第一端电连接，用于在所述栅极驱动信号的控制下，将所述显示数据线上的显示数据电压写入所述驱动电路的第一端；
    所述补偿电路分别与所述栅线、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述栅极驱动信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通或断开。
  5. 如权利要求4所述的像素电路，其中，所述驱动电路包括驱动晶体管；所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一电极为所述驱动电路的第一端，所述驱动晶体管的第二电极为所述驱动电路的第二端；
    所述第一发光控制电路包括第三晶体管；所述第三晶体管的栅极与所述发光控制线电连接，所述第三晶体管的第一电极与所述驱动晶体管的第二电极电连接，所述第三晶体管的第二电极与所述发光元件的阳极电连接；
    所述第二发光控制电路包括第四晶体管；所述第四晶体管的栅极与所述发光控制线电连接，所述第四晶体管的第一电极与所述第二电压线电连接，所述第四晶体管的第二电极与所述驱动晶体管的第一极电连接；
    所述储能电路包括存储电容；所述存储电容的第一极板与所述驱动晶体管的栅极电连接，所述存储电容的第二极板与所述第二电压线电连接；
    所述数据写入电路包括第五晶体管；所述第五晶体管的栅极与所述栅线电连接，所述第五晶体管的第一电极与所述显示数据线电连接，所述第五晶体管的第二电极与所述驱动晶体管的第一电极电连接；
    所述补偿电路包括第六晶体管；所述第六晶体管的栅极与所述栅线电连接，所述第六晶体管的第一电极与所述驱动晶体管的栅极电连接，所述第六 晶体管的第二电极与所述驱动晶体管的第二电极电连接。
  6. 一种驱动方法，应用于如权利要求1至5中任一权利要求所述的像素电路，所述驱动方法包括：
    所述第一初始化电路在第一初始化控制信号的控制下，控制将初始化电压线提供的初始化电压写入所述驱动电路的控制端；所述第二初始化电路在第二初始化控制信号的控制下，控制将所述初始数据线提供的初始数据电压至所述发光元件的阳极。
  7. 如权利要求6所述的驱动方法，其中，所述像素电路还包括数据写入电路，所述像素电路包含于显示面板；所述驱动方法还包括：所述数据写入电路在栅线上的栅极驱动信号的控制下，将显示数据线上的显示数据电压写入驱动电路；
    所述显示面板中的所有像素电路接入的最低显示数据电压大于预定灰阶电压，所述初始数据电压与第一电压线提供的第一电压相同；或者，
    所述最低显示数据电压小于所述预定灰阶电压，所述初始数据电压与所述第一电压不相同，所述初始数据电压与所述第一电压的差值的绝对值小于预定电压值，所述初始数据电压与所述第一电压之间的差值小于所述发光元件的启亮电压，所述预定电压值为正值。
  8. 一种显示基板，包括衬底基板和设置于所述衬底基板上的如权利要求1至5中任一权利要求所述的像素电路。
  9. 如权利要求8所述的显示基板，其中，所述像素电路包括驱动晶体管和存储电容；所述显示基板还包括设置于所述衬底基板上的初始数据线；
    所述驱动晶体管的栅极复用为所述存储电容的第一极板；
    所述初始数据线与所述驱动晶体管的栅极同层同材料设置，或者，所述初始数据线与所述存储电容的第二极板同层同材料设置。
  10. 如权利要求9所述的显示基板，其中，所述显示基板还包括设置于所述衬底基板上的栅线；
    所述初始数据线的延伸方向与所述栅线的延伸方向相同。
  11. 如权利要求8所述的显示基板，其中，所述显示基板还包括设置于所述衬底基板上的显示数据线；
    初始数据线与所述显示数据线同层同材料设置，或者，所述初始数据线设置于所述显示数据线背向所述衬底基板的一侧。
  12. 如权利要求11所述的显示基板，其中，所述初始数据线的延伸方向与所述显示数据线的延伸方向相同。
  13. 如权利要求11所述的显示基板，其中，所述像素电路还包括第一晶体管；所述显示基板还包括设置于所述衬底基板上的第二初始化控制线和初始数据线；
    所述第一晶体管的栅极与所述驱动晶体管的栅极同层同材料设置，所述第一晶体管的栅极与第二初始化控制线电连接；
    所述第一晶体管的第一电极、所述第一晶体管的第二电极、所述驱动晶体管的第一电极和所述驱动晶体管的第二电极同层同材料设置；
    所述第一晶体管的第一电极与所述初始数据线电连接，所述第一晶体管的第二电极与发光元件的阳极电连接。
  14. 如权利要求8至13中任一权利要求所述的显示基板，其中，所述像素电路包括驱动晶体管和存储电容；
    所述驱动晶体管的栅极复用为所述存储电容的第一极板；
    初始化电压线与所述驱动晶体管的栅极同层同材料设置，或者，所述初始化电压线与所述存储电容的第二极板同层同材料设置。
  15. 如权利要求14所述的显示基板，其中，所述显示基板还包括设置于所述衬底基板上的栅线；
    所述初始化电压线的延伸方向与所述栅线的延伸方向相同。
  16. 一种显示装置，包括如权利要求8至15中任一权利要求所述的显示基板。
  17. 如权利要求16所述的显示装置，其中，还包括驱动芯片和设置于所述衬底基板的有效显示区外的初始数据走线、第一电压线和第二电压走线；
    所述初始数据走线包括直接与所述驱动芯片电连接的第一初始数据走线部；
    所述第一电压线包括直接与所述驱动芯片电连接的第一电压线部，所述第二电压走线包括直接与所述驱动芯片电连接的第一电压走线部；
    所述第一初始数据走线部设置于所述第一电压线部与所述第一电压走线部之间。
  18. 如权利要求17所述的显示装置，其中，所述第一初始数据走线部、所述第一电压线部和所述第一电压走线部都沿第二方向延伸；
    所述第二方向为显示数据线延伸的方向。
  19. 如权利要求16所述的显示装置，其中，还包括驱动芯片和设置于所述衬底基板的有效显示区外的初始数据走线、初始化电压走线、第一电压线和第二电压走线；
    所述初始数据走线包括直接与所述驱动芯片电连接的第一初始数据走线部；
    所述初始化电压走线包括直接与所述驱动芯片电连接的第一初始化电压走线部；
    所述第一电压线包括直接与所述驱动芯片电连接的第一电压线部，所述第二电压走线包括直接与所述驱动芯片电连接的第一电压走线部；
    所述第一初始化电压走线部、所述第一初始数据走线部、所述第一电压线部和所述第一电压走线部沿着靠近有效显示区的方向依次排列。
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