WO2021227623A9 - 像素单元、显示基板及显示装置 - Google Patents

像素单元、显示基板及显示装置 Download PDF

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WO2021227623A9
WO2021227623A9 PCT/CN2021/079704 CN2021079704W WO2021227623A9 WO 2021227623 A9 WO2021227623 A9 WO 2021227623A9 CN 2021079704 W CN2021079704 W CN 2021079704W WO 2021227623 A9 WO2021227623 A9 WO 2021227623A9
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Prior art keywords
electrode
pixel unit
base substrate
transistor
source
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PCT/CN2021/079704
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English (en)
French (fr)
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WO2021227623A1 (zh
Inventor
徐攀
林奕呈
王玲
王国英
张星
韩影
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京东方科技集团股份有限公司
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Publication of WO2021227623A1 publication Critical patent/WO2021227623A1/zh
Publication of WO2021227623A9 publication Critical patent/WO2021227623A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel unit, a display substrate and a display device.
  • OLED display substrates are favored for their advantages of self-luminescence, low power consumption, fast response and low cost.
  • Embodiments of the present disclosure provide a pixel unit, a display substrate, and a display device, and the technical solutions are as follows:
  • a pixel unit in one aspect, includes: a thin film transistor on a base substrate and a storage capacitor; the thin film transistor includes: an active layer, a gate and a source and drain; the storage capacitor includes : a first electrode, a second electrode and a third electrode sequentially stacked along a direction perpendicular to the base substrate;
  • the first electrode is located on the side of the active layer close to the base substrate;
  • the second electrode and the active layer or the gate are located in the same layer;
  • the third electrode and the source and drain electrodes are located in the same layer, and the third electrode is electrically connected to the first electrode.
  • the orthographic projections of any two electrodes of the first electrode, the second electrode and the third electrode on the base substrate at least partially overlap.
  • the thin film transistor includes: a driving transistor, and the source and drain electrodes include a source electrode and a drain electrode;
  • the second electrode is electrically connected to the first electrode of the driving transistor, and the third electrode and the first electrode that are electrically connected are electrically connected to the gate of the driving transistor; wherein the first electrode of the driving transistor is electrically connected.
  • a pole is one of the source and drain of the driving transistor.
  • the orthographic projection of the first electrode on the base substrate does not overlap with the orthographic projection of the second electrode of the driving transistor on the base substrate; wherein, the first electrode of the driving transistor The diode is the other of the source and drain of the drive transistor.
  • the thin film transistor includes: a driving transistor, and the source and drain electrodes include a source electrode and a drain electrode;
  • the second electrode is electrically connected to the gate of the driving transistor, and the third electrode and the first electrode that are electrically connected are electrically connected to the first electrode of the driving transistor; wherein the first electrode of the driving transistor is electrically connected.
  • a pole is one of the source and drain of the driving transistor.
  • the orthographic projection of the first electrode on the base substrate overlaps with the orthographic projection of the second electrode of the driving transistor on the base substrate; wherein, the second electrode of the driving transistor is the other of the source and drain of the driving transistor.
  • the second pole of the driving transistor is used to electrically connect to the driving power supply terminal.
  • the third electrode is electrically connected to the first electrode through a via hole.
  • the pixel unit further includes: a light-emitting element, the light-emitting element is an organic light-emitting diode; wherein, the light-emitting element is electrically connected to the first electrode of the driving transistor.
  • the thin film transistor further includes: a switch transistor;
  • the orthographic projection of any one of the first electrode, the second electrode and the third electrode on the base substrate, and the active layer of the switching transistor on the base substrate The orthographic projection of the gate of the switching transistor on the base substrate, and the orthographic projection of the source and drain of the switching transistor on the base substrate do not overlap.
  • the thin film transistor further includes: a compensation transistor;
  • the orthographic projection of any one of the first electrode, the second electrode and the third electrode on the base substrate, and the active layer of the compensation transistor on the base substrate The orthographic projection of the gate of the compensation transistor on the base substrate, and the orthographic projection of the source and drain of the compensation transistor on the base substrate do not overlap.
  • the storage capacitor further includes: an insulating layer located between every two adjacent electrodes.
  • the pixel unit is a top emission type pixel unit, or a bottom emission type pixel unit.
  • the second electrode and the active layer are located in the same layer and have the same material; or, the second electrode and the gate are located in the same layer and have the same material.
  • the third electrode is made of the same material as the source and drain electrodes.
  • the pixel unit further includes: a passivation layer, a flat layer, an anode and a pixel definition layer that are located on a side of the third electrode away from the base substrate and stacked in sequence, and the anode is connected to the source Drain is electrically connected.
  • the active layer, the gate and the source and drain are sequentially stacked along a direction away from the base substrate.
  • a display substrate comprising: a base substrate, and a plurality of pixel units located on the base substrate and arranged in an array;
  • At least one of the pixel units is the pixel unit described in the above aspect.
  • the display substrate further includes: a wire; wherein a part of the wire is the first electrode included in the pixel unit.
  • a display device comprising: a driving circuit, and the display substrate according to the above aspect;
  • the driving circuit is connected to the pixel unit in the display substrate, and the driving circuit is used to provide a driving signal for the thin film transistor included in the pixel unit.
  • FIG. 1 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the composition of a storage capacitor provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another pixel unit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another storage capacitor provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another pixel unit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another storage capacitor provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another pixel unit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure.
  • the pixel unit may include: a thin film transistor M1 on a base substrate 00 and a storage capacitor Cst.
  • the thin film transistor M1 may include: an active (active, ACT) layer 01, a gate (gate, G) 02 and a source and drain (source & drain, SD) 03, and the source and drain 03 and the active Layer 01 can be connected.
  • the active layer 01 , the gate electrode 02 , and the source and drain electrodes 03 may be sequentially stacked and arranged in a direction away from the base substrate 00 , and this structure may also be referred to as a bottom gate structure.
  • the active layer 01 , the gate 02 and the source and drain 03 can also be arranged in other ways, for example, the active layer 01 , the source and the drain 03 and the gate 02 are arranged away from the base substrate
  • the 00 directions are arranged in layers in sequence, and the structure may also be called a top gate structure, which is not limited in this embodiment of the present disclosure.
  • the storage capacitor Cst may include: a first electrode 04 , a second electrode 05 and a third electrode 06 stacked in sequence along a direction perpendicular to the base substrate 00 .
  • the first electrode 04 may be located on the side of the active layer 01 close to the base substrate 00 . That is, the first electrode 04 may be located between the active layer 01 and the base substrate 00 . Also, in order to form the storage capacitor Cst, the first electrode 04 may be made of a conductive material capable of conducting electricity. For example, the first electrode may be made of a metallic material. Correspondingly, the first electrode 04 may also be referred to as a metal layer.
  • the second electrode 05 may be located in the same layer as the active layer 01 or the gate 02 .
  • the second electrode 05 is shown in the same layer as the active layer 01 .
  • the third electrode 06 may be located in the same layer as the source and drain electrodes 03 , and the third electrode 06 may be electrically connected to the first electrode 04 .
  • the orthographic projection of one electrode on the base substrate 00 overlaps with the orthographic projection of the other electrode on the base substrate 00 . That is, referring to FIG. 1 , the orthographic projection of the second electrode 05 on the base substrate 00 may overlap with the orthographic projection of the first electrode 04 on the base substrate 00 , and the orthographic projection of the second electrode 05 on the base substrate 00 may overlap. The projection may also overlap with the orthographic projection of the third electrode 06 on the base substrate 00 , and the orthographic projection of the first electrode 04 on the base substrate 00 and the orthographic projection of the third electrode 06 on the base substrate 00 exist overlapping part.
  • the second electrode 05 may be located between the first electrode 04 and the third electrode 06 .
  • the second electrode 05 and the third electrode 06 can form a capacitor C1
  • the second electrode 05 and the first electrode 04 can form another capacitor C2
  • the storage capacitor Cst can be composed of the two capacitors.
  • C1 and C2 are formed in parallel.
  • capacitor value the capacitance value of the capacitor C1
  • capacitance value of the capacitor C2 the capacitance value of the capacitor C2
  • the storage capacitor provided by the embodiment of the present disclosure has a larger capacitance value.
  • more layers of electrodes stacked in sequence may also be provided (for example, two or more layers of first electrodes 04 may be provided).
  • the embodiments of the present disclosure provide a pixel unit.
  • the storage capacitor includes a first electrode, a second electrode and a third electrode that are stacked in sequence. Since every two adjacent layers of electrodes can form a capacitor, the storage capacitor can be composed of two capacitors connected in parallel. Correspondingly, the capacitance of the storage capacitor is the sum of the capacitances of the two capacitors connected in parallel.
  • the storage capacitor in the pixel unit described in the embodiments of the present disclosure has a larger capacitance value, and further, the light-emitting element included in the pixel unit has higher luminous accuracy, and the display substrate including the pixel unit has a better display effect.
  • the same material can be used to form the second electrode 05 and the active layer 01 on the same layer through a single patterning process, or, the same material can be used to form the second electrode 05 and the active layer 01 on the same layer through a single patterning process.
  • the patterning process forms the second electrode 05 and the gate 02 on the same layer.
  • the same material can also be used to form the third electrode 06 and the source and drain electrodes 03 on the same layer through a patterning process, and the source and drain electrodes 03 can include a source electrode and a drain electrode.
  • the ACT pattern may include the active layer 01 and the second electrode 05 .
  • the GT pattern may include a gate electrode 02 and a second electrode 05 .
  • the source-drain SD pattern may include the source-drain 03 and the third electrode 06 .
  • the thin film transistor M1 may further include a gate insulator (GI) layer on the side of the gate electrode 02 close to the base substrate 00 . That is, before forming the GT pattern, a GI pattern may also be formed first. In this way, the problem of signal interference between the gate electrode and the active layer can be avoided.
  • GI gate insulator
  • FIG. 3 shows a schematic structural diagram of another pixel unit provided by an embodiment of the present disclosure. It can be seen with reference to FIG. 3 that the second electrode 05 and the active layer 01 may be of an integrated structure, and the third electrode 06 and the source and drain electrodes 03 may be of an integrated structure.
  • the first electrode 04 is a metal layer newly added on the base substrate 00 by a separate patterning process.
  • the following embodiments all take the second electrode 05 and the active layer 01 as an integral structure, and the third electrode 06 and the source and drain 03 as an integral structure as an example to introduce the pixel units described in the embodiments of the present disclosure.
  • FIG. 4 is an equivalent circuit diagram of a pixel unit provided by an embodiment of the present disclosure.
  • the pixel unit may further include a light-emitting element L1, and the light-emitting element L1 may be an organic light-emitting diode OLED.
  • the thin film transistor M1 may include: a driving transistor M11 , a switching transistor M12 , a compensation transistor M13 and a storage capacitor Cst.
  • the gate of the switch transistor M12 may be connected to a gate line g1, the first pole of the switch transistor M12 may be connected to the node n, and the second pole of the switch transistor M12 may be connected to a data line d1.
  • One end of the storage capacitor Cst may be connected to the node n, and the other end of the storage capacitor Cst may be connected to the first end of the light emitting element L1.
  • the second end of the light-emitting element L1 can be connected to the ground.
  • one end may be an anode, and the other end may be a cathode.
  • the first end of the light-emitting element L1 is the anode, and the second end is the cathode.
  • the gate of the driving transistor M11 may be connected to the node n, the first terminal of the driving transistor M11 may be connected to the first terminal of the light emitting element L1, and the second terminal of the driving transistor M11 may be connected to the driving power terminal OVDD.
  • the gate of the compensation transistor M13 may be connected to another gate line g2, the first pole of the compensation transistor M13 may be connected to the reference power supply terminal Vref and an external compensation circuit (not shown), and the second pole of the compensation transistor M13 may be connected to the light-emitting element The first end of L1 is connected.
  • the first electrode of the driving transistor M11 may be one of the source electrode and the drain electrode of the driving transistor M11, and the second electrode of the driving transistor M11 may be the other one of the source electrode and the drain electrode of the driving transistor M11 pole, the same is true for other transistors.
  • the second pole of the driving transistor M11 may refer to a pole for electrically connecting the driving power supply terminal OVDD.
  • the first pole described in the embodiment of the present disclosure is the source (S)
  • the second pole is the drain (D).
  • a parasitic capacitance is formed between the first electrode and the second electrode of each transistor and its gate electrode.
  • a parasitic capacitance Cgd1 is formed between the second electrode (ie the drain electrode) and the gate electrode of the driving transistor M11, and a parasitic capacitance Cgd1 is formed between the first electrode (ie the source electrode) and the gate electrode of the driving transistor M11 Parasitic capacitance Cgs1.
  • a parasitic capacitor Cgd2 is formed between the second electrode and the gate of the switching transistor M12, and a parasitic capacitor Cgs2 is formed between the first electrode and the gate of the switching transistor M12.
  • a parasitic capacitance Cgd3 is formed between the second electrode and the gate of the compensation transistor M13, and a parasitic capacitance Cgs3 is formed between the first electrode and the gate of the compensation transistor M13. Moreover, the first end and the second end of the light-emitting element L1 also form a parasitic capacitance Cl1.
  • the switching transistor M12 can be turned on when the gate line g1 provides a gate driving signal with an effective potential.
  • the data line d1 can write a data signal to the node n through the switching transistor M12, and the data signal can also be called gray scale data Vgs.
  • the storage capacitor Cst can be used to store and hold the gray-scale data Vgs written to the node n until the data signal is written again next time, that is, within one frame scan time, keeping Vgs unchanged.
  • the driving transistor M11 can generate a driving current and output it to the light-emitting element L1 in response to the driving power supply signal provided by the driving power supply terminal OVDD and the potential at the node n, so as to drive the light-emitting element L1 to emit light.
  • the compensation transistor M13 can be turned on when the gate line g2 provides a gate driving signal with an effective potential, and the reference power supply terminal Vref can write the reference power supply signal to one end of the light-emitting element L1 (ie, the first pole of the driving transistor M11 ) through the compensation transistor M13 , so as to achieve noise reduction for the first pole of the driving transistor M11.
  • the compensation transistor M13 can collect the drive current written by the drive transistor M11 to the light-emitting element L1, and output the collected drive current to the external compensation circuit, so that the external compensation circuit can reliably compensate the data signal based on the drive current.
  • the switching transistor M12 since the switching transistor M12 may have a leakage phenomenon, the potential at the node n may change, that is, the gray-scale data stored in the storage capacitor Cst may change within a frame time.
  • the variation ⁇ V of the gray-scale data stored in the storage capacitor Cst can satisfy:
  • I off is the leakage current of the switching transistor M12 , and the leakage current is related to the device characteristics of the switching transistor M12 and cannot be avoided.
  • ⁇ t is the scanning time of one frame, and ⁇ t is generally fixed.
  • cst is the capacitance of the storage capacitor Cst. Based on formula (1), it can be known that the larger the capacitance value cst of the storage capacitor Cst, the smaller the change amount ⁇ V, the smaller the ⁇ V, the better the light emission accuracy of the light emitting element L1.
  • cgd1 is the capacitance of the parasitic capacitance Cgd1
  • cgd2 is the capacitance of the parasitic capacitance Cgd2
  • cgs1 is the capacitance of the parasitic capacitance Cgs1
  • ⁇ Vg1 is the potential change of the gate line g1.
  • cgd1, cgd2, cgs1 and ⁇ Vg1 are generally not adjustable, so, based on this formula (2), it can be seen that the larger the capacitance value cst of the storage capacitor Cst, the smaller the ⁇ Vn, and the smaller the change of the potential at node n.
  • the smaller the loss of grayscale data is, the better the light-emitting accuracy of the light-emitting element L1 is.
  • the potential of the first electrode (ie, the source electrode) of the driving transistor M11 will gradually rise. Due to the coupling effect of the storage capacitor Cst, the gate (ie, the node The potential of n) also rises accordingly.
  • the raised potential ⁇ Vn1 can satisfy:
  • cgs2 is the capacitance of the parasitic capacitance Cgs2
  • ⁇ Vs is the potential variation of the first electrode of the driving transistor M11.
  • both cgs2 and ⁇ Vs are generally not adjustable. Therefore, based on the formula (3), it can be known that the larger the capacitance value cst of the storage capacitor Cst, the smaller the ⁇ Vn1. That is, under the coupling action of the storage capacitor Cst, the potential at the node n and the potential of the first electrode of the driving transistor M11 change closer.
  • the thinner the change of Vgs the smaller the loss of gray-scale data, and the better the light-emitting accuracy of the light-emitting element L1.
  • the thin film transistors M1 shown in FIG. 1 and FIG. 3 both refer to the driving transistors M11 .
  • FIG. 5 is a schematic diagram of a film layer structure of a storage capacitor provided by an embodiment of the present disclosure.
  • the second electrode 05 can be electrically connected to the first electrode of the driving transistor M11, and the electrically connected third electrode 06 and the first electrode 04 It may be electrically connected to the gate G of the driving transistor M11.
  • the first electrode of the driving transistor M11 is the source S of the driving transistor M11 .
  • FIG. 6 is a schematic diagram of a film layer structure of another pixel unit provided by an embodiment of the present disclosure.
  • the orthographic projection of the first electrode 04 on the base substrate 00 is different from the orthographic projection of the second electrode of the driving transistor M11 on the base substrate 00. overlapping.
  • the second pole of the driving transistor M11 is the drain G of the driving transistor M11.
  • FIG. 7 is a schematic diagram of a film layer structure of another storage capacitor provided by an embodiment of the present disclosure.
  • the second electrode 05 may be electrically connected to the gate G of the driving transistor M11
  • the third electrode 06 electrically connected to The first electrode 04 may be electrically connected to the first electrode S of the driving transistor M11.
  • FIG. 8 is a schematic diagram of a film layer structure of still another pixel unit provided by an embodiment of the present disclosure. 8 , for the storage capacitor shown in FIG. 7 , the orthographic projection of the first electrode 04 on the base substrate 00 may overlap with the orthographic projection of the second electrode of the driving transistor M11 on the base substrate 00 .
  • the orthographic projection of the first electrode 04 shown on the base substrate 00 completely overlaps with the orthographic projection of the second electrode of the driving transistor M11 on the base substrate 00 . That is, the storage capacitor Cst may "wrap" the driving transistor M11.
  • the first electrode 04 included in the storage capacitor Cst can be used to shield the driving transistor M11 from light, that is, the first electrode 04 can be used as a shielding metal for the driving transistor M11.
  • a thinner active layer 01 can be avoided, that is, the second electrode 05 shown in FIG. 8 straddles the first electrode 04 to ensure the yield.
  • the arrangement shown in FIG. 8 may require more via holes.
  • the capacitance value of the storage capacitor Cst corresponding to the capacitance value of the storage capacitor Cst formed by the structure shown in FIG. 8 is about 10 smaller. %.
  • the third electrode 06 included in the storage capacitor Cst can be electrically connected to the first electrode 04 through the via K1 (only K1 is schematically marked in FIG. 7 ). ).
  • the gate 02 of each transistor may be located in the same layer, the source and drain electrodes 03 may be located in the same layer, and the active layer 01 may also be located in the same layer.
  • the orthographic projection of any one of the first electrode 04, the second electrode 05 and the third electrode 06 included in the storage capacitor Cst on the base substrate 00 is the same as the active layer of the switching transistor M12 on the base substrate.
  • the orthographic projection of the gate of the switching transistor M12 on the base substrate, and the orthographic projection of the source and drain of the switching transistor M12 on the base substrate may not overlap.
  • the orthographic projection of the storage capacitor Cst on the base substrate 00 does not overlap with the orthographic projection of the switching transistor M12 on the base substrate 00 .
  • This setting method can avoid increasing the capacitance value of the parasitic capacitance Cgd2 and the capacitance value of Cgs2 in the switching transistor M12, thereby avoiding the influence of the parasitic capacitances Cgd2 and Cgs2 on the light emission accuracy, and further ensuring a better display effect.
  • the orthographic projection of any one of the first electrode 04, the second electrode 05, and the third electrode 06 included in the storage capacitor Cst on the base substrate 00 is the same as the active layer of the compensation transistor M13 on the base substrate.
  • the orthographic projection on the substrate, the orthographic projection of the gate of the compensation transistor M13 on the base substrate, and the orthographic projection of the source and drain of the compensation transistor M13 on the base substrate may also not overlap.
  • this setting method can avoid increasing the capacitance value of the parasitic capacitance Cgd3 and the capacitance value of Cgs3 in the compensation transistor M13, thereby avoiding the influence of the parasitic capacitances Cgd3 and Cgs3 on the luminous accuracy, and further ensuring a better display effect.
  • the storage capacitor Cst may further include: an insulating layer located between every two adjacent electrodes.
  • the storage capacitor Cst may further include a buffer layer 07 between the first electrode 04 and the second electrode 05 , and a layer between the second electrode 05 and the third electrode 06 Interlayer dielectric (ILD) layer 08.
  • ILD Interlayer dielectric
  • the size of the storage capacitor Cst is small, which is beneficial to the realization of high resolution.
  • the pixel unit may further include: a passivation layer (PVX) 09 located on the side of the third electrode 06 away from the base substrate 00, a flat (PVX) 09 located on the side of the passivation layer 09 away from the base substrate 00 resin) layer 10, an anode 11 located on the side of the flat layer 10 away from the base substrate 00, and the anode 11 is electrically connected to the source and drain electrodes 06, and a pixel definition layer located on the side of the anode 11 away from the base substrate 00 (pixel definition layer, PDL) 12.
  • PVX passivation layer
  • PVX flat
  • anode 11 located on the side of the flat layer 10 away from the base substrate 00
  • PDL pixel definition layer
  • the pixel unit may further include an luminescent layer (electroluminescent layer, EL) and a cathode (cathode), which are not shown in the figure, but are located on the side of the anode layer 11 away from the base substrate 00 .
  • EL electroactive layer
  • cathode cathode
  • the pixel unit described in the embodiment of the present disclosure may be a top emission type pixel unit. That is, the light generated by the light emitting element L1 in the pixel unit can be emitted from the side of the cathode away from the base substrate 00 .
  • the top emission type pixel unit is not affected by whether the base substrate 00 transmits light or not, which can effectively improve the aperture ratio of the display substrate and is conducive to achieving high resolution.
  • the pixel units described in the embodiments of the present disclosure may also be bottom emission pixel units. That is, the light generated by the light-emitting element L1 in the pixel unit can be emitted from the side of the anode 11 close to the base substrate 00 through the base substrate 00 .
  • each transistor described in the above embodiments may be an N-type switching transistor or a P-type switching transistor.
  • the pixel unit in the related art can generally only use the gate electrode 02 and the source and drain electrodes.
  • the source/drain 03 is used as an external signal terminal of a wire, or is electrically connected to any two ends that need to be turned on.
  • the embodiment of the present disclosure adds a conductive metal layer (ie, the first electrode 04 ) in addition to the gate 02 and the source-drain 03 to form the storage capacitor Cst, so the embodiment of the present disclosure
  • the first electrode 04 can also be reused as part of the wires, which avoids the problem that wires located in the same layer are relatively dense, and ensures a good yield of the final display substrate.
  • the embodiments of the present disclosure provide a pixel unit.
  • the storage capacitor includes a first electrode, a second electrode and a third electrode that are stacked in sequence. Since every two adjacent layers of electrodes can form a capacitor, the storage capacitor can be composed of two capacitors connected in parallel. Correspondingly, the capacitance of the storage capacitor is the sum of the capacitances of the two capacitors connected in parallel.
  • the capacitance of the storage capacitor in the pixel unit described in this application is larger, and further, the light-emitting element included in the pixel unit has higher luminous accuracy, and the display substrate including the pixel unit has a better display effect.
  • FIG. 9 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate may include: a base substrate 00 , and a plurality of pixel units 001 located on the base substrate 00 and arranged in an array.
  • at least one pixel unit 001 may include a pixel unit as shown in any one of FIG. 1 , FIG. 3 , FIG. 6 and FIG. 8 .
  • FIG. 10 is a design layout of a display substrate provided by an embodiment of the present disclosure. Referring to FIG. 10, it can be seen that each pixel unit includes a storage capacitor, and the storage capacitor Cst is located in the area where the first electrode 04 shown in FIG. 10 is located. A second electrode and a third electrode are stacked on the electrode 04 in sequence.
  • Each pixel unit further includes a driving transistor M11, a switching transistor M12 and a compensation transistor M13, and the storage capacitor Cst does not have an overlapping area with the switching transistor M12 and the compensation transistor M13.
  • the wire L1 made of the first electrode 04 is also included, and the wire L1 can extend along the row arrangement direction.
  • this arrangement also solves the problem that wires in the same layer are denser, and accordingly, reduces the occurrence rate of defects.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device may include: a driving circuit 200 and a display substrate 100 as shown in FIG. 9 or FIG. 10 .
  • the driving circuit 200 may be connected to a pixel unit in the display substrate 100 (not shown in FIG. 11 ), and the driving circuit 200 may be used to provide driving signals for the thin film transistors included in the pixel unit.
  • the driving circuit 200 may include a gate driving circuit and a source driving circuit.
  • the gate driving circuit can be connected to the gate lines g1 and g2, and the gate driving circuit can be used to provide gate driving signals at effective potentials to the gate lines g1 and g2 at different stages, Therefore, the switching transistor M11 connected to the control gate line g1 is turned on, and the compensation transistor M13 connected to the control gate line g2 is turned on.
  • the source driver circuit can be connected to the data line d1, and the source driver circuit can be used to provide a data signal to the data line d1 to which it is connected.
  • a plurality of pixel units 001 located in the same row can be connected to the same gate line g1, and can be connected to the same gate line g2, and the gate lines g1 connected to the pixel units 001 located in different rows can be different,
  • the connected gate lines g2 may be different.
  • Multiple pixel units 001 located in the same column may be connected to the same data line d1, and pixel units 001 located in different rows may be connected to different data lines d1.
  • the display device provided by the embodiment of the present disclosure may be any product or component with display function, such as electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, and navigator.
  • display function such as electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, and navigator.
  • first and second are used for descriptive purposes only and should not be construed to indicate or imply relative importance.
  • plurality refers to two or more, unless expressly limited otherwise. The above are only optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection of the present disclosure. within the range.

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Abstract

本公开提供了一种像素单元、显示基板及显示装置，属于显示技术领域。该像素单元中，存储电容包括依次层叠的第一电极、第二电极和第三电极。由于每相邻两层电极可以形成一电容，因此该存储电容可以由并联的两个电容组成，相应的，该存储电容的容值即为该并联的两个电容的容值之和。相对于相关技术，本申请记载的像素单元中存储电容的容值更大，进而，该像素单元包括的发光元件的发光准确度更高，包括该像素单元的显示基板显示效果较好。

Description

像素单元、显示基板及显示装置
本公开要求于2020年5月9日提交的申请号为202010386995.5、发明名称为“像素单元、显示基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种像素单元、显示基板及显示装置。
背景技术
有机发光二极管(organic light emitting diode，OLED)显示基板因其自发光、功耗小、响应快和成本低等优点而备受青睐。
发明内容
本公开实施例提供了一种像素单元、显示基板及显示装置，所述技术方案如下：
一方面，提供了一种像素单元，所述像素单元包括：位于衬底基板上的薄膜晶体管和存储电容；所述薄膜晶体管包括：有源层，栅极和源漏极；所述存储电容包括：沿与所述衬底基板垂直的方向依次层叠的第一电极、第二电极和第三电极；
其中，所述第一电极位于所述有源层靠近所述衬底基板的一侧；
所述第二电极与所述有源层或所述栅极位于同层；
所述第三电极与所述源漏极位于同层，且所述第三电极与所述第一电极电连接。
可选的，所述第一电极、所述第二电极和所述第三电极中的任意两个电极在所述衬底基板上的正投影至少部分重叠。
可选的，所述薄膜晶体管包括：驱动晶体管，所述源漏极包括源极和漏极；
所述第二电极与所述驱动晶体管的第一极电连接，电连接的所述第三电极和所述第一电极与所述驱动晶体管的栅极电连接；其中，所述驱动晶体管的第 一极为所述驱动晶体管的源极和漏极中的一极。
可选的，所述第一电极在所述衬底基板上的正投影，与所述驱动晶体管的第二极在所述衬底基板上的正投影不重叠；其中，所述驱动晶体管的第二极为所述驱动晶体管的源极和漏极中的另一极。
可选的，所述薄膜晶体管包括：驱动晶体管，所述源漏极包括源极和漏极；
所述第二电极与所述驱动晶体管的栅极电连接，电连接的所述第三电极和所述第一电极与所述驱动晶体管的第一极电连接；其中，所述驱动晶体管的第一极为所述驱动晶体管的源极和漏极中的一极。
可选的，所述第一电极在所述衬底基板上的正投影，与所述驱动晶体管的第二极在所述衬底基板上的正投影重叠；其中，所述驱动晶体管的第二极为所述驱动晶体管的源极和漏极中的另一极。
可选的，所述驱动晶体管的第二极用于电连接驱动电源端。
可选的，所述第三电极通过过孔与所述第一电极电连接。
可选的，所述像素单元还包括：发光元件，所述发光元件为有机发光二极管；其中，所述发光元件与所述驱动晶体管的第一极电连接。
可选的，所述薄膜晶体管还包括：开关晶体管；
所述第一电极、所述第二电极和所述第三电极中的任一所述电极在所述衬底基板上的正投影，与所述开关晶体管的有源层在所述衬底基板上的正投影，所述开关晶体管的栅极在所述衬底基板上的正投影，以及所述开关晶体管的源漏极在所述衬底基板上的正投影均不重叠。
可选的，所述薄膜晶体管还包括：补偿晶体管；
所述第一电极、所述第二电极和所述第三电极中的任一所述电极在所述衬底基板上的正投影，与所述补偿晶体管的有源层在所述衬底基板上的正投影，所述补偿晶体管的栅极在所述衬底基板上的正投影，以及所述补偿晶体管的源漏极在所述衬底基板上的正投影均不重叠。
可选的，所述存储电容还包括：位于每相邻两个所述电极之间的绝缘层。
可选的，所述像素单元为顶发射型像素单元，或，底发射型像素单元。
可选的，所述第二电极与所述有源层位于同层，且材料相同；或者，所述第二电极与所述栅极位于同层，且材料相同。
可选的，所述第三电极与所述源漏极的材料相同。
可选的，所述像素单元还包括：位于所述第三电极远离所述衬底基板一侧且依次层叠的钝化层、平坦层、阳极和像素定义层，且所述阳极与所述源漏极电连接。
可选的，所述有源层，所述栅极和所述源漏极沿远离所述衬底基板的方向依次层叠。
另一方面，提供了一种显示基板，所述显示基板包括：衬底基板，以及位于所述衬底基板上且阵列排布的多个像素单元；
其中，至少一个所述像素单元为如上述方面所述的像素单元。
可选的，所述显示基板还包括：导线；其中，所述导线的一部分为所述像素单元包括的第一电极。
又一方面，提供了一种显示装置，所述显示装置包括：驱动电路，以及如上述方面所述的显示基板；
所述驱动电路与所述显示基板中的像素单元连接，所述驱动电路用于为所述像素单元包括的薄膜晶体管提供驱动信号。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种像素单元的结构示意图；
图2是本公开实施例提供的一种存储电容的组成示意图；
图3是本公开实施例提供的另一种像素单元的结构示意图；
图4是本公开实施例提供的一种像素单元的等效电路图；
图5是本公开实施例提供的另一种存储电容的结构示意图；
图6是本公开实施例提供的又一种像素单元的结构示意图；
图7是本公开实施例提供的又一种存储电容的结构示意图；
图8是本公开实施例提供的再一种像素单元的结构示意图；
图9是本公开实施例提供的一种显示基板的结构示意图；
图10是本公开实施例提供的另一种显示基板的结构示意图；
图11是本公开实施例提供的一种显示装置的结构示意图。
附图标记说明：
00-衬底基板，01-有源层，02-栅极，03-源漏极，04-第一电极，05-第二电极，06-第三电极，07-缓冲层，08-层间介定层，09-钝化层，10-平坦层，11-阳极，12-像素定义层，Cst-存储电容，M1-薄膜晶体管；
M11-驱动晶体管，M12-开关晶体管，M13-补偿晶体管，g1、g2-栅线，d1-数据线，Cgd1、Cgd2、Cgd3、Cgs1、Cgs2、Cgs3、Cl1-寄生电容，L1-发光元件；
S-驱动晶体管的第一极，G-驱动晶体管的第二极，K1-过孔，001-像素单元，L1-导线，100-显示基板，200-驱动电路。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
图1是本公开实施例提供的一种像素单元的结构示意图。如图1所示，该像素单元可以包括：位于衬底基板00上的薄膜晶体管M1和存储电容Cst。
其中，参考图1，该薄膜晶体管M1可以包括：有源(active，ACT)层01，栅极(gate，G)02和源漏极(source&drain，SD)03，且源漏极03与有源层01可以连接。
可选的，如图1所示，该有源层01、栅极02和源漏极03可以沿远离衬底基板00方向依次层叠排布，该结构也可以称为底栅结构。当然，在一些实施例中，该有源层01、栅极02和源漏极03也可以按照其他方式排布，如，有源层01、源漏极03和栅极02沿远离衬底基板00方向依次层叠排布，该结构也可以称为顶栅结构，本公开实施例对此不做限定。
继续参考图1，该存储电容Cst可以包括：沿与衬底基板00垂直的方向依次层叠的第一电极04、第二电极05和第三电极06。
其中，该第一电极04可以位于有源层01靠近衬底基板00的一侧。即，该第一电极04可以位于有源层01和衬底基板00之间。且，为了形成该存储电容Cst，该第一电极04可以由能够导电的导电材料制成。例如，该第一电极可以由金属材料制成。相应的，该第一电极04也可以称为金属(metal)层。
该第二电极05可以与有源层01或栅极02位于同层。例如，参考图1，其 示出的第二电极05与有源层01位于同层。
该第三电极06可以与源漏极03位于同层，且该第三电极06可以与第一电极04电连接。
另，该存储电容Cst包括的任意两个电极中，一个电极在衬底基板00上的正投影，与另一个电极在衬底基板00上的正投影存在重叠部分。即，参考图1，第二电极05在衬底基板00上的正投影可以与第一电极04在衬底基板00上的正投影存在重叠部分，第二电极05在衬底基板00上的正投影也可以与第三电极06在衬底基板00上的正投影存在重叠部分，且第一电极04在衬底基板00上的正投影与第三电极06在衬底基板00上的正投影存在重叠部分。
相应的，如图1所示，第二电极05可以位于第一电极04和第三电极06之间。进一步，结合图2可以看出，第二电极05可以与第三电极06形成一个电容C1，且第二电极05可以与第一电极04形成另一个电容C2，存储电容Cst可以由该两个电容C1和C2并联组成。
假设电容C1的电容值(以下简称“容值”)为c1，电容C2的容值为c2，则基于电容并联公式可知，存储电容Cst的容值cst即为：cst＝c1+c2。
如此，相对于存储电容仅由两层相邻的金属层组成的相关技术，本公开实施例提供的存储电容的容值更大。当然，为了形成更大容值的存储电容，还可以设置更多层依次层叠的电极(如，可以设置两层或两层以上的第一电极04)。
综上所述，本公开实施例提供了一种像素单元。该像素单元中，存储电容包括依次层叠的第一电极、第二电极和第三电极。由于每相邻两层电极可以形成一个电容，因此该存储电容可以由并联的两个电容组成，相应的，该存储电容的容值即为该并联的两个电容的容值之和。相对于相关技术，本公开实施例记载的像素单元中存储电容的容值更大，进而，该像素单元包括的发光元件的发光准确度更高，包括该像素单元的显示基板显示效果较好。
可选的，为了避免增加制造成本和制造工艺的复杂度，可以采用相同的材料，通过一次构图工艺形成位于同层的第二电极05和有源层01，或，采用相同的材料，通过一次构图工艺形成位于同层的第二电极05和栅极02。同理，也可以采用相同的材料，通过一次构图工艺形成位于同层的第三电极06和源漏极03，该源漏极03可以包括源极和漏极。
即，假设通过一次构图工艺形成ACT图案，则该ACT图案可以包括有源层01和第二电极05。假设通过一次构图工艺形成栅金属(gate metal，GT)图案，则该GT图案可以包括栅极02和第二电极05。假设通过一次构图工艺形成源漏极SD图案，则该源漏极SD图案可以包括源漏极03和第三电极06。
除此之外，薄膜晶体管M1还可以包括位于栅极02靠近衬底基板00一侧的栅绝缘(gate insulator，GI)层。即，在形成GT图案之前，还可以先形成一GI图案。如此，可以避免栅极与有源层之间产生信号干扰问题。
示例的，以第二电极05与有源层01位于同层为例，图3示出了本公开实施例提供的另一种像素单元的结构示意图。结合图3可以看出，第二电极05与有源层01可以为一体结构，第三电极06与源漏极03可以为一体结构。第一电极04为采用单独的构图工艺新增于衬底基板00上的一层金属层。
下述实施例均以第二电极05与有源层01为一体结构，且第三电极06与源漏极03为一体结构为例对本公开实施例记载的像素单元进行介绍。
可选的，图4是本公开实施例提供的一种像素单元的等效电路图。如图4所示，该像素单元还可以包括发光元件L1，该发光元件L1可以为有机发光二极管OLED。相应的，结合图4，该薄膜晶体管M1可以包括：驱动晶体管M11、开关晶体管M12、补偿晶体管M13和存储电容Cst。
其中，开关晶体管M12的栅极可以与一条栅线g1连接，开关晶体管M12的第一极可以与节点n连接，开关晶体管M12的第二极可以与一条数据线d1连接。
存储电容Cst的一端可以与节点n连接，存储电容Cst的另一端可以与发光元件L1的第一端连接。且发光元件L1的第二端可以与地端连接。可选的，发光元件L1的第一端和第二端中，一端可以为阳极，另一端可以为阴极。如，图4示出的像素单元中发光元件L1的第一端为阳极，第二端为阴极。
驱动晶体管M11的栅极可以与节点n连接，驱动晶体管M11的第一极可以与发光元件L1的第一端连接，驱动晶体管M11的第二极可以与驱动电源端OVDD连接。
补偿晶体管M13的栅极可以与另一条栅线g2连接，补偿晶体管M13的第一极可以与参考电源端Vref和外部补偿电路(未示出)连接，补偿晶体管M13的第二极可以与发光元件L1的第一端连接。
需要说明的是，驱动晶体管M11的第一极可以为驱动晶体管M11的源极和漏极中的一极，驱动晶体管M11的第二极可以为驱动晶体管M11的源极和漏极中的另一极，其他晶体管同理。且，驱动晶体管M11的第二极可以是指用于电连接驱动电源端OVDD的一极，相应的，结合图4可以看出，本公开实施例记载的第一极即为源极(S)，第二极即为漏极(D)。
除此之外，除存储电容Cst之外，该像素单元中，每个晶体管的第一极和第二极均与其栅极之间会形成一寄生电容。
例如，如图4所示，驱动晶体管M11的第二极(即漏极)与栅极之间形成一寄生电容Cgd1，驱动晶体管M11的第一极(即源极)与栅极之间形成一寄生电容Cgs1。开关晶体管M12的第二极与栅极之间形成一寄生电容Cgd2，开关晶体管M12的第一极与栅极之间形成一寄生电容Cgs2。补偿晶体管M13的第二极与栅极之间形成一寄生电容Cgd3，补偿晶体管M13的第一极与栅极之间形成一寄生电容Cgs3。且，发光元件L1的第一端和第二端也形成一寄生电容Cl1。
结合图4所示的像素单元，对像素单元的工作原理进行下述介绍：
开关晶体管M12可以在栅线g1提供有效电位的栅极驱动信号时开启，此时，数据线d1可以通过开关晶体管M12向节点n写入数据信号，该数据信号也可以称为灰阶数据Vgs。存储电容Cst可以用于存储并维持(hold)写入至节点n的灰阶数据Vgs，直至下一次再次写入数据信号，即在一帧扫描时间内，保持Vgs不变。驱动晶体管M11可以响应于驱动电源端OVDD提供的驱动电源信号和节点n处的电位，生成驱动电流并输出至发光元件L1，以驱动发光元件L1发光。补偿晶体管M13可以在栅线g2提供有效电位的栅极驱动信号时开启，参考电源端Vref可以通过补偿晶体管M13向发光元件L1的一端(即，驱动晶体管M11的第一极)写入参考电源信号，以实现对驱动晶体管M11的第一极的降噪。且，补偿晶体管M13可以采集驱动晶体管M11写入至发光元件L1的驱动电流，并将采集到的驱动电流输出至外部补偿电路，以供外部补偿电路基于该驱动电流实现对数据信号的可靠补偿。
结合图4和上述工作原理对存储电容Cst的容值对发光效果的影响进行下述分析：
一方面：由于开关晶体管M12可能会出现漏电现象，因此可能导致节点n处的电位发生变化，即导致存储电容Cst存储的灰阶数据在一帧时间内发生变化。 其中，存储电容Cst存储的灰阶数据的变化量ΔV可以满足：
ΔV＝(I off*Δt)/cst   公式(1)；
其中，I off为开关晶体管M12的漏电流，且该漏电流与开关晶体管M12的器件特性有关，无法避免。Δt为一帧扫描时间，且Δt一般是固定的。cst为存储电容Cst的容值。基于公式(1)可知，存储电容Cst的容值cst越大，变化量ΔV即可以越小，ΔV越小，发光元件L1的发光准确度越好。
另一方面：在开关晶体管M12关断瞬间，节点n处于悬空(floating)状态。此外，因寄生电容Cgs2的存在，节点n处的电位会被下拉，下拉至的电位ΔVn可以满足：
Figure PCTCN2021079704-appb-000001
其中，cgd1为寄生电容Cgd1的容值，cgd2为寄生电容Cgd2的容值，cgs1为寄生电容Cgs1的容值，ΔVg1为栅线g1的电位变化量。且cgd1、cgd2、cgs1和ΔVg1一般都是不可调节的，如此，基于该公式(2)可知，存储电容Cst的容值cst越大，ΔVn越小，节点n处的电位的变化即越小，相应的，灰阶数据的损失也越小，发光元件L1的发光准确度越好。
再一方面：在驱动发光元件L1发光的发光阶段，驱动晶体管M11的第一极(即，源极)的电位会逐渐抬升，因存储电容Cst的耦合作用，驱动晶体管M11的栅极(即节点n)的电位也会相应抬升。抬升至的电位ΔVn1可以满足：
Figure PCTCN2021079704-appb-000002
其中，cgs2为寄生电容Cgs2的容值，ΔVs为驱动晶体管M11的第一极的电位变化量，如上分析，cgs2和ΔVs一般也都是不可调节的。故，基于该公式(3)可知，存储电容Cst的容值cst越大，ΔVn1越小。即在存储电容Cst的耦合作用下，节点n处的电位和驱动晶体管M11的第一极的电位的变化越接近。相应的，Vgs的变化即越小，灰阶数据的损失越小，发光元件L1的发光准确度越好。另，上述图1和图3示出的薄膜晶体管M1均指驱动晶体管M11。
图5是本公开实施例提供的一种存储电容的膜层结构示意图。作为一种可选的实现方式，结合图1、图3至图5可以看出，第二电极05可以与驱动晶体管M11的第一极电连接，电连接的第三电极06和第一电极04可以与驱动晶体管M11的栅极G电连接。结合上述分析和图5可知，驱动晶体管M11的第一极为驱动晶体管M11的源极S。
图6是本公开实施例提供的另一种像素单元的膜层结构示意图。参考图6可以看出，对于图5所示结构的驱动晶体管M11，第一电极04在衬底基板00上的正投影，与驱动晶体管M11的第二极在衬底基板00上的正投影不重叠。结合上述分析可知，驱动晶体管M11的第二极为驱动晶体管M11的漏极G。
通过图5和图6的设置方式，可以避免增加驱动晶体管M11的第二极与栅极形成的寄生电容Cgd1。结合上述公式(2)和公式(3)可知，避免增加Cgd1，即可以进一步避免Cgd1对发光元件L1发光准确度的影响，确保显示效果较好。
图7是本公开实施例提供的另一种存储电容的膜层结构示意图。作为另一种可选的实现方式，结合图1、图3、图4和图7可以看出，第二电极05可以与驱动晶体管M11的栅极G电连接，电连接的第三电极06和第一电极04可以与驱动晶体管M11的第一极S电连接。
图8是本公开实施例提供的再一种像素单元的膜层结构示意图。参考图8可以看出，对于图7所示的存储电容，第一电极04在衬底基板00上的正投影，可以与驱动晶体管M11的第二极在衬底基板00上的正投影重叠。
例如，参考图8，其示出的第一电极04在衬底基板00上的正投影，与驱动晶体管M11的第二极在衬底基板00上的正投影完全重叠。即，存储电容Cst可以“包裹”驱动晶体管M11。
通过图7和图8的设置方式，可以采用该存储电容Cst包括的第一电极04对驱动晶体管M11进行遮光，即该第一电极04可以作为驱动晶体管M11的遮光金属。且，对比图6和图8，可以避免较薄的有源层01，即图8所示的第二电极05跨第一电极04，保证良率。但图8所示设置方式可能会需要较多的过孔，相对于图6所示实现方式，图8所示结构最终形成的存储电容Cst的容值对应的存储电容Cst的容值小大约10％。
可选的，结合上述图1、图3、图5至图8可以看出，存储电容Cst包括的第三电极06可以通过过孔K1与第一电极04电连接(仅图7示意性标注K1)。
可选的，结合图6和图8可以看出，各晶体管的栅极02可以位于同层，源漏极03可以位于同层，有源层01也可以位于同层。
可选的，存储电容Cst包括的第一电极04、第二电极05和第三电极06中的任一电极在衬底基板00上的正投影，与开关晶体管M12的有源层在衬底基板上的正投影，开关晶体管M12的栅极在衬底基板上的正投影，以及开关晶体管 M12的源漏极在衬底基板上的正投影可以均不重叠。
即，结合图6和图8，存储电容Cst在衬底基板00上的正投影，与开关晶体管M12在衬底基板00上的正投影不重叠。通过该设置方式，可以避免增加开关晶体管M12中寄生电容Cgd2的容值和Cgs2的容值，进而可以避免寄生电容Cgd2和Cgs2对发光准确度产生影响，进一步保证显示效果较好。
可选的，存储电容Cst包括的第一电极04、第二电极05和第三电极06中的任一电极在衬底基板00上的正投影，与补偿晶体管M13的有源层在衬底基板上的正投影，补偿晶体管M13的栅极在衬底基板上的正投影，以及补偿晶体管M13的源漏极在衬底基板上的正投影也可以均不重叠。
即，结合图6和图8，存储电容Cst在衬底基板00上的正投影，与补偿晶体管M13在衬底基板00上的正投影不重叠。同理，通过该设置方式，可以避免增加补偿晶体管M13中寄生电容Cgd3的容值和Cgs3的容值，进而可以避免寄生电容Cgd3和Cgs3对发光准确度产生影响，进一步保证显示效果较好。
可选的，为了形成存储电容，结合上述附图可以看出，存储电容Cst还可以包括：位于每相邻两个电极之间的绝缘层。
例如，结合图6和图8，存储电容Cst还可以包括位于第一电极04和第二电极05之间的缓冲(buffer)层07，以及位于第二电极05和第三电极06之间的层间介定(inter layer dielectric，ILD)层08。本公开实施例保护的像素单元中，存储电容Cst的尺寸较小，有利于高分辨率实现。
继续结合图6和图8，像素单元还可以包括：位于第三电极06远离衬底基板00一侧的钝化层(PVX)09，位于钝化层09远离衬底基板00一侧的平坦(resin)层10，位于平坦层10远离衬底基板00一侧的阳极(anode)11，且该阳极11与源漏极06电连接，以及位于阳极11远离衬底基板00一侧的像素定义层(pixel definition layer，PDL)12。除此之外，像素单元还可以包括图中未示出，但位于阳极层11远离衬底基板00一侧的发光层(electro luminescent layer，EL)和阴极(cathode)。
可选的，本公开实施例记载的像素单元可以为顶发射型像素单元。即，该像素单元中发光元件L1产生的光可以从阴极背离衬底基板00的一侧发出。相应的，顶发射型像素单元不受衬底基板00是否透光的影响，可以效提高显示基板的开口率，且有利于实现高分辨率。或者，本公开实施例记载的像素单元也 可以为底发射型像素单元。即，该像素单元中发光元件L1产生的光可以从阳极11靠近衬底基板00的一侧，经衬底基板00发出。本公开实施例对此不做限定。另，上述实施例记载的各晶体管可以均为N型开关晶体管或P型开关晶体管。
由于相关技术中，像素单元包括的各层级结构中，仅栅极02和源漏极03由能够导电的金属材料制成，相应的，相关技术中的像素单元，一般仅能采用栅极02和源漏极03作为导线外接信号端，或，电连接需要导通的任意两端。
而，由于本公开实施例相对于相关技术，除栅极02和源漏极03外，新增了一层能够导电的金属层(即第一电极04)形成存储电容Cst，因此本公开实施例还可以复用该第一电极04作为部分导线，避免了位于同层的导线较为密集的问题，确保了最终制成的显示基板的良率较好。
综上所述，本公开实施例提供了一种像素单元。该像素单元中，存储电容包括依次层叠的第一电极、第二电极和第三电极。由于每相邻两层电极可以形成一电容，因此该存储电容可以由并联的两个电容组成，相应的，该存储电容的容值即为该并联的两个电容的容值之和。相对于相关技术，本申请记载的像素单元中存储电容的容值更大，进而，该像素单元包括的发光元件的发光准确度更高，包括该像素单元的显示基板显示效果较好。
图9是本公开实施例提供的一种显示基板的结构示意图。如图9所示，该显示基板可以包括：衬底基板00，以及位于衬底基板00上且阵列排布的多个像素单元001。其中，至少一个像素单元001可以包括如图1、图3、图6和图8任一所示的像素单元。
图10是本公开实施例提供的一种显示基板的设计版图，参考图10可以看出，每个像素单元包括存储电容，存储电容Cst位于图10示出的第一电极04所在区域，第一电极04上依次再层叠有第二电极和第三电极。
每个像素单元还包括驱动晶体管M11、开关晶体管M12和补偿晶体管M13，且存储电容Cst与开关晶体管M12和补偿晶体管M13均不存在交叠区域。
再，还包括采用第一电极04做成的导线L1，该导线L1可以沿行排布方向延伸。如此，相对于相关技术仅能采用栅极和源漏极作导线，该设置还解决了位于同层的导线较密集的问题，相应的，降低了不良发生率。
图11是本公开实施例提供的一种显示装置的结构示意图。如图11所示，该显示装置可以包括：驱动电路200，以及如图9或图10所示的显示基板100。
其中，驱动电路200可以与显示基板100中的像素单元连接(图11未示出)，驱动电路200可以用于为像素单元包括的薄膜晶体管提供驱动信号。
例如，该驱动电路200可以包括栅极驱动电路和源极驱动电路。结合图4所示的像素单元，该栅极驱动电路可以与栅线g1和g2连接，该栅极驱动电路可以用于在不同阶段向栅线g1和g2提供处于有效电位的栅极驱动信号，从而控制栅线g1连接的开关晶体管M11开启，以及控制栅线g2连接的补偿晶体管M13开启。该源极驱动电路可以与数据线d1连接，该源极驱动电路可以用于向其所连接的数据线d1提供数据信号。
另，结合图9，位于同一行的多个像素单元001可以与同一条栅线g1连接，以及可以与同一条栅线g2连接，且位于不同行的像素单元001连接的栅线g1可以不同，连接的栅线g2可以不同。位于同一列的多个像素单元001可以与同一条数据线d1连接，且位于不同行的像素单元001连接的数据线d1可以不同。
可选的，本公开实施例提供的显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、导航仪等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。
另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。
通篇相似的参考标记指示相似的元件。
术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种像素单元，所述像素单元包括：位于衬底基板上的薄膜晶体管和存储电容；
    所述薄膜晶体管包括：有源层，栅极和源漏极；所述存储电容包括：沿与所述衬底基板垂直的方向依次层叠的第一电极、第二电极和第三电极；
    其中，所述第一电极位于所述有源层靠近所述衬底基板的一侧；
    所述第二电极与所述有源层或所述栅极位于同层；
    所述第三电极与所述源漏极位于同层，且所述第三电极与所述第一电极电连接。
  2. 根据权利要求1所述的像素单元，其中，所述第一电极、所述第二电极和所述第三电极中的任意两个电极在所述衬底基板上的正投影至少部分重叠。
  3. 根据权利要求1或2所述的像素单元，其中，所述薄膜晶体管包括：驱动晶体管，所述源漏极包括源极和漏极；
    所述第二电极与所述驱动晶体管的第一极电连接，电连接的所述第三电极和所述第一电极与所述驱动晶体管的栅极电连接；
    其中，所述驱动晶体管的第一极为所述驱动晶体管的源极和漏极中的一极。
  4. 根据权利要求3所述的像素单元，其中，所述第一电极在所述衬底基板上的正投影，与所述驱动晶体管的第二极在所述衬底基板上的正投影不重叠；
    其中，所述驱动晶体管的第二极为所述驱动晶体管的源极和漏极中的另一极。
  5. 根据权利要求1或2所述的像素单元，其中，所述薄膜晶体管包括：驱动晶体管，所述源漏极包括源极和漏极；
    所述第二电极与所述驱动晶体管的栅极电连接，电连接的所述第三电极和所述第一电极与所述驱动晶体管的第一极电连接；
    其中，所述驱动晶体管的第一极为所述驱动晶体管的源极和漏极中的一极。
  6. 根据权利要求5所述的像素单元，其中，所述第一电极在所述衬底基板上的正投影，与所述驱动晶体管的第二极在所述衬底基板上的正投影重叠；
    其中，所述驱动晶体管的第二极为所述驱动晶体管的源极和漏极中的另一极。
  7. 根据权利要求3至6任一所述的像素单元，其中，所述驱动晶体管的第二极用于电连接驱动电源端。
  8. 根据权利要求1至7任一所述的像素单元，其中，所述第三电极通过过孔与所述第一电极电连接。
  9. 根据权利要求3至8任一所述的像素单元，其中，所述像素单元还包括：发光元件，所述发光元件为有机发光二极管；
    其中，所述发光元件与所述驱动晶体管的第一极电连接。
  10. 根据权利要求1至9任一所述的像素单元，其中，所述薄膜晶体管还包括：开关晶体管；
    所述第一电极、所述第二电极和所述第三电极中的任一电极在所述衬底基板上的正投影，与所述开关晶体管的有源层在所述衬底基板上的正投影，所述开关晶体管的栅极在所述衬底基板上的正投影，以及所述开关晶体管的源漏极在所述衬底基板上的正投影均不重叠。
  11. 根据权利要求1至10任一所述的像素单元，其中，所述薄膜晶体管还包括：补偿晶体管；
    所述第一电极、所述第二电极和所述第三电极中的任一电极在所述衬底基板上的正投影，与所述补偿晶体管的有源层在所述衬底基板上的正投影，所述补偿晶体管的栅极在所述衬底基板上的正投影，以及所述补偿晶体管的源漏极在所述衬底基板上的正投影均不重叠。
  12. 根据权利要求1至11任一所述的像素单元，其中，所述存储电容还包括：位于每相邻两个所述电极之间的绝缘层。
  13. 根据权利要求1至12任一所述的像素单元，其中，所述像素单元为顶发射型像素单元，或，底发射型像素单元。
  14. 根据权利要求1至13任一所述的像素单元，其特征在于，所述第二电极与所述有源层位于同层，且材料相同；或者，所述第二电极与所述栅极位于同层，且材料相同。
  15. 根据权利要求1至14任一所述的像素单元，其特征在于，所述第三电极与所述源漏极的材料相同。
  16. 根据权利要求1至15任一所述的像素单元，其特征在于，所述像素单元还包括：位于所述第三电极远离所述衬底基板一侧且依次层叠的钝化层、平坦层、阳极和像素定义层，且所述阳极与所述源漏极电连接。
  17. 根据权利要求1至16任一所述的像素单元，其特征在于，所述有源层，所述栅极和所述源漏极沿远离所述衬底基板的方向依次层叠。
  18. 一种显示基板，其中，所述显示基板包括：衬底基板，以及位于所述衬底基板上且阵列排布的多个像素单元；
    其中，至少一个所述像素单元为如权利要求1至17任一所述的像素单元。
  19. 根据权利要求18所述的显示基板，其中，所述显示基板还包括：导线；
    其中，所述导线的一部分为所述像素单元包括的第一电极。
  20. 一种显示装置，其中，所述显示装置包括：驱动电路，以及如权利要求18或19所述的显示基板；
    所述驱动电路与所述显示基板中的像素单元连接，所述驱动电路用于为所 述像素单元包括的薄膜晶体管提供驱动信号。
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