WO2022107728A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2022107728A1
WO2022107728A1 PCT/JP2021/041957 JP2021041957W WO2022107728A1 WO 2022107728 A1 WO2022107728 A1 WO 2022107728A1 JP 2021041957 W JP2021041957 W JP 2021041957W WO 2022107728 A1 WO2022107728 A1 WO 2022107728A1
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Prior art keywords
peak
region
helium
chemical concentration
concentration
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PCT/JP2021/041957
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English (en)
French (fr)
Japanese (ja)
Inventor
祐一 原田
晴司 野口
典宏 小宮山
巧裕 伊倉
洋輔 桜井
啓久 鈴木
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP2022563746A priority Critical patent/JP7517466B2/ja
Priority to CN202180030596.8A priority patent/CN115443543A/zh
Publication of WO2022107728A1 publication Critical patent/WO2022107728A1/ja
Priority to US17/971,636 priority patent/US20230038712A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/617—Combinations of vertical BJTs and only diodes
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/18—Diffusion lifetime killers
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
    • H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors

Definitions

  • the present invention relates to a semiconductor device.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2008-135439
  • the semiconductor device may include a semiconductor substrate having a first conductive type drift region.
  • the semiconductor device may be provided between the drift region and the lower surface of the semiconductor substrate, and may include a first conductive type buffer region having a doping concentration higher than that of the drift region.
  • the buffer region may have two or more helium chemical concentration peaks located at different positions in the depth direction of the semiconductor substrate.
  • the helium chemical concentration of two or more helium chemical concentration peaks may be the same.
  • the buffer region may have a first helium chemical concentration peak and a second helium chemical concentration peak located farther from the lower surface of the semiconductor substrate than the first helium chemical concentration peak.
  • the distribution width of the second helium chemical concentration peak may be larger than the distribution width of the first helium chemical concentration peak.
  • the first helium chemical concentration peak may have a higher helium chemical concentration than the second helium chemical concentration peak.
  • the first helium chemical concentration peak may have a lower helium chemical concentration than the second helium chemical concentration peak.
  • the peak spacing between two adjacent helium chemical concentration peaks in the depth direction may be uniform in the buffer region.
  • Two or more helium chemical concentration peaks may be arranged with their respective peak intervals in the depth direction.
  • the first peak spacing may be larger than the second peak spacing at a position away from the lower surface of the semiconductor substrate than the first peak spacing.
  • the first peak spacing may be smaller than the second peak spacing at a position away from the lower surface of the semiconductor substrate than the first peak spacing.
  • the buffer region may have one or more hydrogen chemical concentration peaks.
  • Each helium chemical concentration peak may be arranged at a depth position different from that of any hydrogen chemical concentration peak.
  • the half-value full width of each helium chemical concentration peak may be smaller than the half-value full width of any hydrogen chemical concentration peak arranged away from the lower surface of the semiconductor substrate than each helium chemical concentration peak.
  • the buffer region may have two or more doping concentration peaks arranged at different positions in the depth direction of the semiconductor substrate.
  • the two or more doping concentration peaks may include the deepest doping concentration peak located farthest from the bottom surface of the semiconductor substrate.
  • the two or more helium chemical concentration peaks may be arranged between the deepest doping concentration peak and the lower surface of the semiconductor substrate.
  • the full width at half maximum of each helium chemical concentration peak may be 1 ⁇ m or less.
  • the buffer region may include a depletion layer edge position where the integrated concentration obtained by integrating the net doping concentration of the drift region and the buffer region reaches the critical integrated concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate.
  • the buffer region may have a first helium chemical concentration peak located on the lower surface side of the semiconductor substrate with respect to the depletion layer edge position.
  • the buffer region may have a second helium chemical concentration peak located on the upper surface side of the semiconductor substrate with respect to the depletion layer edge position.
  • the first helium chemical concentration peak may have a higher helium chemical concentration than the second helium chemical concentration peak.
  • the buffer region includes a first doping concentration peak, a second doping concentration peak located farther from the lower surface of the semiconductor substrate than the first doping concentration peak, and a lower surface of the semiconductor substrate than the second doping concentration peak. It may have a third doping concentration peak located away from.
  • the first helium chemical concentration peak may be located between the first doping concentration peak and the second doping concentration peak.
  • the second helium chemical concentration peak may be located between the second doping concentration peak and the third doping concentration peak.
  • the depletion layer edge position may be arranged in the range of the full width at half maximum of the second doping concentration peak.
  • the semiconductor device may include an upper surface side lifetime killer arranged on the upper surface side of the semiconductor substrate.
  • An example of the carrier concentration distribution and the helium chemical concentration distribution in the buffer region 20 of the comparative example is shown. It is a figure which shows the other example of the ee cross section. It is a figure which shows an example of the doping concentration distribution and the hydrogen chemical concentration distribution in the FF line of FIG. It is a figure which shows an example of the formation method of the buffer area 20. It is a figure which shows the cross-sectional shape of the collector area 22 which concerns on a comparative example. It is a figure which shows the result of the withstand voltage test of a semiconductor device. It is a figure which shows the result of the withstand voltage test of a semiconductor device. It is a figure which shows another example of a semiconductor device 100.
  • FIG. 21 It is a figure which shows another example of the manufacturing process of a semiconductor device 100. It is a figure which shows an example of a doping concentration distribution and a hydrogen chemical concentration distribution of the semiconductor device 100 shown in FIG. 21. It is a figure which shows the other example of the ee cross section. It is a figure which shows an example of the formation method of the buffer area 20 shown in FIG. 23.
  • one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper”, and the other side is referred to as “lower”.
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the “up” and “down” directions are not limited to the direction of gravity or the direction when the semiconductor device is mounted.
  • orthogonal coordinate axes of X-axis, Y-axis, and Z-axis Orthogonal axes only specify the relative positions of the components and do not limit a particular direction.
  • the Z axis does not limit the height direction with respect to the ground.
  • the + Z-axis direction and the ⁇ Z-axis direction are opposite to each other. When positive or negative is not described and is described as the Z-axis direction, it means the direction parallel to the + Z-axis and the -Z-axis.
  • the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are defined as the X axis and the Y axis. Further, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is defined as the Z axis.
  • the direction of the Z axis may be referred to as a depth direction. Further, in the present specification, the direction parallel to the upper surface and the lower surface of the semiconductor substrate including the X-axis and the Y-axis may be referred to as a horizontal direction.
  • the region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate may be referred to as the upper surface side.
  • the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate may be referred to as the lower surface side.
  • error When referred to as “same” or “equal” in the present specification, it may include a case where there is an error due to manufacturing variation or the like.
  • the error is, for example, within 10%.
  • the conductive type of the doping region doped with impurities is described as P type or N type.
  • an impurity may mean, in particular, either an N-type donor or a P-type acceptor, and may be referred to as a dopant.
  • doping means that a donor or acceptor is introduced into a semiconductor substrate to obtain a semiconductor showing an N-type conductive type or a semiconductor showing a P-type conductive type.
  • the doping concentration means the concentration of a donor or the concentration of an acceptor in a thermal equilibrium state.
  • the net doping concentration means the net concentration of the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge.
  • the donor concentration is N D and the acceptor concentration is NA
  • the net net doping concentration at any position is N D - NA .
  • the net doping concentration may be simply referred to as a doping concentration.
  • the donor has the function of supplying electrons to the semiconductor.
  • the acceptor has a function of receiving electrons from a semiconductor.
  • Donors and acceptors are not limited to the impurities themselves.
  • the VOH defect to which the pores (V), oxygen (O) and hydrogen (H) present in the semiconductor are bonded functions as a donor for supplying electrons.
  • VOH defects are sometimes referred to herein as hydrogen donors.
  • N-type bulk donors are distributed throughout the semiconductor substrate.
  • a bulk donor is a donor due to a dopant contained in the ingot substantially uniformly during the manufacture of the ingot that is the basis of the semiconductor substrate.
  • the bulk donor in this example is an element other than hydrogen.
  • Bulk donor dopants are, but are not limited to, for example phosphorus, antimony, arsenic, selenium or sulfur.
  • the bulk donor in this example is phosphorus.
  • Bulk donors are also included in the P-shaped region.
  • the semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by fragmenting the wafer.
  • the semiconductor ingot may be manufactured by any one of a Czochralski method (CZ method), a magnetic field application type Czochralski method (MCZ method), and a float zone method (FZ method).
  • the ingot in this example is manufactured by the MCZ method.
  • the oxygen concentration contained in the substrate manufactured by the MCZ method is 1 ⁇ 10 17 to 7 ⁇ 10 17 / cm 3 .
  • the oxygen concentration contained in the substrate manufactured by the FZ method is 1 ⁇ 10 15 to 5 ⁇ 10 16 / cm 3 .
  • the bulk donor concentration may be a chemical concentration of bulk donors distributed throughout the semiconductor substrate and may be between 90% and 100% of the chemical concentration.
  • the bulk donor concentration (D0) of the non-doping substrate is, for example, 1 ⁇ 10 10 / cm 3 or more and 5 ⁇ 10 12 / cm 3 or less.
  • the bulk donor concentration (D0) of the non-doping substrate is preferably 1 ⁇ 10 11 / cm 3 or more.
  • the bulk donor concentration (D0) of the non-doping substrate is preferably 5 ⁇ 10 12 / cm 3 or less.
  • Each concentration in the present invention may be a value at room temperature. As the value at room temperature, the value at 300 K (Kelvin) (about 26.9 ° C.) may be used as an example.
  • P + type or N + type in the present specification it means that the doping concentration is higher than that of P type or N type, and when described as P-type or N-type, it means that the doping concentration is higher than that of P type or N type. It means that the concentration is low. Further, when described as P ++ type or N ++ type in the present specification, it means that the doping concentration is higher than that of P + type or N + type.
  • the unit system of the present specification is an SI unit system unless otherwise specified. The unit of length may be displayed in cm, but various calculations may be performed after converting to meters (m).
  • the chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • SIMS secondary ion mass spectrometry
  • the net doping concentration described above can be measured by a voltage-capacity measurement method (CV method).
  • the carrier concentration measured by the spread resistance measurement method (SR method) may be used as the net doping concentration.
  • Carrier means charge carriers of electrons or holes.
  • the carrier concentration measured by the CV method or the SR method may be a value in a thermal equilibrium state.
  • the donor concentration is sufficiently higher than the acceptor concentration, so the carrier concentration in the region may be used as the donor concentration.
  • the carrier concentration in the region may be used as the acceptor concentration.
  • the doping concentration in the N-type region may be referred to as a donor concentration
  • the doping concentration in the P-type region may be referred to as an acceptor concentration.
  • the peak value may be used as the concentration of donor, acceptor or net doping in the region.
  • the concentration of the donor, the acceptor or the net doping is substantially uniform, the average value of the concentration of the donor, the acceptor or the net doping in the region may be used as the concentration of the donor, the acceptor or the net doping.
  • at Budapest time is used to indicate the concentration per unit volume. This unit is used for the donor or acceptor concentration in the semiconductor substrate, or the chemical concentration. The at Budapestms notation may be omitted.
  • the carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor.
  • the carrier mobility of the semiconductor substrate In the range where a current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state.
  • the decrease in carrier mobility occurs when carriers are scattered due to disorder of the crystal structure due to lattice defects or the like.
  • the reason why the carrier concentration decreases is as follows.
  • the SR method the spread resistance is measured, and the carrier concentration is converted from the measured value of the spread resistance. At this time, the mobility in the crystalline state is used as the carrier mobility.
  • the carrier concentration is calculated from the carrier mobility in the crystalline state even though the carrier mobility is lowered. Therefore, the value is lower than the actual carrier concentration, that is, the concentration of the donor or the acceptor.
  • the concentration of the donor or acceptor calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor.
  • the donor concentration of phosphorus or arsenic as a donor in a silicon semiconductor, or the acceptor concentration of boron (boron) as an acceptor is about 99% of these chemical concentrations.
  • the donor concentration of hydrogen as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • FIG. 1 is a top view showing an example of the semiconductor device 100.
  • FIG. 1 shows a position where each member is projected onto the upper surface of the semiconductor substrate 10. In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.
  • the semiconductor device 100 includes a semiconductor substrate 10.
  • the semiconductor substrate 10 is a substrate made of a semiconductor material.
  • the semiconductor substrate 10 is a silicon substrate.
  • the semiconductor substrate 10 has an end side 162 in a top view. When simply referred to as a top view in the present specification, it means that the semiconductor substrate 10 is viewed from the top surface side.
  • the semiconductor substrate 10 of this example has two sets of end sides 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either end 162. The Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.
  • the semiconductor substrate 10 is provided with an active portion 160.
  • the active portion 160 is a region in which a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates.
  • An emitter electrode is provided above the active portion 160, but it is omitted in FIG.
  • the active unit 160 is provided with at least one of a transistor unit 70 including a transistor element such as an IGBT and a diode unit 80 including a diode element such as a freewheeling diode (FWD).
  • a transistor unit 70 including a transistor element such as an IGBT and a diode unit 80 including a diode element such as a freewheeling diode (FWD).
  • the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10.
  • the active unit 160 may be provided with only one of the transistor unit 70 and the diode unit 80.
  • the symbol “I” is attached to the region where the transistor portion 70 is arranged, and the symbol “F” is attached to the region where the diode portion 80 is arranged.
  • the direction perpendicular to the arrangement direction in the top view may be referred to as a stretching direction (Y-axis direction in FIG. 1).
  • the transistor portion 70 and the diode portion 80 may each have a longitudinal length in the stretching direction. That is, the length of the transistor portion 70 in the Y-axis direction is larger than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is larger than the width in the X-axis direction.
  • the stretching direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.
  • the diode portion 80 has an N + type cathode region in a region in contact with the lower surface of the semiconductor substrate 10.
  • the region provided with the cathode region is referred to as a diode portion 80. That is, the diode portion 80 is a region that overlaps with the cathode region in the top view.
  • a P + type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the cathode region.
  • the diode portion 80 may also include an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring described later.
  • a collector area is provided on the lower surface of the extension area 81.
  • the transistor portion 70 has a P + type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor portion 70, a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10.
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10.
  • the semiconductor device 100 of this example has a gate pad 164.
  • the semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged in the vicinity of the end side 162.
  • the vicinity of the end side 162 refers to the region between the end side 162 and the emitter electrode in the top view.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • a gate potential is applied to the gate pad 164.
  • the gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160.
  • the semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, diagonal hatching is attached to the gate wiring.
  • the gate wiring of this example has an outer peripheral gate wiring 130 and an active side gate wiring 131.
  • the outer peripheral gate wiring 130 is arranged between the active portion 160 and the end side 162 of the semiconductor substrate 10 in a top view.
  • the outer peripheral gate wiring 130 of this example surrounds the active portion 160 in a top view.
  • the region surrounded by the outer peripheral gate wiring 130 in the top view may be the active portion 160.
  • the outer peripheral gate wiring 130 is connected to the gate pad 164.
  • the outer peripheral gate wiring 130 is arranged above the semiconductor substrate 10.
  • the outer peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.
  • the active side gate wiring 131 is provided in the active portion 160. By providing the active side gate wiring 131 in the active portion 160, it is possible to reduce the variation in the wiring length from the gate pad 164 in each region of the semiconductor substrate 10.
  • the active side gate wiring 131 is connected to the gate trench portion of the active portion 160.
  • the active side gate wiring 131 is arranged above the semiconductor substrate 10.
  • the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.
  • the active side gate wiring 131 may be connected to the outer peripheral gate wiring 130.
  • the active side gate wiring 131 of this example extends in the X-axis direction from one outer peripheral gate wiring 130 sandwiching the active portion 160 to the other outer peripheral gate wiring 130 so as to cross the active portion 160 substantially at the center in the Y-axis direction. It is provided.
  • the transistor portion 70 and the diode portion 80 may be alternately arranged in the X-axis direction in each divided region.
  • the semiconductor device 100 includes a temperature sense unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160. May be good.
  • a temperature sense unit (not shown) which is a PN junction diode made of polysilicon or the like
  • a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160. May be good.
  • the semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the end side 162 in a top view.
  • the edge terminal structure portion 90 of this example is arranged between the outer peripheral gate wiring 130 and the end side 162.
  • the edge termination structure 90 relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure 90 may include at least one of a guard ring, a field plate and a resurf provided in an annular shape surrounding the active portion 160.
  • FIG. 2 is an enlarged view of the region D in FIG.
  • the region D is a region including the transistor portion 70, the diode portion 80, and the active side gate wiring 131.
  • the semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10.
  • the gate trench portion 40 and the dummy trench portion 30 are examples of trench portions, respectively.
  • the semiconductor device 100 of this example includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10.
  • the emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.
  • An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in FIG.
  • a contact hole 54 is provided in the interlayer insulating film of this example so as to penetrate the interlayer insulating film. In FIG. 2, each contact hole 54 is hatched with diagonal lines.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15.
  • the emitter electrode 52 passes through the contact hole 54 and comes into contact with the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10. Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film.
  • the emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.
  • the active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film.
  • the active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction.
  • the active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.
  • the emitter electrode 52 is made of a material containing metal.
  • FIG. 2 shows a range in which the emitter electrode 52 is provided.
  • the region of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, for example, a metal alloy such as AlSi or AlSiCu.
  • the emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of the region formed of aluminum or the like.
  • the contact hole may have a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like.
  • the well region 11 is provided so as to overlap with the active side gate wiring 131.
  • the well region 11 is extended to a predetermined width even in a range that does not overlap with the active side gate wiring 131.
  • the well region 11 of this example is provided away from the end of the contact hole 54 in the Y-axis direction on the active side gate wiring 131 side.
  • the well region 11 is a second conductive type region having a higher doping concentration than the base region 14.
  • the base region 14 of this example is P-type, and the well region 11 is P + type.
  • Each of the transistor portion 70 and the diode portion 80 has a plurality of trench portions arranged in the arrangement direction.
  • the transistor portion 70 of this example one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the arrangement direction.
  • the diode portion 80 of this example is provided with a plurality of dummy trench portions 30 along the arrangement direction.
  • the diode portion 80 of this example is not provided with the gate trench portion 40.
  • the gate trench portion 40 of this example connects two straight line portions 39 (portion portions that are linear along the stretching direction) extending along a stretching direction perpendicular to the arrangement direction and two straight line portions 39. It may have a tip 41.
  • the stretching direction in FIG. 2 is the Y-axis direction.
  • the tip portion 41 is provided in a curved shape in a top view.
  • the dummy trench portion 30 is provided between the straight line portions 39 of the gate trench portion 40.
  • One dummy trench portion 30 may be provided between the straight line portions 39, and a plurality of dummy trench portions 30 may be provided.
  • the dummy trench portion 30 may have a linear shape extending in the stretching direction, and may have a straight portion 29 and a tip portion 31 as in the gate trench portion 40.
  • the semiconductor device 100 shown in FIG. 2 includes both a linear dummy trench portion 30 having no tip portion 31 and a dummy trench portion 30 having a tip portion 31.
  • the diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • the ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in the top view. That is, at the end of each trench in the Y-axis direction, the bottom of each trench in the depth direction is covered with the well region 11. Thereby, the electric field concentration at the bottom of each trench can be relaxed.
  • a mesa part is provided between each trench part in the arrangement direction.
  • the mesa portion refers to a region sandwiched between trench portions inside the semiconductor substrate 10.
  • the upper end of the mesa portion is the upper surface of the semiconductor substrate 10.
  • the depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion.
  • the mesa portion of this example is provided on the upper surface of the semiconductor substrate 10 by extending in the stretching direction (Y-axis direction) along the trench.
  • the transistor portion 70 is provided with a mesa portion 60
  • the diode portion 80 is provided with a mesa portion 61.
  • a mesa portion when simply referred to as a mesa portion in the present specification, it refers to each of the mesa portion 60 and the mesa portion 61.
  • a base region 14 is provided in each mesa section. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is referred to as the base region 14-e.
  • FIG. 2 shows the base region 14-e arranged at one end of each mesa portion in the stretching direction, but the base region 14-e is also arranged at the other end portion of each mesa portion. Has been done.
  • Each mesa portion may be provided with at least one of a first conductive type emitter region 12 and a second conductive type contact region 15 in a region sandwiched between base regions 14-e in a top view.
  • the emitter region 12 of this example is N + type
  • the contact region 15 is P + type.
  • the emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.
  • the mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the mesa portion 60 in contact with the gate trench portion 40 may be provided with an exposed contact region 15 on the upper surface of the semiconductor substrate 10.
  • Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion in the X-axis direction to the other trench portion.
  • the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the stretching direction (Y-axis direction) of the trench portion.
  • the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the stretching direction (Y-axis direction) of the trench portion.
  • the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.
  • the emitter region 12 is not provided in the mesa portion 61 of the diode portion 80.
  • a base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61.
  • a contact region 15 may be provided in contact with the respective base regions 14-e in the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61.
  • a base region 14 may be provided in a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61.
  • the base region 14 may be arranged over the entire region sandwiched between the contact regions 15.
  • a contact hole 54 is provided above each mesa portion.
  • the contact hole 54 is arranged in a region sandwiched between the base regions 14-e.
  • the contact hole 54 of this example is provided above each region of the contact region 15, the base region 14, and the emitter region 12.
  • the contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11.
  • the contact hole 54 may be arranged at the center of the mesa portion 60 in the arrangement direction (X-axis direction).
  • an N + type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10.
  • a P + type collector region 22 may be provided on the lower surface of the semiconductor substrate 10 in a region where the cathode region 82 is not provided.
  • the cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.
  • the cathode region 82 is arranged away from the well region 11 in the Y-axis direction.
  • the withstand voltage can be improved by securing a distance between the P-shaped region (well region 11) having a relatively high doping concentration and being formed to a deep position and the cathode region 82.
  • the end portion of the cathode region 82 of this example in the Y-axis direction is arranged farther from the well region 11 than the end portion of the contact hole 54 in the Y-axis direction.
  • the end of the cathode region 82 in the Y-axis direction may be located between the well region 11 and the contact hole 54.
  • FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2.
  • the ee cross section is an XZ plane that passes through the emitter region 12 and the cathode region 82.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the cross section.
  • the interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10.
  • the interlayer insulating film 38 is a film containing at least one layer of an insulating film such as silicate glass to which impurities such as boron and phosphorus are added, a thermal oxide film, and other insulating films.
  • the interlayer insulating film 38 is provided with the contact hole 54 described with reference to FIG.
  • the emitter electrode 52 is provided above the interlayer insulating film 38.
  • the emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38.
  • the collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum.
  • the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.
  • the semiconductor substrate 10 has an N-type or N-type drift region 18.
  • the drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.
  • the mesa portion 60 of the transistor portion 70 is provided with an N + type emitter region 12 and a P-type base region 14 in order from the upper surface 21 side of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14.
  • the mesa portion 60 may be provided with an N + type storage region 16.
  • the storage area 16 is arranged between the base area 14 and the drift area 18.
  • the emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40.
  • the emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60.
  • the emitter region 12 has a higher doping concentration than the drift region 18.
  • the base region 14 is provided below the emitter region 12.
  • the base region 14 of this example is provided in contact with the emitter region 12.
  • the base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.
  • the storage area 16 is provided below the base area 14.
  • the accumulation region 16 is an N + type region having a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18.
  • IE effect carrier injection promoting effect
  • the storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.
  • the mesa portion 61 of the diode portion 80 is provided with a P-type base region 14 in contact with the upper surface 21 of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14.
  • the storage region 16 may be provided below the base region 14.
  • an N + type buffer region 20 may be provided below the drift region 18.
  • the doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18.
  • the buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18.
  • the doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Further, as the doping concentration in the drift region 18, the average value of the doping concentrations in the region where the doping concentration distribution is substantially flat may be used.
  • the buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10.
  • the concentration peak of the buffer region 20 may be provided at the same depth position as the chemical concentration peak of hydrogen (proton) or phosphorus, for example.
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P + type collector region 22 and the N + type cathode region 82.
  • the depth position of the upper end of the buffer area 20 is Zf.
  • the depth position Zf may be a position where the doping concentration is higher than the doping concentration in the drift region 18.
  • a P + type collector area 22 is provided below the buffer area 20.
  • the acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14.
  • the collector region 22 may include the same acceptors as the base region 14, or may include different acceptors.
  • the acceptor of the collector region 22 is, for example, boron.
  • an N + type cathode region 82 is provided below the buffer region 20.
  • the donor concentration in the cathode region 82 is higher than the donor concentration in the drift region 18.
  • the donor of the cathode region 82 is, for example, hydrogen or phosphorus.
  • the elements that serve as donors and acceptors in each region are not limited to the above-mentioned examples.
  • the collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24.
  • the collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least one of the emitter region 12, the contact region 15 and the storage region 16 is provided, each trench portion also penetrates these doping regions and reaches the drift region 18.
  • the fact that the trench portion penetrates the doping region is not limited to those manufactured in the order of forming the doping region and then forming the trench portion. Those in which the doping region is formed between the trench portions after the trench portion is formed are also included in those in which the trench portion penetrates the doping region.
  • the transistor portion 70 is provided with a gate trench portion 40 and a dummy trench portion 30.
  • the diode portion 80 is provided with a dummy trench portion 30 and is not provided with a gate trench portion 40.
  • the boundary between the diode portion 80 and the transistor portion 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.
  • the gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 provided on the upper surface 21 of the semiconductor substrate 10.
  • the gate insulating film 42 is provided so as to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is provided inside the gate trench inside the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate conductive portion 44 may be provided longer than the base region 14 in the depth direction.
  • the gate trench portion 40 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.
  • the gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed on the surface layer of the interface of the base region 14 in contact with the gate trench portion 40.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section.
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10.
  • the dummy conductive portion 34 is electrically connected to the emitter electrode 52.
  • the dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10.
  • the dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.
  • the dummy conductive portion 34 is formed of a conductive material such as polysilicon.
  • the dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.
  • the gate trench portion 40 and the dummy trench portion 30 of this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.
  • the bottom of the dummy trench portion 30 and the gate trench portion 40 may be curved downward (curved in cross section). In the present specification, the depth position of the lower end of the gate trench portion 40 is Zt.
  • the upper surface side lifetime killer 210 may be provided on the upper surface 21 side of the semiconductor substrate 10.
  • the upper surface side lifetime killer 210 is a recombination center such as a lattice defect locally formed in the depth direction.
  • the peak position of the density distribution of the lifetime killer in the depth direction is schematically shown by a cross. In the present specification, the peak position is described as the position of the lifetime killer.
  • the cross marks are arranged discretely in the X-axis direction, but unless otherwise specified, the lifetime killer is uniformly provided in the X-axis direction.
  • the upper surface side lifetime killer 210 can be formed by injecting particles such as helium into a predetermined depth position from the upper surface 21 of the semiconductor substrate 10.
  • the concentration peak of particles such as helium may be arranged at the same depth position as the upper surface side lifetime killer 210.
  • the upper surface side lifetime killer 210 may be arranged below each trench portion. Further, it is preferable that the upper surface side lifetime killer 210 is provided at a position that does not overlap with the gate trench portion 40 in the upper surface view. As a result, particles such as helium can be injected to form the upper surface side lifetime killer 210 without damaging the gate insulating film 42.
  • the upper surface side lifetime killer 210 of this example is provided on the entire diode portion 80 in the upper surface view.
  • the upper surface side lifetime killer 210 in FIG. 3 is not provided in the transistor portion 70, but in another example, the upper surface side lifetime killer 210 may be provided in a part of the region of the transistor portion 70.
  • the lower surface side lifetime killer 220 is provided on the lower surface 23 side of the semiconductor substrate 10.
  • the lower surface side lifetime killer 220 may be formed by injecting particles such as helium from the lower surface 23 side of the semiconductor substrate 10.
  • a plurality of bottom surface side lifetime killer 220s may be arranged at different positions in the depth direction.
  • the first lower surface side lifetime killer 220-1 and the second lower surface side lifetime killer 220-2 are arranged at different depth positions.
  • the lower surface side lifetime killer 220 may be provided at three or more depth positions.
  • a peak of helium chemical concentration may be provided at the same depth position as each lower surface side lifetime killer 220.
  • Two or more lower surface side lifetime killer 220s may be provided in the buffer area 20. This makes it easier to control the distribution of the lifetime killer in the buffer area 20. Therefore, the carrier lifetime can be controlled accurately.
  • the lower surface side lifetime killer 220 may be provided on the entire diode portion 80 in the upper view. Further, the lower surface side lifetime killer 220 may be provided on the entire transistor portion 70 in the upper view. The bottom surface side lifetime killer 220 may be provided on the entire active portion 160 in the top view, or may be provided on the entire semiconductor substrate 10 in the top view. The first lower surface side lifetime killer 220-1 and the second lower surface side lifetime killer 220-2 may be provided in the same range in top view.
  • FIG. 4A is a diagram showing an example of a doping concentration distribution, a hydrogen chemical concentration distribution, a helium chemical concentration distribution, and a recombination center concentration distribution in the FF line of FIG.
  • the central position of the semiconductor substrate 10 in the depth direction is Zc. That is, the region on the upper surface 21 side of the semiconductor substrate 10 is the region between the upper surface 21 and the central position Zc, and the region on the lower surface 23 side is the region between the lower surface 23 and the central position Zc.
  • the emitter region 12 contains an N-type dopant such as phosphorus.
  • the base region 14 contains a P-type dopant such as boron.
  • the storage region 16 contains an N-type dopant such as phosphorus or hydrogen.
  • the doping concentration distribution may have concentration peaks in the emitter region 12, the base region 14, and the storage region 16, respectively.
  • the drift region 18 is a region where the doping concentration is almost flat.
  • the doping concentration Dd of the drift region 18 may be the same as the bulk donor concentration of the semiconductor substrate 10, and may be higher than the bulk donor concentration.
  • the buffer region 20 of this example has a plurality of doping concentration peaks 25-1, 25-2, 25-3, 25-4 in the doping concentration distribution.
  • Each doping concentration peak 25 may be formed by locally injecting hydrogen ions.
  • each doping concentration peak 25 may be formed by injecting an N-type dopant such as phosphorus.
  • the collector region 22 contains a P-type dopant such as boron.
  • the cathode region 82 shown in FIG. 3 contains an N-type dopant such as phosphorus.
  • the hydrogen chemical concentration distribution of this example has a plurality of local hydrogen chemical concentration peaks 103 in the buffer region 20.
  • the hydrogen chemical concentration peak 103 of this example is provided at the same depth position as the doping concentration peak 25.
  • the fact that two peaks are provided at the same depth position means that the vertices of the other peak are arranged within the range of the full width at half maximum of one peak. If the concentration of the hydrogen chemical concentration peak 103 is not sufficiently high, a clear doping concentration peak 25 may not be observed at the same depth position as the hydrogen chemical concentration peak 103.
  • the hydrogen chemical concentration of this example drops sharply immediately after entering the drift region 18 from the buffer region 20. Therefore, almost no VOH defect is formed in the drift region 18.
  • hydrogen may diffuse into the interior of the drift region 18 to form VOH defects.
  • the doping concentration of the drift region 18 will be higher than the bulk donor concentration.
  • the buffer region 20 has two or more helium chemical concentration peaks 221 arranged at different positions in the depth direction of the semiconductor substrate 10.
  • the first helium chemical concentration peak 221-1 and the second helium chemical concentration peak 221-2 are provided in the buffer region 20.
  • the second helium chemical concentration peak 221-2 is located farther from the lower surface 23 than the first helium chemical concentration peak 221-1.
  • the lower surface side lifetime killer 220 is formed in the vicinity of each helium chemical concentration peak 221.
  • the bottom lifetime killer 220 may be a recombination center that promotes carrier recombination.
  • the recombination center may be a lattice defect.
  • the lattice defect may be mainly a vacancy such as a single atom vacancy (V) or a double atom vacancy (VV), may be a dislocation, may be an interstitial atom, may be a transition metal, or the like. ..
  • V single atom vacancy
  • VV double atom vacancy
  • VV double atom vacancy
  • a dislocation may be an interstitial atom
  • an atom adjacent to a vacancies has a dangling bond.
  • lattice defects may include donors and acceptors, but in the present specification, lattice defects mainly composed of vacancies may be referred to as vacancies-type lattice defects, vacancies-type defects, or simply lattice defects.
  • a lattice defect may be referred to simply as a recombination center or a lifetime killer as a recombination center that contributes to carrier recombination.
  • the lifetime killer may be formed by injecting helium ions into the semiconductor substrate 10. Since the lifetime killer formed by injecting helium may be terminated by hydrogen existing in the buffer region 20, the depth position of the density peak of the lifetime killer and the depth of the helium chemical concentration peak 221 It may not match the position.
  • 3 He or 4 He may be injected into each depth position.
  • 3He is a helium isotope containing two protons and one neutron.
  • 4He is a helium isotope containing two protons and two neutrons.
  • the half-price width in the depth direction of the concentration peak of the helium chemical concentration can be made smaller.
  • FIG. 4B is a diagram showing the relationship between the ion injection depth (Rp) and the acceleration energy required for injection.
  • Rp ion injection depth
  • helium ions are directly injected into the silicon semiconductor substrate 10 without passing through a cushioning material.
  • the horizontal axis is the range Rp ( ⁇ m)
  • the vertical axis is the acceleration energy E (eV) required for injection.
  • E acceleration energy required for injection.
  • an example of 3 He is shown by a solid line
  • an example of 4 He is shown by a broken line.
  • x log 10 (Rp) and y be log 10 (E).
  • E the relationship between the range Rp and the acceleration energy E may be given by the equation (1).
  • y 4.52505E-03x 6-4.71471E -02x 5 + 1.67185E-01x 4-1.72038E -01x 3-2.92723E -01x 2 + 1.39782E + 00x + 5.33858E + 00 ... Equation (1) )
  • EA is 10- A
  • E + A is 10 A.
  • E be the acceleration energy calculated by substituting the actual range Rp'at the time of manufacturing the semiconductor device 100 into the equation (1). If the actual acceleration energy E'at the time of manufacture is within ⁇ 20% of the acceleration energy E calculated from the equation (1), it may be considered that 3 He is used.
  • the relationship between the range Rp and the acceleration energy E may be given by the equation (2).
  • y 2.90157E-03x 6-3.66593E -02x 5 + 1.59363E-01x 4-2.31938E - 01x 3-2.000999E-01x 2 + 1.45891E + 00x + 5.27160E + 00 ... Equation (2) ) If the actual acceleration energy E'at the time of manufacture is within ⁇ 20% of the acceleration energy E calculated from the equation (2) using the actual range Rp', it is considered that 4 He is used. good.
  • the value in the region where the range Rp is 8 ⁇ m to 10 ⁇ m is set as the boundary value, and when the range Rp is equal to or more than the boundary value, the acceleration energy of 4 He is higher than the acceleration energy of 3 He. Is also about 10% higher.
  • the acceleration energy of 3He is about 10% higher than the acceleration energy of 4He. It is presumed that the balance between electron stopping power and nuclear stopping power changes depending on the number of isotope neutrons.
  • the range Rp is 10 ⁇ m or less, 4 He may be used. This makes it possible to inject helium ions with an acceleration energy that is about 10% smaller. If the range Rp is greater than 10 ⁇ m, 3 He may be used.
  • FIG. 4C is a diagram showing the relationship between the ion injection depth (Rp) and the struggling ( ⁇ Rp, standard deviation) in the injection direction.
  • the injection direction in this example is the depth direction of the semiconductor substrate 10.
  • helium ions are directly injected into the silicon semiconductor substrate 10 without passing through the cushioning material.
  • the horizontal axis is the range Rp ( ⁇ m)
  • the vertical axis is the struggling ⁇ Rp ( ⁇ m).
  • an example of 3 He is shown by a solid line
  • an example of 4 He is shown by a broken line.
  • the struggling ⁇ Rp may be calculated assuming that the helium concentration distribution is a Gaussian distribution.
  • the struggling ⁇ Rp may be a distance (distribution width) between two points having a concentration of 0.60653 times the concentration peak value, or may be a distance between two points having a concentration of 0.6 times the concentration peak value. ..
  • the distance between the inflection points such as the minimum value of the concentration distribution may be set as the struggling ⁇ Rp.
  • ⁇ Rp be the struggling calculated by substituting the actual range Rp'at the time of manufacturing the semiconductor device 100 into the equation (3). If the actual struggling ⁇ Rp'at the time of manufacture is within ⁇ 20% of the struggling ⁇ Rp calculated from the equation (3), it may be considered that 3 He is used.
  • the actual struggling ⁇ Rp' preferably does not contain the diffusion of helium due to thermal annealing.
  • the actual struggling ⁇ Rp' may be a value measured after the injection of helium and before the thermal annealing, or may be a value measured after the thermal annealing minus the diffusion component of helium. ..
  • the relationship between the range Rp and the struggling ⁇ Rp may be given by the equation (4).
  • y 3.1234E-03x 6-9.20762E - 03x 5-6.13612E-02x 4 + 2.34304E-01x 3 + 3.88591E-02x 2 + 2.2295E-01x-8.10967E-01 ... Equation (4) If the actual struggling ⁇ Rp'at the time of manufacture is within ⁇ 20% of the struggling ⁇ Rp calculated from the equation (4) using the actual range Rp', it is considered that 4 He is used. good.
  • the actual struggling ⁇ Rp' preferably does not contain the diffusion of helium due to thermal annealing.
  • the range Rp is a value in the region of 10 to 20 ⁇ m as the boundary value and the range Rp is equal to or less than the boundary value
  • the 3 He struggling ⁇ Rp is better than the 4 He struggling ⁇ Rp. It is about 10% smaller than that.
  • the range Rp is equal to or greater than the boundary value
  • the struggling ⁇ Rp is almost equal between 3 He and 4 He. It is presumed that the balance between electron stopping power and nuclear stopping power changes depending on the number of isotope neutrons.
  • the range Rp when the range Rp is 20 ⁇ m or less, 3 He may be used. This makes it possible to make the struggling ⁇ Rp smaller by about 10%.
  • the difference of about 10% in the struggling ⁇ Rp has a sufficiently small difference in the helium chemical concentration distribution or the electrical characteristics, even when the range Rp is 20 ⁇ m or less, the stra is 3 He and 4 He. Gling ⁇ Rp may be considered to be approximately equal.
  • the helium atom injected into the semiconductor substrate 10 may be 3 He or 4 He.
  • the full width at half maximum of the helium chemical concentration peak 221 when 4 He is injected is 1 ⁇ m or less.
  • the full width at half maximum of the helium chemical concentration peak 221 may be 0.5 ⁇ m or less.
  • the total concentration of the lower surface side lifetime killer 220 can be maintained high. Therefore, the lifetime of the carrier can be shortened and the tail current can be suppressed at the time of turn-off of the semiconductor device 100 or the like.
  • the acceleration energy E of 3 He is about 20 MeV or more (range Rp is 270 ⁇ m or more), and the struggling ⁇ Rp is 10 ⁇ m or more.
  • the acceleration energy E of 4 He is about 21 MeV or more (range Rp is 250 ⁇ m or more), and the struggling ⁇ Rp is 10 ⁇ m or more.
  • the full width at half maximum of the helium chemical concentration peak 221 cannot be made sufficiently smaller than the width of the buffer region 20 in the depth direction. Therefore, VOH defects are formed in a wide range of the buffer region 20, and the doping concentration distribution fluctuates. Therefore, the electric field may be locally concentrated in the buffer region 20, and the short-circuit current withstand may decrease.
  • the acceleration energy E when injecting any of 3 He and 4 He, the acceleration energy E may be 20 MeV or less, and may be 10 MeV or less.
  • the acceleration energy E of at least one or more or two or more helium chemical concentration peaks 221 among the plurality of helium chemical concentration peaks 221 may be 10 MeV or less, and may be 5 MeV or less.
  • FIG. 5A is a diagram showing an example of a doping concentration distribution, a hydrogen chemical concentration distribution, a helium chemical concentration distribution, and a recombination center concentration distribution in the buffer region 20. Each concentration distribution may be similar to each concentration distribution described in FIG. 4A.
  • the doping concentration distribution of this example has doping concentration peaks 25-1, 25-2, 25-3, and 25-4 in order from the lower surface 23 side of the semiconductor substrate 10.
  • the doping concentration peak 25-4 is an example of the deepest doping concentration peak arranged farthest from the lower surface 23.
  • the depth positions of the respective doping concentration peaks 25 are set to Zd1, Zd2, Zd3, and Zd4 in order from the lower surface 23 side. Each depth position Zd indicates the distance from the lower surface 23.
  • any doping concentration peak 25 does not have to be a clear peak.
  • the inflection point (kink) of the slope of the doping concentration distribution may be set as the doping concentration peak 25.
  • the doping concentration peak 25-1 may be the doping concentration peak 25 having the maximum concentration value.
  • the doping concentration peak 25-2 may be the doping concentration peak 25 having the second highest concentration value.
  • the doping concentration peak 25-3 may be the doping concentration peak 25 having the smallest concentration value.
  • the doping concentration peak 25-4 may be a doping concentration peak 25 having a higher concentration than the doping concentration peak 25-3.
  • the hydrogen chemical concentration distribution of this example has hydrogen chemical concentration peaks 103-1, 103-2, 103-3, 103-4 in order from the lower surface 23 side of the semiconductor substrate 10.
  • the depth positions of the respective hydrogen chemical concentration peaks 103 are Zh1, Zh2, Zh3, and Zh4 in order from the lower surface 23 side.
  • Each depth position Zh indicates the distance from the lower surface 23.
  • the depth position Zdk may be the same as the depth position Zhk. However, k is an integer from 1 to 4.
  • the hydrogen chemical concentration peak 103-1 may be the hydrogen chemical concentration peak 103 having the maximum concentration value.
  • the hydrogen chemical concentration peak 103-2 may be the hydrogen chemical concentration peak 103 having the second largest concentration value.
  • the hydrogen chemical concentration peak 103-3 may be the hydrogen chemical concentration peak 103 having the smallest concentration value.
  • the hydrogen chemical concentration peak 103-4 may be a hydrogen chemical concentration peak 103 having a higher concentration than the hydrogen chemical concentration peak 103-3.
  • the helium chemical concentration distribution of this example has a first helium chemical concentration peak 221-1 and a second helium chemical concentration peak 221-2 in order from the lower surface 23 side of the semiconductor substrate 10.
  • the depth position of each helium chemical concentration peak 221 is set to Zk1 and Zk2 in order from the lower surface 23 side.
  • Each depth position Zk indicates the distance from the lower surface 23.
  • the concentration values of the respective helium chemical concentration peaks 221 are set to Pk1 and Pk2 in order from the lower surface 23 side.
  • Two or more helium chemical concentration peaks 221 are arranged between the doping concentration peak 25-4, which is the deepest doping concentration peak, and the lower surface 23 of the semiconductor substrate 10. At least one helium chemical concentration peak 221 may be located between the depth positions Zd1 and Zd2. In this example, all helium chemical concentration peaks 221 are located between the depth positions Zd1 and Zd2.
  • the full width at half maximum of the helium chemical concentration peak 221-2 may be larger than the full width at half maximum of the helium chemical concentration peak 221-1.
  • the full width at half maximum of the helium chemical concentration peak 221-1 and the helium chemical concentration 221-2 may be different depending on the difference in acceleration energy.
  • a plurality of bottom surface side lifetime killer 220s can be arranged in the vicinity of the collector region 22.
  • FIG. 5B is a diagram showing an example of a doping concentration distribution, a hydrogen chemical concentration distribution, a helium chemical concentration distribution, and a recombination center concentration distribution in the buffer region 20.
  • the helium chemical concentration distribution and the recombination center concentration distribution are different from the example of FIG. 5A.
  • Other distributions may be similar to the example in FIG. 5A.
  • the buffer region 20 of this example has one helium chemical concentration peak 221-0 and one bottom surface lifetime killer 220-0.
  • the position of the helium chemical concentration peak 221-0 in the depth direction is Zk0, and the concentration is Pk0.
  • the depth position Zk0 of the helium chemical concentration peak 221-0 is arranged between the depth positions Zk1 and Zk2.
  • a recombination center concentration peak (bottom side lifetime killer 220-0) is arranged in the vicinity of the depth position Zk0.
  • the concentration Pk0 of the helium chemical concentration peak 221-0 may be higher than any of Pk1 and Pk2.
  • the bottom surface lifetime killer 220-0 may also have a higher concentration than any of the bottom surface lifetime killer 220-1 and 220-2.
  • the recombination center functions as a carrier generation center.
  • the leakage current increases, the heat generation of the semiconductor device is promoted, the temperature of the semiconductor device rises, and the withstand capacity such as turn-off may decrease.
  • the peak concentration of the helium chemical concentration (rebinding center concentration) can be reduced by using a plurality of lower surface side lifetime killer 220s.
  • the concentration of the carrier generation center can be reduced, the leakage current can be reduced, the temperature rise of the semiconductor device can be suppressed, and the withstand capacity such as turn-off can be increased. Further, it is possible to suppress the injection of hole carriers from the collector region 22 into the drift region 18.
  • Zk1 may be at least half the distance (Zd2-Zd1).
  • the distance between adjacent helium chemical concentration peaks 221 in the depth direction (Zk2-Zk1 in this example) may be 2 ⁇ m or more, 3 ⁇ m or more, 4 ⁇ m or more, and 5 ⁇ m or more. You may.
  • the concentration value Pk of each helium chemical concentration peak 221 may be the same. In another example, any concentration value Pk may be different from the other concentration value Pk.
  • the injection dose of helium ion corresponding to each helium chemical concentration peak 221 may be 1 ⁇ 10 11 (/ cm 2 ) or more, 3 ⁇ 10 11 (/ cm 2 ) or more, and 1 ⁇ . It may be 10 12 (/ cm 2 ) or more.
  • the injection dose of helium ion corresponding to each helium chemical concentration peak 221 may be 1 ⁇ 10 13 (/ cm 2 ) or less, 3 ⁇ 10 12 (/ cm 2 ) or less, and 1 ⁇ . It may be 10 12 (/ cm 2 ) or less.
  • each helium chemical concentration peak 221 may be arranged at a depth position different from that of any hydrogen chemical concentration peak 103. That is, the depth position Zk of the apex of each helium chemical concentration peak 221 is not included in the full width at half maximum of any hydrogen chemical concentration peak 103. This prevents the lifetime killer formed by injecting helium from being terminated by hydrogen, and makes it easier to maintain the concentration of the bottom lifetime killer 220.
  • the concentration value Pk of each helium chemical concentration peak 221 may increase as the distance from the depth position Zh of the hydrogen chemical concentration peak 103 increases. As a result, it is possible to suppress the formation of VOH defects in the lifetime killer formed by helium injection, and it is possible to suppress fluctuations in the shape of the doping concentration distribution in the buffer region 20.
  • the doping concentration distribution may have a valley portion 35 at the same depth position as any helium chemical concentration peak 221.
  • the valley portion 35 is a region where the doping concentration shows a minimum value.
  • the valley portion 35 is omitted at the same depth position as the helium chemical concentration peak 221.
  • the valley portion 35 may be provided.
  • FIG. 6 is a diagram showing another example of the helium chemical concentration distribution and the recombination center concentration distribution in the buffer region 20.
  • the doping concentration distribution and the hydrogen chemical concentration distribution in FIG. 6 are the same as the example of FIG. 5A.
  • the helium chemical concentration distribution of this example is, in order from the lower surface 23 side of the semiconductor substrate 10, the first helium chemical concentration peak 221-1, the second helium chemical concentration peak 221-2, and the third helium chemical concentration peak 221.
  • the depth position of each helium chemical concentration peak 221 is set to Zk1, Zk2, and Zk3 in order from the lower surface 23 side.
  • the concentration value of each helium chemical concentration peak 221 is set to Pk1, Pk2, and Pk3 in order from the lower surface 23 side.
  • the recombination center concentration has a distribution similar to that of the helium chemical concentration.
  • all the helium chemical concentration peaks 221 are arranged between the depth positions Zd1 and Zd2.
  • any helium chemical concentration peak 221 may be located in the other region of the buffer region 20.
  • the first helium chemical concentration peak 221-1 may have a higher concentration value Pk than at least one of the second helium chemical concentration peak 221-2 and the third helium chemical concentration peak 223-1.
  • the first helium chemical concentration peak 221-1 may be the helium chemical concentration peak 221 having the maximum concentration value Pk. Further, the concentration value Pk of the helium chemical concentration peak 221 may become smaller as the distance from the lower surface 23 of the semiconductor substrate 10 increases. Further, the helium chemical concentration peak 221 may have a larger struggling ⁇ Rp or full width at half maximum as the distance from the lower surface 23 of the semiconductor substrate 10 increases.
  • the relative magnitude relationship of the concentration of each lower surface side lifetime killer 220 may be the same as the relative magnitude relationship of the concentration of the corresponding helium chemical concentration peak 221. That is, the higher the concentration of the corresponding helium chemical concentration peak 221 is, the higher the concentration of the lower surface lifetime killer 220 may be.
  • the high-concentration lower surface side lifetime killer 220 is arranged in the vicinity of the lower surface 23. Therefore, it is possible to suppress the injection of hole carriers from the semi-collector region 22 into the drift region 18. In addition, it is possible to suppress an increase in leakage current and improve the withstand capacity at the time of turn-off or the like.
  • FIG. 7 is a diagram showing another example of the helium chemical concentration distribution and the recombination center concentration distribution in the buffer region 20.
  • the doping concentration distribution and the hydrogen chemical concentration distribution in FIG. 7 are the same as the example of FIG. 5A.
  • the helium chemical concentration distribution of this example differs from the example of FIG. 6 in the relative magnitude relationship of the concentrations of the respective helium chemical concentration peaks 221.
  • Other structures are the same as in the example of FIG.
  • the recombination center concentration has a distribution similar to that of the helium chemical concentration.
  • the first helium chemical concentration peak 221-1 may have a lower concentration value Pk than at least one of the second helium chemical concentration peak 221-2 and the third helium chemical concentration peak 223-1.
  • the first helium chemical concentration peak 221-1 may be the helium chemical concentration peak 221 having the smallest concentration value Pk. Further, the concentration value Pk of the helium chemical concentration peak 221 may become larger as the distance from the lower surface 23 of the semiconductor substrate 10 increases. Further, the helium chemical concentration peak 221 may have a larger struggling ⁇ Rp or full width at half maximum as the distance from the lower surface 23 of the semiconductor substrate 10 increases.
  • the high concentration lower surface side lifetime killer 220 is arranged in the vicinity of the drift region 18. Therefore, when the semiconductor device 100 is turned off or the like, the lifetime of the carrier flowing from the drift region 18 to the lower surface 23 side can be shortened. Therefore, the period in which the tail current flows can be shortened. In addition, it is possible to suppress an increase in leakage current and improve the withstand capacity at the time of turn-off or the like.
  • FIG. 8 is a diagram showing another example of the helium chemical concentration distribution and the recombination center concentration distribution in the buffer region 20.
  • the doping concentration distribution and the hydrogen chemical concentration distribution in FIG. 8 are the same as the example of FIG. 5A.
  • the peak interval between the helium chemical concentration peak 221-k and the helium chemical concentration peak 221- (k + 1) in the depth direction is Lk (L1 and L2 in FIG. 8).
  • Other structures are identical to any of the examples described in FIGS. 5A-7.
  • the peak spacing (L1 and L2 in FIG. 8) of two adjacent helium chemical concentration peaks 221 in the depth direction may be uniform in the buffer region 20.
  • the recombination center concentration has a distribution similar to that of the helium chemical concentration.
  • FIG. 9 is a diagram showing another example of the helium chemical concentration distribution and the recombination center concentration distribution in the buffer region 20.
  • the doping concentration distribution and the hydrogen chemical concentration distribution in FIG. 9 are the same as the example of FIG. 5A.
  • each peak interval Lk is different from the example of FIG.
  • Other structures are the same as in the example of FIG.
  • the first peak interval L1 is smaller than the second peak interval L2 at a position farther from the lower surface 23 than the first peak interval L1 (L1 ⁇ L2). That is, in the buffer region 20, the closer to the lower surface 23, the higher the density of the helium chemical concentration peak 221.
  • the recombination center concentration has a distribution similar to that of the helium chemical concentration.
  • FIG. 10A is a diagram showing other examples of the helium chemical concentration distribution and the recombination center concentration distribution in the buffer region 20.
  • the doping concentration distribution and the hydrogen chemical concentration distribution in FIG. 10A are the same as the example of FIG. 5A.
  • each peak interval Lk is different from the example of FIG.
  • Other structures are the same as in the example of FIG.
  • the first peak interval L1 is larger than the second peak interval L2 (L1> L2). That is, in the buffer region 20, the closer to the drift region 18, the higher the density of the helium chemical concentration peak 221.
  • the recombination center concentration has a distribution similar to that of the helium chemical concentration.
  • many lower surface side lifetime killer 220s can be formed in the vicinity of the drift region 18. Therefore, when the semiconductor device 100 is turned off or the like, the lifetime of the carrier flowing from the drift region 18 to the lower surface 23 side can be shortened. Therefore, the period in which the tail current flows can be shortened.
  • FIG. 10B is a diagram showing other examples of the helium chemical concentration distribution and the recombination center concentration distribution in the buffer region 20.
  • the doping concentration distribution and the hydrogen chemical concentration distribution in FIG. 10B are the same as the example of FIG. 5A.
  • the region between two adjacent doping concentration peaks 25 in the depth direction is referred to as an inter-peak region 105.
  • the region between two adjacent hydrogen chemical concentration peaks 103 in the depth direction may be a peak-to-peak region 105.
  • the inter-peak region 105-1 is between the depth positions Zd1 and Zd2 (or Zh1 and Zh2), and the inter-peak region 105-2 is between the depth positions Zd2 and Zd3 (or Zh2 and Zh3).
  • the area between the positions Zd3 and Zd4 (or Zh3 and Zh4) is defined as the inter-peak region 105-3.
  • the helium chemical concentration peak 221 is arranged in the region between two or more peaks 105.
  • the helium chemical concentration peak 221 may be located in two peak-to-peak regions 105 adjacent to each other.
  • One or more helium chemical concentration peaks 221 may be arranged in each inter-peak region 105.
  • the closer to the lower surface 23, the more helium chemical concentration peaks 221 may be arranged.
  • two helium chemical concentration peaks 221 are arranged in the inter-peak region 105-1 and one helium chemical concentration peak 221 is arranged in the inter-peak region 105-2.
  • the magnitude relationship of the concentration of each helium chemical concentration peak 221 may be the same as any of the examples described in FIGS. 5A to 10A.
  • the concentration of the helium chemical concentration peak 221 decreases as the distance from the lower surface 23 increases.
  • the spacing between the respective helium chemical concentration peaks 221 may be similar to any of the examples described in FIGS. 5A-10A.
  • the recombination center concentration may have a distribution similar to that of the helium chemical concentration.
  • FIG. 10C is a diagram showing other examples of the helium chemical concentration distribution and the recombination center concentration distribution in the buffer region 20.
  • the doping concentration distribution and the hydrogen chemical concentration distribution in FIG. 10C are the same as the example of FIG. 5A.
  • the helium chemical concentration peak 221 is not arranged in the inter-peak region 105 between the two inter-peak regions 105 in which the helium chemical concentration peak 221 is arranged.
  • two helium chemical concentration peaks 221 are arranged in the inter-peak region 105-1, and the helium chemical concentration peak 221 is not arranged in the inter-peak region 105-2, and the inter-peak region 105-3 is not arranged.
  • One helium chemical concentration peak 221 is arranged in.
  • the concentration of each helium chemical concentration peak 221 may be similar to the example of FIG. 10B.
  • the recombination center concentration may have a distribution similar to that of the helium chemical concentration.
  • FIG. 10D is a diagram illustrating the depletion layer edge position Ze included in the buffer region 20.
  • FIG. 10D shows the doping concentration distribution, the hydrogen chemical concentration distribution, the helium chemical concentration distribution, the recombination center concentration distribution, and the integrated concentration distribution of the doping concentration in the buffer region 20. These distributions may be the same as or different from any of the distributions described in FIGS. 1-10C.
  • the doping concentration distribution and the hydrogen chemical concentration distribution shown in FIG. 10D are the same as those in FIG. 10B.
  • the integrated concentration distribution of this example is the distribution of the integrated value (/ cm 2 ) obtained by integrating the doping concentration from the lower end position Zt of the trench portion toward the lower surface 23.
  • the depletion layer edge position Ze is a depth position where the integrated concentration obtained by integrating the net doping concentrations of the drift region 18 and the buffer region 20 reaches the critical integrated concentration nc from the upper end of the drift region 18 toward the lower surface 23 of the semiconductor substrate 10. Is.
  • a forward bias is applied between the collector electrode 24 and the emitter electrode 52 and avalanche breakdown occurs, the drift is performed when the upper end of the drift region 18 to a specific position of the buffer region 20 is depleted.
  • the value obtained by integrating the net doping concentration from the upper end of the region 18 to the specific position is referred to as a critical integral concentration.
  • the depletion layer edge position Ze is the position on the lowermost surface 23 side where the depletion layer spreading from the lower end of the base region 14 toward the lower surface 23 of the semiconductor substrate 10 reaches when the avalanche breakdown occurs.
  • the critical integral concentration n c depends on the constituent atoms of the semiconductor substrate 10. When the semiconductor substrate 10 is made of silicon, the critical integral concentration n c is about 1.2 ⁇ 10 12 / cm 2 .
  • the position on the lowermost surface 23 side where the depletion layer reaches may be the depletion layer edge position Ze.
  • the upper end of the drift region 18 is the boundary position between the drift region 18 and the storage region 16 in the example shown in FIG.
  • the lower end position Zt of the trench portion may be set as the lower end of the drift region 18.
  • the buffer region 20 of this example has a first helium chemical concentration peak 221-1 and a second helium chemical concentration peak 221-2. At the positions corresponding to the first helium chemical concentration peak 221-1 and the second helium chemical concentration peak 221-2, the first lower surface side lifetime killer 220-1 and the second lower surface side lifetime killer 220 are located. -2 is arranged.
  • the first helium chemical concentration peak 221-1 is arranged on the lower surface 23 side of the depletion layer edge position Ze. As a result, the first helium chemical concentration peak 221-1 can be arranged outside the range reached by the depletion layer, so that the leakage current can be suppressed.
  • the second helium chemical concentration peak 221-2 is arranged on the upper surface 21 side of the depletion layer edge position Ze.
  • the helium chemical concentration peaks 221 in a dispersed manner, it is possible to prevent the concentration of each peak from becoming too high. Therefore, the current fluctuation di / dt at the time of carrier disappearance can be moderated to suppress the occurrence of surge.
  • the second helium chemical concentration peak 221-2 carrier disappearance can be promoted at a timing earlier than the depletion layer reaches the depletion layer edge position Ze. As a result, the current fluctuation di / dt at the end of the reverse recovery operation such as the tail period can be moderated, and the occurrence of surge can be suppressed.
  • the concentration Pk1 of the first helium chemical concentration peak 221-1 may be higher than the concentration Pk2 of the second helium chemical concentration peak 221-2.
  • the concentration Pk1 may be 1.1 times or more, 1.5 times or more, 2 times or more, 5 times or more, or 10 times or more the concentration Pk2. good.
  • the first helium chemical concentration peak 221-1 is an interpeak region 105 between the doping concentration peak 25-1 (first doping concentration peak) and the doping concentration peak 25-2 (second doping concentration peak). It may be arranged at -1.
  • the second helium chemical concentration peak 221-2 is between the peaks between the doping concentration peak 25-2 (second doping concentration peak) and the doping concentration peak 25-3 (third doping concentration peak). It may be located in region 105-2.
  • the full width at half maximum of the first helium chemical concentration peak 221-1 is smaller than the inter-peak region 105-1.
  • the full width at half maximum of the first helium chemical concentration peak 221-1 may be half or less of the inter-peak region 105-1, 0.2 times or less, and 0.1 times or less.
  • the full width at half maximum of the second helium chemical concentration peak 221-2 is smaller than the interpeak region 105-2.
  • the full width at half maximum of the second helium chemical concentration peak 221-2 may be half or less of the inter-peak region 105-2, 0.2 times or less, or 0.1 times or less.
  • the respective helium chemical concentration peaks 221 do not have to overlap.
  • the overlap of the helium chemical concentration peaks 221 may mean that the depth range of the full width at half maximum of each peak overlaps.
  • the distribution of the bottom surface lifetime killer 220 may be the same as the distribution of the helium chemical concentration peak 221.
  • the description regarding the concentration, shape, arrangement, etc. of the helium chemical concentration peak 221 described in the present specification can also be applied to the bottom surface side lifetime killer 220.
  • the depletion layer edge position Ze may be arranged in the range of the full width at half maximum FWHM of the doping concentration peak 25-2. As a result, it is possible to prevent the depletion layer from reaching below the buffer region 20.
  • FIG. 10E is a diagram showing other examples of the doping concentration distribution, the hydrogen chemical concentration distribution, and the integrated concentration distribution in the buffer region 20.
  • the helium chemical concentration distribution and the recombination center concentration distribution in FIG. 10E are the same as any of the examples described in FIGS. 1 to 10D.
  • FIG. 10E shows a helium chemical concentration distribution and a recombination center concentration distribution similar to the example of FIG. 10D.
  • the peak-to-peak period 105-1 is larger than the peak-to-peak period 105-2.
  • the inter-peak period 105-2 is larger than the inter-peak period 105-1.
  • Other structures of the doping concentration distribution are similar to any of the examples described in FIGS. 1-10D.
  • the depletion layer edge position Ze may be arranged within the full width at half maximum of the doping concentration distribution 25-2.
  • FIG. 10F is a diagram showing an example of the upper surface side lifetime killer 210 and the lower surface side lifetime killer 220.
  • the helium chemical concentration peak 211 corresponding to the upper surface side lifetime killer 210 and the helium chemical concentration peak 221 corresponding to the lower surface side lifetime killer 220 are shown together.
  • the distribution of the bottom surface lifetime killer 220 and the helium chemical concentration peak 221 is similar to any of the examples described in FIGS. 1 to 10E.
  • the upper surface side lifetime killer 210 is arranged on the upper surface 21 side of the semiconductor substrate 10.
  • the upper surface side lifetime killer 210 may be arranged on the upper surface 21 side of the center in the depth direction of the semiconductor substrate 10.
  • the upper surface side lifetime killer 210 may be arranged on the upper surface side 21 side of the center in the depth direction of the drift region 18.
  • the diode portion 80 is provided with the upper surface side lifetime killer 210, but the upper surface side lifetime killer 210 may be provided in at least a part of the transistor portion 70.
  • the distribution example shown in FIG. 10F may be a distribution example in the diode portion 80, or may be a distribution example in the transistor portion 70.
  • FIG. 10G is a diagram showing an example of a voltage waveform and a current waveform in the diode unit 80.
  • FIG. 10G shows the waveform of the voltage applied between the emitter electrode 52 and the collector electrode 24 and the waveform of the current flowing between the emitter electrode 52 and the collector electrode 24.
  • FIG. 10G shows the waveforms in Reference Example 1, Reference Example 2, and Example when the diode portion 80 is turned off.
  • Reference Example 1 and Reference Example 2 only one helium chemical concentration peak is provided in the buffer region 20.
  • the helium chemical concentration peak is located in the buffer region 20 on the lower surface 23 side of the depletion layer edge position Ze and the buffer region 20 on the upper surface 21 side of the depletion layer edge position Ze. Are provided one by one.
  • the concentration of the helium chemical concentration peak (that is, the concentration at the center of recombination) is larger than that in Reference Example 2.
  • the current sharply decreases when the depletion layer reaches the helium chemical concentration peak during reverse recovery. Therefore, a surge occurs in the voltage waveform.
  • the recoupling center concentration is small, a large amount of carriers remain until the end of the reverse recovery operation. Therefore, in Reference Example 2, a current bump is generated at the end of the reverse recovery operation, and the current decreases sharply. Therefore, a surge occurs in the voltage waveform.
  • the concentration of each peak can be suppressed and the generation of surge can be suppressed by providing a plurality of helium chemical concentration peaks 221. Further, by providing the second helium chemical concentration peak 221-2, the carrier disappearance can be promoted at an early timing, the generation of the current bump at the final stage of the reverse recovery can be suppressed, and the generation of the voltage surge can be suppressed.
  • FIG. 11 is a diagram illustrating a full width at half maximum Wk of the helium chemical concentration peak 221.
  • the full width at half maximum of the hydrogen chemical concentration peak 103 is Wh.
  • FIG. 11 only one helium chemical concentration peak 221 and one hydrogen chemical concentration peak 103 are shown, and the other peaks are omitted.
  • the half-value full width Wk of each helium chemical concentration peak 221 is smaller than the half-value full width Wh of any hydrogen chemical concentration peak 103 arranged away from the lower surface 23 of the semiconductor substrate than each helium chemical concentration peak 221.
  • the full width at half maximum of each helium chemical concentration peak 221-1, 221-2, 221-3 shown in FIG. 10A is larger than the full width at half maximum of any of the hydrogen chemical concentration peaks 103-2, 103-3, 103-4. small.
  • Each full width at half maximum Wk may be less than half of the full width at half maximum Wh of the hydrogen chemical concentration peak 103 further away from the lower surface 23.
  • FIG. 12A is a diagram showing an example of the doping concentration distribution in the buffer region 20 and the hydrogen chemical concentration distribution.
  • the doping concentration distribution and the hydrogen chemical concentration distribution may be similar to the examples described in FIGS. 5A to 11. Further, the helium chemical concentration distribution is the same as any of the examples described in FIGS. 5A to 11.
  • the two doping concentration peaks 25-3 and the doping concentration peak 25-4 farthest from the lower surface 23 of the semiconductor substrate 10 are not observed as clear concentration peaks.
  • the ratio of the minimum value of the doping concentration in the region between the doping concentration peak 25-3 and the doping concentration peak 25-4 to the larger one of the doping concentration peaks 25-3 and the doping concentration peak 25-4 is n.
  • the ratio n may be 50% or less, 20% or less, or 10% or less.
  • the ratio m may be larger than the ratio n. That is, in the range from the depth position Zd3 to Zd4, the amplitude m of the fluctuation of the hydrogen chemical concentration distribution may be larger than the amplitude n of the fluctuation of the doping concentration distribution.
  • the area X is defined from the depth position Zd1 to the depth position Zd2, and the area Y is defined as the depth position Zd4 from the depth position Zd2.
  • the ratio of the minimum value of the hydrogen chemical concentration to the minimum value of the doping concentration is defined as ⁇ .
  • the ratio of the minimum value of the hydrogen chemical concentration to the minimum value of the doping concentration is ⁇ .
  • the ratio ⁇ may be larger than the ratio ⁇ .
  • the region Y may be longer than the region X.
  • the region Y may be 1.5 times or more the length of the region X, and may be twice or more the length.
  • FIG. 12B is a diagram showing a part of the steps in the manufacturing method of the semiconductor device 100.
  • the structure on the upper surface 21 side of the semiconductor substrate 10 is formed in the upper surface side structure forming step S1200.
  • the structure on the upper surface 21 side may include at least one of each doping region on the upper surface 21 side of the semiconductor substrate 10, such as an emitter region 12, a base region 14, and a storage region 16.
  • the structure on the upper surface 21 side may include each trench portion.
  • the structure on the upper surface 21 side may include a structure above the upper surface 21 of the semiconductor substrate 10, such as an emitter electrode 52.
  • the structure on the upper surface 21 side may include an edge end structure portion 90.
  • the lower surface 23 of the semiconductor substrate 10 is ground to thin the semiconductor substrate 10.
  • the semiconductor substrate 10 may be thinned to a thickness corresponding to the withstand voltage that the semiconductor device 100 should have.
  • the lower surface doped region of the semiconductor substrate 10 is formed.
  • the lower surface dope region is a dope region in contact with an electrode formed on the lower surface 23 such as the collector electrode 24 formed in a later step.
  • the bottom surface dope region may include at least one of the cathode region 82 and the collector region 22.
  • ions for forming the buffer region 20 are implanted into the semiconductor substrate 10.
  • ions may be implanted from the lower surface 23 of the semiconductor substrate 10 into the region where the buffer region 20 should be formed.
  • a hydrogen ion for example, a proton
  • a donor ion such as a phosphorus ion
  • the semiconductor substrate 10 is thermally annealed.
  • the semiconductor substrate 10 may be put into an electric furnace to anneal the entire semiconductor substrate 10 (or wafer).
  • the annealing temperature in S1208 may be 320 ° C. or higher and 420 ° C. or lower.
  • S1208 may be annealed in an atmosphere containing hydrogen and nitrogen.
  • ions for forming the lower surface side lifetime killer 220 are implanted into the semiconductor substrate 10.
  • ions may be injected from the lower surface 23 of the semiconductor substrate 10.
  • hydrogen ions such as protons or helium ions may be injected.
  • helium ion is injected.
  • the lower surface side lifetime killer 220 described in FIGS. 5A to 10G is formed.
  • the lower surface side lifetime killer 220 can be formed at a plurality of positions in the depth direction.
  • helium ions or the like may be injected in order from a position closer to the lower surface 23 among a plurality of positions in the depth direction, or helium ions or the like may be injected in order from a position farther from the lower surface 23. good.
  • helium ions are injected in order from a position farther from the lower surface 23.
  • ions may be implanted in order from the lower surface side lifetime killer 220 having a large dose amount, or ions may be implanted in order from the lower surface side lifetime killer 220 having a small dose amount.
  • the semiconductor substrate 10 is thermally annealed.
  • the semiconductor substrate 10 may be put into an electric furnace to anneal the entire semiconductor substrate 10 (or wafer).
  • the annealing temperature in S1212 may be lower than the annealing temperature in S1208.
  • the annealing temperature in S1212 may be 300 ° C. or higher and 400 ° C. or lower.
  • annealing may be performed in a nitrogen atmosphere or an atmosphere containing hydrogen and nitrogen.
  • S1212 may be performed every time helium ion or the like is injected into one depth position in S1210, or may be performed every time helium ion or the like is injected into a plurality of depth positions.
  • the set of steps S1210 and S1212 may be repeated a plurality of times (S1213).
  • an electrode in contact with the lower surface 23 is formed.
  • the collector electrode 24 may be formed.
  • FIG. 13 shows an example of the carrier concentration distribution and the helium chemical concentration distribution in the buffer region 20 of the comparative example.
  • the buffer region 20 of this example has only one peak of helium chemical concentration formed by injecting 3 He.
  • the carrier concentration distribution when helium is not injected is shown by a solid line, and the carrier concentration distribution when helium is injected is shown by a broken line.
  • the carrier concentration distribution when helium is not injected is the same as the doping concentration distribution in FIG. 5A and the like.
  • a single helium chemical concentration peak is provided in the buffer region 20. Therefore, it becomes difficult to control the distribution of the lifetime killer. Further, when the half width of the helium chemical concentration peak is large, the carrier concentration distribution fluctuates in a wide range as compared with the case where helium is not injected. On the other hand, in the examples of FIGS. 1 to 12B, since a plurality of helium chemical concentration peaks are arranged in the buffer region 20, the distribution of the lifetime killer can be adjusted accurately. Further, by reducing the half width of the helium chemical concentration peak, it is possible to suppress fluctuations in the carrier concentration distribution over a wide range.
  • FIG. 14 is a diagram showing another example of the ee cross section.
  • the method of forming the buffer region 20 is different from that of the first embodiment described with reference to FIGS. 1 to 13.
  • the method of forming the buffer area 20 will be described later.
  • Other parts are the same as those in the first embodiment.
  • the lower surface side lifetime killer 220 may or may not be provided in the buffer region 20. That is, the helium chemical concentration peak 221 may or may not be provided in the buffer region 20.
  • FIG. 15 is a diagram showing an example of a doping concentration distribution and a hydrogen chemical concentration distribution in the FF line of FIG.
  • the doping concentration distribution and the hydrogen chemical concentration distribution may be similar to the example of FIG. 5A.
  • FIG. 15 shows an example in which each doping concentration peak can be clearly observed in the doping concentration distribution, any doping concentration peak may not be clearly observed as in the example of FIG. 5A.
  • FIG. 16 is a diagram showing an example of a method of forming the buffer area 20.
  • FIG. 16 shows an injection step of injecting a dopant into the buffer region 20.
  • the N-type first dopant is injected from the injection surface of the semiconductor substrate 10 to the first injection position (S1601).
  • the injection surface is the lower surface 23, and the first injection position is the depth position Zd1 (or Zh1) described in FIG. 5A and the like.
  • the first dopant is, for example, a hydrogen ion or a phosphorus ion.
  • the N-type second dopant is injected from the injection surface (lower surface 23 in this example) of the semiconductor substrate 10 to the second injection position where the distance from the injection surface is larger than the first injection position. (S1602).
  • the second injection position is the depth position Zd2 (or Zh2) described in FIG. 5A and the like.
  • the second dopant is, for example, a hydrogen ion or a phosphorus ion.
  • the second dopant may be the same element as the first dopant.
  • both the first dopant and the second dopant are hydrogen ions.
  • one of the first dopant and the second dopant may be a phosphorus ion and the other may be a hydrogen ion.
  • the N-type third dopant is injected from the injection surface (lower surface 23 in this example) of the semiconductor substrate 10 to the third injection position where the distance from the injection surface is larger than the second injection position. (S1603).
  • the third injection position is the depth position Zd3 (or Zh3) described in FIG. 5A and the like.
  • the third dopant is, for example, a hydrogen ion or a phosphorus ion.
  • the third dopant may be the same element as the first dopant or the second dopant.
  • the first dopant, the second dopant, and the third dopant are all hydrogen ions.
  • a part of the first dopant, the second dopant and the third dopant may be a hydrogen ion, and a part may be a phosphorus ion.
  • the N-type fourth dopant is injected from the injection surface (lower surface 23 in this example) of the semiconductor substrate 10 to the fourth injection position where the distance from the injection surface is larger than the third injection position. (S1604).
  • the fourth injection position is the depth position Zd4 (or Zh4) described in FIG. 5A and the like.
  • the fourth dopant is, for example, a hydrogen ion or a phosphorus ion.
  • the fourth dopant may be the same element as the first dopant, the second dopant or the third dopant.
  • the first dopant, the second dopant, the third dopant, and the fourth dopant are all hydrogen ions.
  • a part of the first dopant, the second dopant, the third dopant and the fourth dopant may be a hydrogen ion, and a part may be a phosphorus ion.
  • three or more N-type dopants including the first dopant and the second dopant may be injected from the injection surface of the semiconductor substrate 10 to injection positions having different depths.
  • the dopant is injected at four depth positions, but the depth position at which the dopant is injected may be two or more.
  • the first dopant is injected, and then the second dopant is injected at a deeper position. Therefore, even if foreign matter adheres to the injection surface in the step of injecting the second dopant (S1602), it does not affect the injection of the first dopant. Therefore, it is possible to accurately inject the first dopant having a relatively small acceleration energy.
  • the injection step it is preferable to first inject the dopant to be injected at the injection position closest to the lower surface 23 of the semiconductor substrate 10 among the plurality of dopants to be injected into the buffer region 20.
  • the first dopant to be injected is first injected at the injection position closest to the bottom surface 23. This makes it possible to accurately inject the first dopant having the smallest acceleration energy.
  • the buffer region 20 may include a dopant that is injected after the first dopant and is injected closer to the bottom surface 23 than the first dopant.
  • the dopant to be injected at the injection position farthest from the lower surface 23 of the semiconductor substrate 10 may be injected last.
  • the fourth dopant to be injected at the injection position farthest from the bottom surface 23 is injected last.
  • the dopant in the injection step, may be injected in order from the injection position where the distance from the lower surface 23 of the semiconductor substrate 10 is short.
  • the dopants having the smallest acceleration energies can be injected in order, so that each dopant can be injected with high accuracy.
  • the distance between the injection position Zd4, which is the farthest from the lower surface 23 of the semiconductor substrate 10, and the lower surface 23 of the semiconductor substrate 10 is the thickness of the semiconductor substrate 10. It may be less than half of. That is, the injection position Zd4 is arranged between the central position Zc (see FIG. 4A) of the semiconductor substrate 10 and the lower surface 23.
  • the same conductive type dopant that is injected from the same injection surface (lower surface 23 in this example) into the region of the semiconductor substrate 10 on the injection surface side (lower surface 23 side in this example) is said. Injections may be made in order from the one closest to the injection surface.
  • the range in which the first dopant is injected and the range in which the second dopant is injected may be the same.
  • the injection range of all the first conductive type dopants to be injected into the buffer region 20 in the injection step may be the same.
  • FIG. 17 is a diagram showing a cross-sectional shape of the collector region 22 according to the comparative example.
  • the dopant is injected into the buffer region 20 in order from the position far from the lower surface 23.
  • a dopant having a shallow injection position and a small acceleration energy, such as the first dopant may be shielded by particles on the injection surface.
  • the doping concentration peak 25-1 is locally missing in the XY plane.
  • the doping concentration peak 25-1 is locally absent, the donor concentration in the region becomes low, so that the collector region 22 easily enters the region. As a result, as shown in FIG. 17, a portion protruding upward is generated in a part of the collector region 22. Therefore, when the semiconductor device 100 is turned off, the depletion layer spreading from the lower end of the base region 14 easily reaches the collector region 22, and the withstand voltage is lowered.
  • FIG. 18 is a diagram showing the results of a withstand voltage test of a semiconductor device.
  • the horizontal axis of FIG. 18 shows the voltage applied between the emitter collectors of the semiconductor device in the off state, and the vertical axis shows the current flowing between the emitter collectors of the semiconductor device.
  • the semiconductor device of the comparative example described with reference to FIG. 17 when the emitter-collector voltage Vce is 1400 V or less, a large emitter-collector current Ices flows.
  • the semiconductor device 100 according to the embodiment even if the emitter-collector voltage Vce is about 1600 V, a large emitter-collector current Ices does not flow. That is, the semiconductor device 100 according to the embodiment has a higher withstand voltage than the comparative example.
  • FIG. 19 is a diagram showing the results of a withstand voltage test of a semiconductor device.
  • FIG. 19 shows the number of semiconductor devices determined to be defective by the withstand voltage test. In the withstand voltage test, a semiconductor device having a withstand voltage or less of a predetermined withstand voltage is determined to be defective.
  • FIG. 19 shows the test results of the semiconductor device of the reference example in which the injection surface was washed and each dopant was injected, in addition to the comparative example shown in FIG. 17 and the semiconductor device 100 according to the embodiment. In the reference example, the dopant was injected into the buffer region 20 in the same injection order as in the comparative example, and the injection surface was washed with water each time the dopant was injected.
  • the number of defects could be significantly reduced without changing the design of each concentration distribution in the buffer region 20 as compared with the comparative example.
  • the number of defects can be reduced in the examples as compared with the reference example in which the injection surface is cleaned.
  • FIG. 20 is a diagram showing another example of the semiconductor device 100.
  • the buffer region 20 has a plurality of doping concentration peaks 25 has been described.
  • the storage region 16 has a plurality of doping concentration peaks 25.
  • a step of injecting a dopant into the storage region 16 will be described.
  • the buffer region 20 may or may not have a plurality of doping concentration peaks 25 formed in the same steps as in the examples of FIGS. 14 to 16.
  • each dopant may be injected in the same order as the dopant injection step into the buffer region 20 described with reference to FIGS. 14 to 16.
  • the injection surface is the upper surface 21, and the reference position of the injection position of each dopant is the upper surface 21, which is different from the examples of FIGS. 14 to 16.
  • Other contents may be the same as the examples of FIGS. 14 to 16.
  • "buffer area 20" may be read as “accumulation area 16”
  • bottom surface 23" may be read as "top surface 21".
  • the N-type first dopant is injected from the injection surface of the semiconductor substrate 10 to the first injection position (S2001).
  • the injection surface is the upper surface 21.
  • the first injection position is a position separated from the upper surface 21 by a distance Zd1 or Zh1.
  • the first dopant is, for example, a hydrogen ion or a phosphorus ion.
  • the N-type second dopant is injected from the injection surface (upper surface 21 in this example) of the semiconductor substrate 10 to the second injection position where the distance from the injection surface is larger than the first injection position.
  • the second injection position is a position separated from the upper surface 21 by a distance Zd2 or Zh2.
  • the first depth position (first injection position) for injecting the first dopant and the second depth position (second injection position) for injecting the second dopant are arranged in the storage region 16.
  • the second dopant is, for example, a hydrogen ion or a phosphorus ion.
  • the second dopant may be the same element as the first dopant.
  • both the first dopant and the second dopant are hydrogen ions.
  • one of the first dopant and the second dopant may be a phosphorus ion and the other may be a hydrogen ion.
  • the accumulation region 16 has two doping concentration peaks 25, but the number of doping concentration peaks 25 may be two or more.
  • the first dopant is injected and then the second dopant is injected at a deeper position. Therefore, even if foreign matter adheres to the injection surface in the step of injecting the second dopant (S2002), it does not affect the injection of the first dopant. Therefore, it is possible to accurately inject the first dopant having a relatively small acceleration energy.
  • FIG. 21 is a diagram showing another example of the manufacturing process of the semiconductor device 100.
  • the passage region forming step S2102 is executed before the injection step described with reference to FIG.
  • any dopant injected into the buffer region 20 is a hydrogen ion.
  • At least one of the first dopant and the second dopant having a relatively high doping concentration may be hydrogen ions. Further, the other dopant may be a hydrogen ion.
  • charged particles are injected from the lower surface 23.
  • Charged particles are hydrogen ions, helium ions, electron beams and the like.
  • the range of charged particles is more than half the thickness of the semiconductor substrate 10.
  • the range of the charged particles may be larger than the thickness of the semiconductor substrate 10.
  • the region of the semiconductor substrate 10 through which the charged particles have passed is referred to as a passing region.
  • the passage region may include more than half of the drift region 18 in the depth direction, or may include the entire region.
  • the injection step S2103 is performed.
  • An annealing step S2102 for annealing the semiconductor substrate 10 may be performed between the pass region forming step S2102 and the injection step S2103.
  • the injection step S2103 includes the steps S1601 to S1604 described with reference to FIG. As described above, in the injection step S2103, hydrogen ions are injected into at least one depth position of the buffer region 20. Therefore, the buffer region 20 contains hydrogen.
  • the hydrogen diffusion step S2104 is performed.
  • the hydrogen in the buffer region 20 is diffused into the passage region by annealing the semiconductor substrate 10.
  • the annealing temperature in the hydrogen diffusion step S2104 may be equal to or lower than the annealing temperature in the annealing step S2102.
  • Oxygen is contained in the entire semiconductor substrate 10.
  • the oxygen is intentionally or unintentionally introduced during the manufacture of semiconductor ingots.
  • H hydrogen
  • V pores
  • O oxygen
  • the VOH defect functions as a donor that supplies electrons.
  • VOH defects may be referred to simply as hydrogen donors.
  • a hydrogen donor is formed in a region through which hydrogen ions pass.
  • the hydrogen donor in the passage region is formed by terminating the dangling bonds of the pore-shaped lattice defects formed in the passage region with hydrogen and further combining with oxygen. Therefore, the doping concentration distribution of the hydrogen donor in the transit region may follow the vacancy concentration distribution.
  • the hydrogen chemical concentration in the passing region may be 10 times or more, or 100 times or more, the concentration of pores formed in the passing region.
  • the hydrogen in the passing region may be hydrogen remaining after the passage of hydrogen ions, or may be hydrogen diffused from a hydrogen supply source described later.
  • the doping concentration of the hydrogen donor is lower than the chemical concentration of hydrogen.
  • the activation rate may be a value of 0.1% to 30%. In this example, the activation rate is 1% to 5%.
  • the donor concentration in the passing region can be made higher than the bulk donor concentration.
  • the semiconductor substrate 10 having a predetermined bulk donor concentration must be prepared according to the characteristics of the element to be formed on the semiconductor substrate 10, particularly the rated voltage or the withstand voltage. In this case, as described in FIG. 4A, the doping concentration in the drift region 18 is approximately equal to the bulk donor concentration.
  • the donor concentration of the semiconductor substrate 10 can be adjusted by controlling the dose amount of charged particles or hydrogen ions.
  • a semiconductor device 100 having a drift region 18 having a predetermined doping concentration can be manufactured by using a semiconductor substrate having a bulk donor concentration that does not correspond to the characteristics of the device or the like.
  • the variation in bulk donor concentration during manufacturing of the semiconductor substrate 10 is relatively large, the dose amount of hydrogen ions can be controlled with relatively high accuracy. Therefore, the concentration of lattice defects generated by injecting hydrogen ions can be controlled with high accuracy, and the donor concentration in the passing region can be controlled with high accuracy.
  • the injection step S2103 was performed after the passage region forming step S2101.
  • the passage region forming step S2101 may be performed between the injection step S2103 and the hydrogen diffusion step S2104.
  • FIG. 22 is a diagram showing an example of the doping concentration distribution and the hydrogen chemical concentration distribution of the semiconductor device 100 shown in FIG. 21.
  • the concentration distribution at the position corresponding to the FF line shown in FIG. 3 is shown.
  • charged particles are injected into the semiconductor substrate 10 with a range larger than the thickness of the semiconductor substrate 10. That is, most of the charged particles penetrate the semiconductor substrate 10.
  • the entire semiconductor substrate 10 is a passing region. Then, the hydrogen diffused from the buffer region 20 in the hydrogen diffusion step S2102 combines with the lattice defect to form a VOH defect. Therefore, the doping concentration in the transit region is higher than the bulk donor concentration D0.
  • the hydrogen chemical concentration may decrease monotonically from the buffer region 20 toward the upper surface 21, may be flat, or may increase monotonically.
  • the hydrogen chemical concentration may monotonically increase from the buffer region 20 toward the upper surface 21.
  • the doping concentration may decrease monotonically from the buffer region 20 toward the top surface 21, may be flat, or may increase monotonically.
  • FIG. 23 is a diagram showing another example of the ee cross section.
  • the semiconductor device 100 of this example differs from each of the examples described in FIGS. 1 to 22 in that the buffer region 20 has a plurality of doping concentration peaks 25 and a plurality of bottom surface side lifetime killer 220.
  • the structure and method of forming the plurality of doping concentration peaks 25 are the same as those of the second embodiment described in FIGS. 14 to 22. Further, the structure and the forming method of the plurality of lower surface side lifetime killer 220 are the same as those of the first embodiment described with reference to FIGS. 1 to 13.
  • the buffer region 20 has a plurality of bottomside lifetime killer 220s and a plurality of helium chemical concentration peaks 221 corresponding to the same as in the first embodiment described with reference to FIGS. 1 to 13.
  • the structure other than the buffer area 20 is the same as any of the examples described with reference to FIGS. 1 to 22.
  • FIG. 24 is a diagram showing an example of a method of forming the buffer area 20 shown in FIG. 23.
  • a dopant such as hydrogen ion is injected into a plurality of depth positions in the buffer region 20.
  • the injection step S2401 includes the steps S1601 to S1604 described with reference to FIG.
  • the semiconductor substrate 10 is annealed. As a result, a plurality of doping concentration peaks 25 can be formed in the buffer region 20.
  • helium ions are injected from the lower surface 23 to different depth positions in the buffer region 20.
  • helium ions may be injected in order from a depth position close to the lower surface 23.
  • the helium ions may be injected in different orders.
  • helium ions may be injected in order from a depth position far from the lower surface 23. Even when the helium chemical concentration peak 221 is locally missing, the protrusion of the collector region 22 as shown in FIG. 17 is not formed.
  • the second annealing step S2404 for annealing the semiconductor substrate 10 may be performed.
  • the annealing temperature of the second annealing step S2404 may be lower than the annealing temperature of the first annealing step S2402.
  • the helium injection step S2403 is performed after the injection step S2401.
  • the injection step S2401 may be performed after the helium injection step S2403. It is preferable to perform an annealing step after each injection step.

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